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RT9108NL ? ds9108nl-01 june 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin configur atio ns (top view) ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. tssop-28 (exposed pad) 9w stereo class-d audio power amplifier general description the RT9108NL is a high efficiency class d stereo audio amplifier for driving bridge tied load (btl) speakers. the RT9108NL can drive stereo speakers with load as low as 4 . its high efficiency eliminates the need for an extra heat sink when playing music. the gain of the amplifier can be controlled by two gain select pins. the outputs are fully protected against shorts to gnd, pv cc , and output to output with an auto recovery feature and monitored output. features z z z z z 8v to 16v input supply range z z z z z 9w/ch into an 8 load from 12v supply at 10% thd+n z z z z z 88% efficiency eliminates need for heat sinks z z z z z four selectable or fixed gain settings z z z z z robust pin-to-pin short circuit protection z z z z z thermal protection with auto recovery option z z z z z surface mount tssop-28 (exposed pad) package z z z z z rohs compliant and halogen free applications z lcd-tv z monitors z dvd players marking information 6 7 8 9 10 11 12 13 14 4 5 2 3 21 22 23 18 19 20 16 15 17 24 25 26 27 28 sd fault linp linn pgnd outpl bspl pvccl gain0 gain1 outnl nc avcc agnd gvdd plimit rinn rinp outpr pgnd outnr bsnl bspr bsnr nc mute nc pvccr agnd 29 RT9108NLzcp : product number ymdnn : date code RT9108NL zcpymdnn simplified application circuit fb fb fb fb bspl outpl pgnd outnl bsnl bsnr outnr pgnd outpr bspr RT9108NL pv cc gain0 gain1 audio source linp gain0 gain1 rinp pvccx agnd RT9108NL package type cp : tssop-28 (exposed pad-option 3) lead plating system z : eco (ecological element with halogen free and pb free)
RT9108NL 2 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 sd shutdown logic input for audio amp (high = outputs enabled). ttl logic levels with compliance to avcc. 2 fau lt open drain output used to display short circuit fault status. voltage compliant to avcc. short circuit faults can be set to auto recovery by connecting fault pin to sd pin. 3 linp positive audio input for left channel. biased at 2v. 4 linn negative audio input for left channel. biased at 2v. 5 gain0 gain select least significant bit. 6 gain1 gain select most significant bit. 7 avcc analog supply input. 8, 29 (exposed pad) agnd analog ground. connect to the thermal pad. the exposed pad must be soldered to a large pcb and connected to agnd for maximum power dissipation. 9 gvdd high side fet gate drive supply. nominal voltage is 4.6v. 10 plimit power limit level adjustment. 11 rinn negative audio input for right channel. biased at 2v. 12 rinp positive audio input for right channel. biased at 2v. 13, 16, 27 nc no internal connection. 14 mute mute logic input for audio amp (low = outputs enabled). 15 pvccr power supply input for right channel h-bridge. right channel and left channel power supply inputs are connected internally. 17 bspr bootstrap i/o for right channel. positive high side fet. 18 outpr class-d h-bridge positive output for right channel. 19, 24 pgnd power ground for h-bridges. 20 outnr class-d h-bridge negative output for right channel. 21 bsnr bootstrap i/o for right channel. negative high side fet. 22 bsnl bootstrap i/o for left channel. negative high side fet. 23 outnl class-d h-bridge negative output for left channel. 25 outpl class-d h-bridge positive output for left channel. 26 bspl bootstrap i/o for left channel. positive high side fet. 28 pvccl power supply input for left channel h-bridge. right channel and left channel power supply inputs are connected internally.
RT9108NL 3 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram pvccl gvdd bsnl outnl bspl outpl pgnd vddp driver driver pvccr bsnr outnr bspr outpr pgnd vddp driver driver modulator uvlo ovp otp ocp avcc agnd gain control gain1 mute gain0 rinp rinn linp linn plimit sd fault
RT9108NL 4 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation the RT9108NL is a 9w (per channel) efficient class-d audio power amplifier for driving bridged-tied stereo speakers. the RT9108NL uses the three-level modulation scheme (bd model) that allows operation without the classic lc reconstruction filter when the amplifier drives is driving an inductive load. the internal close-loop modulator enables the negative error feedback, which improves the thd+n of output signal. an adjustable power limiter is included in the modulator to protect the load speaker. the adjustable power limiter allows the user to set a ? virtual ? voltage rail lower than the chip supply to limit the amount of current through the speaker. RT9108NL has protection from over current conditions caused by a short circuit on the output stage. the short circuit protection fault is reported on the fault pin as a low state. the amplifier outputs are switched to a hi-z state when the short circuit protection latch is engaged. the latch can be cleared by cycling the sd pin through the low state. if automatic recovery from the short circuit protection latch is desired, connect the fault pin directly to the sd pin. this allows the fault pin function to automatically drive the sd pin low which clears the short- circuit protection latch. the RT9108NL can drive stereo speakers as low as 4 . the high efficiency of the RT9108NL, 88%, eliminates the need for an external heat sink when playing music.
RT9108NL 5 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics parameter symbol test conditions min typ max unit logic-high v ih 3 -- -- sd, gain0, gain1, mute input voltage logic-low v il -- -- 0.8 v low level output voltage v ol fault, r pull-up = 100k -- -- 0.8 v high level input current i ih sd, gain0, gain1, mute, v i = 3v -- -- 50 a low level input current i il sd, gain0, gain1, mute, v i = 0.8v -- -- 10 a class-d output offset voltage (measured differentially) |v os | v i = 0v, gain = 36db -- 5 30 mv quiescent supply current i q v sd = 3v, no load -- 20 50 ma quiescent supply current in shutdown mode i q_sd v sd = 0.8v, no load -- 250 400 a high side -- 250 -- drain-source on-state resistance r ds(on) i o = 500ma, t j = 25 c low side -- 250 -- m v gain0 = 0.8v 19 20 21 v gain1 = 0.8v v gain0 = 3v 25 26 27 v gain0 = 0.8v 31 32 33 gain g v gain1 = 3v v gain0 = 3v 35 36 37 db recommended operating conditions (note 4) z supply input voltage, pv cc ------------------------------------------------------------------------------- 8v to 16v z junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, pvccl, pvccr, a vcc ------------------------------------------------------- ? 0.3v to 22v z input voltage, sd, gain0, gain1, faul t -------------------------------------------------------------- ? 0.3v to (avcc + 0.3v) z output voltage, outpr, outpl, out nr, outnl -------------------------------------------------- ? 0.3v to (pvccx + 0.3v) z bootstrap voltage, bspr, bspl, bsnr, bsnl ----------------------------------------------------- ? 0.3v to (pvccx + gvdd) z other pins ------------------------------------------------------------------------------------------------------ ? 0.3v to (gvdd + 0.3v) z power dissipation, p d @ t a = 25 c tssop-28 (exposed pad) ---------------------------------------------------------------------------------- 3.571w z package thermal resistance (note 2) tssop-28 (exposed pad), ja ---------------------------------------------------------------------------- 28 c/w tssop-28 (exposed pad), jc --------------------------------------------------------------------------- 7 c/w z junction temperature ---------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z storage temperature range ------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) --------------------------------------------------------------------------------- 2kv mm (ma chine model) ---------------------------------------------------------------------------------------- 200v (pv ccx = 12v, r l = 8 , t a = 25 c, unless otherwise specified)
RT9108NL 6 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a low effective thermal conductivity single-layer test board per jedec 51-3. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit pvcc over voltage lockout pv cc_ov -- 18 -- v turn-on time t on v sd = 3v -- 50 -- ms turn-off time t off v sd = 0.8v -- 2 -- ms gate drive supply v gvdd i gvdd = 2ma 4.2 4.6 5 v power supply ripple rejection psrr 200mvpp ripple at 1khz, gain = 20db, inputs ac-coupled to agnd -- ? 60 -- db continuous output power p o thd + n = 10%, f in = 1khz, pv cc = 13v -- 10 -- w total harmonic distortion + noise thd + n f in = 1khz, p o = 7.5w (half-power), r l = 8 -- 0.15 -- % -- 120 -- v output integrated noise v n 20hz to 22khz, a-weighted filter, gain = 20db -- ? 80 -- dbv crosstalk v o = 1v rms , gain = 20db, f in = 1khz -- ? 80 -- db signal-to-noise ratio snr maximum output at thd + n < 1%, f in = 1khz, gain = 20db, a-weighted filter -- 95 -- db oscillator frequency f osc 220 300 380 khz thermal trip point t sd -- 150 -- c thermal hysteresis t sd -- 15 -- c
RT9108NL 7 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit figure 1. typical application circuit figure 2. typical lc output filter pv cc pvccl 28 0.1f 1nf 100f fb fb fb fb pv cc 0.1f 100f 1nf 26 25 24 23 22 21 20 19 18 17 15 bspl outpl pgnd outnl bsnl bsnr outnr pgnd outpr bspr pvccr 1nf 1nf 1nf 1nf RT9108NL pv cc gain0 gain1 1f pv cc 1f 0.22f 0.22f 0.22f 0.22f audio source sd mute sd fault linp linn gain0 gain1 avcc agnd gvdd rinn rinp mute 10 100k 1k 14 12 11 9 8, 29 (exposed pad) 7 6 5 4 3 2 1 0.22f 0.22f 0.22f 0.22f plimit 10 pv cc pvccl 28 0.1f 1nf 100f pv cc 0.1f 100f 1nf 26 25 24 23 22 21 20 19 18 17 15 bspl outpl pgnd outnl bsnl bsnr outnr pgnd outpr bspr pvccr 0.47f RT9108NL pv cc gain0 gain1 1f pv cc 1f 0.22f 0.22f 0.22f 0.22f audio source sd mute sd fault linp linn gain0 gain1 avcc agnd gvdd rinn rinp mute 10 100k 1k 14 12 11 9 8, 29 (exposed pad) 7 6 5 4 3 2 1 0.22f 0.22f 0.22f 0.22f plimit 10 0.47f 0.47f 0.47f 22h 22h 22h 22h
RT9108NL 8 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics thd+n vs. output power thd+n (%) output power (w) pv cc = 12v, r l = 8 , gain = 20db 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 1khz 10khz 20hz 10m 20m 50m 100m 200m 1 2 5 10 20 efficiency vs. output power 0 10 20 30 40 50 60 70 80 90 100 012345678910 output power (w) efficiency (%) pv cc = 12v, f = 1khz, gain = 20db z l = 8 , lc filter = 22 h + 0.47 f, efficiency vs. output power 0 10 20 30 40 50 60 70 80 90 100 012345678910 output power (w) efficiency (%) pv cc = 12v, f = 1khz, gain = 20db z l = 4 , lc filter = 22 h + 0.47 f, 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 thd+n vs. frequency thd+n (%) frequency (hz) pv cc = 12v, r l = 8 , gain = 20db 20 50 100 200 500 1k 2k 5k 10k 20k 7w 0.5w 1w 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10m 20m 50m 100m 200m 1 2 5 10 20 thd+n vs. output power thd+n (%) output power (w) pv cc = 12v, r l = 4 , gain = 20db 1khz 10khz 20hz thd+n vs. frequency thd+n (%) frequency (hz) pv cc = 12v, r l = 4 , gain = 20db 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k 5w 10w 1w
RT9108NL 9 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. output power vs. supply voltage 0 5 10 15 20 25 30 8 10121416 supply power (v) output power (w) thd + n = 10% thd + n = 1% z l = 8 + 66 h, gain = 20db, stereo out crosstalk vs. frequency frequency (hz) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 r to l l to r 20 50 100 200 500 1k 2k 5k 10k 20k crosstalk (db) pv cc = 12v, r l = 8 , gain = 20db
RT9108NL 10 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information amplifier gain setting the gain of the RT9108NL amplifier can be set by two input terminals, gain0 and gain1, shown as table 1. the gain setting is realized by changing the taps on the input resistors and feedback resistors inside the amplifier. this causes the input impedance (z i ) to be dependent on the gain setting. the actual gain settings are controlled by the ratios of the resistors, so the gain variation from part-to-part is small. however, the input impedance from part-to-part at the same gain may shift by 20% due to shifts in the actual resistance of the input resistor. amplifier gain (db) input impedance ( ) gain1 gain0 typ typ 0 0 20 100k 0 1 26 50k 1 0 32 25k 1 1 36 12.5k table 1. gain setting () 2 l pvcc output power = width_factor r1.35 plimit voltage (v) width_factor 4.6 (gvdd) 1 2.7 to 2.9 0.765 2.3 to 2.5 0.578 1.9 to 2.1 0.410 1.6 to 1.7 0.265 1.2 to 1.3 0.149 table 2. plimit width limit pvcc = 12v, v in = 1.5v rms ,r l =8 gain = 20db gain = 26db gain = 32db gain = 36db plimit voltage (v) output power (w) output power (w) output power (w) output power (w) 4.6 (gvdd) 11.6 13.3 14 14.3 2.7 to 2.9 9.13 10.2 10.7 10.8 2.3 to 2.5 7.01 7.67 7.95 8.2 1.9 to 2.1 5.07 5.36 5.47 5.6 1.6 to 1.7 3.36 3.43 3.55 3.6 1.2 to 1.3 1.95 1.97 1.98 2 table 3. typical plimit operation at 12v power supply for the best power off pop performance, tarn off the amplifier in the shutdown mode prior to removing the power supply voltage. gvdd supply the gvdd supply is used to supply the gate drivers for the output full bridge transistors. connect a 1 f capacitor from this pin to ground. the typical gvdd output voltage is 4.6v. power limit the voltage at pin 10 can used to limit the power to levels below the supply rail. add a resistor divider from gvdd to ground to set the voltage at the plimlt pin. an external reference may also be used if tighter tolerance is required. also add a 1 f capacitor from pin 10 to ground. there are five steps to sets a limit on the output peak-to- peak voltage. the limiting is done by limiting the duty cycle to fixed maximum value. plimit pin directly connect to gvdd for no power limit. sd operation the RT9108NL employs a shutdown mode operation designed to reduce supply current (i cc ) to the absolute minimum level for power saring. the sd input terminal should be held high (see specification table for trip point) in normal operation. pulling sd low causes the outputs to mute and the amplifier to enter a low current state. leaving sd floating will cause the, amplifier operation to be unpredictable. never leave sd pin unconnected!
RT9108NL 11 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 3. derating curve of maximum power dissipation 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 single-layer pcb short circuit protection and automatic recovery the RT9108NL has protection from over current conditions caused by a short circuit on the output stage. the short circuit protection fault is reported on the fault pin as a low state. the amplifier outputs are switched to a hi-z state when the short circuit protection latch is engaged. the latch can be cleared by cycling the sd pin through the low state. if automatic recovery from the short circuit protection latch is desired, connect the fault pin directly to the sd pin. this allows the fault pin function to automatically drive the sd pin low which clears the short-circuit protection latch. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. thermal protection thermal protection on the RT9108NL prevents damage to the device when the internal die temperature exceeds 150 c. there is a 15 c tolerance on this trip point from device to device. once the die temperature exceeds the thermal set point, the device enters shutdown state and the outputs are disabled. this is not a latched fault. the thermal fault is cleared once the temperature of the die is reduced by 15 c. the device begins normal operation at this point with no external system interaction. thermal protection faults are not reported on the fault terminal. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for tssop-28 (exposed pad) package, the thermal resistance, ja , is 28 c/w on a standard jedec 51-3 single-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (28 c/w) = 3.571w for tssop-28 (exposed pad) package the maximum power dissipation depends on the operating ambient temperature for fixed t j (max) and thermal resistance, ja . the derating curve in figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
RT9108NL 12 ds9108nl-01 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations for the best performance of the RT9108NL, the below pcb layout guidelines must be strictly followed. ` place the decoupling capacitors as close as possible to the avcc, pvccl, pvccr and gnd pins. for achieving a good quality, consider adding a small, good performance low esr ceramic capacitor between 220 pf and 1000pf and a larger mid-frequency capacitor between 0.1 f and 1 f to the pvcc pins of the chip. do not trace out the nc pins (pin13, 16 and pin27) to avoid the pin short issue. 6 7 8 9 10 11 12 13 14 4 5 2 3 21 22 23 18 19 20 16 15 17 24 25 26 27 28 sd fault linp linn pgnd outpl bspl pvccl gain0 gain1 outnl nc avcc agnd gvdd plimit rinn rinp outpr pgnd outnr bsnl bspr bsnr nc mute nc pvccr agnd 29 c s pvcc c in audio input c in audio input gnd the decoupling capacitor (c s ) must be placed as close to the ic as possible c g c b c s gnd c s gnd c b c b fb fb fb fb gnd gnd do not trace out the decoupling capacitor (c s ) must be placed as close to the ic as possible do not trace out the decoupling capacitor (c s ) must be placed as close to the ic as possible figure 4. pcb layout guide ` keep the differential output traces as wide and short as possible. ` the traces of (linp & linn, rinp & rinn) and (outpl & outnl, outpr & outnr) should be kept equal width and length respectively. ` the thermal pad must be soldered to the pcb for proper thermal performance and optimal reliability. the dimensions of the thermal pad and thermal land should be larger for application. the vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the pcb.
RT9108NL 13 ds9108nl-01 june 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 1.000 1.200 0.039 0.047 a1 0.000 0.150 0.000 0.006 a2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 d 9.600 9.800 0.378 0.386 e 0.650 0.026 e 6.300 6.500 0.248 0.256 e1 4.300 4.500 0.169 0.177 l 0.450 0.750 0.018 0.030 u 4.410 5.510 0.174 0.217 option 1 v 2.400 3.000 0.094 0.118 u 5.500 6.170 0.217 0.243 option 2 v 1.600 2.210 0.063 0.087 u 5.800 6.200 0.228 0.244 option 3 v 2.600 3.000 0.102 0.118 28-lead tssop (exposed pad) plastic package

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