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february 2009 rev 11 1/34 1 stlc3055n wll and isdn-ta subscriber line interface circuit features monochip subscriber line interface circuit (slic) optimised for wll and voip applications implement all key features of the borsht function single supply (5.5 v to 12 v) built in dc/dc converter controller soft battery reversal with programmable transition time. on-hook transmission. programmable off-hook detector threshold metering pulse generation and filter integrated ringing integrated ring trip parallel control interface (3.3 v logic level) programmable constant current feed surface mount package integrated thermal protection dual gain value option bcd iii s, 90 v technology -40 to +85 c operating range description the stlc3055n is a slic device specifically designed for wireless local loop (wll) and isdn- terminal adaptors (isdn-ta) and voip applications. one of the distinctive characteristic of this device is the ability to operate with a single supply voltage (from 5.5 v to 12 v) and self generate the negative battery by means of an on chip dc/dc converter controller that drives an external mos switch. the battery level is properly adjusted depending on the operating mode. a useful characteristic for these applications is the integrated ringing generator. the control interface is a parallel type with open drain output and 3.3 v logic levels. the metering pulses are generated on chip starting from two logic signals (0 and 3.3 v) one define the metering pulse frequency and the other the metering pulse duration. an on chip circuit then provides the proper shaping and filtering. metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. a dedicated cancellation circuit avoid possible codec input saturation due to metering pulse echo. constant current feed can be set from 20 ma to 40 ma. off-hook detection threshold is programmable from 5 ma to 9 ma. the device, developed in bcd iii s technology (90 v process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when t j exceeds 140 c. lqfp44 table 1. device summary order code package packing e-stlc3055n (1) 1. ecopack? (see section 10 ) lqfp44 tray www.st.com
contents stlc3055n 2/34 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 dc/dc converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.1 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.2 high impedance feeding (hi-z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.3 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.4 ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 external components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 typical state diagram for s tlc3055n operation . . . . . . . . . . . . . . . . . 30 9 stlc3055q vs stlc3055n compatib ility. . . . . . . . . . . . . . . . . . . . . . . 31 9.1 typical power consumption comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2 hardware differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3 parameter differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
stlc3055n list of tables 3/34 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. slic operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. gain set in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. slic states in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. crest factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. external components @gain set = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 table 12. external components @gain set = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 table 13. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. power consumption differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. hardware differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 16. parameter differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of figures stlc3055n 4/34 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. dc characteristic in hi-z mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. dc characteristic in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. tip/ring typical transition from direct to reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. metering pulse generation circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. tip/ring typical ringing waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. application diagram with metering pulse generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. application diagram without metering pulse generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. 2w return loss 2wrl = 20log(|zref + zs|/|zref-zs|) = 20log(e/2vs) . . . . . . . . . . . . . . . . 26 figure 11. thl trans hybrid loss thl = 20log|vrx/vtx|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. g24 transmit gain g24 = 20log|2vtx/e| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13. g42 receive gain g42 = 20log|vi/vrx| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 14. psrrc power supply rejection vpos to 2w port pssrc = 20log|vn/vl| . . . . . . . . . . . . . 27 figure 15. l/t longitudinal to transversal conversion l/t = 20log|vcm/vl| . . . . . . . . . . . . . . . . . . . . . 27 figure 16. t/l transversal to longitudinal conversion t/l = 20log|vrx/vcm|. . . . . . . . . . . . . . . . . . . . 28 figure 17. vttx metering pulse level on line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. v2wp and w4wp: idle channel psophometric noise at line and tx. v2wp = 20log|vl/0.774l|; v4wp = 20log|vtx/0.774l| . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 19. simplified configuration for indoor overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 20. standard overvoltage protection configuration for k20 compliance . . . . . . . . . . . . . . . . . . 29 figure 21. state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 22. lqfp44 (10 x 10 x 1.4 mm) mechanical data and package dimensions . . . . . . . . . . . . . . 32
stlc3055n block diagram 5/34 1 block diagram figure 1. block diagram pd d0 d1 d2 det rttx cac iltf rd iref rlim rth csvr cvcc vpos bgnd tip ring vbat agnd tx rx zac1 zac rs zb cttx1 cttx2 fttx ckttx supervision ttx proc ac proc reference stage line driver crev input logic and decoder output logic volt. vcc vss agnd output reg. status and functions clk rsense gate vf dc/dc conv. dc proc vbat gain setting
pin description stlc3055n 6/34 2 pin description figure 2. pin connection (top view) 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 n.c. gain set pd d1 d0 d2 cttx2 cttx1 ckttx n.c. det rttx fttx rx zac1 rs zac zb cac tx vf clk vbat1 crev n.c. tip n.c. n.c. n.c. ring n.c. vbat bgnd rlim agnd cvcc rsense gate vpos csvr iltf rd iref rth d00tl488-mod 12 13 14 15 16 table 2. pin description n pin function 1 d0 control interface: input bit 0. 2 d1 control interface: input bit 1. 3 d2 control interface: input bit 2. 4 pd power down input. normally connected to cvcc (or to logic level high). 5 gain set control gain interface: 0 level r xgain = 0db t xgain = -6db 1 level r xgain = +6db t xgain = -12db 6,7,36, 38,39,40,42 nc not connected. 8 det logic interface output of the supervision detector (active low). 9 ckttx metering pulse clock input (12 khz or 16khz square wave). 10 cttx1 metering burst shaping external capacitor. 11 cttx2 metering burst shaping external capacitor. 12 rttx metering pulse cancellation buffer output. ttx filter network should be connected to this point. if not used should be left open. 13 fttx metering pulse buffer input this signal is sent to the line and used to perform ttx filtering. 14 rx 4 wire input port (rx input). a 100 k external resistor must be connected to agnd to bias the input stage. this signal is referred to agnd. if connected to single supply codec output it must be dc decoupled with proper capacitor. 15 zac1 rx buffer output, (the ac impedanc e is connected from this node to zac). 16 zac ac impedance synthesis.
stlc3055n pin description 7/34 17 rs protection resistors image (the image resist or is connected from this node to zac). 18 zb balance network for 2 to 4 wire conversion (the balance impedance zb is connected from this node to agnd. za impedance is connected from this node to zac1). 19 cac ac feedback input, ac/dc split capacitor (cac). 20 tx 4 wire output port (tx output). the signal is referred to agnd. if connected to single supply codec input it must be dc decoupled with proper capacitor. 21 vf feedback input for dc/dc converter controller. 22 clk power switch controller clock (typ. 125 khz). this pin can also be connected to cvcc or agnd. when the clk pin is connected to cvcc an auto-oscillation is internally generated and it is used instead of the ex ternal clock. when the clk pin is connected to agnd, the gate output is disabled. 23 gate driver for external power mos transistor (p-channel). 24 rsense voltage input for current sensing. rsense should be connected close to this pin and vpos pin. the pcb layout should minimize the extra resistance introduced by the copper tracks. 25 vpos positive supply 26 cvcc internal positive voltage supply filter. 27 agnd analog ground, must be shorted with bgnd. 28 rlim constant current feed programming pin (via rlim). rlim should be connected close to this pin and agnd pin to avoid noise injection. 29 iref internal bias current setting pin. rref should be connected close to this pin and agnd pin to avoid noise injection. 30 rth off-hook threshold programming pin (via rth) . rth should be connected close to this pin and agnd pin to avoid noise injection. 31 rd dc feedback and ring trip input. rd should be connected close to this pin and agnd pin to avoid noise injection. 32 iltf transversal line current image output. 33 csvr battery supply filter capacitor. 34 bgnd battery ground, must be shorted with agnd. 35 vbat regulated battery voltage self generated by the device via dc/dc converter. must be shorted to vbat1. 37 ring 2 wire port; ring wire (ib is the current sunk into this pin). 41 tip 2 wire port; tip wire (ia is the current sourced from this pin). 43 crev reverse polarity transition time control. one proper capacitor connected between this pin and agnd is setting the reverse polarity transition time. this is the same transition time used to shape the "trapezoidal ringing" during ringing injection. 44 vbat1 frame connection. must be shorted to vbat. table 2. pin description (continued) n pin function
electrical specification stlc3055n 8/34 3 electrical specification 3.1 absolute maximum rating 3.2 operating range 3.3 thermal data table 3. absolute maximum ratings symbol parameter value unit v pos positive supply voltage -0.4 to +13 v a/bgnd agnd to bgnd -1 to +1 v v dig pin d0, d1, d2, det , ckttx -0.4 to 5.5 v t j max. junction temperature 150 c v btot (1) 1. vbat is self generated by the on chip dc/dc converter and can be programmed via rf1 and rf2. rf1 and rf2 shall be selected in order to fulfil the a.m limits (see table 10: external components on page 17 ). vbtot=|vpos|+|vbat|. (total voltage applied to the device supply pins). 90 v esd rating human body model 1750 v charged device model 500 v table 4. operating range symbol parameter value unit v pos positive supply voltage 5.5 to +12 v a/bgnd agnd to bgnd -100 to +100 mv v dig pin d0, d1, d2, det , ckttx, pd -0.25 to 5.25 v t op ambient operating temperature range -40 to +85 c v bat (1) 1. vbat is self generated by the on chip dc/dc converter and can be programmed via rf1 and rf2. rf1 and rf2 shall be selected in order to fulfill the a.m limits (see table 10: external components on page 17 ). self generated battery voltage -74 max. v table 5. thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient typ. 60 c/w
stlc3055n functional description 9/34 4 functional description the stlc3055n is a device specifically deve loped for wll voip and isdn-ta applications. it is based on a slic core, on purpose optimised for these applications, with the addition of a dc/dc converter controller to fulfil the wll and isdn-ta design requirements. the slic performs the standard feedin g, signalling and tr ansmission functions. it can be set in four different operating modes via the d0, d1, d2 pins of the control logic interface (0 to 3.3 v logic levels). the loop status is carried out on the det pin (active low). the det pin is an open drain output to allow easy interfacing with both 3.3 v and 5 v logic levels. the four possible slic?s operating modes are: power down high impedance feeding (hi-z) active ringing ta bl e 6 shows how to set the different slic operating modes. 4.1 dc/dc converter the dc/dc converter controller is driving an external power mos transistor (p-channel) in order to generate the negative battery voltage needed for device operation. the dc/dc converter controller is synchronised with an external clk (125 khz typ.) or with an internal clock generated when the pin clk is connected to cvcc. one sensing resistor in series to vpos supply allows to fix the maximum allowed input peak current. this feature is implemented in order to avoid overload on vpos supply in case of line transient (ex. ring trip detection). the typical value is obtained for a sensing resistor equal to 110 m that will guarantee an average current consumption from vpos < 700 ma. when in on-hook the self generated battery voltage is set to a predefined value. this value can be adjusted via one external re sistor (rf1) and it is typical -50 v. when ring mode is selected this va lue is increased to -70 v typ. table 6. slic operating modes. pd d0 d1 d2 operating mode 000xpower down 1 0 0 x h.i. feeding (hi-z) 1 0 1 0 active normal polarity 1011active reverse polarity 1 1 1 0 active ttx injection (n.p.) 1 1 1 1 active ttx injection (r.p.) 1 1 0 0/1 ring (d2 bit toggles @ fring)
functional description stlc3055n 10/34 once the line goes in off-hook condition, the dc/dc converter automatically adjust the generated battery voltage in order to feed the line with a fixed dc current (programmable via rlim) optimising in this way the power dissipation. 4.2 operating modes 4.2.1 power down when this mode is selected the slic is switched off and the tip and ring pins are in high impedance. also the line detectors are disabled therefore the off-hook condition cannot be detected. this mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. this mode is also forced by stlc3055n in case of thermal overload (t j > 140 c). in this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. no ac transmission is possible in this mode. 4.2.2 high impedanc e feeding (hi-z) this operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. the output voltage in on-hook condition is equal to the self generated battery voltage (-50 v typ). when off-hook occurs the det becomes active (low logic level). the off-hook threshold in hi-z mode is the same value as programmed in active mode. the dc characteristic in hi-z mode is just equal to the self generated battery with 2x(1600 +rp) in series (see figure 3 ), where rp is the external protection resistance. no ac transmission is possible in this mode. figure 3. dc characteristic in hi-z mode. 4.2.3 active dc characteristics and supervision when this mode is selected the stlc3055n provides both dc feeding and ac transmission. vbat il vl vbat (-50v) 2x(r1+rp) slope: 2x(r1+rp) (r1=1600ohm)
stlc3055n functional description 11/34 the stlc3055n feeds the line with a constant current fixed by rlim (20 ma to 40 ma range). the on-hook voltage is typically 40 v allowing on-hook transmission; the self generated vbat is -50 v typ. if the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the stlc3055n behaves like a 40 v voltage source with a series impedance equal to the protection resistors 2xrp (typ. 2 x 50 ). figure 4 shows the typical dc characteristic in active mode. figure 4. dc characteristic in active mode the line status (on/off-hook) is monitored by the slic?s supervision circuit. the off-hook threshold can be programmed via the external resistor rth in the range from 5 ma to 9 ma. independently on the programmed constant current value, the tip and ring buffers have a current source capability limited to 80 ma typ. moreover the power available at vbat is controlled by the dc/dc converter that limits the peak current drawn from the vpos supply. the maximum allowed current peak is set by r sense resistor. ac characteristics the slic provides the standard slic transmission functions: once in active mode the slic can operate with two different tx, rx gain. setting properly by the gain set control bit (see ta b l e 7 ). input impedance synthesis: can be real or complex and is set by a scaled (x 50 or x 25) external zac impedance. transmit and receive: the ac signal present on the 2w port (tip and ring pins) is transferred to the tx output with a -6 db or -12 db gain and from the rx input to the 2w port with a 0 db or +6 db gain. 2 to 4 wire conversion: the balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedance za and zb once in active mode (d1=1) the slic can operate in different states setting properly d0 and d2 control bits (see also ta b l e 8 ). table 7. gain set in active mode gain set 4 to 2 wire gain 2 to 4 wire gain impedance synthesis scale factor 0 0 db -6 db x 50 1 +6 db -12 db x 25 il ilim vl vbat (-50v) 10v 2rp (20 to 40ma)
functional description stlc3055n 12/34 polarity reversal the d2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way. this means that the tip and ring wire exchange their polarities following a ramp transition (see figure 5 ). the transition time is controlled by an external capacitor crev. this capacitor is also setting the shape of the ringing trapezoidal waveform. when the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (crev). figure 5. tip/ring typical transition from direct to reverse polarity metering pulse injection (ttx) the metering pulses circuit consists of a burst shaping generator that gives a square wave shaped and a low pass filter to reduce the harmonic distortion of the output signal. the metering pulse is obtained starting from two logic signals: ckttx: is a square wave at the ttx frequency (12 or 16 khz) and should be permanently applied to the ckttx pin or at least for all the duration of the ttx pulse (including rising and decay phases). d0: enable the ttx generation circuit and define the ttx pulse duration. these two signals are processed by a dedicated circuitry integrated on chip that generate the metering pulse as an amplitude modulated shaped squarewave (sqttx) (see figure 6 ). both the amplitude and the envelope of the squarewave (sqttx) can be programmed by means of external components. in particular the amplitude is set by the two resistors rlv and the shaping by the capacitor cs. table 8. slic states in active mode d0 d1 d2 operating mode 0 1 0 active normal polarity 0 1 1 active reverse polarity 1 1 0 active ttx injection (normal polarity) 1 1 1 active ttx injection (reverse polarity) gnd tip ring dv/dt set by crev 4v typ. 40v typ on-hook
stlc3055n functional description 13/34 figure 6. metering pulse generation circuit. the waveform so generated is then filtered and injected on the line. the low pass filter can be obtained using the integrated buffer op1 connected between pin fttx (op1 non inverting input) and rttx (op1 output) (see figure 6 ) and implementing a "sallen and key" configuration. depending on the external components count it is possible to build an optimised application depending on the distortion level required. in particular harmonic distortion levels equal to 13 %, 6 % and 3 % can be obtained respectively with first, second and third order filters (see figure 6 ). the circuit showed in figure 8: application diagram with metering pulse generation. on page 20 is related to the simple first order filter. once the shaped and filtered signal is obtained at rttx buffer output it is injected on the tip/ring pins with a +6 db gain or +12 db gain. it should be noted that this is the nominal condition obtained in presence of ideal ttx echo cancellation (obtained via proper setting of rttx and cttx). in addition, the effective leve l obtained on the lin e will depend on the lin e impedanc e and the protection resistors value. in the typical application (ttx line impedance =200 , rp = 50 , and ideal ttx echo cancellation) the metering pulse level on the line will be 1.33 or 2.66 times the level applied to the rttx pin. as already mentioned the metering pulse echo cancellation is obtained by means of two external components (rttx and cttx) that should match the line impedance at the ttx frequency. this simple network has a double effect: synthesize a low output impedance at the tip/ring pins at the ttx frequency. cut the eventual ttx echo that will be tran sferred from the line to the tx output. 4.2.4 ringing when this mode is selected stlc3055n self generate an higher negative battery (-70 v typ.) in order to allow a balanced ringing signal of typically 65 vpeak. in this condition both the dc and ac feedback are disabled and the slic line drivers operate as voltage buffers. the ring waveform is obtained toggling the d2 control bit at the cttx1 cttx2 cs rlv rlv sqttx burst d0 ckttx shaping generator square wave pulse metering sinusoidal wave pulse metering rttx fttx low pass filter - + op1 cfl r1 r2 c2 c1 required external components vs. filter order. order cfl r1 c1 r2 c2 thd 1 x13% 2 xxxx6% 3 xxxxx3%
functional description stlc3055n 14/34 desired ring frequency. this bit in fact controls the line polarity (0=direct; 1=reverse). as in the active mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see figure 7 ). the shaping is defined by the crev external capacitor. selecting the proper capacitor value it is possible to get different crest factor values. the following table shows the crest factor values obtained with a 20 hz and 25 hz ring frequency and with 1ren. these value are valid either with european or usa specification. figure 7. tip/ring typical ringing waveform the ring trip detection is performed sensing the variation of the ac line impedance from on- hook (relatively high) to off-hook (low). this particular ring trip method allows to operate without dc offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. it should be noted that such a method is optimised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500 ). once ring trip is detected, the det output is activated (logic level low), at this po int the card controller or a simple logic circuit should stop the d2 toggling in order to effectively disconnect the ring signal and then set the stlc3055n in the proper operating mode (normally active). ring level in presence of more telephone in parallel as already mentioned above the maximum current that can be drawn from the vpos supply is controlled and limited via the external r sense . this will limit also the power available at the self generated negative battery. if for any reason the ringer load will be too low th e self generated battery will drop in order to keep the power consumption to the fixed limit an d therefore also the ring voltage level will be reduced. in the typical application with r sense = 110 m the peak current from vpos is limited to about 900 ma, which correspond to an average current of 700 ma max. in this condition the stlc3055n can drive up to 3ren with a ring frequency fr=25 hz (1ren = 1800 + 1.0 f, european standard). table 9. crest factor crev crest factor @20 hz crest factor @25 hz 22nf 1.2 1.26 27nf 1.25 1.32 33nf 1.33 not significant (1) 1. distortion already less than 10%. gnd tip ring dv/dt set by crev 2.5v typ. 65v typ. vbat 2.5v typ.
stlc3055n functional description 15/34 in order to drive up to 5ren (1ren= 6930 + 8 f, us standard) it is necessary to modify the external components as follows: crev = 15 nf rd = 2.2 k rsense = 100 m .
application information stlc3055n 16/34 5 application information 5.1 layout recommendation a properly designed pcb layout is a basic issue to guarantee a correct behavior and good noise performances. noise sources can be identified in not enough good grounds, not enough low impedance supplies and parasitic coupling between pcb tracks and high impedance pins of the device. particular care must be taken on the ground connection and in this case the star configuration allows surely to avoid possible problems (see figure 8 on page 20 and figure 9 on page 21 ). the ground of the power supply (vpos) has to be connected to the center of the star, let?s call this point supply gnd. this point should show a resistance as low as possible, that means it should be a ground plane. in particular to avoid noise problems the layout should prevent any coupling between the dc/dc converter components that are referred to pgnd (cvpos, cd, l) and analog pins that are referred to agnd (ex: rd, iref, rth, rlim, vf). agnd and bgnd must be shorter together. the gnd connection of protection components have to be connected to the supply gdnd. as a first recommendation the components cv, l, d1, cvpos, rsense should be kept as close as possible to each other and isolated from the other components. additional improvements can be obtained: decoupling the center of the star from the analog ground of stlc3055n using small chokes. adding a capacitor in the range of 100 nf between vpos and agnd in order to filter the switch frequency on vpos.
stlc3055n application information 17/34 5.2 external components list in order to properly define the external components value the following system parameters have to be defined: the ac input impedance shown by the slic at the line terminals "zs" to which the return loss measurement is referred. it can be real (typ. 600 ) or complex. the ac balance impedance, it is the equiva lent impedance of the line "zl" used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). it is usually a complex impedance. the value of the two protection resistors rp in series with the line termination. the line impedance at the ttx frequency "zlttx". the metering pulse level amplitude measured at line termination "vlottx". in case of low order filtering, vlottx represents the amplitude (vrms) of the fundamental frequency component. (typ 12 or 16 khz). pulse metering envelope rise and decay time constant " ". the slope of the ringing waveform " v tr / t ". the value of the constant current limit current "ilim". the value of the off-hook current threshold "i th ". the value of the ring trip rectified average threshold current "i rth ". the value of the required self generated negative battery "v batr " in ring mode (max value is 70 v). this value can be obtained from the desired ring peak level +5 v. the value of the maximum current peak sunk from vpos "ipk". table 10. external components name function formula typ. value rrx rx input bias resistor 100 k 5% rref bias setting current rref = 1.3/ibias ibias = 50 a 26 k 1% csvr negative battery filter csvr = 1/(2 ? fp ? 1.8 m ) fp = 50 hz 1.5 nf 10% 100 v rd ring trip threshold setting resistor rd = 100/i rth 2k < rd < 5 k 4.12 k 1% @ irth = 24 ma cac ac/dc split capacitance 22 f 20% 15 v @ rd = 4.12 k rp line protection resistor rp > 30 50 1% rlim current limiting programming rlim = 1300/ilim 32.5k < rlim < 65k 52.3 k 1% @ ilim = 25 ma rth off-hook threshold programming (active mode) rth = 290/i th 27 k < rth < 52 k 32.4 k 1% @i th = 9 ma crev reverse polarity transition time programming crev = ((1/3750) t/ v tr ) 22 nf 10% 10 v @ 12 v/ms rdd pull up resistors 100 k cvcc internally supply filter capacitor 100 nf 20% 10 v
application information stlc3055n 18/34 4 rf1 sets the self generated battery voltage in ring and active (il=0) mode as follows: v batr should be defined considering the ring peak level re quired (vringpeak=v batr -6 v typ.). the above relation is valid provided that the vpos power supply cu rrent capability and the rsense programming allow to source all the current requested by the particular ringer load configuration. 5 for high efficiency in hi-z mode coil resistance @125 khz must be < 3 cvpos positive supply filter capacitor with low impedance for switch mode power supply 100 f (1) cv battery supply filter capacitor with low impedance for switch mode power supply 100 f 20% 100 v (2) cvb high frequency noise filter 470 nf 20% 100 v crd (3) high frequency noise filter 100 nf 10% 15 v q1 dc/dc converter switch p- channel mos transistor rds(on) 1.2 ,vds = -100 v total gate charge = 20 nc max. with vgs = 4.5 v and vds = 1 v id > 500 ma possible choiches: irf9510 or irf9520 or irf9120 or equivalent d1 dc/dc converter series diode v r > 100 v, t rr 50 ns smbyw01-200 or equivalent rsense dc/dc converter peak current limiting r sense = 100 mv/i pk 110 m @i pk = 900 ma rf1 negative battery programming level 250 k < rf1 < 300 k (4) 300 k 1% @ v batr = -70 v rf2 negative battery programming leve l 9.1 k 1% l dc/dc converter inductor dc resistance 0.1 (5) l=100 h sumida cdrh125 or equivalent 1. cvpos should be defined depending on the power supply current capability and ma ximum allowable ripple. 2. for low ripple application use 2 x 47 f in parallel. 3. can be saved if proper pcb layout avoid noise coupling on rd pi n (high impedance input). 267 k 280 k 294 k 300 k v bat(active) -46 v -48 v -49 v -50 v v batr(ring) -62 v -65 v -68 v -70 v table 10. external components (continued) name function formula typ. value table 11. external components @gain set = 0 name function formula typ. value rs protection resistance image rs = 50 ? (2rp) 5 k @ rp = 50 zac two wire ac impedance zac = 50 ? (zs - 2rp) 25 k 1% @ zs = 600 za (1) slic impedance balancing network za = 50 ? zs 30 k 1% @ zs = 600
stlc3055n application information 19/34 zb (1) line impedance balancing network zb = 50 ? zl 30 k 1% @ zl = 600 ccomp ac feedback loop compensation fo = 250 khz ccomp = 1/(2 ? fo ? 100 ? (rp)) 120 pf 10% 10 v @ rp = 50 ch trans-hybrid loss frequency compensation ch = ccomp 120 pf 10% 10 v rttx (2) pulse metering cancellation resistor rttx = 50re (zlttx+2rp) 15 k @zlttx = 200 real cttx (2) pulse metering cancellation capacitor cttx = 1/{50 ? 2 ? fttx[- lm(zlttx)]} 100nf 10% 10v (3) @ zlttx = 200 real rlv pulse metering level resistor rlv = 63.310 3 v lottx = (|zlttx + 2rp|/|zlttx|) 16.2 k @ v lottx = 170mvrms cs pulse metering shaping capacitor cs = /(2 ? rlv) 100 nf 10% 10v @ = 3.2 ms, rlv = 16.2 k cfl pulse metering filt er capacitor cfl = 2/(2 ? fttx ? rlv) 1.5 nf 10% 10 v @fttx = 12 khz rlv = 16.2 k 1. in case zs=zl, za and zb can be replaced by two resistors of same value: ra=rb=|zs|. 2. defining zttx as the impedance of rttx in series with c ttx, rttx and cttx can also be calculated from the following formula: zttx=50*(zlttx+2rp). 3. in this case cttx is just operating as a dc decoupling capacitor (fp=100 hz). table 11. external components @gain set = 0 (continued) name function formula typ. value table 12. external components @gain set = 1 name function formula typ. value rs protection resistance image rs = 25 ? (2rp) 2.55 k @ rp = 50 zac two wire ac impedance zac = 25 ? (zs - 2rp) 12.5 k 1% @ zs = 600 za (1) slic impedance balancing network za = 25 ? zs 15 k 1% @ zs = 600 zb (1) line impedance balancing network zb = 25 ? zl 15 k 1% @ zi = 600 ccomp ac feedback loop compensation fo = 250khz ccomp = 2/(2 ? fo ? 100 ? (rp)) 220 pf 10% 10vl @ rp = 50 ch trans-hybrid loss frequency compensation ch = ccomp 220 pf 10% 10 v rttx (2) pulse metering cancellation resistor rttx = 25re (zlttx+2rp) 7.5 k @zlttx = 200 real cttx (2) pulse metering cancellation capacitor cttx = 1/25 ? 2 ? fttx ? [-lm(zlttx)] 100 nf 10% 10 v (3) @ zlttx = 200 real rlv pulse metering level resistor rlv = 31.710 3 v lottx = (|zlttx + 2rp|/|zlttx|) 16.2 k @ v lottx = 340 mvrms
application information stlc3055n 20/34 5.3 application diagram figure 8. application diagram with metering pulse generation. cs pulse metering shaping capacitor cs = /(2 ? rlv) 100 nf 10% 10v @ = 3.2 ms, rlv = 16.2 k cfl pulse metering filt er capacitor cfl = 2/(2 ? fttx ? rlv) 1.5nf 10% 10 v @fttx = 12 khz rlv = 16.2 k 1. in case zs=zl, za and zb can be replaced by two resistors of same value: ra=rb=|zs|. 2. defining zttx as the impedance of rttx in series with c ttx, rttx and cttx can also be calculated from the following formula: zttx=50*(zlttx+2rp). 3. in this case cttx is just operating as a dc decoupling capacitor (fp=100 hz). table 12. external components @gain set = 1 (continued) name function formula typ. value zac rs rrx za zb ccomp tx zac1 zac zb tx control interface d0 gain set d1 d2 bgnd cvcc cac cac iref rref gate vbat p-ch q1 rf1 clk crev crev d00tl489a csvr stlc3055n d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cs cfl rlv rlv ttx clock cttx cvcc rsense rf2 cv vf l clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx rttx system gnd agnd bgnd suggested ground lay-out vdd cvb crd pgnd pd pd
stlc3055n application information 21/34 figure 9. application diagram wi thout metering pulse generation zac rs za zb ccomp tx zac1 zac zb tx control interface d0 d1 d2 bgnd cvcc cac cac iref rref gate vbat p-ch q1 rf1 clk crev crev d00tl490/b csvr stlc3055n d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cvcc rsense rf2 cv vf l clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx system gnd agnd bgnd suggested ground lay-out vdd cvb crd pgnd gain set pd pd rrx
electrical characteristics stlc3055n 22/34 6 electrical characteristics table 13. electrical characteristics test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25 c. external components as listed in the "typical values" column of external components table. note: testing of all parameter is performed at 25 c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the operating range: -40 to +85 c. symbol parameter test condition min. typ. max. unit dc characteristics v lohi line voltage il = 0, hi-z (high impedance feeding) t amb = 0 to 85 c 44 50 v v lohi line voltage il = 0, hi-z (high impedance feeding) t amb = -40 to 85 c 42 48 v v loa line voltage il = 0, active t amb = 0 to 85 c 33 40 v v loa line voltage il = 0, active t amb = -40 to 85 c 31 37 v ilim lim. current programming range active mode 20 40 ma ilima lim. current accuracy active mode. rel. to programmed value 20 ma to 40 ma -10 10 % rfeed hi feeding resistance hi-z (high impedance feeding) 2.4 3.6 k ac characteristics l/t long. to transv. (see section 6.1: test circuits .) rp = 50 , 1% tol., active n. p., r l = 600 (1) f = 300 to 3400 hz 50 58 db t/l transv. to long. (see section 6.1: test circuits .) rp = 50 , 1% tol., active n. p., r l = 600 (1) f = 300 to 3400 hz 40 45 db t/l transv. to long. (see section 6.1: test circuits .) rp = 50 , 1% tol., active n. p., r l = 600 (1) f = 1 khz 48 53 db 2wrl 2w return loss 300 to 3400 hz, active n. p., r l = 600 (1) 22 26 db thl trans-hybrid loss 300 to 3400 hz, 20log|vrx/vtx|, active n. p., r l = 600 (1) 30 db
stlc3055n electrical characteristics 23/34 ovl 2w overload level at line terminals on ref. imped. active n. p., r l = 600 (1) 3.2 dbm txoff tx output offset active n. p., r l = 600 (1) -250 250 mv g24 transmit gain abs. 0dbm @ 1020hz, active n. p., r l = 600 (1) -6.4 -5.6 db g42 receive gain abs. 0dbm @ 1020hz, active n. p., r l = 600 (1) -0.4 0.4 db g24f tx gain variation vs. freq. rel. 1020hz; 0 dbm, 300 to 3400 hz, active n. p., r l = 600 (1) -0.12 0.12 db g24f rx gain variation vs. freq. rel. 1020 hz; 0 dbm, 300 to 3400 hz, active n. p., r l = 600 (1) -0.12 0.12 db v2wp idle channel noise at line 0db gainset psophometric filtered active n. p., r l = 600 (1) t amb = 0 to +85 c -73 -68 dbmp v2wp idle channel noise at line 0db gainset psophometric filtered active n. p., r l = 600 (1) t amb = -40 to +85 c -68 dbmp v4wp idle channel noise at line 0db gainset psophometric filtered active n. p., r l = 600 (1) t amb = 0 to +85 c -75 -70 dbmp v4wp idle channel noise at line 0db gainset psophometric filtered active n. p., r l = 600 (1) t amb = -40 to +85 c -75 dbmp thd total harmonic distortion active n. p., r l = 600 (1) -44 db vttx metering pulse level on line active - ttx; gain set = 1 zl = 200 fttx = 12 khz; 260 340 mvrms clkfreq clk operating range -10% 125 10% khz ring vring line voltage ring d2 toggling @ fr = 25 hz load = 3ren; crest factor = 1.25 1ren = 1800 + 1.0 f t amb = 0 to +85c 45 49 vrms table 13. electrical characteristics (continued) test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25 c. external components as listed in the "typical values" column of external components table. note: testing of all parameter is performed at 25 c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the operating range: -40 to +85 c. symbol parameter test condition min. typ. max. unit
electrical characteristics stlc3055n 24/34 vring line voltage ring d2 toggling @ fr = 25hz load = 3ren; crest factor = 1.25 1ren = 1800 + 1.0 f t amb = -40 to +85c 44 48 vrms detectors iofftha off/hook current threshold act. mode, rth = 32.4k 1% (prog. ith = 9ma) 10.5 ma roftha off/hook loop resistance threshold act. mode, rth = 32.4k 1% (prog. ith = 9ma) 3.4 k iontha on/hook current threshold act. mode, rth = 32.4k 1% (prog. ith = 9ma) 6ma rontha on/hook loop resistance threshold act. mode, rth = 32.4k 1% (prog. ith = 9ma) 8k ioffthi off/hook cu rrent threshold hi z mode, rth = 32.4k 1% (prog. ith = 9ma) 10.5 ma roffthi off/hook loop resistance threshold hi z mode, rth = 32.4k 1% (prog. ith = 9ma) 800 ionthi on/hook cu rrent threshold hi z mode, rth = 32.4k 1% (prog. ith = 9ma) 6ma ronthi on/hook loop resistance threshold hi z mode, rth = 32.4k 1% (prog. ith = 9ma) 8k irt ring trip detector threshold range ring mode 20 50 ma irta ring trip detector threshold accuracy ring mode -15 15 % trtd ring trip detection time ring mode 60 ms td dialling distortion active mode -1 1 ms rlrt (2) loop resistance 500 thal tj for th. alarm activation 160 c table 13. electrical characteristics (continued) test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25 c. external components as listed in the "typical values" column of external components table. note: testing of all parameter is performed at 25 c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the operating range: -40 to +85 c. symbol parameter test condition min. typ. max. unit
stlc3055n electrical characteristics 25/34 digital interface inputs: d0, d1, d2, pd, clk outputs: det vih in put high voltage 2 v vil input low voltage 0.8 v iih input high current -10 10 a iil input low current -10 10 a vol output low voltage iol = 1ma 0.45 v psrr and power consumption pserrc power supply rejection vpos to 2w port vripple = 100mvrms 50 to 4000hz 26 36 db ivpos vpos supply current @ ii = 0 hi-z on-hook active on-hook, ring (line open) 13 50 55 25 80 90 ma ma ma ipk peak current limiting accuracy ring off-hook rsense = 110m -20% 950 +20% mapk 1. r l : line resistance 2. rlrt = maximum loop resistance (incl. telephone) for correct ring trip detection. table 13. electrical characteristics (continued) test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25 c. external components as listed in the "typical values" column of external components table. note: testing of all parameter is performed at 25 c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the operating range: -40 to +85 c. symbol parameter test condition min. typ. max. unit
electrical characteristics stlc3055n 26/34 6.1 test circuits referring to the application diagram shown in figure 8 on page 20 and using as external components the typical values specified in the table 10 on page 17 and table 11 on page 18 , find below the proper configuration for each measurement. all measurements requiring dc current termination should be performed using "wandel & goltermann dc loop holding circuit gh-1" or equivalent. figure 10. 2w return loss 2wrl = 20log(|zref + zs|/|zref-zs|) = 20log(e/2vs) figure 11. thl trans hybrid loss thl = 20log|vrx/vtx| figure 12. g24 transmit gain g24 = 20log|2vtx/e| tip ring rx tx stlc3055n application circuit w&g gh1 zref e vs 1kohm 1kohm 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm 100 f tip ring rx tx stlc3055n application circuit w&g gh1 vrx vtx 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm tip ring rx tx stlc3055n application circuit w&g gh1 e vtx 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm
stlc3055n electrical characteristics 27/34 figure 13. g42 receive gain g42 = 20log|vi/vrx| figure 14. psrrc power supply rejection vpos to 2w port pssrc = 20log|vn/vl| figure 15. l/t longitudinal to transversal conversion l/t = 20log|vcm/vl| tip ring rx tx stlc3055n application circuit w&g gh1 vrx vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm tip ring rx tx stlc3055n application circuit w&g gh1 vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm vn vpos ~ tip ring rx tx stlc3055n application circuit w&g gh1 vcm vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 f 300ohm 100 f impedance matching better than 0.1%
electrical characteristics stlc3055n 28/34 figure 16. t/l transversal to longitudinal conversion t/l = 20log|vrx/vcm| figure 17. vttx metering pulse level on line figure 18. v2wp and w4wp: idle channel psophometric noise at line and tx. v2wp = 20log|vl/0.774l|; v4wp = 20log|vtx/0.774l| 600ohm tip ring rx tx stlc3055n application circuit vcm w&g gh1 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 f 300ohm 100 f impedance matching better than 0.1% vrx tip ring rx tx stlc3055n application circuit fttx (12 or 16khz) vlttx 200ohm ckttx tip ring rx tx stlc3055n application circuit w&g gh1 vl psophometric filtered 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm vtx psophometric filtered
stlc3055n overvoltage protection 29/34 7 overvoltage protection figure 19. simplified configuration for indoor overvoltage protection figure 20. standard overvoltage protection configuration for k20 compliance tip ring bgnd vbat rp1 rp2 rp1 rp2 2 x sm6t39a stlc3055n tip ring rp1 = 30ohm: rp2 =fuse or ptc > 18ohm stpr120a stpr120a tip bgnd vbat rp1 rp2 rp1 = 30ohm: rp2 =fuse or ptc > 18ohm 2 x sm6t39a stlc3055n tip ring rp1 rp2 ring lcp1521
typical state diagram for stlc3055n operation stlc3055n 30/34 8 typical state diagram for stlc3055n operation figure 21. state diagram tj>tth pd=0, d0=d1=0 pd=1, d0=d1=0 power down hi-z feeding off hook detection active off hook on hook detection for t>tref active on hook ringing ring burst d0=1, d1=0, d2=0/1 ring trip detection normally used for on hook transmission ring pause d0=0, d1=1, d2=0 ring burst off hook detection d0=0, d1=1, d2=0 on hook condition note: all state transitions are under the microprocessor control.
stlc3055n stlc3055q vs stlc3055n compatibility. 31/34 9 stlc3055q vs stlc3055n compatibility. stlc3055n is pin to pin compatible with the old stlc3055q but offer a better performance in term of power consumption and can be set in a new gain configuration in order to be compatible with the 3.3 v codec. 9.1 typical power consumption comparison to meet this result some differences, with a minimum impact on the application, has been introduced in stlc3055n. 9.2 hardware differences rx input. in stlc3055n it is necessary a 100 k external resistor between rx input and agnd to bias the input stage. rp. the stlc3055n required a rp value of 50 instead of 41 . ttx filter. to optimize the ttx signal dynamic, the values of rlv and cfl have been changed; 9.3 parameter differences table 14. power consumption differences operative mode stlc3055q stlc3055n hi-z 52 - 60 ma 13 - 25 ma active on hook 93 - 115 ma 50 - 80 ma ring (no ren) 120 - 140 ma 55 - 90 ma table 15. hardware differences component stlc3055q stlc3055n rrx 100 k rp 41 50 rlv 27 k 16.2 k cfl 1 nf 1.5 nf table 16. parameter differences parameter stlc3055q stlc3055n absolute max. rating 17 v 13 v operating range 15.8 v 12 v typ. metering pulse level (gs 1) 340 mvrms typ. metering pulse level (gs 0) 200 mv rms 170 mv rms
package information stlc3055n 32/34 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 22. lqfp44 (10 x 10 x 1.4 mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 8.00 0.315 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 8.00 0.315 e0.80 0.031 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?(min.), 3.5?(typ.), 7?(max.) ccc 0.10 0.0039 lqfp44 (10 x 10 x 1.4mm) 0076922 e
stlc3055n revision history 33/34 11 revision history table 17. document revision history date revision changes 11-sep-2003 4 first issue 01-oct-2004 5 update functional description and electrical characteristics. aligned the graphic style to be compliant with the new ?corporate technical publications design guide? 15-oct-2004 6 modified the application diagrams and some typo errors. 05-nov-2004 7 removed all max. values of the ?line voltage? parameter on the page 14/24. changed the unit from ma to % of the ?ilima? parameter on the page 14/24. 15-jan-2005 8 add pin 4 pd in applications and block diagram add in table 2 ?esd rating? 01-jul-2005 9 changed vttx value 21-feb-2006 10 added part number ?e-stlc3055n? (ecopack). added rrx resistance in the figures 9 and 10. added appendix d. 12-feb-2009 11 document reformatted. updated section 10: package information on page 32 .
stlc3055n 34/34 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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