regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 8-bit single-chip microcomputer 740 family / 38000 series 3850/3851 group users manual
keep safety first in your circuit designs ! l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
rev. rev. no. date 1.0 first edition 981021 revision description list 3850/3851 group users manual (1/1) revision description
preface this users manual describes mitsubishis cmos 8- bit microcomputers 3851 group and 3850 group. after reading this manual, the user should have a through knowledge of their functions and features, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. the difference between the 3851 group and 3850 group is the i 2 c-bus built-in or not. the 3850 group does not have the built-in i 2 c-bus. accordingly, use this users manual with care, considering the difference between the 3851 group and 3850 group. this users manual mainly explains the 3851 group. the difference is explained in the section functional description supplement of chapter 1 . for details of software, refer to the 740 series software manual. for details of development support tools, refer to the data book or the data sheet of development support tools for 740 family.
before using this manual this users manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. chapter 3 also includes necessary information for systems development. you must refer to that chapter. 1. organization l chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. l chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. l chapter 3 appendix this chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers, the mask rom confirmation form (for mask rom version), the rom programming confirmation form (for one time prom version), and the mark specification form which are to be submitted when ordering. 2. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows : note 2 : bit attributes......... the attributes of control register bits are classified into 3 bytes : read-only, write- only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is arranged 0 1 : name function at reset rw b 0 1 2 3 4 0 0 0 0 0 5 5 5 6 7 1 b0 b1 b2 b3 b4 b5 b6 b7 contents immediately after reset release bit attributes (note 1) processor mode bits stack page selection bit nothing arranged for these bits. these are write disabled bits. when these bits are read out, the contents are ?. fix this bit to ?. main clock (x in -x out ) stop bit internal system clock selection bit 0 0 : single-chip mode 1 0 : 1 1 : not available b1 b0 0 : 0 page 1 : 1 page 0 : operating 1 : stopped 0 : x in -x out selected 1 : x cin -x cout selected : bit that is not used for control of the corresponding function 0 note 1 :. contents immediately after reset release 0....... ??at reset release 1....... ??at reset release ?....... undefined at reset release ] .......contents determined by option at reset release r....... read ...... read enabled 5 .......read disabled w......write ..... write enabled 5 ...... write disabled ] .......??write (note 2) cpu mode register (cpum) [address : 3b 16 ] bits ] ]
i 3850/3851 group users manual table of contents table of contents chapter 1 hardware description ............................................................................................................................... . 1-2 features ............................................................................................................................... ....... 1-2 application ............................................................................................................................... . 1-2 pin configuration (top view) ........................................................................................... 1-2 functional block .................................................................................................................. 1-3 pin description ........................................................................................................................ 1-4 part numbering ....................................................................................................................... 1-5 group expansion .................................................................................................................... 1-6 memory type ............................................................................................................................ 1-6 memory size ............................................................................................................................. 1- 6 packages ............................................................................................................................... .... 1-6 functional description ...................................................................................................... 1-7 central processing unit (cpu) .............................................................................................. 1-7 memory ............................................................................................................................... .. 1-11 i/o ports .............................................................................................................................. 1 -13 interrupts .......................................................................................................................... 1-16 timers ............................................................................................................................... .... 1-19 serial i/o .............................................................................................................................. 1 -21 multi-master i 2 c-bus interface ............................................................................... 1-25 pulse width modulation (pwm) ................................................................................ 1-36 a-d converter .................................................................................................................. 1-38 watchdog timer .............................................................................................................. 1-39 reset circuit .................................................................................................................... 1-40 clock generating circuit ......................................................................................... 1-42 notes on programming ..................................................................................................... 1-45 processor status register .................................................................................................... 1-45 interrupts ............................................................................................................................... .. 1-45 decimal calculations .............................................................................................................. 1-45 timers ............................................................................................................................... ....... 1-45 multiplication and division instructions ............................................................................... 1-45 ports ............................................................................................................................... .......... 1-45 serial i/o ............................................................................................................................... .. 1-45 a-d converter ......................................................................................................................... 1-45 instruction excution time ...................................................................................................... 1-45 data required for mask orders ................................................................................ 1-46 data required for rom writing orders ................................................................. 1-46 rom programming method .............................................................................................. 1-46 functional description supplement ......................................................................... 1-47 interrupt ............................................................................................................................... .... 1-47 timing after interrupt ............................................................................................................. 1-48 a-d converter ......................................................................................................................... 1-49 misrg ............................................................................................................................... ...... 1-51 3850 group ............................................................................................................................. 1- 53
ii 3850/3851 group users manual table of contents chapter 2 application 2.1 i/o port ............................................................................................................................... ...... 2-2 2.1.1 memory map ................................................................................................................... 2-2 2.1.2 relevant registers .......................................................................................................... 2-2 2.1.3 handling of unused pins ............................................................................................... 2-3 2.1.4 notes on input and output pins ................................................................................... 2-4 2.1.5 termination of unused pins .......................................................................................... 2-5 2.2 timer ............................................................................................................................... .......... 2-6 2.2.1 memory map ................................................................................................................... 2-6 2.2.2 relevant registers .......................................................................................................... 2-6 2.2.3 timer application examples ........................................................................................ 2-12 2.2.4 notes on timer .............................................................................................................. 2-25 2.3 serial i/o ............................................................................................................................... . 2-26 2.3.1 memory map ................................................................................................................. 2-26 2.3.2 relevant registers ........................................................................................................ 2-27 2.3.3 serial i/o connection examples ................................................................................. 2-31 2.3.4 setting of serial i/o transfer data format ................................................................. 2-33 2.3.5 serial i/o application examples ................................................................................. 2-34 2.3.6 notes on serial i/o ...................................................................................................... 2-52 2.4 muti-master i 2 c-bus interface .......................................................................................... 2-55 2.4.1 memory map ................................................................................................................. 2-55 2.4.2 relevant registers ........................................................................................................ 2-55 2.4.3 i 2 c-bus overview ......................................................................................................... 2-61 2.4.4 communication format ................................................................................................. 2-62 2.4.5 synchronization and arbitration lost .......................................................................... 2-63 2.4.6 smbus communication usage example ................................................................... 2-65 2.4.7 notes on muti-master i 2 c-bus interface .................................................................. 2-81 2.4.8 notes on programming for smbus interface ........................................................... 2-84 2.5 pwm ............................................................................................................................... ......... 2-85 2.5.1 memory map ................................................................................................................. 2-85 2.5.2 relevant registers ........................................................................................................ 2-85 2.5.3 pwm output circuit application example ................................................................... 2-87 2.5.4 notes on pwm ............................................................................................................. 2-89 2.6 a-d converter ....................................................................................................................... 2-90 2.6.1 memory map ................................................................................................................. 2-90 2.6.2 relevant registers ........................................................................................................ 2-90 2.6.3 a-d converter application examples .......................................................................... 2-93 2.6.4 notes on a-d converter .............................................................................................. 2-95 2.7 reset ............................................................................................................................... ........ 2-96 2.7.1 connection example of reset ic ................................................................................ 2-96 2.7.2 notes on reset pin ................................................................................................... 2-97
iii 3850/3851 group users manual table of contents chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 absolute maximum ratings ............................................................................................ 3-2 3.1.2 recommended operating conditions ............................................................................ 3-3 3.1.3 electrical characteristics ................................................................................................ 3-5 3.1.4 a-d converter characteristics ....................................................................................... 3-6 3.1.5 timing requirements ...................................................................................................... 3-7 3.1.6 switching characteristics ............................................................................................... 3-8 3.1.7 multi-master i 2 c-bus bus line characteristics .......................................................... 3-11 3.2 standard characteristics .................................................................................................... 3-12 3.2.1 power source current characteristic examples ........................................................ 3-12 3.2.2 port standard characteristic examples ...................................................................... 3-15 3.2.3 a-d conversion standard characteristics ................................................................... 3-17 3.3 notes on use ........................................................................................................................ 3-18 3.3.1 notes on interrupts ...................................................................................................... 3-18 3.3.2 notes on timer .............................................................................................................. 3-19 3.3.3 notes on serial i/o ...................................................................................................... 3-19 3.3.4 notes on multi-master i 2 c-bus interface ................................................................. 3-21 3.3.5 notes on a-d converter .............................................................................................. 3-24 3.3.6 notes on watchdog timer ............................................................................................ 3-24 3.3.7 notes on reset pin ................................................................................................... 3-24 3.3.8 notes on input and output pins ................................................................................. 3-25 3.3.9 notes on low-speed operation mode ........................................................................ 3-26 3.3.10 notes on restarting oscillation .................................................................................. 3-26 3.3.11 notes on programming .............................................................................................. 3-27 3.3.12 programming and test of built-in prom version ................................................... 3-29 3.3.13 notes on built-in prom version .............................................................................. 3-29 3.3.14 termination of unused pins ...................................................................................... 3-31 3.4 countermeasures against noise ...................................................................................... 3-32 3.4.1 shortest wiring length .................................................................................................. 3-32 3.4.2 connection of bypass capacitor across v ss line and v cc line ............................... 3-34 3.4.3 wiring to analog input pins ........................................................................................ 3-35 3.4.4 oscillator concerns ....................................................................................................... 3-35 3.4.5 setup for i/o ports ....................................................................................................... 3-37 3.4.6 providing of watchdog timer function by software .................................................. 3-38 3.5 list of registers ................................................................................................................... 3-39 3.6 mask rom confirmation form ........................................................................................... 3-56 3.7 rom programming confirmation form ............................................................................ 3-66 3.8 mark specification form ..................................................................................................... 3-74 3.9 package outline ................................................................................................................... 3-76 3.10 machine instructions ........................................................................................................ 3-78 3.11 list of instruction codes ................................................................................................. 3-89 3.12 sfr memory map .............................................................................................................. 3-90 3.13 pin configurations ............................................................................................................. 3-91
3850/3851 group users manual i list of figures list of figures chapter 1 hardware fig. 1 m38513m4-xxxfp/sp pin configuration ......................................................................... 1-2 fig. 2 functional block diagram ................................................................................................... 1-3 fig. 3 part numbering .................................................................................................................... 1-5 fig. 4 memory expansion plan ..................................................................................................... 1-6 fig. 5 740 family cpu register structure ................................................................................... 1-7 fig. 6 register push and pop at interrupt generation and subroutine call ........................... 1-8 fig. 7 structure of cpu mode register ..................................................................................... 1-10 fig. 8 memory map diagram ...................................................................................................... 1-11 fig. 9 memory map of special function register (sfr) .......................................................... 1-12 fig. 10 port block diagram (1) ................................................................................................... 1-14 fig. 11 port block diagram (2) ................................................................................................... 1-15 fig. 12 interrupt control ............................................................................................................... 1-18 fig. 13 structure of interrupt-related registers (1) .................................................................. 1-18 fig. 14 structure of timer xy mode register ............................................................................ 1-19 fig. 15 structure of timer count source selection register ..................................................... 1-19 fig. 16 block diagram of timer x, timer 1 and timer 2 .......................................................... 1-20 fig. 17 block diagram of clock synchronous serial i/o .......................................................... 1-21 fig. 18 operation of clock synchronous serial i/o function ................................................... 1-21 fig. 19 block diagram of uart serial i/o ............................................................................... 1-22 fig. 20 operation of uart serial i/o function ........................................................................ 1-23 fig. 21 structure of serial i/o control registers ....................................................................... 1-24 fig. 22 block diagram of multi-master i 2 c-bus interface ...................................................... 1-25 fig. 23 structure of i 2 c address register .................................................................................. 1-26 fig. 24 structure of i 2 c clock control register ......................................................................... 1-27 fig. 25 sda/scl pin selection bit ............................................................................................. 1-28 fig. 26 structure of i 2 c control register .................................................................................... 1-28 fig. 27 structure of i 2 c status register ..................................................................................... 1-30 fig. 28 interrupt request signal generating timing .................................................................. 1-30 fig. 29 start condition generating timing diagram .............................................................. 1-31 fig. 30 stop condition generating timing diagram ................................................................ 1-31 fig. 31 start/stop condition detecting timing diagram ..................................................... 1-31 fig. 32 stop condition detecting timing diagram ................................................................... 1-31 fig. 33 structure of i 2 c start/stop condition control register ............................................ 1-33 fig. 34 address data communication format ............................................................................ 1-33 fig. 35 timing of pwm period ................................................................................................... 1-36 fig. 36 block diagram of pwm function ................................................................................... 1-36 fig. 37 structure of pwm control register ............................................................................... 1-37 fig. 38 pwm output timing when pwm register or pwm prescaler is changed ................ 1-37 fig. 39 structure of ad control register ................................................................................... 1-38 fig. 40 structure of a-d conversion registers ......................................................................... 1-38 fig. 41 block diagram of a-d converter ................................................................................... 1-38 fig. 42 block diagram of watchdog timer ................................................................................ 1-39 fig. 43 structure of watchdog timer control register ............................................................. 1-39 fig. 44 reset circuit example .................................................................................................... 1-40 fig. 45 reset sequence .............................................................................................................. 1-40 fig. 46 internal status at reset .................................................................................................. 1-41 fig. 47 ceramic resonator circuit .............................................................................................. 1-42
ii 3850/3851 group users manual list of figures chapter 2 application fig. 2.1.1 memory map of registers relevant to i/o port ......................................................... 2-2 fig. 2.1.2 structure of port pi (i = 0, 1, 2, 3, 4) ...................................................................... 2-2 fig. 2.1.3 structure of port pi direction register (i = 0, 1, 2, 3, 4) ....................................... 2-3 fig. 2.2.1 memory map of registers relevant to timers ............................................................ 2-6 fig. 2.2.2 structure of prescaler 12, prescaler x, prescaler y .............................................. 2-6 fig. 2.2.3 structure of timer 1 .................................................................................................... 2-7 fig. 2.2.4 structure of timer 2, timer x, timer y ................................................................... 2-7 fig. 2.2.5 structure of timer xy mode register ........................................................................ 2-8 fig. 2.2.6 structure of timer count source set register ........................................................... 2-9 fig. 2.2.7 structure of interrupt request register 1 ................................................................. 2-10 fig. 2.2.8 structure of interrupt request register 2 ................................................................. 2-10 fig. 2.2.9 structure of interrupt control register 1 .................................................................. 2-11 fig. 2.2.10 structure of interrupt control register 2 ................................................................ 2-11 fig. 2.2.11 timers connection and setting of division ratios ................................................. 2-13 fig. 2.2.12 relevant registers setting ....................................................................................... 2-14 fig. 2.2.13 control procedure ..................................................................................................... 2-15 fig. 2.2.14 peripheral circuit example ....................................................................................... 2-16 fig. 2.2.15 timers connection and setting of division ratios ................................................. 2-16 fig. 2.2.16 relevant registers setting ....................................................................................... 2-17 fig. 2.2.17 control procedure ..................................................................................................... 2-18 fig 2.2.18 judgment method of valid/invalid of input pulses ................................................ 2-19 fig. 2.2.19 relevant registers setting ....................................................................................... 2-20 fig. 2.2.20 control procedure ..................................................................................................... 2-21 fig. 2.2.21 timers connection and setting of division ratios ................................................. 2-22 fig. 2.2.22 relevant registers setting ....................................................................................... 2-23 fig. 2.2.23 control procedure ..................................................................................................... 2-24 fig. 2.3.1 memory map of registers relevant to serial i/o ..................................................... 2-26 fig. 2.3.2 structure of transmit/receive buffer register ........................................................ 2-27 fig. 2.3.3 structure of serial i/o status register ..................................................................... 2-27 fig. 2.3.4 structure of serial i/o control register .................................................................... 2-28 fig. 2.3.5 structure of uart control register .......................................................................... 2-28 fig. 2.3.6 structure of baud rate generator ............................................................................. 2-29 fig. 2.3.7 structure of interrupt edge selection register ........................................................ 2-29 fig. 2.3.8 structure of interrupt request register 2 ................................................................. 2-29 fig. 2.3.9 structure of interrupt control register 2 .................................................................. 2-30 fig. 48 external clock input circuit ............................................................................................ 1-42 fig. 49 structure of misrg ........................................................................................................ 1-43 fig. 50 system clock generating circuit block diagram (single-chip mode) ........................ 1-43 fig. 51 state transitions of system clock ................................................................................. 1-44 fig. 52 programming and testing of one time prom version ............................................ 1-46 fig. 53 timing chart after an interrupt occurs ......................................................................... 1-48 fig. 54 time up to execution of the interrupt processing routine ........................................ 1-48 fig. 55 a-d conversion equivalent circuit ................................................................................. 1-50 fig. 56 a-d conversion timing chart .......................................................................................... 1-50 fig. 57 structure of misrg ........................................................................................................ 1-52 fig. 58 structure of i 2 c start/stop condition control register ......................................... 1-52 fig. 59 memory expansion plan of 3850 group ....................................................................... 1-53 fig. 60 structure of interrupt request register 1 of 3850 group ........................................... 1-54 fig. 61 structure of interrupt control register 1 of 3850 group ............................................ 1-54
3850/3851 group users manual iii list of figures fig. 2.3.10 serial i/o connection examples (1) ....................................................................... 2-31 fig. 2.3.11 serial i/o connection examples (2) ....................................................................... 2-32 fig. 2.3.12 serial i/o transfer data format ............................................................................... 2-33 fig. 2.3.13 connection diagram ................................................................................................. 2-34 fig. 2.3.14 timing chart (using clock synchronous serial i/o) .............................................. 2-34 fig. 2.3.15 registers setting relevant to transmitting side ..................................................... 2-35 fig. 2.3.16 registers setting relevant to receiving side ......................................................... 2-36 fig. 2.3.17 control procedure of transmitting side .................................................................. 2-37 fig. 2.3.18 control procedure of receiving side ...................................................................... 2-38 fig. 2.3.19 connection diagram ................................................................................................. 2-39 fig. 2.3.20 timing chart .............................................................................................................. 2-39 fig. 2.3.21 registers setting relevant to serial i/o ................................................................. 2-40 fig. 2.3.22 setting of serial i/o transmission data ................................................................. 2-40 fig. 2.3.23 control procedure of serial i/o .............................................................................. 2-41 fig. 2.3.24 connection diagram ................................................................................................. 2-42 fig. 2.3.25 timing chart .............................................................................................................. 2-43 fig. 2.3.26 relevant registers setting ....................................................................................... 2-43 fig. 2.3.27 control procedure of master unit ........................................................................... 2-44 fig. 2.3.28 control procedure of slave unit ............................................................................. 2-45 fig. 2.3.29 connection diagram (communication using uart) ............................................ 2-46 fig. 2.3.30 timing chart (using uart) ..................................................................................... 2-46 fig. 2.3.31 registers setting relevant to transmitting side ..................................................... 2-48 fig. 2.3.32 registers setting relevant to receiving side ......................................................... 2-49 fig. 2.3.33 control procedure of transmitting side .................................................................. 2-50 fig. 2.3.34 control procedure of receiving side ...................................................................... 2-51 fig. 2.3.35 sequence of setting serial i/o control register again ......................................... 2-53 fig. 2.4.1 memory map of registers relevant to i 2 c-bus interface ...................................... 2-55 fig. 2.4.2 structure of i 2 c data shift register ........................................................................... 2-55 fig. 2.4.3 structure of i 2 c address register ............................................................................. 2-56 fig. 2.4.4 structure of i 2 c status register ................................................................................. 2-56 fig. 2.4.5 structure of i 2 c control register ............................................................................... 2-57 fig. 2.4.6 structure of i 2 c clock control register ..................................................................... 2-58 fig. 2.4.7 structure of i 2 c start/stop condition control register ..................................... 2-59 fig. 2.4.8 structure of interrupt request register 1 ................................................................. 2-59 fig. 2.4.9 structure of interrupt control register 1 .................................................................. 2-60 fig. 2.4.10 i 2 c-bus connection structure ................................................................................. 2-61 fig. 2.4.11 i 2 c-bus communication format example .............................................................. 2-62 fig. 2.4.12 restart condition of master reception .............................................................. 2-63 fig. 2.4.13 scl waveforms when synchronizing clocks ......................................................... 2-64 fig. 2.4.14 initial setting example using smbus communication ......................................... 2-66 fig. 2.4.15 read word protocol communication as smbus master device ....................... 2-67 fig. 2.4.16 transmission process of start condition and slave address ......................... 2-68 fig. 2.4.17 transmission process of command ....................................................................... 2-69 fig. 2.4.18 transmission process of restart condition and slave address + read bit . 2-70 fig. 2.4.19 reception process of lower data ........................................................................... 2-71 fig. 2.4.20 reception process of upper data .......................................................................... 2-72 fig. 2.4.21 generating of stop condition ............................................................................... 2-73 fig. 2.4.22 communication example as smbus slave device .............................................. 2-74 fig. 2.4.23 reception process of start condition and slave address .............................. 2-75 fig. 2.4.24 reception process of command ............................................................................. 2-76 fig. 2.4.25 reception process of restart condition and slave address + read bit ....... 2-77 fig. 2.4.26 transmission process of lower data ...................................................................... 2-78
iv 3850/3851 group users manual list of figures fig. 2.4.27 transmission process of upper data ..................................................................... 2-79 fig. 2.4.28 reception of stop condition ................................................................................. 2-80 fig. 2.5.1 memory map of registers relavant to pwm ........................................................... 2-85 fig. 2.5.2 structure of pwm control register ........................................................................... 2-85 fig. 2.5.3 structure of pwm prescaler ..................................................................................... 2-86 fig. 2.5.4 structure of pwm register ........................................................................................ 2-86 fig. 2.5.5 connection diagram ................................................................................................... 2-87 fig. 2.5.6 pwm output timing ..................................................................................................... 2-87 fig. 2.5.7 setting of related registers ....................................................................................... 2-88 fig. 2.5.8 pwm output ................................................................................................................ 2-88 fig. 2.5.9 control procedure ....................................................................................................... 2-89 fig. 2.6.1 memory map of registers relevant to a-d converter ............................................ 2-90 fig. 2.6.2 structure of a-d control register .............................................................................. 2-90 fig. 2.6.3 structure of a-d conversion register (high-order) ................................................. 2-91 fig. 2.6.4 structure of a-d conversion register (low-order) ................................................... 2-91 fig. 2.6.5 structure of interrupt request register 2 ................................................................. 2-92 fig. 2.6.6 structure of interrupt control register 2 .................................................................. 2-92 fig. 2.6.7 connection diagram ................................................................................................... 2-93 fig. 2.6.8 relevant registers setting ......................................................................................... 2-93 fig. 2.6.9 control procedure for 8-bit read .............................................................................. 2-94 fig. 2.6.10 control procedure for 10-bit read .......................................................................... 2-94 fig. 2.7.1 example of poweron reset circuit ............................................................................ 2-96 fig. 2.7.2 ram backup system .................................................................................................. 2-96 chapter 3 appendix fig. 3.1.1 circuit for measuring output switching characteristics (1) ..................................... 3-9 fig. 3.1.2 circuit for measuring output switching characteristics (2) ..................................... 3-9 fig. 3.1.3 timing chart ................................................................................................................ 3-10 fig. 3.1.4 timing diagram of multi-master i 2 c-bus ................................................................ 3-11 fig. 3.2.1 power source current characteristic examples (f(x in ) = 8mhz, in high-speed mode) ............................................................................................................................... ...... 3-12 fig. 3.2.2 power source current characteristic examples (f(x in ) = 8mhz, in middle-speed mode) ............................................................................................................................... ...... 3-12 fig. 3.2.3 power source current characteristic examples (f(x in ) = 4mhz, in high-speed mode) ............................................................................................................................... ...... 3-13 fig. 3.2.4 power source current characteristic examples (f(x in ) = 4mhz, in middle-speed mode) ............................................................................................................................... ...... 3-13 fig. 3.2.5 power source current characteristic examples (f(x cin ) = 32khz, in low-speed mode) ............................................................................................................................... ...... 3-14 fig. 3.2.6 standard characteristic examples of cmos output port at p-channel drive ..... 3-15 fig. 3.2.7 standard characteristic examples of cmos output port at n-channel drive ..... 3-15 fig. 3.2.8 standard characteristic examples of n-channel open-drain output port at n-channel drive ............................................................................................................................. 3- 16 fig. 3.2.9 standard characteristic examples of cmos large current output port at n-channel drive ............................................................................................................................. 3- 16 fig. 3.2.10 a-d conversion standard characteristics ............................................................... 3-17 fig. 3.3.1 sequence of switch the detection edge .................................................................. 3-18 fig. 3.3.2 sequence of check of interrupt request bit ............................................................ 3-18 fig. 3.3.3 sequence of setting serial i/o control register again ........................................... 3-20 fig. 3.3.4 ceramic resonator circuit .......................................................................................... 3-26 fig. 3.3.5 initialization of processor status register ................................................................ 3-27 fig. 3.3.6 sequence of plp instruction execution .................................................................. 3-27
3850/3851 group users manual v list of figures fig. 3.3.7 stack memory contents after php instruction execution ..................................... 3-27 fig. 3.3.8 interrupt routine .......................................................................................................... 3-28 fig. 3.3.9 status flag at decimal calculations .......................................................................... 3-28 fig. 3.3.10 programming and testing of one time prom version ...................................... 3-29 fig. 3.4.1 selection of packages ............................................................................................... 3-32 fig. 3.4.2 wiring for the reset pin ......................................................................................... 3-32 fig. 3.4.3 wiring for clock i/o pins ........................................................................................... 3-33 fig. 3.4.4 wiring for cnvss pin ............................................................................................... 3-33 fig. 3.4.5 wiring for the v pp pin of the one time prom and the eprom version ......... 3-34 fig. 3.4.6 bypass capacitor across the vss line and the vcc line ....................................... 3-34 fig. 3.4.7 analog signal line and a resistor and a capacitor ................................................ 3-35 fig. 3.4.8 wiring for a large current signal line ...................................................................... 3-35 fig. 3.4.9 wiring of reset pin ................................................................................................. 3-36 fig. 3.4.10 vss pattern on the underside of an oscillator ..................................................... 3-36 fig. 3.4.11 setup for i/o ports ................................................................................................... 3-37 fig. 3.4.12 watchdog timer by software ................................................................................... 3-38 fig. 3.5.1 structure of port pi (i=0, 1, 2, 3, 4) ....................................................................... 3-39 fig. 3.5.2 structure of port pi direction register(i=0, 1, 2, 3, 4) .......................................... 3-39 fig. 3.5.3 structure of transmit/receive buffer register ........................................................ 3-40 fig. 3.5.4 structure of serial i/o status register ..................................................................... 3-40 fig. 3.5.5 structure of serial i/o control register .................................................................... 3-41 fig. 3.5.6 structure of uart control register .......................................................................... 3-41 fig. 3.5.7 structure of baud rate generator ............................................................................. 3-42 fig. 3.5.8 structure of pwm control register ........................................................................... 3-42 fig. 3.5.9 structure of pwm prescaler ..................................................................................... 3-43 fig. 3.5.10 structure of pwm register ...................................................................................... 3-43 fig. 3.5.11 structure of prescaler 12, prescaler x, prescaler y .......................................... 3-44 fig. 3.5.12 structure of timer 1 ................................................................................................ 3-44 fig. 3.5.13 structure of timer 2, timer x, timer y ............................................................... 3-45 fig. 3.5.14 structure of timer count source selection register .............................................. 3-45 fig. 3.5.15 structure of timer xy mode register .................................................................... 3-46 fig. 3.5.16 structure of i 2 c data shift register ......................................................................... 3-47 fig. 3.5.17 structure of i 2 c address register ........................................................................... 3-47 fig. 3.5.18 structure of i 2 c status register .............................................................................. 3-48 fig. 3.5.19 structure of i 2 c control register ............................................................................. 3-48 fig. 3.5.20 structure of i 2 c clock control register ................................................................... 3-49 fig. 3.5.21 structure of i 2 c start/stop condition control register ................................... 3-50 fig. 3.5.22 structure of a-d control register ............................................................................ 3-50 fig. 3.5.23 structure of a-d conversion register(low-order) .................................................. 3-51 fig. 3.5.24 structure of a-d conversion register (high-order) ............................................... 3-51 fig. 3.5.25 structure of misrg ................................................................................................. 3-52 fig. 3.5.26 structure of watchdog timer control register ....................................................... 3-52 fig. 3.5.27 structure of interrupt edge selection register ...................................................... 3-53 fig. 3.5.28 structure of cpu mode register ............................................................................ 3-53 fig. 3.5.29 structure of interrupt request register 1 ............................................................... 3-54 fig. 3.5.30 structure of interrupt request register 2 ............................................................... 3-54 fig. 3.5.31 structure of interrupt control register 1 ................................................................ 3-55 fig. 3.5.32 structure of interrupt control register 2 ................................................................ 3-55 fig. 3.13.1 m38513m4-xxxfp/sp pin configuration ............................................................... 3-91
3850/3851 group users manual i list of tables list of tables chapter 1 hardware table 1 pin description ................................................................................................................. 1-4 table 2 push and pop instructions of accumulator or processor status register ................. 1-8 table 3 set and clear instructions of each bit of processor status register ......................... 1-9 table 4 i/o port function table ................................................................................................... 1-13 table 5 interrupt vector address and priority .......................................................................... 1-17 table 6 multi-master i 2 c-bus interface functions ................................................................... 1-25 table 7 set values of i 2 c clock control register and scl frequency .................................. 1-27 table 8 start condition generating timing table .................................................................. 1-31 table 9 stop condition generating timing table ..................................................................... 1-31 table 10 start condition/stop condition detecting conditions ............................................ 1-31 table 11 recommended set value to start/stop condition set bits (ssc4Cssc0) for each oscillation frequency .................................................................................................... 1-33 table 12 programming adapter .................................................................................................. 1-46 table 13 interrupt sources, vector addresses and interrupt priority ..................................... 1-47 table 14 change of a-d conversion register during a-d conversion .................................. 1-49 chapter 2 application table 2.1.1 handling of unused pins .......................................................................................... 2-3 table 2.2.1 cntr 0 / cntr 1 active edge switch bit function ................................................... 2-8 table 2.3.1 setting example of baud rate generator values and transfer bit rate values 2-47 table 2.4.1 set value of i 2 c clock control register and scl frequency .............................. 2-58 chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions (1) ................................................................ 3-3 table 3.1.3 recommended operating conditions (2) ................................................................ 3-4 table 3.1.4 electrical characteristics (1) ..................................................................................... 3-5 table 3.1.5 electrical characteristics (2) ................................................................................... 3-6 table 3.1.6 a-d converter characteristics .................................................................................. 3-6 table 3.1.7 timing requirements (1) ........................................................................................... 3-7 table 3.1.8 timing requirements (2) ........................................................................................... 3-7 table 3.1.9 switching requirements (1) ...................................................................................... 3-8 table 3.1.10 switching requirements (2) .................................................................................... 3-8 table 3.1.11 multi-master i 2 c-bus bus line characteristics .................................................. 3-11 table 3.3.1 programming adapters ........................................................................................... 3-29 table 3.3.2 prom programmer address setting ..................................................................... 3-30 table 3.5.1 cntr 0 / cntr 1 active edge switch bit function ................................................. 3-46 table 3.5.2 set value of i 2 c clock control register and scl frequency .............................. 3-49
chapter 1 chapter 1 hardware descripion features application pin configuration functional block pin description part numbering group expansion functional description notes on programming data required for mask orders data required for rom writing orders rom programming method functional descripion supplement
1-2 3850/3851 group users manual hardware description the 3851 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3851 group is designed for the household products and office automation equipment and includes serial i/o functions, 8-bit timer, a-d converter, and i 2 c-bus interface. features l basic machine-language instructions ...................................... 71 l minimum instruction execution time .................................. 0.5 m s (at 8 mhz oscillation frequency) l memory size rom ................................................................ 16 k to 24 kbytes ram ................................................................... 512 to 640 bytes l programmable input/output ports ............................................ 34 l interrupts ................................................. 16 sources, 16 vectors l timers ............................................................................. 8-bit 5 4 l serial i/o ....................... 8-bit 5 1(uart or clock-synchronized) l multi-master i 2 c-bus interface (option) ....................... 1 channel l pwm ............................................................................... 8-bit 5 1 l a-d converter ............................................... 10-bit 5 5 channels l watchdog timer ............................................................ 16-bit 5 1 l clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) pin configuration (top view) fig. 1 m38513m4-xxxfp/sp pin configuration l power source voltage in high-speed mode .................................................. 4.0 to 5.5 v (at 8 mhz oscillation frequency) in high-speed mode .................................................. 2.7 to 5.5 v (at 4 mhz oscillation frequency) in middle-speed mode............................................... 2.7 to 5.5 v (at 8 mhz oscillation frequency) in low-speed mode .................................................... 2.7 to 5.5 v (at 32 khz oscillation frequency) l power dissipation in high-speed mode .......................................................... 34 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................ 60 m w (at 32 khz oscillation frequency, at 3 v power source voltage) l operating temperature range.................................... C20 to 85c application office automation equipment, fa equipment, household products, consumer electronics, etc. p4 0 /cntr 1 p4 1 /int 0 p4 2 /int 1 p4 3 /int 2 av ss p4 4 /int 3 /pwm v ref v cc p3 1 /an 1 p3 2 /an 2 p0 0 p0 4 p0 5 p0 6 p0 7 p1 1 p1 2 p1 3 /(led 0 ) p1 4 /(led 1 ) p1 5 /(led 2 ) p1 0 p0 1 p0 2 p3 0 /an 0 p3 3 /an 3 p3 4 /an 4 p0 3 40 41 42 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 33 3 2 1 21 20 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 10 m38513m4-xxxfp m38513m4-xxxsp p1 6 /(led 3 ) p1 7 /(led 4 ) p2 7 /cntr 0 /s rdy p2 6 /s clk p2 5 /scl 2 /txd p2 4 /sda 2 /rxd p2 3 /scl 1 p2 2 /sda 1 cnv ss p2 1 /x cin p2 0 /x cout reset x in x out v ss package type : fp ........................... 42p2r-a (42-pin plastic-molded ssop) package type : sp ........................... 42p4b (42-pin shrink plastic-molded dip) description/features/application/pin configuration
3850/3851 group users manual hardware 1-3 functional block diagram fig. 2 functional block diagram functional block int 0 C cntr 0 cntr 1 v ref av ss r a m r o m c p u a x y s pc h pc l ps v ss 21 reset 18 v cc 1 15 cnv ss 23 x in 19 20 si/o(8) reset input clock generating circuit main-clock input main-clock output a-d converter (10) timer y( 8 ) timer x( 8 ) prescaler 12(8) prescaler x(8) prescaler y(8) timer 1( 8 ) timer 2( 8 ) sub-clock input x out x cin x cout sub-clock output watchdog timer reset p2(8) p3(5) i/o port p2 i/o port p3 p4(5) i/o port p4 i c int 3 4 6 8 5 7 39 41 38 40 42 9 11 13 17 10 12 14 16 p1(8) i/o port p1 22 24 26 28 23 25 27 29 p0(8) i/o port p0 30 31 32 3334 35 36 37 pwm (8) 2 x cin x cout functional block
1-4 3850/3851 group users manual hardware v cc , v ss pin description functions name pin ?apply voltage of 2.7 v C 5.5 v to vcc, and 0 v to vss. ?this pin controls the operation mode of the chip. ?normally connected to v ss . ?reset input pin for active l. ?input and output pins for the clock generating circuit. ?connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ?when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?p1 3 to p1 7 (5 bits) are enabled to output large current for led drive (m38513e4/m4). ?p1 0 to p1 7 (8 bits) are enabled to output large current for led drive (m38514e6/m6). power source table 1 pin description function except a port function ? sub-clock generating circuit i/o pins (connect a resonator) clock input clock output i/o port p0 i/o port p1 i/o port p2 cnv ss input cnv ss reset reset input x in x out p0 0 Cp0 7 p1 0 Cp1 7 p2 0 /x cout p2 1 /x cin p2 2 /sda 1 p2 3 /scl 1 p2 4 /sda 2 /rxd p2 5 /scl 2 /txd p2 6 /s clk p2 7 /cntr 0 / s rdy i/o port p3 i/o port p4 ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?p2 2 to p2 5 can be switched between cmos compat- ible input level or smbus input level in the i 2 c-bus interface function. ?p2 0 , p2 1 , p2 4 to p2 7 : cmos3-state output structure. ?p2 4 , p2 5 : n-channel open-drain structure in the i 2 c- bus interface function. ?p2 2 , p2 3 : n-channel open-drain structure. ?8-bit cmos i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ?8-bit cmos i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ? i 2 c-bus interface function pins ? i 2 c-bus interface function pin/ serial i/o function pins ? serial i/o function pin ? serial i/o function pin/ timer x function pin ? a-d converter input pin ? timer y function pin ? interrupt input pins ? interrupt input pin ? pwm output pin p3 0 /an 0 C p3 4 /an 4 p4 0 /cntr 1 p4 1 /int 0 C p4 3 /int 2 p4 4 /int 3 /pwm pin description
3850/3851 group users manual hardware 1-5 part numbering m3851 3 m 4 - xxx fp product name package type fp : 42p2r-a sp : 42p4b rom number omitted in the one time prom version shipped in blank. rom/prom size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m e : mask rom version : one time prom version ram size 0 1 2 3 4 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes ?: standard ?is omitted in the one time prom version shipped in blank. 9: 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes a b c d e f 5 6 7 8 9 : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes part numbering fig. 3 part numbering
1-6 3850/3851 group users manual hardware group expansion mitsubishi plans to expand the 3851 group as follows: memory type support for mask rom and one time prom versions. memory size rom size ............................................................ 16 k to 24 kbytes ram size .............................................................. 512 to 640 bytes packages 42p2r-a ............................................ 42-pin plastic molded ssop 42p4b ......................................... 42-pin shrink plastic-molded dip fig. 4 memory expansion plan memory expansion plan 48k rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 128 192 256 ram size (bytes) 384 512 640 768 896 1024 m38513e4fp/sp m38513m4-xxxfp/sp new production m38514e6fp/sp m38514m6-xxxfp/sp mass production group expansion
3850/3851 group users manual hardware 1-7 functional description central processing unit (cpu) the 3851 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 series software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. the central processing unit (cpu) has the six registers. accumulator (a) the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. index register x (x), index register y (y) both index register x and index register y are 8-bit registers. in the index addressing modes, the value of the operand is added to the contents of register x or register y and specifies the real address. when the t flag in the processor status register is set to 1, the value contained in index register x becomes the address for the sec- ond operand. stack pointer (s) the stack pointer is an 8-bit register used during sub-routine calls and interrupts. the stack is used to store the current address data and processor status when branching to subroutines or interrupt rou- tines. the lower eight bits of the stack address are determined by the con- tents of the stack pointer. the upper eight bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0, then the ram in the zero page is used as the stack area. if the stack page selection bit is 1, then ram in page 1 is used as the stack area. the stack page selection bit is located in the sfr area in the zero page. note that the initial value of the stack page selection bit var- ies with each microcomputer type. also some microcomputer types have no stack page selection bit and the upper eight bits of the stack address are fixed. the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 8. program counter (pc) the program counter is a 16-bit counter consisting of two 8-bit regis- ters pc h and pc l . it is used to indicate the address of the next in- struction to be executed. fig. 5 740 family cpu register structure b7 b0 x b7 b0 s b7 b0 y b7 b0 pc l processor status register (ps) carry flag b7 b0 b7 b0 a b15 pc h zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag program counter stack pointer index register y index register x accumulator c z i d b t v n functional description
1-8 3850/3851 group users manual hardware table 2 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call execute jsr on-going routine m (s) (pc h ) (s) (s ?1) m (s) (pc l ) execute rts (pc l ) m (s) (s) (s ?1) (s) (s + 1) (s) (s + 1) (pc h ) m (s) subroutine restore return address store return address on stack m (s) (ps) execute rti (ps) m (s) (s) (s ?1) (s) (s + 1) interrupt service routine restore contents of processor status register m (s) (pc h ) (s) (s ?1) m (s) (pc l ) (s) (s ?1) (pc l ) m (s) (s) (s + 1) (s) (s + 1) (pc h ) m (s) restore return address i flag ??to ?? fetch the jump vector store return address on stack store contents of processor status register on stack interrupt request (note) note : the condition to enable the interrupt interrupt enable bit is ? interrupt disable flag is ? functional description
3850/3851 group users manual hardware 1-9 processor status register (ps) the processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic opera- tion. branch operations can be performed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in deci- mal mode, the z, v, n flags are not valid. after reset, the interrupt disable (i) flag is set to 1, but all other flags are undefined. since the index x mode (t) and decimal mode (d) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. (2) zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0, and cleared if the result is anything other than 0. (3) interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1. when an interrupt occurs, this flag is automatically set to 1 to prevent other interrupts from interfering until the current interrupt is serviced. (4) decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0; decimal arithmetic is executed when it is 1. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. (5) break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1. the saved processor status is the only place where the break flag is ever set. (6) index x mode flag (t) when the t flag is 0, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. when the t flag is 1, direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and i/o, and i/o and i/o. in this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. the address of memory location 1 is specified by index register x, and the address of memory location 2 is specified by normal addressing modes. (7) overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. (8) negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 3 set and clear instructions of each bit of processor status register set instruction clear instruction c flag z flag i flag d flag b flag t flag v flag n flag sec clc _ _ sei cli sed cld _ _ set clt clv _ _ _ functional description
1-10 3850/3851 group users manual hardware [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, etc. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register cpu mode register ( cpum : address 003b 16 ) b7 b0 stack page selection bit 0 : 0 page 1 : 1 page not used (return ??when read) (do not write ??to this bit.) processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : not available 1 1 : port x c switch bit 0 : i/o port function (stop oscillating) 1 : x cin ? cout oscillating function main clock (x in ? out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bits b7 b6 0 0 : f = f(x in )/2 (high-speed mode) 0 1 : f = f(x in )/8 (middle-speed mode) 1 0 : f = f(x cin )/2 (low-speed mode) 1 1 : not available functional description
3850/3851 group users manual hardware 1-11 memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 0100 16 0000 16 0040 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 1536 2048 3072 4032 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 0c3f 16 0fff 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom 0440 16 sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram size (bytes) address xxxx 16 rom size (bytes) address yyyy 16 reserved rom area address zzzz 16 reserved area functional description
1-12 3850/3851 group users manual hardware fig. 9 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) transmit/receive buffer register (tb/rb) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) baud rate generator (brg) interrupt control register 2 (icon2) a-d conversion low-order register (adl) prescaler y (prey) timer y (ty) a-d control register (adcon) a-d conversion high-order register (adh) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) prescaler 12 (pre12) timer 2 (t2) prescaler x (prex) timer x (tx) timer 1 (t1) timer xy mode register (tm) i 2 c data shift register (s0) i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) misrg watchdog timer control register (wdtcon) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) timer count source selection register (tcss) reserved ] reserved ] reserved ] ] reserved : do not write ??to this address. reserved ] functional description
3850/3851 group users manual hardware 1-13 pin name input/output i/o structure non-port function ref.no. table 4 i/o port function related sfrs i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. port p0 port p1 port p3 input/output, individual bits cmos compatible input level cmos 3-state output sub-clock generating circuit cpu mode register (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) p0 0 Cp0 7 p1 0 Cp1 7 p2 0 /x cout p2 1 /x cin p2 2 /sda 1 p2 3 /scl 1 p2 4 /sda 2 /rxd p2 5 /scl 2 /txd port p2 p2 6 /s clk p2 7 /cntr 0 /s rdy p3 0 /an 0 p3 4 /an 4 p4 0 /cntr 1 p4 1 /int 0 p4 3 /int 2 p4 4 /int 3 /pwm port p4 cmos compatible input level cmos/smbus input level (when selecting i 2 c-bus interface function) n-channel open-drain output cmos compatible input level cmos/smbus input level (when selecting i 2 c-bus interface function) cmos 3-state output n-channel open-drain output (when selecting i 2 c-bus interface function) cmos compatible input level cmos 3-state output i 2 c-bus interface func- tion i/o i 2 c-bus interface func- tion i/o serial i/o function i/o serial i/o function i/o serial i/o function i/o timer x function i/o a-d conversion input i 2 c control register i 2 c control register serial i/o control register serial i/o control register serial i/o control register timer xy mode register a-d control register timer y function i/o external interrupt input external interrupt input pwm output timer xy mode register interrupt edge selection register interrupt edge selection register pwm control register (13) functional description
1-14 3850/3851 group users manual hardware fig. 10 port block diagram (1) (1) port p0, p1 direction register data bus port latch (2) port p2 0 port x c switch bit oscillator port p2 1 data bus port latch direction register port x c switch bit (3) port p2 1 port x c switch bit data bus port latch direction register sub-clock generating circuit input (4) port p2 2 data bus port latch direction register sda output i c-bus interface enable bit sda/scl pin selection bit sda input 2 (5) port p2 3 data bus port latch direction register scl output i c-bus interface enable bit sda/scl pin selection bit scl input 2 (6) port p2 4 data bus port latch direction register sda output serial i/o enable bit receive enable bit i c-bus interface enable bit sda/scl pin selection bit 2 sda input serial i/o input (7) port p2 5 data bus port latch direction register scl output i c bus interface enable bit sda/scl pin selection bit serial i/o enable bit transmit enable bit 2 scl input serial i/o output p-channel output disable bit (8) port p2 6 data bus port latch direction register serial clock output serial i/o mode selection bit serial i/o enable bit serial i/o enable bit serial i/o clock selection bit external clock input functional description
3850/3851 group users manual hardware 1-15 fig. 11 port block diagram (2) (10) port p3 0 ?3 4 direction register data bus port latch (11) port p4 0 cntr 1 interrupt input data bus port latch direction register (9) port p2 7 data bus port latch direction register timer output serial i/o enable bit s rdy output enable bit serial i/o mode selection bit cntr 0 interrupt input serial ready output a-d converter input analog input pin selection bit (12) port p4 1 ?4 3 direction register data bus port latch interrupt input pulse output mode timer output (13) port p4 4 pwm output data bus port latch direction register pwm output enable bit pulse output mode pulse output mode functional description
1-16 3850/3851 group users manual hardware interrupts interrupts occur by 16 sources among 16 sources: seven external, eight internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk in- struction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. n notes when the active edge of an external interrupt (int 0 Cint 3 , scl/ sda, cntr 0 , cntr 1 ) is set, the corresponding interrupt request bit may also be set. therefore, take the following sequence: 1. disable the interrupt 2. change the interrupt edge selection register (scl/sda interrupt pin polarity selection bit for scl/sda; the timer xy mode register for cntr 0 and cntr 1 ) 3. clear the interrupt request bit to 0 4. accept the interrupt. functional description
3850/3851 group users manual hardware 1-17 interrupt request generating conditions remarks interrupt source low fffc 16 high fffd 16 priority 1 table 5 interrupt vector addresses and priority notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 scl, sda int 1 int 2 int 3 i 2 c timer x timer y timer 1 timer 2 serial i/o reception serial i/o transmission cntr 0 cntr 1 a-d converter brk instruction at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at completion of data transfer at completion of serial i/o data reception at completion of serial i/o trans- fer shift or when transmission buffer is empty at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected valid when serial i/o is selected external interrupt (active edge selectable) stp release timer underflow external interrupt (active edge selectable) at detection of either rising or falling edge of scl or sda input at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at completion of a-d conversion at brk instruction execution external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) non-maskable software interrupt fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdc 16 ffdd 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 functional description
1-18 3850/3851 group users manual hardware fig. 12 interrupt control fig. 13 structure of interrupt-related registers (1) interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 interrupt edge selection register (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit scl/sda interrupt request bit int 1 interrupt request bit int 2 interrupt request bit int 3 interrupt request bit i 2 c interrupt request bit timer x interrupt request bit timer y interrupt request bit interrupt control register 1 int 0 interrupt enable bit scl/sda interrupt enable bit int 1 interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit i 2 c interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 timer 1 interrupt request bit timer 2 interrupt request bit serial i/o reception interrupt request bit serial i/o transmit interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit ad converter interrupt request bit not used (returns ??when read) (ireq2 : address 003d 16 ) interrupt control register 2 timer 1 interrupt enable bit timer 2 interrupt enable bit serial i/o reception interrupt enable bit serial i/o transmit interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit ad converter interrupt enable bit not used (returns ??when read) (do not write ??to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : no interrupt request issued 1 : interrupt request issued 0 : interrupts disabled 1 : interrupts enabled int 0 active edge selection bit int 1 active edge selection bit int 2 active edge selection bit int 3 active edge selection bit reserved(do not write ??to this bit) not used (returns ??when read) 0 : falling edge active 1 : rising edge active functional description
3850/3851 group users manual hardware 1-19 timers the 3851 group has four timers: timer x, timer y, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are count down. when the timer reaches 00 16 , an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1. timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. the out- put of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. timer x and timer y timer x and timer y can each select in one of four operating modes by setting the timer xy mode register. (1) timer mode the timer counts the count source selected by timer count source selection bit. (2) pulse output mode the timer counts the count source selected by timer count source selection bit. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge selection bit is 0, output begins at h. if it is 1, output starts at l. when using a timer in this mode, set the corresponding port p2 7 ( or port p4 0 ) direction register to out- put mode. (3) event counter mode operation in event counter mode is the same as in timer mode, ex- cept that the timer counts signals input through the cntr 0 or cntr 1 pin. when the cntr 0 (or cntr 1 ) active edge selection bit is 0, the rising edge of the cntr 0 (or cntr 1 ) pin is counted. when the cntr 0 (or cntr 1 ) active edge selection bit is 1, the falling edge of the cntr 0 (or cntr 1 ) pin is counted. (4) pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is 0, the timer counts the selected signals by the count source selection bit while the cntr 0 (or cntr 1 ) pin is at h. if the cntr 0 (or cntr 1 ) ac- tive edge selection bit is 1, the timer counts it while the cntr 0 (or cntr 1 ) pin is at l. the count can be stopped by setting 1 to the timer x (or timer y) count stop bit in any mode. the corresponding interrupt request bit is set each time a timer underflows. fig. 14 structure of timer xy mode register n note when switching the count source by the timer 12, x and y count source selection bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. therefore, select the timer count source before set the value to the prescaler and the timer. fig. 15 structure of timer count source selection register timer x count stop bit 0: count start 1: count stop timer xy mode register (tm : address 0023 16 ) timer y operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 1 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b7 cntr 0 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b0 timer x operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode b1b0 b5b4 timer y count stop bit 0: count start 1: count stop timer count source selection register (tcss : address 0028 16 ) b7 b0 timer x count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer y count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer 12 count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x cin ) not used (returns ??when read) functional description
1-20 3850/3851 group users manual hardware fig. 16 block diagram of timer x, timer y, timer 1, and timer 2 q q ? ? p2 7 /cntr 0 q q p4 0 /cntr 1 ? ? r r ? ? ? ? t t prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) to timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode to cntr 0 interrupt request bit pulse output mode port p2 7 latch port p2 7 direction register cntr 0 active edge selection bit timer x latch write pulse pulse output mode timer mode pulse output mode prescaler y latch (8) prescaler y (8) timer y latch (8) timer y (8) to timer y interrupt request bit toggle flip-flop timer y count stop bit to cntr 1 interrupt request bit pulse output mode port p4 0 latch port p4 0 direction register cntr 1 active edge selection bit timer y latch write pulse pulse output mode timer mode pulse output mode data bus data bus prescaler 12 latch (8) prescaler 12 (8) timer 1 latch (8) timer 1 (8) data bus timer 2 latch (8) timer 2 (8) to timer 2 interrupt request bit to timer 1 interrupt request bit cntr 0 active edge selection bit cntr 1 active edge selection bit pulse width measure- ment mode event counter mode f(x cin ) timer 12 count source selection bit f(x in )/16 f(x in )/2 timer y count source selection bit f(x in )/16 f(x in )/2 timer x count source selection bit f(x in )/16 functional description
3850/3851 group users manual hardware 1-21 serial i/o serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the serial i/o mode selection bit of the serial i/o control register (bit 6 of address 001a 16 ) to 1. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. fig. 17 block diagram of clock synchronous serial i/o fig. 18 operation of clock synchronous serial i/o function d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. receive enable signal s rdy 1/4 1/4 f/f p2 6 /s clk serial i/o status register serial i/o control register p2 7 /s rdy p2 4 /r x d p2 5 /t x d x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register functional description
1-22 3850/3851 group users manual hardware (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o mode selection bit (b6) of the serial i/o con- trol register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig.19 block diagram of uart serial i/o x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o control register p2 6 /s clk1 serial i/o status register p2 4 /r x d p2 5 /t x d functional description
3850/3851 group users manual hardware 1-23 fig. 20 operation of uart serial i/o function [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. [serial i/o status register (siosts)] 0019 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o status register are initialized to 0 at re- set, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. [serial i/o control register (siocon)] 001a 16 the serial i/o control register consists of eight control bits for the serial i/o function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p2 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. n note when using the serial i/o, clear the i 2 c-bus interface enable bit to 0 or the sda/scl pin selection bit to 0. tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?,? can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the serial i/o control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes serial output t x d serial input r x d receive buffer read signal functional description
1-24 3850/3851 group users manual hardware fig. 21 structure of serial i/o control registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns ??when read) serial i/o status register serial i/o control register b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy output enable bit (srdy) 0: p2 7 pin operates as ordinary i/o pin 1: p2 7 pin operates as s rdy output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p2 4 to p2 7 operate as ordinary i/o pins) 1: serial i/o enabled (pins p2 4 to p2 7 operate as serial i/o pins) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p2 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return ??when read) b0 (siosts : address 0019 16 ) (siocon : address 001a 16 ) (uartcon : address 001b 16 ) functional description
3850/3851 group users manual hardware 1-25 function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 6 multi-master i 2 c-bus interface functions item format communication mode system clock f = f(x in )/2 (high-speed mode) f = f(x in )/8 (middle-speed mode) multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchro- nous functions, is useful for the multi-master serial communications. figure 19 shows a block diagram of the multi-master i 2 c-bus in- terface and table 4 lists the multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address register, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register, the i 2 c start/stop condition control register and other control circuits. when using the multi-master i 2 c-bus interface, set 1 mhz or more to f . note: mitsubishi electric corporation assumes no responsibility for in- fringement of any third-partys rights or originating in the use of the connection control function between the i 2 c-bus interface and the ports scl 1 , scl 2 , sda 1 and sda 2 with the bit 6 of i 2 c control regis- ter (002e 16 ). fig. 22 block diagram of multi-master i 2 c-bus interface ] : purchase of mitsubishi electric corporations i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. scl clock frequency i 2 c address register b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit address comparator b7 i 2 c data shift register b0 data control circuit system clock ( f ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 s1 b7 b0 tiss 10bit sad als bc2 bc1 bc0 s1d bit counter bb circuit clock control circuit noise elimination circuit b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s 0 s2 s0d al circuit es0 sis i 2 c start/stop condition control register sip ssc4 ssc3 ssc2 ssc1 ssc0 i 2 c clock control register i 2 c status register s2d i 2 c clock control register s1d i c control register 2 serial data (s da ) serial clock (s cl ) tsel functional description
1-26 3850/3851 group users manual hardware [i 2 c data shift register (s0)] 002b 16 the i 2 c data shift register (s0 : address 002b 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. the minimum 2 machine cycles are required from the rising of the s cl clock until input to this register. the i 2 c data shift register is in a write enable status only when the i 2 c-bus interface enable bit (es0 bit : bit 3 of address 002e 16 ) of the i 2 c control register is 1. the bit counter is reset by a write in- struction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (address 002d 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled re- gardless of the es0 bit value. [i 2 c address register (s0d)] 002c 16 the i 2 c address register (address 002c 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the start condition is de- tected. ?bit 0: read/write bit (rwb) this is not used in the 7-bit addressing mode. in the 10-bit ad- dressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address reg- ister. the rwb bit is cleared to 0 automatically when the stop condi- tion is detected. ?bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address fig. 23 structure of i 2 c address register sad6 sad5 sad4 sad3 sad2 sad1 sad0 rwb slave address i 2 c address register (s0d: address 002c 16 ) read/write bit b7 b0 functional description
3850/3851 group users manual hardware 1-27 table 7 set values of i 2 c clock control register and scl frequency fig. 24 structure of i 2 c clock control register scl frequency (at f = 4 mhz, unit : khz) setting value of ccr4Cccr0 standard clock mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 setting disabled setting disabled setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (note 3) 166 C (note 2) C (note 2) [i 2 c clock control register (s2)] 002f 16 the i 2 c clock control register (address 002f 16 ) is used to set ack control, scl mode and scl frequency. ?bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. refer to table 5. ?bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the standard clock mode is selected. when the bit is set to 1, the high-speed clock mode is selected. when connecting the bus of the high-speed mode i 2 c bus stan- dard (maximum 400 kbits/s), use 8 mhz or more oscillation frequency f(x in ) and 2 division clock. ?bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is selected and sda goes to l at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is selected. the sda is held in the h status at the occurrence of an ack clock. however, when the slave address agree with the address data in the reception of address data at ack bit = 0, the sda is auto- matically made l (ack is returned). if there is a disagreement between the slave address and the address data, the sda is auto- matically made h (ack is not returned). ] ack clock: clock for acknowledgment ?bit 7: ack clock bit (ack) this bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. when this bit is set to 0, the no ack clock mode is selected. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is selected and the master generates an ack clock each completion of each 1-byte data transfer. the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (makes sda h) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transfer. if data is written during transfer, the i 2 c clock generator is reset, so that data cannot be transferred normally. ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 i 2 c clock control register (s2 : address 002f 16 ) b7 b0 s cl frequency control bits refer to table 5. s cl mode specification bit 0 : standard clock mode 1 : high-speed clock mode ack bit 0 : ack is returned. 1 : ack is not returned. ack clock bit 0 : no ack clock 1 : ack clock 500/ccr value (note 3) 1000/ccr value (note 3) 17.2 16.6 16.1 notes 1: duty of s cl clock output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at f = 4 mhz). h duration of the clock fluctuates from C4 to +2 machine cycles in the standard clock mode, and fluctuates from C2 to +2 machine cycles in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because l duration is extended instead of h duration reduction. these are value when s cl clock synchronization by the synchro- nous function is not performed. ccr value is the decimal notation value of the s cl frequency control bits ccr4 to ccr0. 2: each value of s cl frequency exceeds the limit at f = 4 mhz or more. when using these setting value, use f of 4 mhz or less. 3: the data formula of s cl frequency is described below: f /(8 5 ccr value) standard clock mode f /(4 5 ccr value) high-speed clock mode (ccr value 1 5) f /(2 5 ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of f frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the s cl frequency by set- ting the s cl frequency control bits ccr4 to ccr0. functional description
1-28 3850/3851 group users manual hardware fig. 26 structure of i 2 c control register [i 2 c control register (s1d)] 002e 16 the i 2 c control register (address 002e 16 ) controls data communi- cation format. ?bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c interrupt request signal occurs immediately after the number of count specified with these bits (ack clock is added to the number of count when ack clock is selected by ack clock bit (bit 7 of address 002f 16 )) have been transferred, and bc0 to bc2 are returned to 000 2 . also when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. ?bit 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c-bus interface. when this bit is set to 0, the use disable status is provided, so that the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when es0 = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (which are bits of the i 2 c status register at address 002d 16 ). ? writing data to the i 2 c data shift register (address 002b 16 ) is dis- abled. ?bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to i 2 c status register, bit 1) is received, transfer processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recognized. ?bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address regis- ter (address 002c 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, and all the bits of the i 2 c address register are compared with address data. ?bit 6: sda/scl pin selection bit this bit selects the input/output pins of scl and sda of the multi- master i 2 c-bus interface. ?bit 7: i 2 c-bus interface pin input level selection bit this bit selects the input level of the scl and sda pins of the multi-master i 2 c-bus interface. fig. 25 sda/scl pin selection bit scl sda multi-master i c-bus interface 2 tsel scl 1 /p2 3 scl 2 /txd/p2 5 sda 1 /p2 2 sda 2 /rxd/p2 4 tsel tsel tsel b7 tiss tsel 10 bit sad als es0 bc2 bc1 bc0 b0 sda/scl pin selection bit 0 : connect to ports p2 2 , p2 3 1 : connect to ports p2 4 , p2 5 i 2 c control register (s1d : address 002e 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 i 2 c-bus interface enable bit 0 : disabled 1 : enabled data format selection bit 0 : addressing format 1 : free data format addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format i 2 c-bus interface pin input level selection bit 0 : cmos input 1 : smbus input functional description
3850/3851 group users manual hardware 1-29 ?bit 4: scl pin low hold bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the pin bit changes from 1 to 0. at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 25 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions: ? executing a write instruction to the i 2 c data shift register (ad- dress 002b 16 ). (this is the only condition which the prohibition of the internal clock is released and data can be communicated ex- cept for the start condition detection.) ? when the es0 bit is 0 ? at reset ? when writing 1 to the pin bit by software the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately af- ter completion of slave address agreement or general call address reception ? in the slave reception mode, with als = 1 and immediately af- ter completion of address data reception ?bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. the bb flag is set/reset by the scl, sda pins input signal regardless of master/slave. this flag is set to 1 by detecting the start condition, and is set to 0 by detecting the stop condition. the condition of these detecting is set by the start/stop condition setting bits (ssc4Cssc0) of the i 2 c start/stop condition control register (address 0030 16 ). when the es0 bit of the i 2 c control register (address 002e 16 ) is 0 or reset, the bb flag is set to 0. for the writing function to the bb flag, refer to the sections start condition generating method and stop condition gen- erating method described later. [i 2 c status register (s1)] 002d 16 the i 2 c status register (address 002d 16 ) controls the i 2 c-bus in- terface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. set 0000 2 to the low-order 4 bits, because these bits become the reserved bits at writing. ?bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 002b 16 ). ?bit 1: general call detecting flag (ad0) when the als bit is 0, this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives con- trol data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition, or reset. ] general call: the master transmits the general call address 00 16 to all slaves. ?bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data when the als bit is 0. in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions: ? the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-or- der 7 bits of the i 2 c address register (address 002c 16 ). ? a general call is received. in the slave receive mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition: ? when the address data is compared with the i 2 c address reg- ister (8 bits consisting of slave address and rbw bit), the first bytes agree. a this bit is set to 0 by executing a write instruction to the i 2 c data shift register (address 002b 16 ) when es0 is set to 1 or reset. ?bit 3: arbitration lost ] detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitration was lost is completed, the mst bit is set to 0. the arbitration lost can be detected only in the master transmission mode. when ar- bitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. ] arbitration lost : the status in which communication as a master is dis- abled. functional description
1-30 3850/3851 group users manual hardware fig. 28 interrupt request signal generating timing fig. 27 structure of i 2 c status register ?bit 6: communication mode specification bit (transfer direc- tion specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a transmitting device is received. when the bit is 1, the transmis- sion mode is selected and address data and control data are output onto the sda in synchronization with the clock generated on the s cl . this bit is set/reset by software and hardware. about set/reset by hardware is described below. this bit is set to 1 by hardware when all the following conditions are satisfied: ? when als is 0 ? in the slave reception mode or the slave transmission mode ? when the r/w bit reception is 1 this bit is set to 0 in one of the following conditions: ? when arbitration lost is detected. ? when a stop condition is detected. ? when writing 1 to this bit by software is invalid by the start condition duplication preventing function (note) . ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset ?bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for data communi- cation are generated on the scl. this bit is set to 0 in one of the following conditions. ? immediately after completion of 1-byte data transfer when arbi- tration lost is detected ? when a stop condition is detected. ? writing 1 to this bit by software is invalid by the start condi- tion duplication preventing function (note) . ? at reset note: start condition duplication preventing function the mst, trx, and bb bits is set to 1 at the same time after con- firming that the bb flag is 0 in the procedure of a start condition occurrence. however, when a start condition by another master device occurs and the bb flag is set to 1 immediately after the con- tents of the bb flag is confirmed, the start condition duplication preventing function makes the writing to the mst and trx bits in- valid. the duplication preventing function becomes valid from the rising of the bb flag to reception completion of slave address. s cl pin iicirq b7 mst b0 i 2 c status register (s1 : address 002d 16 ) last receive bit (note) 0 : last bit = ?? 1 : last bit = ?? general call detecting flag (note) 0 : no general call detected 1 : general call detected slave address comparison flag (note) 0 : address disagreement 1 : address agreement arbitration lost detecting flag (note) 0 : not detected 1 : detected scl pin low hold bit 0 : scl pin low hold 1 : scl pin low release bus busy flag 0 : bus free 1 : bus busy communication mode specification bits 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode trx bb pin al aas ad0 lrb note: these bits and flags can be read out, but cannot be written. write ??to these bits at writing. functional description
3850/3851 group users manual hardware 1-31 fig. 31 start/stop condition detecting timing diagram start/stop condition detecting operation the start/stop condition detection operations are shown in figures 28, 29, and table 8. the start/stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the s cl and s da pins satisfy three conditions: s cl re- lease time, setup time, and hold time (see table 8). the bb flag is set to 1 by detecting the start condition and is reset to 0 by detecting the stop condition. the bb flag set/reset timing is different in the standard clock mode and the high-speed clock mode. refer to table 8, the bb flag set/ reset time. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq occurs to the cpu. start condition generating method when writing 1 to the mst, trx, and bb bits of the i 2 c status register (address 002d 16 ) at the same time after writing the slave address to the i 2 c data shift register (address 002b 16 ) with the condition in which the es0 bit of the i 2 c control register (address 002e 16 ) is 1 and the bb flag is 0, a start condition occurs. after that, the bit counter becomes 000 2 and an s cl for 1 byte is output. the start condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 26, the start condition generating timing diagram, and table 6, the start condition generating timing table. stop condition generating method when the es0 bit of the i 2 c control register (address 002e 16 ) is 1, write 1 to the mst and trx bits, and write 0 to the bb bit of the i 2 c status register (address 002d 16 ) simultaneously. then a stop condition occurs. the stop condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 27, the stop condition generating timing diagram, and table 7, the stop condition generating timing table. fig. 29 start condition generating timing diagram fig. 30 stop condition generating timing diagram table 9 stop condition generating timing table item setup time hold time standard clock mode 5.0 m s (20 cycles) 4.5 m s (18 cycles) note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. high-speed clock mode 3.0 m s (12 cycles) 2.5 m s (10 cycles) table 8 start condition generating timing table item setup time hold time standard clock mode 5.0 m s (20 cycles) 5.0 m s (20 cycles) note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. high-speed clock mode 2.5 m s (10 cycles) 2.5 m s (10 cycles) table 10 start condition/stop condition detecting conditions note: unit : cycle number of system clock f ssc value is the decimal notation value of the start/stop condi- tion set bits ssc4 to ssc0. do not set 0 or an odd number to ssc value. the value in parentheses is an example when the i 2 c start/ stop condition control register is set to 18 16 at f = 4 mhz. fig. 32 stop condition detecting timing diagram s cl release time standard clock mode high-speed clock mode 4 cycles (1.0 m s) 2 cycles (1.0 m s) 2 cycles (0.5 m s) 3.5 cycles (0.875 m s) scc value + 1 2 scc value + 1 2 scc value C1 2 setup time hold time bb flag set/ reset time scc value + 1 cycle (6.25 m s) cycle < 4.0 m s (3.125 m s) cycle < 4.0 m s (3.125 m s) + 2 cycles (3.375 m s) i 2 c status register write signal hold time setup time s cl s da i 2 c status register write signal hold time setup time s cl s da hold time setup time s cl s da bb flag s cl release time bb flag reset time hold time setup time s cl s da bb flag s cl release time bb flag reset time functional description
1-32 3850/3851 group users manual hardware [i 2 c start/stop condition control register (s2d)] 0030 16 the i 2 c start/stop condition control register (address 0030 16 ) controls start/stop condition detection. ?bits 0 to 4: start/stop condition set bit (ssc4Cssc0) scl release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(x in ) because these time are measured by the internal system clock. accordingly, set the proper value to the start/stop condition set bits (ssc4 to ssc0) in considered of the system clock frequency. refer to table 8. do not set 00000 2 or an odd number to the start/stop condi- tion set bit (ssc4 to ssc0). refer to table 9, the recommended set value to start/stop condition set bits (ssc4Cssc0) for each oscillation frequency. ?bit 5: scl/sda interrupt pin polarity selection bit (sip) an interrupt can occur when detecting the falling or rising edge of the scl or sda pin. this bit selects the polarity of the scl or sda pin interrupt pin. ?bit 6: scl/sda interrupt pin selection bit (sis) this bit selects the pin of which interrupt becomes valid between the scl pin and the sda pin. note: when changing the setting of the s cl /s da interrupt pin polarity se- lection bit, the s cl /s da interrupt pin selection bit, or the i 2 c-bus interface enable bit es0, the s cl /s da interrupt request bit may be set. when selecting the s cl /s da interrupt source, disable the inter- rupt before the s cl /s da interrupt pin polarity selection bit, the s cl / s da interrupt pin selection bit, or the i 2 c-bus interface enable bit es0 is set. reset the request bit to 0 after setting these bits, and enable the interrupt. address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective address communication formats are described below. 7-bit addressing format to adapt the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 002e 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 002c 16 ). at the time of this comparison, address com- parison of the rwb bit of the i 2 c address register (address 002c 16 ) is not performed. for the data transmission format when the 7-bit addressing format is selected, refer to figure 31, (1) and (2). 10-bit addressing format to adapt the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 002e 16 ) to 1. an address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the i 2 c address register (address 002c 16 ). at the time of this comparison, an address comparison between the rwb bit of the i 2 c address register (address 002c 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the rwb bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is pro- cessed as an address data bit. when the first-byte address data agree with the slave address, the aas bit of the i 2 c status register (address 002d 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 002b 16 ), perform an address com- parison between the second-byte data and the slave address by software. when the address data of the 2 bytes agree with the slave address, set the rbw bit of the i 2 c address register (address 002c 16 ) to 1 by software. this processing can make the 7-bit slave address and r/w data agree, which are re- ceived after a restart condition is detected, with the value of the i 2 c address register (address 002c 16 ). for the data trans- mission format when the 10-bit addressing format is selected, refer to figure 31, (3) and (4). functional description
3850/3851 group users manual hardware 1-33 start/stop condition control register oscillation frequency f(x in ) (mhz) fig. 34 address data communication format fig. 33 structure of i 2 c start/stop condition control register note: do not set an odd number to the start/stop condition set bit (ssc4 to ssc0). table 11 recommended set value to start/stop condition set bits (ssc4Cssc0) for each oscillation frequency main clock divide ratio system clock f (mhz) scl release time ( m s) setup time ( m s) hold time ( m s) 8 8 4 2 2 8 2 2 xxx11010 xxx11000 xxx00100 xxx01100 xxx01010 xxx00100 3.375 m s (13.5 cycles) 3.125 m s (12.5 cycles) 2.5 m s (2.5 cycles) 3.25 m s (6.5 cycles) 2.75 m s (5.5 cycles) 2.5 m s (2.5 cycles) 6.75 m s (27 cycles) 6.25 m s (25 cycles) 5.0 m s (5 cycles) 6.5 m s (13 cycles) 5.5 m s (11 cycles) 5.0 m s (5 cycles) 3.375 m s (13.5 cycles) 3.125 m s (12.5 cycles) 2.5 m s (2.5 cycles) 3.25 m s (6.5 cycles) 2.75 m s (5.5 cycles) 2.5 m s (2.5 cycles) 4 1 2 1 b7 b0 i 2 c start/stop condition control register start/stop condition set bit s cl /s da interrupt pin polarity selection bit 0 : falling edge active 1 : rising edge active s cl /s da interrupt pin selection bit 0 : s da valid 1 : s cl valid reserved do not write ??to this bit. sis sip ssc4 ssc3 ssc2 ssc1 ssc0 (s2d : address 0030 16 ) s slave address r/w a data a/a p a data 7 bits ? 1 to 8 bits 1 to 8 bits (1) a master-transmitter transnmits data to a slave-receiver s slave address r/w a data a p a data 7 bits ? 1 to 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitter 7 bits ? 8 bits (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address 1 to 8 bits 1 to 8 bits s r/w a slave address 1st 7 bits slave address 2nd bytes a a data data p a/a 7 bits ? 8 bits (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s : start condition a : ack bit sr : restart condition p : stop condition r/w : read/write bit 7 bits ? 1 to 8 bits 1 to 8 bits s r/w a slave address 1st 7 bits slave address 2nd bytes a sr slave address 1st 7 bits r/w a data data p a : master to slave : slave to master a functional description
1-34 3850/3851 group users manual hardware example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 002c 16 ) and 0 into the rwb bit. set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 002f 16 ). a set 00 16 in the i 2 c status register (address 002d 16 ) so that transmission/reception mode can become initializing condition. ? set a communication enable status by setting 08 16 in the i 2 c control register (address 002e 16 ). ? confirm the bus free condition by the bb flag of the i 2 c status register (address 002d 16 ). ? set the address data of the destination of transmission in the high-order 7 bits of the i 2 c data shift register (address 002b 16 ) and set 0 in the least significant bit. ? set f0 16 in the i 2 c status register (address 002d 16 ) to gener- ate a start condition. at this time, an scl for 1 byte and an ack clock automatically occur. ? set transmit data in the i 2 c data shift register (address 002b 16 ). at this time, an scl and an ack clock automatically occur. when transmitting control data of more than 1 byte, repeat step ? . set d0 16 in the i 2 c status register (address 002d 16 ) to gener- ate a stop condition if ack is not returned from slave reception side or transmission ends. example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode and using the addressing format is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 002c 16 ) and 0 in the rwb bit. set the no ack clock mode and scl = 400 khz by setting 65 16 in the i 2 c clock control register (address 002f 16 ). a set 00 16 in the i 2 c status register (address 002d 16 ) so that transmission/reception mode can become initializing condition. ? set a communication enable status by setting 08 16 in the i 2 c control register (address 002e 16 ). ? when a start condition is received, an address comparison is performed. ? ?when all transmitted addresses are 0 (general call): ad0 of the i 2 c status register (address 002d 16 ) is set to 1 and an interrupt request signal occurs. ? when the transmitted addresses agree with the address set in : ass of the i 2 c status register (address 002d 16 ) is set to 1 and an interrupt request signal occurs. ? in the cases other than the above ad0 and aas of the i 2 c sta- tus register (address 002d 16 ) are set to 0 and no interrupt request signal occurs. ? set dummy data in the i 2 c data shift register (address 002b 16 ). ? when receiving control data of more than 1 byte, repeat step ? . when a stop condition is detected, the communication ends. functional description
3850/3851 group users manual hardware 1-35 (2) start condition generating procedure using multi-master 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 5. : : lda (taking out of slave address value) sei (interrupt disabled) bbs 5, s1, busbusy (bb flag confirming and branch pro- cess) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) : : busbusy: cli (interrupt enabled) : : 2. use branch on bit set of bbs 5, $002d, C for the bb flag confirming and branch process. 3. use sta $2b, stx $2b or sty $2b of the zero page ad- dressing instruction for writing the slave address value to the i 2 c data shift register. 4. execute the branch instruction of above 2 and the store instruc- tion of above 3 continuously shown the above procedure example. 5. disable interrupts during the following three process steps: ? bb flag confirming ? writing of slave address value ? trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. (3) restart condition generating procedure 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 4.) execute the following procedure when the pin bit is 0. : : ldm #$00, s1 (select slave receive mode) lda (t aking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 ( trigger of restart condition generating ) cli (interrupt enabled) : : 2. select the slave receive mode when the pin bit is 0. do not write 1 to the pin bit. neither 0 nor 1 is specified for the writing to the bb bit. the trx bit becomes 0 and the s da pin is released. 3. the s cl pin is released by writing the slave address value to the i 2 c data shift register. 4. disable interrupts during the following two process steps: ? writing of slave address value ? trigger of restart condition generating (4) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simulta- neously. it is because it may enter the state that the s cl pin is released and the s da pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to 0 from 1 simultaneously when the pin bit is 1. it is because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c sta- tus register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem. n precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction the precautions when the read-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ?i 2 c data shift register (s0: address 002b 16 ) when executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended. ?i 2 c address register (s0d: address 002c 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the stop condition, data may become a value not intended. it is because h/w changes the read/write bit (rbw) at the above timing. ?i 2 c status register (s1: address 002d 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by h/w. ?i 2 c control register (s1d: address 002e 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the start condition or at completing the byte transfer, data may become a value not intended. because h/w changes the bit counter (bc0-bc2) at the above timing. ?i 2 c clock control register (s2: address 002f 16 ) the read-modify-write instruction can be executed for this regis- ter. ?i 2 c start/stop condition control register (s2d: address 0030 16 ) the read-modify-write instruction can be executed for this regis- ter. functional description
1-36 3850/3851 group users manual hardware pulse width modulation (pwm) the 3851 group has a pwm function with an 8-bit resolution, based on a signal that is the clock input x in or that clock input di- vided by 2. data setting the pwm output pin also functions as port p4 4 . set the pwm pe- riod by the pwm prescaler, and set the h term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 5 (n+1) / f(x in ) = 31.875 5 (n+1) m s (when f(x in ) = 8 mhz, count source is f(x in )) output pulse h term = pwm period 5 m / 255 = 0.125 5 (n+1) 5 m m s (when f(x in ) = 8 mhz, count source is f(x in )) fig. 35 timing of pwm period fig. 36 block diagram of pwm function 31.875 5 m 5 (n+1) 255 m s t = [31.875 5 (n+1)] m s pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm period (when f(x in ) = 8 mhz, count source is f(x in )) pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to 1, operation starts by initializing the pwm output circuit, and pulses are output starting at an h. if the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. data bus count source selection bit ? ? pwm prescaler pre-latch pwm register pre-latch pwm prescaler latch pwm register latch transfer control circuit pwm register 1/2 x in port p4 4 latch pwm enable bit port p4 4 pwm prescaler functional description
3850/3851 group users manual hardware 1-37 fig. 37 structure of pwm control register fig. 38 pwm output timing when pwm register or pwm prescaler is changed pwm control register (pwmcon : address 001d 16 ) pwm function enable bit count source selection bit not used (return ??when read) b7 b0 0: pwm disabled 1: pwm enabled 0: f(x in ) 1: f(x in )/2 abc b t c t2 = pwm output pwm register write signal pwm prescaler write signal (changes ??term from ??to ??) (changes pwm period from ??to ?2?) when the contents of the pwm register or pwm prescaler have changed, the pwm output will change from the next period after the change. t t t2 functional description n note the pwm starts after the pwm enable bit is set to enable and l level is output from the pwm pin. the length of this l level output is as follows: sec (count source selection bit = 0, where n is the value set in the prescaler) sec (count source selection bit = 1, where n is the value set in the prescaler) n+1 2 ? f(x in ) n+1 f(x in )
1-38 3850/3851 group users manual hardware a-d converter [a-d conversion registers (adl, adh)] 0035 16 , 0036 16 the a-d conversion registers are read-only registers that store the result of an a-d conversion. do not read these registers during an a-d conversion [ad control register (adcon)] 0034 16 the ad control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 4 indicates the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion and changes to 1 when an a-d conversion ends. writing 0 to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref into 1024 and outputs the divided voltages. channel selector the channel selector selects one of ports p3 0 /an 0 to p3 4 /an 4 and inputs the voltage to the comparator. comparator and control circuit the comparator and control circuit compare an analog input volt- age with the comparison voltage, and the result is stored in the a-d conversion registers. when an a-d conversion is completed, the control circuit sets the a-d conversion completion bit and the a-d interrupt request bit to 1. note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a-d conversion. the m38514e6/m6 can operate at even low-speed mode, be- cause of the a-d converter of the m38514e6/m6 has a built-in self-oscillation circuit. fig. 39 structure of ad control register fig. 40 structure of a-d conversion registers ad control register (adcon : address 0034 16 ) analog input pin selection bits 0 0 0: p3 0 /an 0 0 0 1: p3 1 /an 1 0 1 0: p3 2 /an 2 0 1 1: p3 3 /an 3 1 0 0: p3 4 /an 4 not used (returns ??when read) a-d conversion completion bit 0: conversion in progress 1: conversion completed not used (returns ??when read) b7 b0 b2 b1 b0 10-bit reading (read address 0036 16 before 0035 16 ) (address 0036 16 ) (address 0035 16 ) 8-bit reading (read only address 0035 16 ) (address 0035 16 ) b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 b9 b7 b0 note : the high-order 6 bits of address 0036 16 become ? at reading. b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 channel selector a-d control circuit a-d conversion low-order register resistor ladder v ref av ss comparator a-d conversion interrupt request b7 b0 3 10 p3 0 /an 0 p3 1 /an 1 p3 2 /an 2 p3 3 /an 3 p3 4 /an 4 data bus ad control register a-d conversion high-order register (address 0034 16 ) (address 0036 16 ) (address 0035 16 ) fig. 41 block diagram of a-d converter functional description
3850/3851 group users manual hardware 1-39 watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 0039 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16 ) and an internal reset occurs at an underflow of the watch- dog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. when the watchdog timer control reg- ister (address 0039 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watch- dog timer h count source selection bit are read. l initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0039 16 ), each watchdog timer h and l is set to ff 16 . fig. 43 structure of watchdog timer control register l watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 0039 16 ) per- mits selecting a watchdog timer h count source. when this bit is set to 0, the count source becomes the underflow signal of watchdog timer l. the detection time is set to 131.072 ms at f(x in ) = 8 mhz frequency and 32.768 s at f(x cin ) = 32 khz frequency. when this bit is set to 1, the count source becomes the signal divided by 16 for f(x in ) (or f(x cin )). the detection time in this case is set to 512 m s at f(x in ) = 8 mhz frequency and 128 ms at f(x cin ) = 32 khz frequency. this bit is cleared to 0 after resetting. l operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 0039 16 ) per- mits disabling the stp instruction when the watchdog timer is in operation. when this bit is 0, the stp instruction is enabled. when this bit is 1, the stp instruction is disabled, once the stp instruction is executed, an internal reset occurs. when this bit is set to 1, it cannot be rewritten to 0 by program. this bit is cleared to 0 after resetting. fig. 42 block diagram of watchdog timer x in data bus x cin ?0 ?0 ?1 main clock division ratio selection bits (note) ? ? 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ?f 16 ?is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. stp instruction ?f 16 ?is set when watchdog timer control register is written to. b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 0039 16 ) b7 functional description
1-40 3850/3851 group users manual hardware reset circuit to reset the microcomputer, reset pin must be held at an "l" level for 2 m s or more. then the reset pin is returned to an "h" level (the power source voltage must be between 2.7 v and 5.5 v, and the oscillation must be stable), reset is released. after the re- set is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.54 v for v cc of 2.7 v. fig. 45 reset sequence fig. 44 reset circuit example (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.7 v reset data f address sync x in : 8 to 13 clock cycles x in ? ? ? ? ? fffc fffd ad h , l ? ? ? ? ? ad l ad h 1: the frequency relation of f(x in ) and f( f ) is f(x in ) = 2 f( f ). 2: the question marks (?) indicate an undefined state that depends on the previous state. 3: all signals except x in and reset are internals. reset address from the vector table. notes reset out functional description
3850/3851 group users manual hardware 1-41 fig. 46 internal status at reset port p0 direction register (p0d) port p1 direction register (p1d) port p2 direction register (p2d) port p3 direction register (p3d) port p4 direction register (p4d) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) pwm control register (pwmcon) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) timer count source select register i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) ad control register (adcon) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) processor status register program counter (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) note : x indicates not fixed . address register contents 0001 16 0003 16 0005 16 0007 16 0009 16 0019 16 001a 16 001b 16 001d 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 002c 16 002d 16 002e 16 002f 16 0030 16 0034 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 (ps) (pc h ) (pc l ) 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 01 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0001000x 0 00xxxxx 10000000 11100000 1 01001 0 0 xx xx xx x 00010000 00111111 0 fffd 16 contents fffc 16 contents functional description
1-42 3850/3851 group users manual hardware clock generating circuit the 3851 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock f is the frequency of x in divided by 8. after re- set, this mode is selected. (2) high-speed mode the internal clock f is half the frequency of x in . (3) low-speed mode the internal clock f is half the frequency of x cin . n note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub-clock to stabilize, especially immediately af- ter power on and at returning from the stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3?f(x cin ). (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted (by setting the main clock stop bit to 0), set sufficient time for oscillation to stabilize. the sub-clock x cin -x cout oscillating circuit can not directly input clocks that are generated externally. accordingly, make sure to cause an external resonator to oscillate. oscillation control (1) stop mode if the stp instruction is executed, the internal clock f stops at an h level, and x in and x cin oscillation stops. when the oscillation stabilizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. either x in or x cin divided by 16 is input to the prescaler 12 as count source. oscillator restarts when an external interrupt is re- ceived, but the internal clock f is not supplied to the cpu (remains at h) until timer 1 underflows. the internal clock f is supplied for the first time, when timer 1 underflows. this ensures time for the clock oscillation using the ceramic resonators to be stabilized. when the oscillator is restarted by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not fig. 47 ceramic resonator circuit fig. 48 external clock input circuit x cin x cout x in x out c in c out c cin c cout rf rd x cin x cout x in x out c cin c cout rf rd open external oscillation circuit vcc vss be generated. (2) wait mode if the wit instruction is executed, the internal clock f stops at an h level, but the oscillator does not stop. the internal clock f re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that the interrupts will be received to release the stp or wit state, their interrupt enable bits must be set to 1 before ex- ecuting of the stp or wit instruction. when releasing the stp state, the prescaler 12 and timer 1 will start counting the clock xin divided by 16. accordingly, set the timer 1 interrupt enable bit to 0 before executing the stp instruc- tion. n note when using the oscillation stabilizing time set after stp instruction released bit set to 1, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. functional description
3850/3851 group users manual hardware 1-43 fig. 50 system clock generating circuit block diagram (single-chip mode) wit instruction stp instruction timing f (internal clock) s r q stp instruction s r q main clock stop bit s r q 1/2 1/4 x in x out x cout x cin interrupt request reset interrupt disable flag l 1/2 port x c switch bit ? ? low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (note 1) notes 1: any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. when low-speed mode is selected, set port xc switch bit (b1) to ?? 2: when the oscillation stabilizing time set after stp instruction released bit is ?? main clock division ratio selection bits (note 1) ff 16 01 16 prescaler 12 timer 1 reset or stp instruction (note 2) functional description misrg (misrg : address 0038 16 ) oscillation stabilizing time set after stp instruction released bit middle-speed mode automatic switch set bit middle-speed mode automatic switch wait time set bit middle-speed mode automatic switch start bit (depending on program) not used (return ??when read) b7 b0 0: automatically set 01 16 ?to timer 1, ?f 16 ?to prescaler 12 1: automatically set nothing 0: not set automatically 1: automatic switching enable 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles 0: invalid 1: automatic switch start fig. 49 structure of misrg middle-speed mode automatic switch set bit by setting the middle-speed mode automatic switch set bit to 1 while operating in the low-speed mode, x in oscillation automati- cally starts and the mode is automatically switched to the middle-speed mode when defecting a rising/falling edge of the s cl or s da pin. the middle-speed automatic switch wait time set bit can select the switch timing from the low-speed to the middle- speed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5 machine cycles in the low-speed mode. select it according to os- cillation start characteristics of used x in oscillator. the middle-speed mode automatic switch start bit is used to auto- matically make to x in oscillation start and switch to the middle-speed mode by setting this bit to 1 while operating in the low-speed mode.
1-44 3850/3851 group users manual hardware fig. 51 state transitions of system clock cm 4 : port xc switch bit 0 : i/o port function (stop oscillating) 1 : x cin -x cout oscillating function cm 5 : main clock (x in - x out ) stop bit 0 : oscillating 1 : stopped cm 7 , cm 6 : main clock division ratio selection bit b7 b6 0 0 : f = f(x in )/2 ( high-speed mode) 0 1 : f = f(x in )/8 (middle-speed mode) 1 0 : f = f(x cin )/2 (low-speed mode) 1 1 : not available notes reset cm 4 1 ?? 0 cm 4 0 ?? 1 cm 6 1 ?? 0 cm 4 1 ?? 0 cm 6 1 ?? 0 cm 7 1 ?? 0 cm 4 1 ?? 0 cm 5 1 ?? 0 cm 6 1 ?? 0 cm 6 1 ?? 0 cpu mode register b7 b4 cm 7 0 ?? 1 cm 6 1 ?? 0 (cpum : address 003b 16 ) cm 7 =0 cm 6 =1 cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) middle-speed mode (f( f )=1 mhz) cm 7 =0 cm 6 =1 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) middle-speed mode (f( f )=1 mhz) cm 7 =0 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) high-speed mode (f( f )=4 mhz) cm 7 =1 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode (f( f )=16 khz) cm 7 =1 cm 6 =0 cm 5 =1(8 mhz stopped) cm 4 =1(32 khz oscillating) low-speed mode (f( f )=16 khz) cm 7 =0 cm 6 =0 cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) high-speed mode (f( f )=4 mhz) 1 : switch the mode by the allows shown between the mode blocks. (do not switch between the modes directly without an allow.) 2 : the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mo de is ended. 3 : timer operates in the wait mode. 4 : when the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 in middle/high-speed mode. 5 : when the stop mode is ended, a delay of approximately 16 ms occurs by timer 1 and timer 2 in low-speed mode. 6 : wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle/high-speed mode. 7 : the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal clock. functional description
3850/3851 group users manual hardware 1-45 notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. after a reset, initialize flags which affect program execution. in particu- lar, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. ? the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o continues to output the final bit from the t x d pin after transmission is completed. when an external clock is used as synchronous clock in serial i/o, write transmission data to the transmit buffer register while the transfer clock is h. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency in high-speed mode. notes on programming
1-46 3850/3851 group users manual hardware data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form 2.mark specification form 3.data to be written to rom, in eprom form (three identical cop- ies) data required for rom writing orders the following are necessary when ordering a rom writing: 1.rom writing confirmation form 2.mark specification form 3.data to be written to rom, in eprom form (three identical copies) rom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general-purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. fig. 52 programming and testing of one time prom version table 12 programming adapter package 42p2r-a 42p4b name of programming adapter pca4738f-42a pca4738s-42a the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 52 is recommended to verify programming. programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution : data required for mask orders/rom programming method
3850/3851 group users manual hardware 1-47 functional description supplement interrupt 3851 group permits interrupts on the basis of 15 sources. it is vec- tor interrupts with a fixed priority system. accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. this priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. for interrupt sources, vector addresses and interrupt priority, refer to table 13. vector addresses fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 table 13 interrupt sources, vector addresses and interrupt priority high-order low-order priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 interrupt sources reset (note 1) int 0 interrupt scl, sda int 1 interrupt int 2 interrupt int 3 interrupt i 2 c interrupt timer x interrupt timer y interrupt timer 1 interrupt timer 2 interrupt serial i/o receive interrupt serial i/o transmit interrupt cntr 0 interrupt cntr 1 interrupt a-d conversion interrupt brk instruction interrupt remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) stp instruction release timer underflow valid when serial i/o is selected valid when serial i/o is selected external interrupt (active edge selectable) external interrupt (active edge selectable) non-maskable software interrupt note : reset functions in the same way as an interrupt with the highest priority. functional description supplement
1-48 3850/3851 group users manual hardware timing after interrupt the interrupt processing routine begins with the machine cycle fol- lowing the completion of the instruction that is currently in execution. figure 53 shows a timing chart after an interrupt occurs, and fig- ure 54 shows the time up to execution of the interrupt processing routine. fig. 53 timing chart after an interrupt occurs fig. 54 time up to execution of the interrupt processing routine : cpu operation code fetch cycle : vector address of each interrupt : jump destination address of each interrupt : ?0 16 ?or ?1 16 (all signals are internals.) sync b l , b h a l , a h sps data bus not used pc h pc l ps a l a h address bus s, sps s-2, sps s-1, sps pc b l b h a l , a h sync rd wr f functional description supplement generation of interrupt request main routine interrupt processing routine 7 to 23 cycles (at performing 8.0 mhz, in high-speed mode, 1.75 m s to 5.75 m s) 2 cycles 5 cycles start of interrupt processing 0 to 16 cycles waiting time for post-processing of pipeline stack push and vector fetch ] ] : when executing the div instruction
3850/3851 group users manual hardware 1-49 a-d converter a-d conversion is started by setting ad conversion completion bit to 0. during a-d conversion, internal operations are performed as follows. 1. after the start of a-d conversion, a-d conversion register goes to 0016. 2. the highest-order bit of a-d conversion register is set to 1. and the comparison voltage vref is input to the comparator. then, vref is compared with analog input voltage vin. 3. as a result of comparison, when vref < vin, the highest- order bit of a-d conversion register be- comes 1. when vref > vin, the highest-order bit becomes 0. by repeating the above operations up to the lowest-order bit of the a-d conversion register, an analog value converts into a digital value. a-d conversion completes at 61 clock cycles (15.25 m s at f(xin) = 8.0 mhz) after it is started, and the result of the conversion is stored into the a-d conversion register. concurrently with the completion of a-d conversion, the a-d con- version completion bit is set to 1 and an a-d conversion interrupt request occurs, so that the ad conversion interrupt request bit is set to 1. relative formula for a reference voltage v ref of a-d converter and vref when n = 0 vref = 0 when n = 1 to 1023 vref = 5 n n : the value of a-d converter (decimal numeral) v ref 1024 ] 1C ] 10: a result of the first to tenth comparison table 14 change of a-d conversion register during a-d conversion at start of conversion first comparison second comparison third comparison after completion of tenth comparison 100000 1000000 10000000 00000 0 0 0 v ref 2 v ref 4 v ref 2 28 4 v ref v ref v ref a result of a-d conversion ] 1 ] 1 ] 2 ]] ] ]]]] ] 12345678 change of a-d conversion register value of comparison voltage (vref) 00 0 00 00 00 ] 9 ] 10 2 1024 4 v ref v ref v ref ??? ? ? ? ? ? ? ? ? ? functional description supplement
1-50 3850/3851 group users manual hardware figure 55 shows a-d conversion equivalent circuit, and figure 56 shows a-d conversion timing chart. fig. 55 a-d conversion equivalent circuit fig. 56 a-d conversion timing chart v ss v cc av ss v cc v ref av ss a-d control register built-in d-a converter v ref reference clock a-d conversion low-order register a-d converter interrupt request chopper amplifier sampling clock v in an 0 an 1 an 3 c b1 b2 b0 an 2 an 4 approximately 2 k w b4 a-d conversion high-order register write signal for a-d control register ad conversion completion bit sampling clock 61 cycles f functional description supplement
3850/3851 group users manual hardware 1-51 misrg (1) oscillation stabilizing time set after stp instruction released bit (bit 0 of address 0038 16 ) usually, when the mcu stops the clock oscillation by the stp in- struction and the stp instruction has been released by an external interrupt source, the fixed values of timer 1 and prescaler 12 (timer 1 = 01 16 , prescaler 12 = ff 16 ) are automati- cally reloaded in order for the oscillation to stabilize. the user can inhibit the automatic setting by writing 1 to bit 0 of misrg (ad- dress 0038 16 ). however, by setting this bit to 1, the previous values, set just be- fore the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the stp instruction. figure 57 shows the structure of misrg. (2) middle-speed mode automatic switch function in order to switch the clock mode of an mcu which has a subclock, the following procedure is necessary: set cpu mode register (003b 16 ) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). however, the 3851 group has the built-in function which automati- cally switches from low to middle-speed mode either by the scl/ sda interrupt or by program. figure 58 shows the structure of the i 2 c start/stop condition con- trol register. ? middle-speed mode automatic switch by scl/sda interrupt the scl/sda interrupt source enables an automatic switch when the middle-speed mode automatic switch set bit (bit 1) of misrg (address 0038 16 ) is set to 1. the conditions for an au- tomatic switch execution depend on the settings of bits 5 and 6 of the i 2 c start/stop condition control register (address 0030 16 ). bit 5 is the scl/sda interrupt pin polarity selection bit and bit 6 is the scl/sda interrupt pin selection bit. the main clock oscil- lation stabilizing time can also be selected by middle-speed mode automatic switch wait time set bit (bit 2) of the misrg. ? middle-speed mode automatic switch by program the middle-speed mode can also be automatically switched by program while operating in low-speed mode. by setting the middle-speed automatic switch start bit (bit 3) of misrg (ad- dress 0038 16 ) to 1 while operating in low-speed mode, the mcu will automatically switch to middle-speed mode. in this case, the oscillation stabilizing time of the main clock can be se- lected by the middle-speed automatic switch wait set bit (bit 2) of misrg (address 0038 16 ). functional description supplement
1-52 3850/3851 group users manual hardware functional description supplement fig. 57 structure of misrg b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0. 5 misrg oscillation stabilization time set bit after release of the stp instruction 0 0 : set automatically (note 1) 1 : not set automatically 0 0 0 5 5 5 misrg [address : 38 ] 16 0 : not set automatically 1 : automatic switching enable (notes 2, 3) middle-speed mode automatic switch set bit middle-speed mode automatic switch wait time set bit 0 : 4.5 to 5.5 machine cycles 1 : 6.5 to 7.5 machine cycles middle-speed mode automatic switch start bit (depending on program) notes 1: automatically set 01 16 to timer 1, and ff 16 to priscaler 12. 2: during operation in low-speed mode, it is possible automatically to switch to middle-speed mode owing to s cl /s da interrupt. 3: when automatic switch to middle-speed mode from low-speed mode occurs, the values of cpu mode register (3b 16 ) change. 0 : invalid 1 : automatic switch start (note 3) b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 i 2 c start/stop condition control register (s2d) [address : 30 16 ] i 2 c start/stop condition control register 0 ? 1 start/stop condition set bit (ssc0, ssc1, ssc2, ssc3, ssc4) ( note ) 0 : falling edge active 1 : rising edge active s cl /s da interrupt pin polarity selection bit (sip) s cl /s da interrupt pin select on bit (sis) s cl release time = f ( m s) 5 5 5 (ssc+1) set up time = f ( m s) (ssc+1)/2 hold time = f ( m s) (ssc+1)/2 0 : s da valid 1 : s cl valid fix this bit to 0. 0 note : fix ssc0 bit to 0. fig. 58 structure of i 2 c start/stop condition control register
3850/3851 group users manual hardware 1-53 functional description supplement 3850 group differences between 3850 and 3851 groups 3850 group mcus do not have the built-in i 2 c-bus as in the 3851 group. accordingly, the 3850 group does not have registers relevent to i 2 c-bus interface for the sfr area. the structure of the interrupt control registers also differs. the following is a list of reg- isters which are not included in the 3850 group. (1) i 2 c data shift register (address 002b 16 ) (2) i 2 c address register (address 002c 16 ) (3) i 2 c status register (address 002d 16 ) (4) i 2 c control register (address 002e 16 ) fix es0 bit (bit3) to 0. (5) i 2 c clock control register (address 002f 16 ) (6) i 2 c start/stop condition control register (address 0030 16 ) (7) scl/sda interrupt request bit (bit1) of interrupt request register 1 (address 003c 16 ) (8) i 2 c interrupt request bit (bit5) of interrupt request register 1 (address 003c 16 ) (9) scl/sda interrupt enable bit (bit1) of interrupt control register 1 (address 003e 16 ) fix this bit to 0. (10) i 2 c interrupt enable bit (bit5) of interrupt control register 1 (address 003e 16 ) fix this bit to 0. 48k rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 128 192 256 ram size (bytes) 384 512 640 768 896 1024 m38503m4/e4 under development m38504m6/e6 mass production m38503m2 mass production fig. 59 memory expansion plan of 3850 group
1-54 3850/3851 group users manual hardware functional description supplement interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] int 0 interrupt enable bit fix this bit to 0. 0 : interrupt disabled 1 : interrupt enabled fix this bit to 0. timer x interrupt enable bit int 1 interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer y interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled fig. 61 structure of interrupt control register 1 of 3850 group interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] int 0 interrupt request bit fix this bit to 0. 0 : no interrupt request issued 1 : interrupt request issued timer x interrupt request bit ] : these bits can be cleared to 0 by program, but cannot be set to 1. int 1 interrupt request bit int 2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued int 3 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ] ] ] ] ] ] ] timer y interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ] fix this bit to 0. fig. 60 structure of interrupt request register 1 of 3850 group
chapter 2 chapter 2 application 2.1 i/o port 2.2 timer 2.3 serial i/o 2.4 multi-master i 2 c-bus interface 2.5 pwm 2.6 a-d converter 2.7 reset
3850/3851 group users manual application 2.1 i/o port 2-2 2.1 i/o port this paragraph explains the registers setting method and the notes relevant to the i/o ports. 2.1.1 memory map fig. 2.1.1 memory map of registers relevant to i/o port 2.1.2 relevant registers 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) 0008 16 0009 16 port p4 direction register (p4d) port p4 (p4) port pi b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi 0 port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 in output mode write read l port latch in input mode write : port latch read : value of pins l port pi (pi) (i = 0, 1, 2, 3, 4) [address : 00 16 , 02 16 , 04 16 , 06 16, 08 16 ] ? ? ? ? ? ? ? ? fig. 2.1.2 structure of port pi (i = 0, 1, 2, 3, 4)
3850/3851 group users manual application 2-3 2.1 i/o port port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i = 0, 1, 2, 3, 4) [address : 01 16 , 03 16 , 05 16 , 07 16, 09 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode 5 5 5 5 5 5 5 5 fig. 2.1.3 structure of port pi direction register (i=0, 1, 2, 3, 4) 2.1.3 handling of unused pins table 2.1.1 handling of unused pins pins/ports name p0, p1, p2, p3, p4 v ref av ss x out handling ?set to the input mode and connect each to vcc or vss through a resistor of 1 k w to 10 k w . ?set to the output mode and open at l or h level. ?connect to vss (gnd). ?connect to vss (gnd). ?open, only when using an external clock
3850/3851 group users manual application 2.1 i/o port 2-4 2.1.4 notes on input and output pins (1) notes in stand-by state in stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an i/o port undefined, especially for i/o ports of the p-channel and the n-channel open-drain. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: ? external circuit ? variation of output levels during the ordinary operation l reason even when setting as an output port with its direction register, in the following state : ? p-channel ...... when the content of the port latch is 0 ? n-channel ...... when the content of the port latch is 1 the transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes undefined depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an i/o port are undefined. this may cause power source current. * 1 stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction (2) modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction* 2 , the value of the unspecified bit may be changed. l reason the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. ? as for a bit which is set for an input port : the pin state is read in the cpu, and is written to this bit after bit managing. ? as for a bit which is set for an output port : the bit value of the port latch is read in the cpu, and is written to this bit after bit managing. note the following : ? even when a port which is set as an output port is changed for an input port, its port latch holds the output data. ? as for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : seb , and clb instructions
3850/3851 group users manual application 2-5 2.1 i/o port 2.1.5 termination of unused pins (1) terminate unused pins output ports : open input ports : connect each pin to v cc or v ss through each resistor of 1 k w to 10 k w . as for pins whose potential affects to operation modes such as pins cnv ss , int or others, select the v cc pin or the v ss pin according to their operation mode. a i/o ports : ? set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k w to 10 k w . set the i/o ports for the output mode and open them at l or h. ? when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. ? since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. ? the avss pin when not using the a-d converter : ? when not using the a-d converter, handle a power source pin for the a-d converter, avss pin as follows: ? avss:connect to the vss pin (2) termination remarks input ports and i/o ports : do not open in the input mode. l reason ? the power source current may increase depending on the first-stage circuit. ? an effect due to noise may be easily produced as compared with proper termination and a shown on the above. i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. l reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). a i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. l reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. ? at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
2-6 3850/3851 group users manual application 2.2 timer 2.2 timer this paragraph explains the registers setting method and the notes relevant to the timers. 2.2.1 memory map fig. 2.2.1 memory map of registers relevant to timers 2.2.2 relevant registers fig. 2.2.2 structure of prescaler 12, prescaler x, prescaler y 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) 003c 16 003e 16 interrupt control register 1 (icon1) 0027 16 0028 16 timer count source set register (tcss) timer y (ty) prescaler y (prey) 003d 16 003f 16 interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) prescaler 12, prescaler x, prescaler y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 1 1 prescaler 12 (pre12) [address : 20 16 ] prescaler x (prex) [address : 24 16 ] prescaler y (prey) [address : 26 16 ] ?set a count value of each prescaler. ?the value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time. ?when this register is read out, the count value of the corres- ponding prescaler is read out.
3850/3851 group users manual application 2-7 2.2 timer fig. 2.2.3 structure of timer 1 fig. 2.2.4 structure of timer 2, timer x, timer y timer 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 0 0 0 0 0 0 0 timer 1 (t1) [address : 21 16 ] ?set a count value of timer 1. ?the value set in this register is written to both timer 1 and timer 1 latch at the same time. ?when this register is read out, the timer 1s count value is read out. timer 2, timer x, timer y b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 1 1 timer 2 (t2) [address : 22 16 ] timer x (tx) [address : 25 16 ] timer y (ty) [address : 27 16 ] ?set a count value of each timer. ?the value set in this register is written to both each timer and each timer latch at the same time. ?when this register is read out, each timers count value is read out.
2-8 3850/3851 group users manual application 2.2 timer fig. 2.2.5 structure of timer xy mode register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 0 timer xy mode register (tm) [address : 23 ] timer xy mode register 0 0 0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 1 0 timer x operating mode bits cntr 0 active edge switch bit the function depends on the operating mode of timer x. (refer to table 2.2.1) timer x count stop bit 0 : count start 1 : count stop 16 timer y operating mode bits 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b5 b4 the function depends on the operating mode of timer y. (refer to table 2.2.1) 0 : count start 1 : count stop cntr 1 active edge switch bit timer y count stop bit timer x /timer y operation modes timer mode pulse output mode event counter mode pulse width measurement mode cntr 0 / cntr 1 active edge switch bit (bits 2, 6 of address 23 16 ) contents 0 cntr 0 / cntr 1 interrupt request occurrence: falling edge ; no influence to timer count 1 cntr 0 / cntr 1 interrupt request occurrence: rising edge ; no influence to timer count 0 pulse output start: beginning at h level cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 pulse output start: beginning at l level cntr 0 / cntr 1 interrupt request occurrence: rising edge 0 timer x / timer y: rising edge count cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 timer x / timer y: falling edge count cntr 0 / cntr 1 interrupt request occurrence: rising edge 0 timer x / timer y: h level width measurement cntr 0 / cntr 1 interrupt request occurrence: falling edge 1 timer x / timer y: l level width measurement cntr 0 / cntr 1 interrupt request occurrence: rising edge table 2.2.1 cntr 0 /cntr 1 active edge switch bit function
3850/3851 group users manual application 2-9 2.2 timer fig. 2.2.6 structure of timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name timer count source selection register (tcss) [address : 28 16 ] timer count source selection register timer x count source selection bit timer y count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer 12 count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x cin ) 0 0 0 0 0 0 0 0 5 5 5 5 5 nothing is allocated for these bits. these are write disabled bits. when these bits are read out, the values are 0.
2-10 3850/3851 group users manual application 2.2 timer interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 1 (ireq1) [address : 3c 16 ] int 0 interrupt request bit scl/sda interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued i 2 c interrupt request bit timer x interrupt request bit ] : these bits can be cleared to 0 by program, but cannot be set to 1. 0 : no interrupt request issued 1 : interrupt request issued int 1 interrupt request bit int 2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued int 3 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ] ] ] ] ] ] ] timer y interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ] fig. 2.2.7 structure of interrupt request register 1 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt request register 2 (ireq2) [address : 3d 16 ] nothing is allocated for this bit. this is a write disabled bit. when this bit is read out, the value is 0. 5 timer 1 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued cntr 1 interrupt request bit ad converter interrupt request bit ] : these bits can be cleared to 0 by program, but cannot be set to 1. 0 : no interrupt request issued 1 : interrupt request issued serial i/o receive interrupt request bit serial i/o transmit interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued cntr 0 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ] ] ] ] ] ] ] fig. 2.2.8 structure of interrupt request register 2
3850/3851 group users manual application 2-11 2.2 timer interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 1 (icon1) [address : 3e 16 ] int 0 interrupt enable bit scl/sda interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled i 2 c interrupt enable bit timer x interrupt enable bit int 1 interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled timer y interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled fig. 2.2.9 structure of interrupt control register 1 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 0 0 0 0 0 0 0 0 interrupt control register 2 (icon2) [address : 3f 16 ] fix this bit to 0. timer 1 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled cntr 1 interrupt enable bit ad converter interrupt enable bit serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit cntr 0 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 fig. 2.2.10 structure of interrupt control register 2
2-12 3850/3851 group users manual application 2.2 timer 2.2.3 timer application examples (1) basic functions and uses [function 1] control of event interval (timer x, timer y, timer 1, timer 2) when a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. |
