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mobl ? clock M200/m500 two-pll programmable clock generator for portable applications cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-29139 rev. *c revised november 25, 2010 two-pll programmable clock generator for portable applications features device operating voltage options: ? mobl clock M200 family: 1.8 v ? mobl clock m500 family: 2.5 v, 3.0 v, or 3.3 v selectable clock output voltages for both mobl clock M200 and m500: ? 1.5 v, 1.8 v, 2.5 v, 3.0 v, or 3.3 v fully integrated ultra low power phase-locked loops (plls) input reference clock frequency range: 1?48 mhz output clock frequency range: 3?50 mhz three i 2 c? programmable output clocks programmable output drive strengths 150 ps typical cycle-to-cycle jitter optional spread spectrum for emi reduction 16-pin (3 3 0.6 mm) qfn package industrial temperature range benefits suitable for cell phone, portable, and consumer electronics applications multiple high-performance plls allow synthesis of unrelated frequencies application compatibility in mu ltiple output voltage levels optional spread spectrum capable plls with lexmark or linear profile for maximum emi reduction plls can be programmed for system frequency margin tests meets critical timing requirements in complex system designs individually enable or disable each output using i 2 c ease of output clock selection using programmable crossbar switches logic block diagram pll1 pll2 (ss) output dividers and drive strength control crossbar switch pd#/oe clk1 clk3 clk2 vdd_clk1 vdd_clk3 vdd_clk2 ref sel mux and control logic i2c exclkin scl sda [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 2 of 17 contents pinouts .............................................................................. 3 mobl clock M200 ....................................................... 3 mobl clock m500 ....................................................... 4 general description ......................................................... 5 2 configurable plls .................................................... 5 i2c programming ........................................................ 5 input reference clocks .......... .............. .............. ......... 5 output power supply options ..................................... 5 output source selection ............................................. 5 spread spectrum control ............................................ 5 pd#/oe mode ............................................................. 5 keep alive mode ......................................................... 5 output drive strength .................................................. 5 generic configuration and custom frequency ........... 5 i2c serial interface ........................................................... 6 device address ........................................................... 6 data valid .................................................................... 6 data frame ................................................................. 6 acknowledge pulse ..................................................... 6 write operations ............................................................... 6 writing individual bytes ....... .............. .............. ............ 6 writing multiple bytes .................................................. 6 read operations ............................................................... 6 current address read ................................................. 6 random read .............. .............. .............. ............ ....... 6 sequential read .......................................................... 6 serial programming interface timing ............................. 8 serial i2c progra mming interface timing specifications ...................................................... 8 absolute maximum conditions ....................................... 9 recommended operating conditions ............................ 9 dc electrical specifications .......................................... 10 ac electrical specifications .......................................... 11 test and measurement setup ........................................ 12 voltage and timing definitions ..................................... 12 possible configurations ............................................. 13 ordering code definitions ..... .................................... 14 package drawing and dimensions ............................... 14 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 3 of 17 pinouts mobl clock M200 figure 1. pin diagram - 16 ld qfn 8 mobl clock M200 16 ld qfn 16 15 14 13 1 2 3 4 6 7 9 10 11 12 vss clk2 dnu clk1 pd#/oe 5 vss vss clk3 scl sda vdd_clk1 vdd_clk2 vdd_clk3 vdd exclkin vss table 1. pin definitions - mobl clock M200 family (vdd = 1.8 v supply) pin number name io description 1 vss power gnd 2 clk1 output programmable clock output. output voltage depends on vdd_clk1 voltage 3 vdd_clk1 power power supply for cl k1: 1.5 v/1.8 v/2. 5 v/3.0 v/3.3 v 4 pd#/oe input multifunction programmable pin: output enable or power down modes 5 vss power gnd 6 scl input i 2 c-bus clock line 7 sda input/output i 2 c-bus data line 8 vss power gnd 9 clk2 output programmable clock output. output voltage depends on vdd_clk2 voltage 10 vdd_clk2 power power supply for cl k2: 1.5 v/1.8 v/2. 5 v/3.0 v/3.3 v 11 vdd_clk3 power power supply for output clk3: 1.5 v/1.8 v/ 2.5 v/3.0 v/3.3 v 12 dnu dnu do not use this pin 13 vss power gnd 14 clk3 output programmable clock output. output voltage depends on vdd_clk3 voltage 15 vdd power power supply: 1.8 v 16 exclkin input 1.8 v external reference clock [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 4 of 17 mobl clock m500 figure 2. pin diagram - 16 ld qfn vdd_clk2 8 mobl clock m500 16 ld qfn 16 15 14 13 1 2 3 4 6 7 9 10 11 12 vss clk2 dnu v s s c l k 3 vdd clk1 pd#/oe 5 vss vss sda scl vdd_clk3 vdd_clk1 exclkin table 2. pin definitions - mo bl clock m500 family (vdd = 2.5 v, 3.0 v or 3.3 v supply) pin number name io description 1 vss power gnd 2 clk1 output programmable clock ou tput. output voltage depends on vdd_clk1 voltage 3 vdd_clk1 power power supply for clk1 : 1.5 v/1.8 v/2. 5 v/3.0 v/3.3 v 4 pd#/oe input multifunction programmable pin: output enable or power down modes 5 vss power gnd 6sclinputi 2 c-bus clock line 7 sda input/output i 2 c-bus data line 8 vss power gnd 9 clk2 output programmable clock ou tput. output voltage depends on vdd_clk2 voltage 10 vdd_clk2 power power supply for cl k2: 1.5 v/1.8 v/2. 5 v/3.0 v/3.3 v 11 vdd_clk3 power power supply for output clk3: 1.5 v/1.8 v/ 2.5 v/3.0 v/3.3 v 12 dnu dnu do not use this pin 13 vss power gnd 14 clk3 output programmable clock ou tput. output voltage depends on vdd_clk3 voltage 15 vdd power power supply: 2.5 v/3.0 v/3.3 v 16 exclkin input 2.5 v/3.0 v/3.3 v external reference clock [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 5 of 17 general description 2 configurable plls the mobl ? clock M200/m500 family of products are two-pll clock generator ics designed for cell phone, portable, or consumer electronics applications. it can be used to generate two independent output frequencies ranging from 3 to 50 mhz from a single input reference clock. i 2 c programming the mobl ? clock M200 and m500 have a serial i 2 c interface that programs the configuratio n memory array to synthesize output frequencies by progra mmable output divider, spread characteristics, and drive strength. i 2 c can also be used for in-system control of thes e programmable features. input reference clocks the input to the M200 and m500 are designed to use an external reference clock with a frequency range of 1 mhz to 48 mhz at the exclkin pin. the voltage level for the input reference clock used must follow vdd voltage used for the device as shown in the dc and ac specifications. output power supply options there are three clock outputs clk1, clk2, and clk3 driven by three separate output power supplies: vdd_clk1, vdd_clk2, and vdd_clk3 respectively. different voltage level for each of these power supplies can be used and they can be any of 1.5 v, 1.8 v, 2.5 v, 3.0 v, or 3.3 v giving user multiple choice of output clock voltage levels. output source selection these devices have three clock outputs, clk1, clk2 and clk3. there are three available clock sources for these outputs. these clock sources are: pll1, pll2, or exclkin. output clock source selection is done using three out of three crossbar switch. thus, any one of these three available clock sources can be arbitrarily selected for the clock outputs. this gives user a flexibility to have up to two independent clocks and a reference clock output. spread spectrum control the pll2 has spread spectrum capability for emi reduction in the system. the device uses a cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the pl l. the spread spectrum feature can be turned on or off by i 2 c device programming. it can be factory programmed to either c enter spread range from 0.125% to 2.50%, or down spread range from ?0.25% to ?5.0%, with lexmark or linear modulation profile. pd#/oe mode pd#/oe input (pin 4) can be programmed to operate as either power down (pd#) or output enabl e (oe) mode. note that power down shuts off the entire chip, resulting in minimum power consumption for the device. setting this signal high brings the device in the operational mode with default register settings. the pd# turn-on time is limited by the turn-on time of the plls. disabled outputs are first driven to a low state before turning off. when off, they are held low by internal weak resistors (~160 kohms) when this pin is programmed as output enable (oe), clock outputs can be enabled or disabled using oe (pin 4). individual clock outputs can be programmed to be sensitive to this oe pin. keep alive mode by activating the device in the keep alive mode, power down mode is changed to power saving mode, which disables all plls and outputs, but preserves the co ntents of the volatile registers. thus, any configuration changes made via the i 2 c interface are preserved. by deactivating the keep alive mode, i 2 c memory is not preserved during power down, but power consumption is reduced relative to the keep alive mode. output drive strength the dc drive strength of the individual clock output can be programmed for different values. ta b l e 3 shows the typical rise and fall times for different drive strength settings. generic configuration and custom frequency the device is available with factory specific programmed frequencies as shown in the ordering information page. this factory specific programmed pa rt can be used for the device evaluation purposes. the mobl ? clock can be custom programmed to any desired frequ encies and listed features. for customer specific programming and i 2 c programmable memory bitmap definitions, please contact local cypress field application engineer (fae) or sales representative. table 3. output drive strength output drive strength rise/fall time (ns) (typical value) low 6.8 mid low 3.4 mid high 2.0 high 1.0 [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 6 of 17 i 2 c serial interface to enhance the flexibility and function of the clock synthesizer, a two-signal i 2 c serial interface is provided. this interface is used to write (and optionally read) cont rol registers that control various device functions such as enabling individual clock output buffers. the registers initialize to their default setting upon power up and therefore, use of this interfac e is optional. clock device registers are normally changed upon system init ialization. any data written via i 2 c is volatile and is not retained when the device is powered down. the i 2 c interface uses two signals, sda and scl, that operates up to 400 kbits/s in read or write mode. the sda and scl timing and data transfer sequence is shown in figure 3 on page 7 . the basic write serial format is as follows: start bit; 7-bit device address (da); r/w bit; slave clock acknowledge (ack); 8-bit memory address (ma); ack; 8-bit data; ack; 8-bit data in ma+1 if desired; ack; 8-bit data in ma+2; ack; etc. until stop bit. the basic serial format is illustrated in figure 4 on page 7 . device address the device serial interface address is 69h. the device address is combined with a read/write bit as the lsb and is sent after each start bit. data valid data is valid when the clock is high, and can only be transitioned when the clock is low, as illustrated in figure 5 on page 7 . data frame every new data frame is indicated by a start and stop sequence, as illustrated in figure 6 on page 8 . start sequence ? sda going low when scl is high indicates a start frame. every time a start signal is supplied, the next 8-bit data must be the device address (seven bits) and a r/w bit, followed by register address (eight bits) and register data (eight bits). stop sequence ? sda going high when scl is high indicates a stop frame. a stop frame frees the bus to write to another part on the same bus or to write to another random register address. acknowledge pulse during write mode, the mobl clock m2xx/m5xx responds with an acknowledge pulse after every eight bits. this is done by pulling the sda line low during the n*9 th clock cycle, as illustrated in figure 7 on page 8 (n = the number of bytes transmitted). during read mode , the master generates the acknowledge pulse after reading the data packet. write operations writing individual bytes a valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (ack = 0/low). the next eight bits must contain the data word intended for storage. after the receiving the data word, the slave responds with another acknowledge bit (ack = 0/low), and the master must end the write sequence with a stop condition. writing multiple bytes to write multiple bytes at a ti me, the master must not end the write sequence with a stop condition, but instead sends multiple contiguous bytes of data to be stored. after each byte, the slave responds with an acknowledge bit, the same as after the first byte, and accepts data until the acknowledge bit is responded to by the stop condition. when receiving multiple bytes, the mobl clock m2xx/m5 xx internally increments the register address. read operations read operations are initiated th e same way as write operations except that the r/w bi t of the slave address is set to ?1? (high). there are three basic read operations: current address read, random read, and sequential read. current address read the mobl clock m2xx/m5xx have an onboard address counter that retains ?1? more than the address of the last word accessed. if the last word written or read was word ?n?, then a current address read operation returns the value stored in location ?n+1?. when the mobl clock m2xx/m5xx receives the slave address with the r/w bit set to a ?1?, it issues an acknowledge and transmits the 8-bit word. the master device does not acknowledge the transfer, but generates a stop condition, which causes the mobl clock m2xx/m5xx to stop transmission. random read through random read operations, the master may access any memory location. to perform this type of read operation, first set the word address. to do this, send the address to the mobl clock m2xx/m5xx as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. next, the master reissues the control byte with the r/w byte set to ?1?. the mobl clock m2xx/m5xx then issues an acknowledge and transmits the 8-bit word. the master device does not acknowledge the transfer, but generates a stop condition, which causes the mobl clock M200/m500 to stop transmission. sequential read sequential read operations follow the same process as random reads except that the master i ssues an acknowledge instead of a stop condition after transmission of the first 8-bit data word. this action increments the internal address pointer, and subsequently outputs the next 8- bit data word. by continuing to issue acknowledges instead of stop conditions, the master serially reads the entire contents of the slave device memory. when the internal address pointer points to the ffh register, after the next increment, the pointer points to the 00h register. [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 7 of 17 figure 3. data transfer sequence on the serial bus figure 4. data frame architecture figure 5. data valid and data transition periods scl start condition sda stop data may address or acknowledge valid be changed condition sda write start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 8-bit register data stop signal multiple contiguous registers slave 1 bit ack 8-bit register data (xxh) (xxh) (xxh+1) slave 1 bit ack 8-bit register data (xxh+2) slave 1 bit ack 8-bit register data (ffh) slave 1 bit ack 8-bit register data (00h) slave 1 bit ack slave 1 bit ack sda read start signal device address 7-bit r/w = 1 1 bit 8-bit register data slave 1 bit ack slave 1 bit ack stop signal sda read start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 7-bit device stop signal multiple contiguous registers master 1 bit ack 8-bit register data master 1 bit ack (xxh) (xxh) master 1 bit ack 8-bit register data (xxh+1) master 1 bit ack 8-bit register data (ffh) master 1 bit ack 8-bit register data (00h) master 1 bit ack master 1 bit ack current address read address +r/w=1 repeated start bit sda scl data valid transition to next bit clk low clk high vih vil t su t dh [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 8 of 17 serial programming interface timing figure 6. start and stop frame figure 7. frame format (device address, r/w , register address, register data) serial i 2 c programming interface timing specifications parameter description min max unit f scl frequency of scl ? 400 khz start mode time from sda low to scl low 0.6 ? ? s clk low scl low period 1.3 ? ? s clk high scl high period 0.6 ? ? s t su data transition to scl high 250 ? ns t dh data hold (scl low to data transition) 0 ? ns rise time of scl and sda ? 300 ns fall time of scl and sda ? 300 ns stop mode time from scl high to sda high 0.6 ? ? s stop mode to start mode 1.3 ? ? s sda scl start transition to next bit stop sda scl da6 da5 da0 r/w ack ra7 ra6 ra1 ra0 ack stop start ack d7 d6 d1 d0 +++ + + + [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 9 of 17 absolute maximum conditions parameter description condition min max unit v dd supply voltage for mobl clock m5xx ?0.5 4.4 v v dd supply voltage for mobl clock m2xx ?0.5 2.8 v v dd_clkx supply voltage for mobl clock m2xx/m5xx ?0.5 4.4 v v in input voltage for mobl clock m5xx relative to v ss ?0.5 v dd + 0.5 v v in input voltage for mobl clock m2xx relative to v ss ?0.5 2.2 v t s temperature, storage non functional ?65 +150 c esd hbm esd protection (human body model) jedec eia/jesd22-a114-e 2000 ? v ul-94 flammability rating v-0 @1/8 in. ? 10 ppm msl moisture sensitivity level 3 recommended oper ating conditions the recommended operating conditions table for mobl clock m2xx/m5xx family. parameter description min typ max unit v dd vdd operating voltage for mobl clock m5xx 2.25 ? 3.60 v v dd vdd operating voltage for mobl clock m2xx 1.65 1.80 1.95 v v dd_clkx output driver voltage for mobl clock m2xx/m5xx 1.43 ? 3.60 v t ai industrial ambient temperature ?40 ? 85 c c load maximum load capacitance ? ? 15 pf t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 10 of 17 dc electrical specifications the dc electrical specification table for mobl clock m2xx/m5xx family (v dd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v). parameter description conditions min typ max unit v ol output low voltage i ol = 2 ma, drive strength = [00] ? ? 0.4 v i ol = 3 ma, drive strength = [01] i ol = 7 ma, drive strength = [10] i ol = 12 ma, drive strength = [11] v oh output high voltage i oh = ?2 ma, drive strength = [00] v dd_clkx ? 0.4 ??v i oh = ?3 ma, drive strength = [01] i oh = ?7 ma, drive strength = [10] i oh = ?12 ma, drive strength = [11] v olsd output low voltage, sda i ol = 4 ma ? ? 0.4 v v il1 input low voltage of pd#/oe, sda and scl pins ? ? 0.2 v dd v v il2 input low voltage of exclkin pin ? ? 0.1 v dd v v ih1 input high voltage of pd#/oe, sda and scl pins 0.8 v dd ??v v ih2 input high voltage of exclkin for mobl clock m5xx 0.9 v dd ??v v ih3 input high voltage of exclkin pin mobl clock m2xx 0.9 v dd ?2.2v i ih input high current, pd#/oe v ih = v dd ? ? 10 a i il input low current, pd#/oe v il = 0 v ? ? 10 a r dn pull down resistor of clocks (clk1-clk3) in off-state clock outputs in off-state by setting pd# = low 100 160 250 k ? i dd [1, 2] supply current all outputs running, c load = 0 ? 15 ? ma i dds [1] standby current pd# = low, i 2 c circuit not in keep alive mode ?3?a c in [2] input capacitance scl, sda, and pd#/oe inputs ? ? 7 pf notes 1. this parameter is configuration dependent. the specif ied value is for the drive level setting of [1,1]. 2. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with fully loaded outputs. [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 11 of 17 notes 3. this parameter is configuration dependent. the specif ied value is for the drive level setting of [1,1]. 4. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with fully loaded outputs. ac electrical specifications the ac electrical specifications table for m2xx/m5xx (v dd_clkx = 1.5 v/1.8 v/2.5 v/ 3.0 v/3.3 v) family. parameter description conditions min typ max unit f clk clock output frequency all clock outputs 3 ? 50 mhz f ref driven reference frequency exclkin clock 1 ? 48 mhz dc output clock duty cycle duty cycle as defined in figure 9 on page 12 t 1 /t 2 , 50% of v dd_clkx 45 50 55 % t rf1 [4] output clock rise/fall time measured from 20% to 80% of v dd _ clkx , as shown in figure 10 on page 12 , c load = 15 pf, drive strength [00] ? 6.8 10.0 ns t rf2 [4] output clock rise/fall time measured from 20% to 80% of v dd _ clkx , as shown in figure 10 on page 12 , c load = 15 pf, drive strength [01] ?3.45.0ns t rf3 [4] output clock rise/fall time measured from 20% to 80% of v dd _ clkx , as shown in figure 10 on page 12 , c load = 15 pf, drive strength [10] ?2.03.0ns t rf4 [4] output clock rise/fall time measured from 20% to 80% of v dd _ clkx , as shown in figure 10 on page 12 , c load = 15 pf, drive strength [11] ?1.01.5ns t ccj [3, 4] cycle-to-cycle jitter exclk in = clkx = 48 mhz, c load = 15 pf, 2 plls and 1 output for each pll enabled, drive strength = [11] ?150?ps t lock [4] pll lock time ? 1 3 ms [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 12 of 17 test and measurement setup figure 8. test and measurement setup voltage and timing definitions figure 9. duty cycle definition figure 10. rise time = t rf , fall time = t rf 0.1 ? f v dd outputs c load gnd dut clock output v dd_clkx 50% of v dd_clkx 0v t 1 t 2 clock output t rf t rf v dd_clkx 80% of v dd_clkx 20% of v dd_clkx 0v [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 13 of 17 all product offerings are factory programmed customer specific devices with customized part num bers. the possible configuration s table shows the available device types, but not complete part nu mbers. contact your local cypress fae of sales representative f or more information. possible configurations note 5. xx indicates factory programmed parts based on customer specific configuration. for more details, contact your local cypress fae or sales representative ordering information part number [5] frequency configuration other programmable features package production flow pb-free M200lfxi factory generic configuration with exclkin = 19.2 mhz clk1 = 48.0 mhz clk2 = 27.0 mhz vdd = 1.8 v vdd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v power down = enabled keep alive = disabled spread spectrum = disabled output drive strength = [11] 16-pin qfn industrial, ?40 c to 85 c M200lfxit factory generic configuration with exclkin = 19.2 mhz clk1 = 48.0 mhz clk2 = 27.0 mhz vdd = 1.8 v vdd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v power down = enabled keep alive = disabled spread spectrum = disabled output drive strength = [11] 16-pin qfn- ta p e & r e e l industrial, ?40 c to 85 c m500lfxi factory generic configuration with exclkin = 19.2 mhz clk1 = 48.0 mhz clk2 = 27.0 mhz vdd = 2.5 v/3.0 v/3.3 v vdd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v power down = enabled keep alive = disabled spread spectrum = disabled output drive strength = [11] 16-pin qfn industrial, ?40 c to 85 c m500lfxit factory generic configuration with exclkin = 19.2 mhz clk1 = 48.0 mhz clk2 = 27.0 mhz vdd = 2.5 v/3.0 v/3.3 v vdd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v power down = enabled keep alive = disabled spread spectrum = disabled output drive strength = [11] 16-pin qfn- ta p e & r e e l industrial, ?40 c to 85 c part number [5] frequency configuration other programmable features package production flow m2xxlfxi customer specific configuration vdd = 1.8 v vdd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v 16-pin qfn industrial, ?40c to 85c m2xxlfxit customer specific configuration vdd = 1.8 v vdd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v 16-pin qfn- ta p e & r e e l industrial, ?40c to 85c m5xxlfxi customer specific confi guration vdd = 2.5 v/3.0 v/3.3 v vdd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v 16-pin qfn industrial, ?40c to 85c m5xxlfxit customer specific configuration vdd = 2.5 v/3.0 v/3.3 v vdd_clkx = 1.5 v/1.8 v/2.5 v/3.0 v/3.3 v 16-pin qfn- ta p e & r e e l industrial, ?40c to 85c [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 14 of 17 ordering code definitions package drawing and dimensions figure 11. 16-lead chip on lead 3 3 mm qfn package t = tape and reel; blank = tube temperature range: i = industrial x = pb-free package package: 16-pin qfn configuration: factory generic c onfiguration: mxxx = M200 / m500 xt mxxx i lf 001-09116 *e [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 15 of 17 acronyms document conventions units of measure acronym description emi electromagnetic interference fae field application engineer oe output enable pll phase locked loop qfn quad flat no leads symbol unit of measure c degree celsius k ? kilo ohms khz kilo hertz mhz mega hertz a micro amperes ma milli amperes ms milli seconds mm milli meter ns nano seconds ? ohms % percent pf pico farads ppm parts per million ps pico seconds vvolts [+] feedback
mobl ? clock M200/m500 document number: 001-29139 rev. *c page 16 of 17 document history page document title: mobl ? clock M200/m500 two-pll programmable clock generator for portable applications document number: 001-29139 rev. ecn no. issue date orig. of change description of change ** 1535744 see ecn rgl/aesa new data sheet *a 2748211 08/10/09 tsai posting to external web. *b 2899297 03/25/10 cxq moved ?xx? parts to possible configurations table. updated package diagram *c 3095377 11/25/ 2010 bash added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. [+] feedback
document number: 001-29139 rev. *c revised november 25, 2010 page 17 of 17 purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. mobl is a registered trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. mobl ? clock M200/m500 ? cypress semiconductor corporation, 2007-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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