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rev.0, 10/08, wk page 1 of 12 MT-035 tutorial op amp inputs, outputs, single-s upply, and rail-to-rail issues single-supply op amp issues single-supply operation has become an increasi ngly important requirement because of market demands. automotive, set-top box, camera/camcorder , pc, and laptop computer applications are demanding ic vendors to supply an array of linea r devices that operate on a single-supply rail, with the same performance of dual supply parts. power consumption is now a key parameter for line or battery operated systems, and in some in stances, more important than cost. this makes low-voltage/low supply current operation critica l; at the same time, however, accuracy and precision requirements have forced ic manufacturers to meet the ch allenge of "doing more with less" in their amplifier designs. in a single-supply application, the most immediate effect on the pe rformance of an amplifier is the reduced input and output signa l range. as a result of these lower input and output signal excursions, amplifier circuits become more sens itive to internal and external error sources. precision amplifier offset voltage s on the order of 0.1 mv are less than a 0.04 lsb error source in a 12-bit, 10 v full-scale system . in a single-supply system, however, a "rail-to-rail" precision amplifier with an offset voltage of 1 mv repres ents a 0.8 lsb error in a 5 v fullscale system (or 1.6 lsb for 2.5 v fullscale). gain accuracy in some low voltage single-supply devices is also reduced, so device selection needs careful consideration. many amplifiers with ~120 db open-l oop gains typically operate on dual supplies?for example op07 types. however, ma ny single-supply/rail-to-rail amplifiers for precision applications typically have open-loop gains between 25,000 and 30,000 under light loading (>10 k ). selected devices, like the op113/op213/op413 family, do have high open- loop gains (>120 db), for use in demanding a pplications. another example would be the ad855x chopper-stabilized op amp series. besides these limitations, many other design consider ations that are otherwise minor issues in dual-supply amplifiers now become important. fo r example, signal-to-noise (snr) performance degrades as a result of reduced signal swing. "ground reference" is no longer a simple choice, as one reference voltage may work for some devi ces, but not others. amplifier voltage noise increases as operating supply cu rrent drops, and bandwidth de creases. achieving adequate bandwidth and required precision with a somewhat limited selection of amplifiers presents significant system design challenges in single-supply, low-power applications. most circuit designers take "ground" reference fo r granted. many analog circuits scale their input and output ranges about a ground reference. in dual- supply applications, a reference that splits the supplies (0 v) is very convenient, as there is equal supply headroom in each direction, and 0 v is generally the voltage on the low impedan ce ground plane. in si ngle-supply/rail-to-rail circuits, however, the ground refe rence can be chosen anywhere within the supply range of the circuit, since there is no standard to follow. the choice of ground reference de pends on the type of signals processed and the amplifier characteristics. for example, choosing the negative rail as
MT-035 the ground reference may optimize the dynamic range of an op amp whose output is designed to swing to 0 v. on the other hand, the signal may require level shifting in order to be compatible with the input of other devices (such as adcs) that are not designed to operate at 0 v input. the need for rail-to-rail amplifier output stages is also driven by the need to maintain wide dynamic range in low-supply voltage applications. a single-supply/rail-to-ra il amplifier should have output voltage swings that ar e within at least 100 mv of eith er supply rail (under a nominal load). the output voltage swing is very depend ent on output stage topology and load current. single-supply op amp design issues are summarized in figure 1. ? z z z ? z z z z z single supply offers: lower power battery operated portable equipment requires only one voltage design tradeoffs: reduced signal swing increases sensitivity to errors caused by offset voltage, bias current, finite open- loop gain, noise, etc. must usually share noisy digital supply rail-to-rail input and output needed to increase signal swing precision less than the best dual supply op amps but not required for all applications many op amps specified for single supply, but do not have rail-to-rail inputs or outputs figure 1: single-supply op amp design issues op amp input stages it is extremely important to understand input and output structur es of op amps in order to properly design the required in terfaces. for ease of discussi on, the two can be examined separately, as there is no particular re ason to relate them at this point. bipolar input stages the very common and basic bipolar input stage of figure 2 consists of a "long-tail ed pair" built with bipolar transistors. it has a number of advantages: it is simp le, has very low offset, the bias currents in the inverting and non-inverting inputs are well-matched and do not vary greatly with temperature. in addition, minimizing the initial offset voltage of a bipolar op amp by laser trimming also minimizes its drift over temperatur e. this architecture was used in the very earliest monolithic op amps such as the a709. it is also used with modern high speed types. although npn bipolars are shown, the concept also applies with the us e of pnp bipolars. page 2 of 12
MT-035 v in ? ? ? ? ? ? ? ? ? low offset: as low as 10 p v low offset drift: as low as 0.1 p v/ o c temperature stable i b well-matched bias currents low voltage noise: as low as 1nv/ ? hz high bias currents: 50na - 10 p a (except super-beta: 50pa - 5na, more complex and slower) medium current noise: 1pa/ ? hz matching source impedances minimize offset error due to bias current figure 2: a bipolar tr ansistor input stage bias current compensated bipolar input stage v in ? ? ? ? ? ? ? ? ? low offset voltage: as low as 10p v low offset drift: as low as 0.1 p v/ o c temperature stable i bias low bias currents: <0.5 - 10na low voltage noise: as low as 1nv/ ? hz poor bias current match (currents may even flow in opposite directions) higher current noise not very useful at hf matching source impedances makes offset error due to bias current worse because of additional impedance figure 3: a bias current compensated bipolar input stage a simple bipolar input stage such as used in figure 2 exhibits high bias current because the currents seen externally are in f act the base currents of the tw o input transistors. by providing this necessary bias currents via an internal current s ource, as in figure 3, the only external page 3 of 12
MT-035 current then flowing in the input terminals is th e difference current betwee n the base current and the current source, which can be quite small. most modern precision op amps use some mean s of internal bias current compensation, examples would be the familiar op07 and op27 series. bias current compensated input stages have ma ny of the good features of the simple bipolar input stage, namely: low voltage noise, low offs et, and low drift. add itionally, they have low bias current which is fairly stable with temper ature. however, their current noise is not very good, and their bias current matching is poor. these latter two undesired side effects result from the external bias current being the difference between the compensating current source and the i nput transistor base current. both of these currents inevitably have noise. since they are un correlated, the two noises add in a root-sum-of- squares fashion (even though the dc currents subtract). since the resulting external bias current is the difference between two nearly equal currents , there is no reason why the net current should have a defined polarity. as a result, the bias cu rrents of a bias-compensated op amp may not only be mismatched, they can actually flow in opposite directions. in many cases, the bias current compensation feat ure is not mentioned on an op amp data sheet, and a simplified schematic isn't supplied. it is easy to determine if bias current compensation is used by examining the bias current specification. if the bias current is specified as a " " value, the op amp is most likely compensated for bias current. note that this can easily be verified, by examining the offset current specification (the difference in the bias currents). if internal bias current compensation exists, the offset current will be of the same magnitude as the bias current. without bias current compensation, the offset current will generally be at least a factor of 10 smaller than the bias current. note that these relationships generally hold, regardless of the exact magnitude of the bias currents. the effects of bias current on the output offset voltage of an op amp can often be cancelled by making the source resistances at th e two inputs equal. but, there is an important caveat here. the validity of this practic e only holds true for bipolar input op amps without bias current compensation, that is, where the input currents ar e well matched. in a ca se of an op amp using internal bias current compensation, adding an ex tra resistance to either input will usually make the output offset worse! fet input stages field-effect transistors (fets) have much hi gher input impedance than do bipolar junction transistors (bjts) and would th erefore seem to be ideal de vices for op amp input stages. however, they cannot be manufactured on all bi polar ic processes, and when a process does allow their manufacture, they often have their own problems. page 4 of 12
MT-035 fets have high input impedance, low bias curr ent, and good high frequency performance (in an op amp, the lower g m of the fet devices allows higher tail currents, thereby increasing the maximum slew rate). fets also have much lower current noise. on the other hand, the input offset voltage of f et long-tailed pairs, however, is not as good as the offset of corresponding bjts, and trimming for minimum offset does not simultaneously minimize drift. a separate trim is needed for drif t, and as a result, offset and drift in a jfet op amp, while good, aren't as good as the best bjt ones. it is possible to make jfet op amps with very low voltage noise, but the devices involved are very large and have quite high input capacitance, which varies with input voltage, and so a trade-off is involved between voltage noise and input capacitance. the bias current of an fet op amp is the leakage current of the gate diffusion (or the leakage of the gate protection diode, which has similar characteristics for a mosfet). such leakage currents double with every 10c increase in chip temperature so that a fet op amp bias current is one thousand times greater at 125c than at 25c. obvious ly this can be important when choosing between a bipolar or fet input op amp, es pecially in high temp erature applications where bipolar op amp input bias current actually decreases. thus far, we have spoken generally of all ki nds of fets, that is junction (jfets) and mos (mosfets). in practice, combined bipolar/j fet technology op amps (i.e., bifet) achieve better performance than op amps using purel y mosfet or cmos technology. while adi and others make high performance op amps with mos or cmos input stages, in general these op amps have worse offset and drift, voltage nois e, high-frequency performance than the precision bipolar counterparts. the power consumption is usually somewhat lower than that of bipolar op amps with comparable, or ev en better, performance. jfet devices require more headroom than do bj ts, since their pinchoff voltage is typically greater than a bjts base-emitter voltage. consequen tly, they are more difficult to operate at very low power supply voltages (1-2 v) . in this respect, cmos has th e advantage of requiring less headroom than jfets. rail-rail input stages today, there is common demand for op amps with input cm voltage that includes both supply rails, i.e., rail-to-rail cm operation. while such a feature is undoubtedly useful in some applications, engineers should recognize that there are still relatively few applications where it is absolutely essential. these applications should be distinguished from the many more applications where a cm range close to the supplies, or one that includes one supply is necessary, but true input rail-to-rail operation is not. in many single-supply applications , it is required that the input cm voltage range extend to one of the supply rails (usually ground). high-side or low-side current-se nsing applications are examples of this. many amplifiers can handle 0 v cm inputs, and they are easily designed using pnp (or pmos) differential pairs (or n-channel jfet pairs) as shown in figure 4. the input cm page 5 of 12
MT-035 range of such an op amp generally extends fr om about 200 mv below the negative rail (?v s or ground), to about 1-2 v of the positive rail, +v s . pnps or pmos +v s ?v s n-ch jfets +v s ?v s n-ch jfets +v s ?v s figure 4: pnp/pmos or n-channe l jfet stages allow cm inputs to the negative rail an input stage could also be designed with npn (or nmos) transistors (or p-channel jfets), in which case the input cm range would include the positive rail, and go to within about 1-2 v of the negative rail. this requirement typically occurs in applicati ons such as high-side current sensing. the op282/op482 input stage uses a p-channel jfet input pair whose input cm range includes the positive rail, making it suitable for high-side sensing. a simplified diagram of a true rail- to-rail input stage is shown in fi gure 6. note that this requires use of two long-tailed pairs, one of pnp bipolar transi stors q1-q2, the other of npn transistors q3-q4. similar input stages can al so be made with cmos pairs. +v s ?v s q1 q2 q3 q4 figure 5: a true rail-to-rail bi polar transistor input stage page 6 of 12
MT-035 it should be noted that these two pairs will exhibit different offsets and bias currents, so when the applied cm voltage changes, the amplifier input offset voltage and input bias current does also. in fact, when both current sources remain ac tive throughout most of the entire input common- mode range, amplifier input offset voltage is the average offset voltage of the two pairs. in those designs where the current sources are alternatively switched o ff at some point along the input common-mode voltage, amplifier input offset vo ltage is dominated by the pnp pair offset voltage for signals near the nega tive supply, and by the npn pair o ffset voltage for signals near the positive supply. as noted, a true rail-to-rail input stage can al so be constructed from cmos transistors, for example as in the case of the cmos ad8531/ad8532/ad8534 op amp family. amplifier input bias current, a f unction of transistor current gain, is also a function of the applied input common-mode voltage. the result is relatively poor common-mode re jection (cmr), and a changing common-mode input impedance over th e cm input voltage range, compared to familiar dual-supply devices. these specifications should be considered carefully when choosing a rail-to-rail input op amp, especially for a non- inverting configuration. input offset voltage, input bias current, and even cmr may be quite good over part of the common-mode range, but much worse in the region where operation shif ts between the npn and pnp devices, and vice versa. true rail-to-rail amplifier input stage designs must transition fr om one differential pair to the other differential pair, somewhere along the in put cm voltage range. some devices like the op191/op291/op491 family and the op279 have a common-mode crossover threshold at approximately 1 v below the positive supply (w here signals do not often occur). the pnp differential input stage is active from about 200 mv below the negative supply to within about 1 v of the positive supply. over this common-mode range, amplifier input offset voltage, input bias current, cmr, input noise vo ltage/current are primarily determ ined by the characteristics of the pnp differential pair. at the crossover thre shold, however, amplifier input offset voltage becomes the average offset voltage of the npn/pnp pairs and can change rapidly. also, as noted previously, amplifier bias currents are dominated by the pnp differential pair over most of the input common-mode range, and cha nge polarity and magnitude at the crossover threshold when the npn differential pair becomes active. op amps like the op184/op284/op484 family utilize a rail-to-rail input stage design where both npn and pnp transistor pairs are active throughout most of the entire input cm voltage range. with this approach to biasing, there is no cm cr ossover threshold. amplifie r input offset voltage is the average offset voltage of the npn and the pnp stages, and offset vo ltage exhibits a smooth transition throughout the entire input cm range, due to careful laser trimming of input stage resistors. in the same manner, through careful input stage cu rrent balancing and input transistor design, the op184 family input bias currents also exhibit a smooth transition throughout the entire cm input voltage range. the exception occu rs at the very extr emes of the input range, where amplifier offset voltages and bias currents increase sharply, due to the slight forwar d-biasing of parasitic p- n junctions. this occurs for input voltages with in approximately 1 v of either supply rail. page 7 of 12
MT-035 when both differential pairs are active throughout mo st of the entire input common-mode range, amplifier transient response is faster through the middle of the common-mode range by as much as a factor of 2 for bipolar i nput stages and by a factor of 2 for jfet input stages. this is due to the higher transconductance of two operating input stages. input stage g m determines the slew rate and the unity-gai n crossover frequency of the amplifier, hence response time degrades slightly at the extremes of the input common-mode range when either the pnp stage (signals approaching the positive supply rail) or the npn stage (signals approaching the negative supply rail) are forced into cutoff. the thresholds at which the transconductance changes o ccur are approximately wi thin 1 v of either supply rail, and the behavior is similar to that of the input bi as currents. in light of the many quirks of true rail-to-rail op amp input stages, applications which do require true rail-to-rail inputs should be carefully evaluated, and an amplifier chosen to ensure that its input offset voltage, input bias current, common-mode rejection, and noise (voltage and current) are suitable. output stages the earliest ic op amp output stages were npn emitter followers with npn current sources or resistive pull-downs, as shown in figure 6a. naturally, the sl ew rates were greater for positive- going than they were for negative-going signals. while all modern op amps have push-pull out put stages of some sort, many are still asymmetrical, and have a greater slew rate in one direction than the other. asymmetry tends to introduce distortion on ac signa ls and generally results from the use of ic processes with faster npn than pnp transistors. it may also result in an ability of the output to approach one supply more closely than the other in terms of saturation voltage. npn npn npn pnp +v s +v s ?v s ?v s v out v out nmos nmos +v s ?v s v out (a) (b) (c) figure 6: some traditiona l op amp output stages page 8 of 12
MT-035 in many applications, the output is required to swing only to one rail, usually the negative rail (i.e., ground in single-supply syst ems). a pulldown resistor to the negative rail will allow the output to approach that rail (p rovided the load impedance is hi gh enough, or is also grounded to that rail), but only slowly. using an fet current source instead of a resistor can speed things up, but this adds complexity, as shown in figure 6b. with modern complementary bipolar (cb) proc esses, well matched high speed pnp and npn transistors are readily available. the comple mentary emitter follower output stage shown in figure 6c has many advantages, but the most out standing one is the low output impedance. however, the output voltage of this stage can only swing within about one v be drop of either rail. therefore an output swing of +1 v to +4 v is typical of such a stage, when operated on a single +5 v supply. the complementary common-emitter/common-source output stages shown in figure 7a and b allow the op amp output voltage to swing much clos er to the rails, but these stages have much higher open-loop output impedance than do the em itter follower-based stages of figure 6c. in practice, however, the amplifier' s high open-loop gain and the applied feedback can still produce an application with low output impedance (parti cularly at frequencies below 10 hz). what should be carefully evaluated wi th this type of output stage is the loop gain within the application, with the load in place. typically, the op amp will be specified for a minimum gain with a load resistance of 10 k (or more). care should be taken that the application loading doesn't drop lower than the rated load, or gain accuracy may be lost. it should also be noted these output stages ca n cause the op amp to be more sensitive to capacitive loading than the emitter-follower type. again, this will be noted on the device data sheet, which will indicate a maximum of capacitive loading before overshoot or instability will be noted. pnp npn pmos nmos +v s +v s ?v s ?v s v out v out swings limited by saturation voltage swings limited by fet "on" resistance (a) (b) figure 7: "almost" rail-to- rail output structures page 9 of 12
MT-035 the complementary common emitter output st age using bjts (figure 7a) cannot swing completely to the rails, but only to with in the transistor saturation voltage (v cesat ) of the rails. for small amounts of load current (less than 100 a), the saturatio n voltage may be as low as 5 to 10 mv, but for higher load currents, the satura tion voltage can in crease to several hundred mv (for example, 500 mv at 50 ma). on the other hand, an output stage constructed of cmos fets (figure 7b) can provide nearly true rail-to-rail performance, but only under no-load conditions. if the op amp output must source or sink substantial current, the output voltage swing will be reduced by the i r drop across the fets internal "on" resistance. typically this resistance will be on the order of 100 for precision amplifiers, but it can be less than 10 for high current drive cmos amplifiers. for the above basic reasons, it should be apparent that th ere is no such thing as a true rail-to-rail output stage, hence the caption of figure 7 ("almo st" rail-to-rail output structures). the best any op amp output stage can do is an almost rail -to-rail swing, when it is lightly loaded. circuit design considerations for single supply systems many waveforms are bipolar in nature. this mean s that the signal natura lly swings around the reference level, which is typically ground. th is obviously won?t work in a single supply environment. what is required is to ac couple the signals. 649 v load - + u1 47 f r1 649 = +5v v in 4.99k r3 4.99k + c in r4 c2 r5 r2 c1 + + 220 f 10 f v s + + 0.1 f 100 f/25v c2 1 f 1000 f c out 75 r l c4 c3 10k 649 v load - + u1 47 f r1 649 = +5v v in 4.99k r3 4.99k + c in r4 c2 r5 r2 c1 + + 220 f 10 f v s + + 0.1 f 100 f/25v c2 1 f 1000 f c out 75 r l c4 c3 649 v load - + u1 47 f r1 649 = +5v v in 4.99k r3 4.99k + c in r4 c2 r5 r2 c1 + + 220 f 10 f v s + + 0.1 f 100 f/25v c2 1 f 1000 f c out 75 r l c4 c3 10k figure 8: si ngle supply biasing ac coupling is simply applying a high pass filter and establishing a new reference level typically somewhere around the center of the supply voltage range as shown in figure 8. the series capacitor will block the dc component of the input signal. the corner frequency (the frequency at which the response is 3 db down from the midba nd level) is determined by the value of the components: page 10 of 12
MT-035 cr2 1 f eq c = , eq. 1 where: 5r4r 5r4r r eq + = . eq. 2 it should be noted that if multip le sections are ac coupled, each se ction will be 3 db down at the corner frequency. so if there are two sections wi th the same corner frequency, the total response will be 6 db down, three sections would be 9 db down etc. this should be taken into account so that the overall response of the system will be adequate. also keep in mind that the amplitude response starts to roll off a decade, or more, from the corner frequency. the ac coupling of arbitrary waveforms can actually introduce problems whic h don?t exist at all in dc coupled systems. these problems have to do with the waveform duty cycle, and are particularly acute with signals which approach the rails, as they can in low supply voltage systems which are ac coupled. figure 9: headroom issues with single supply biasing in an amplifier circuit such as that of figure 8, the output bias point will be equal to the dc bias as applied to the op amp? s (+) input. for a symmetric (50% duty cycle) waveform of a 2 vp-p output level, the output signal will swing symmetrical ly about the bias point, or nominally 2.5 v 1 v ( using the values given in figure 9). if however the pulsed waveform is of a very high (or low) duty cycle, the ac averaging effect of c in and r4||r5 will shift the effective peak level (a) 50% duty cycle no clipping (a) 50% duty cycle no clipping 2v p-p 2v p-p 2v p-p 2.5v 1.0v (-) clipping 4.0v (+) clipping 4.0v (+) clipping 2.5v 1.0v (-) clipping 4.0v (+) clipping 2.5v 1.0v (-) clipping (b) low duty cycle clipped positive (c) high duty cycle clipped negative page 11 of 12
page 12 of 12 MT-035 either high or low, dependent upon the duty cy cle. this phenomenon has the net effect of reducing the working headroom of the amplif ier, and is illustrated in figure 9. in figure 9 (a), an example of a 50% duty cycle square wave of about 2 vp-p level is shown, with the signal swing biased symmetrically be tween the upper and lower clip points of a 5 v supply amplifier. this amplifier, for example, (an ad817 biased similarly to figure 8) can only swing to the limited dc levels as marked, about 1 v from either rail. in cases (b) and (c), the duty cycle of the input waveform is adjust ed to both low and high duty cycle extremes while maintaining the same peak-to-peak input level . at the amplifier output, the waveform is seen to clip either negative or positive, in (b) and (c), respectively. references: 1. hank zumbahlen, basic linear design , analog devices, 2006, isbn: 0-915550-28-1. also available as linear circuit design handbook , elsevier-newnes, 2008, isbn-10: 0750687037, isbn-13: 978- 0750687034. chapter 1. 2. walter g. jung, op amp applications , analog devices, 2002, isbn 0-916550-26-5, also available as op amp applications handbook , elsevier/newnes, 2005, isbn 0-7506-7844-5. chapter 1. copyright 2009, analog devices, inc. all rights reserved. analog devices assumes no responsibility for customer product design or the use or application of customers? products or for any infringements of patents or rights of others which may result from analog devices assistance. all trad emarks and logos are property of their respective holders. information furnished by analog devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by analog devices regarding technical accuracy and topicality of the content provided in analog devices tutorials.

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