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? semiconductor ml7000-01/02/03/ml7001-01/02/03 1/19 ? semiconductor ml7000-01/02/03 ml7001-01/02/03 single rail codec general description the ml7000/ml7001 are single-channel cmos codec lsi devices for voice signals ranging from 300 to 3400 hz with filters for a/d and d/a conversion. designed especially for a single-power supply and low-power applications, the devices are optimized for isdn terminals, digital wireless systems, and digital pbxs. the devices use the same transmission clocks as those used in the msm7507. with the differential analog signal outputs which can drive 60 w load, the devices can directly drive a handset receiver. features ? single power supply: +5 v (ml7000-xx) +3 v (ml7001-xx) ? low power consumption operating mode: 25 mw typ. v dd = 5.0 v (ml7000-xx) 20 mw typ. v dd = 3.0 v (ml7001-xx) power-down mode: 0.05 mw typ. v dd = 5.0 v (ml7000-xx) 0.03 mw typ. v dd = 3.0 v (ml7001-xx) ? conforms to itu-t companding law ml7000-01/ml7001-01: m /a-law pin selectable ml7000-02/ml7001-02: m -law ml7000-03/ml7001-03: a-law ? transmission characteristics conform to itu-t g.714 ? short frame sync timing operation ? built-in pll eliminates a master clock ? serial data rate: 64/96/128/192/200/256/384/512/ 768/1024/1536/1544/2048 khz ? adjustable transmit gain ? adjustable receive gain ? built-in reference voltage supply ? package options: 24-pin plastic sop (sop24-p-430-1.27-k) (product name: ml7000-01ma/ml7001-01ma) (product name: ml7000-02ma/ml7001-02ma) (product name: ml7000-03ma/ml7001-03ma) 20-pin plastic ssop (ssop20-p-250-0.95-k) (product name: ml7000-01mb/ml7001-01mb) (product name: ml7000-02mb/ml7001-02mb) (product name: ml7000-03mb/ml7001-03mb) e2u0062-18-84 this version: aug. 1998 preliminary
? semiconductor ml7000-01/02/03/ml7001-01/02/03 2/19 block diagram rc lpf 8th bpf a/d conv. tcont auto zero 5th lpf d/a conv. pwd logic pll rtim rcont pcmout pcmin pdn v dd ag dg sg gen sgc sg pwd C + ainC ain+ gsx C + vfro rsync bclk xsync (alaw) vr gen C + aoutC pwi C + aout+
? semiconductor ml7000-01/02/03/ml7001-01/02/03 3/19 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sg aout+ aoutC pwi vfro v dd dg pdn sgc ain+ ainC gsx ag bclk 20-pin plastic ssop rsync pcmin xsync pcmout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 sg aout+ aoute pwi vfro dg pdn sgc ain+ aine gsx ag 24-pin plastic sop rsync pcmin xsync pcmout v dd bclk (alaw)* nc nc nc (alaw)* nc nc nc * the alaw pin is only supported by the ml7000-01ma/ml7000-01mb/ml7001-01ma/ ml7001-01mb. nc : no connect pin
? semiconductor ml7000-01/02/03/ml7001-01/02/03 4/19 pin functional description ain+, ainC, gsx transmit analog input and transmit level adjustment. ain+ is a non-inverting input to the op-amp; ainC is an inverting input to the op-amp; gsx is connected to the output of the op-amp. the level adjustment should be performed using any of the methods shown below. during power-saving and power-down modes, the gsx output is at ag voltage. ag analog ground. vfro receive filter output. the output signal has an amplitude of 2.4 v pp for ml7000-xx and 2.0 v pp for ml7001-xx above and below the signal ground voltage (sg) when the digital signal of +3 dbm0 is input to pcmin and can drive a load of 20 k w or more. for driving a load of less than 20 k w , connect a resistor of 20 k w or more between the pins vfro and pwi. during power-saving or power-down mode, the vfro output is at an sg level. when adjusting the receive signal on the basis of frequency characteristics, refer to the frequency characteristics adjustment circuit. C + ainC ain+ c1 analog input r1 : variable r2 > 20 k w c1 > 1/(2 3.14 30 r1) r2 gsx sg + C ain+ ainC r3 > 20 k w r4 > 20 k w r5 > 50 k w c2 > 1/ (2 3.14 30 r5) r4 gsx sg c2 analog input r3 r5 r1
? semiconductor ml7000-01/02/03/ml7001-01/02/03 5/19 pwi, aout+, aoutC pwi is connected to the inverting input of the receive driver. the receive driver output is connected to the aoutC pin. therefore, the receive level can be adjusted with the pins vfro, pwi, and aoutC. during power-saving or power down-mode, the outputs of aout+ and aoutC are in a high impedance state. the output of aout+ is inverted with respect to the output of aoutC. since these outputs provide differential drive of an impedance of 1.2 k w , they can directly be connected to a handset using a piezoelectric earphone or a line transformer. refer to the application example. v dd power supply for +5 v (ml7000-xx) or +3 v (ml7001-xx) pcmin pcm data input. a serial pcm data input to this pin is converted to an analog signal in synchronization with the rsync signal and bclk signal. the data rate of pcm is equal to the frequency of the bclk signal. pcm signal is shifted in at the falling edge of the bclk signal and latched into the internal register when shifted by eight bits. the start of the pcm data (msd) is identified at the rising edge of rsync. bclk shift clock signal input for the pcmin and pcmout signals. the frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048 khz. setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. r6 > 20 k w zl > 1.2 k w gain = vo/vi = 2 5 r7/r6 2 r6 r7 C + sg C + sg vfro pwi aoutC aout+ zl receive filter vi vo 20 k w 20 k w
? semiconductor ml7000-01/02/03/ml7001-01/02/03 6/19 rsync receive synchronizing signal input. eight required bits are selected from serial pcm signals on the pcmin pin by the receive synchronizing signal. signals in the receive section are synchronized by this synchronizing signal. this signal must be synchronized in phase with the bclk. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics which are mainly the frequency characteristics of the receive section. however, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 6 to 9 khz, but the electrical characteristics in this specification are not guaranteed. xsync transmit synchronizing signal input. the pcm output signal from the pcmout pin is output in synchronization with this signal. this synchronizing signal triggers the pll and synchronizes all timing signals of the transmit section. this synchronizing signal must be synchronized in phase with bclk. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics which are mainly the frequency characteristics of the transmit section. however, if the frequency characteristic of an applied system is not specified exactly, this device operates in the range of 6 to 9 khz, but the electrical characteristics in this specification are not guaranteed. setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state.
? semiconductor ml7000-01/02/03/ml7001-01/02/03 7/19 dg ground for the digital signal circuits. this ground is separate from the analog signal ground ag. the dg pin must be connected to the ag pin on the printed circuit board to make a common analog ground ag. pdn power down control signal. a logic "0" level drives both transmit and receive circuits to a power down state. pcmout pcm signal output. synchronizing with the rising edge of the bclk signal, the pcm output signal is output from msd in a sequential order. msd may be output at the rising edge of the xsync signal, based on the timing between bclk and xsync. this pin is in a high impedance state except during 8-bit pcm output. it is also in a high impedance state during power saving or power down mode. a pull-up resistor must be connected to this pin because its output is configured as an open drain. this device is compatible with the itu-t recommendation on coding law and output coding format. the ml7000-03 (a-law) and ml7001-03 (a-law) output the character signal, inverting the even bits. input/output level +full scale +0 C0 Cfull scale pcmin/pcmout ml7000-02 ( m -law) ml7001-02 ( m -law) msd 1000 0000 1111 1111 0111 1111 0000 0000 ml7000-03 (a-law) ml7001-03 (a-law) msd 1010 1010 1101 0101 0101 0101 0010 1010 lsd lsd
? semiconductor ml7000-01/02/03/ml7001-01/02/03 8/19 sg signal ground voltage output. the output voltage is 1/2 of the power supply voltage. the output drive current capability is 300 m a for ml7000-xx and 200 m a for ml7001-xx. this pin provides the sg level for codec peripherals. this output voltage level is undefined during power-saving or power-down mode. sgc used to generate the signal ground voltage level by connecting a bypass capacitor. connect a 0.1 m f capacitor with excellent high frequency characteristics between the ag pin and the sgc pin. alaw control signal input of the companding law selection. only the ml7000-01ma/ml7000-01mb/ml7001-01ma/ml7001-01mb have this pin. the codec will operate in the m -law when this pin is at a logic "0" level and the codec will operate in the a-law when this pin is at a logic "1" level. the codec operates in the m -law if the pin is left open, since the pin is internally pulled down.
? semiconductor ml7000-01/02/03/ml7001-01/02/03 9/19 absolute maximum ratings recommended operating conditions unit max. typ. min. condition symbol parameter v 5.25 5.00 4.75 v dd power supply voltage c +85 +25 C30 ta operating temperature v pp 2.4 connect ainC and gsx v ain analog input voltage v v dd 2.2 xsync, rsync, bclk, pcmin, pdn, alaw v ih high level input voltage v 0.8 0 v il low level input voltage 64, 96, 128, 192, 200, 256, 384, 512, 768, 1024, 1536, 1544, 2048 bclk f c clock frequency khz khz 9.0 8.0 6.0 xsync, rsync (C40 to +75 c) f s sync pulse frequency % 60 50 40 bclk d c clock duty ratio ns 50 xsync, rsync, bclk, pcmin, pdn t lr digital input rise time ns 50 t lf digital input fall time transmit sync pulse setting time ns 50 bclk ? xsync, see fig. 1 t cx ns 50 xsync ? bclk, see fig. 1 t xc receive sync pulse setting time ns 50 bclk ? rsync, see fig. 1 t cr ns 50 rsync ? bclk, see fig. 1 t rc ns 50 t rs rsync setup time ns 50 t rh rsync hold time ns 50 t ds pcmin setup time ns 50 t dh pcmin hold time k w 0.5 pull-up resistor r dl pf 100 c dl digital output load mv +10 C10 transmit gain stage, gain = 0 db v off mv +100 C100 transmit gain stage, gain = +20 db analog input allowable dc offset ns 1000 xsync, rsync, bclk allowable jitter width 3.30 3.00 2.70 1.2 v dd 0.45 v dd 0.16 v dd 0 ns 50 t xs xsync setup time ns 50 t xh xsync hold time 10.0 8.0 6.0 parameter power supply voltage analog input voltage digital input voltage symbol v dd v ain v din condition rating C0.3 to +7 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 unit v v v values above the dotted line are for ml7000-xx; those below, for ml7001-xx.
? semiconductor ml7000-01/02/03/ml7001-01/02/03 10/19 electrical characteristics dc and digital interface characteristics parameter power supply current high level input voltage low level input voltage high level input leakage current low level input leakage current digital output low voltage digital output leakage current input capacitance symbol i dd1 i dd3 i dd2 v ih v il i ih i il v ol i o condition operating mode power-saving mode, pdn = 1, xsync ? off power-down mode, pdn = 0, bclk off pull-up resistor = 500 w min. 2.2 0.0 0.0 typ. 5.0 1.5 0.01 0.2 max. 12.0 4.0 0.05 v dd 0.8 2.0 0.5 0.4 10 unit ma ma ma v v m a m a v m a c in 5pf (ml7001-xx: v dd = 2.7 v to 3.3 v, ta = C30 to +85c) (ml7000-xx: v dd = +5.0 v 5%, ta = C30 to +85c) no signal 6.5 10.0 v dd = 5.0 v v dd = 3.0 v 2.0 8.0 0.45 v dd 0.0 v dd 0.16 v dd high level input leakage current i ih2 30.0 m a alaw values above the dotted line are for ml7000-xx; those below, for ml7001-xx.
? semiconductor ml7000-01/02/03/ml7001-01/02/03 11/19 transmit analog interface characteristics receive analog interface characteristics input resistance output load resistance output load capacitance r inpw r lvf r lao c lvf c lao pwi 10 20 0.6 30 50 m w k w k w pf pf vfro with respect to sg output amplitude offset voltage v ovf v oao v osvf v osao C1.2 C1.3 C100 C100 +1.2 +1.3 +100 +100 v0p mv mv vfro, r l = 20 k w with respect to sg aout+, aoutC (each) with respect to sg vfro aout+, aoutC aout+, aoutC, r l = 0.6 k w with respect to sg vfro with respect to sg aout+, aoutC, gain = 1 with respect to sg parameter symbol condition min. typ. max. unit (ml7001-xx: v dd = 2.7 v to 3.3 v, ta = C30 to +85c) (ml7000-xx: v dd = +5.0 v 5%, ta = C30 to +85c) C1.0 C1.0 +1.0 +1.0 input resistance output load resistance output load capacitance output amplitude offset voltage r inx r lgx c lgx v ogx v osgx ain+, ainC gain = 1 10 20 C1.2 C20 30 +1.2 +20 m w k w pf v0p mv gsx with respect to sg parameter symbol condition min. typ. max. unit (ml7001-xx: v dd = 2.7 v to 3.3 v, ta = C30 to +85c) (ml7000-xx: v dd = +5.0 v 5%, ta = C30 to +85c) C0.7 +0.7 values above the dotted line are for ml7000-xx; those below, for ml7001-xx. values above the dotted line are for ml7000-xx; those below, for ml7001-xx.
? semiconductor ml7000-01/02/03/ml7001-01/02/03 12/19 ac characteristics condition (ml7001-xx: f s = 8 khz, v dd = 2.7 v to 3.3 v, ta = C30 to +85c) (ml7000-xx: f s = 8 khz, v dd = +5.0 v 5%, ta = C30 to +85c) parameter symbol min. typ. max. unit transmit frequency response loss t1 level (dbm0) 60 20 26 freq. (hz) loss t2 300 C0.15 +0.07 +0.2 loss t3 1020 reference db 0 loss t4 2020 C0.15 C0.04 +0.2 loss t5 3000 C0.15 +0.07 +0.2 loss t6 3400 0 0.4 0.8 receive frequency response loss r1 300 C0.15 C0.03 +0.2 loss r2 1020 reference loss r3 2020 C0.15 0.00 +0.2 db 0 loss r4 3000 C0.15 +0.05 +0.2 loss r5 3400 0 0.54 0.8 sd t1 35 43 3 sd t2 35 41 0 sd t3 35.0 38.0 C30 transmit signal to distortion ratio 1020 db sd t4 26.0 31.0 C40 sd t5 24.0 25.0 C45 sd r1 36 43 3 sd r2 36 41 0 sd r3 36.0 40.0 C30 receive signal to distortion ratio 1020 db sd r4 32.0 C40 sd r5 27.0 C45 transmit gain tracking gt t1 C0.3 +0.01 +0.3 gt t2 reference gt t3 1020 C0.3 C0.05 +0.3 db C40 gt t4 C0.6 C0.05 +0.6 gt t5 C1.2 C0.08 +1.2 3 C10 C50 C55 receive gain tracking gt r1 C0.3 C0.06 +0.3 gt r2 reference gt r3 1020 C0.3 +0.08 +0.3 db gt r4 C0.6 +0.12 +0.6 gt r5 C1.2 +0.15 +1.2 C40 3 C10 C50 C55 *1 32.0 27.0 25.0 25.0 26.0 *1 26.0 30.0 25.0 34.0 38.0 40.0 35.0 *1 psophometric filter is used. values above the dotted line are for ml7000-xx; those below, for ml7001-xx.
? semiconductor ml7000-01/02/03/ml7001-01/02/03 13/19 ac characteristics (continued) absolute level (initial difference) nidle t C73.0 C66.0 dbm0p nidle r C78.0 av t 0.58 0.6007 0.622 av r 0.338 0.35 0.362 vrms 1020 absolute delay av tt C0.2 0.2 0 av rt C0.2 0.2 td 1020 0.6 ms 0 a to a bclk = 64 khz transmit group delay t gd t1 0.19 0.75 t gd t2 0.11 0.35 t gd t3 0.02 0.125 0 t gd t4 0.05 0.125 ms *4 0.07 t gd t5 0.75 receive group delay 0.00 0.75 0.00 0.00 0.125 ms 0 0.09 0.125 0.12 0.75 C71.0 idle channel noise ain = sg *1 *2 *1 *2 db v dd = 5 v 5%, ta = C30 to 85c v dd = 2.7 to 3.3 v, ta = C30 to 85c absolute level (deviation of temperature and power) 500 600 1000 2600 2800 crosstalk attenuation cr t C85 C75 cr r C76 1020 db 0 trans ? recv recv ? trans t gd r1 t gd r2 t gd r3 t gd r4 t gd r5 500 600 1000 2600 2800 *4 C70 0.35 condition (ml7001-xx: f s = 8 khz, v dd = 2.7 v to 3.3 v, ta = C30 to +85c) (ml7000-xx: f s = 8 khz, v dd = +5.0 v 5%, ta = C30 to +85c) parameter symbol min. typ. max. unit level (dbm0) freq. (hz) *3 C65.0 C69.5 C65.0 C75.0 v dd = 5.0 v, ta = 25c v dd = 3.0 v, ta = 25c 0.6007 0.58 0.622 0.483 0.518 0.5 *3 *3 *1 psophometric filter is used. *2 input "0" code to pcmin. *3 avr is defined at vfro output. *4 with respect to minimum value of the group delay distortion. values above the dotted line are for ml7000-xx; those below, for ml7001-xx.
? semiconductor ml7000-01/02/03/ml7001-01/02/03 14/19 ac characteristics (continued) *5 measured under idle channel noise. dis 4.6 khz to 30 32 db digital output delay time t xd1 20 200 t xd2 20 200 ns discrimination 0 0 to 4000 hz c l = 100 pf + 1 lsttl pull-up resistor = 500 w s 300 to C37.5 C35 dbm0 out-of-band spurious 0 4.6 khz to imd fa = 470 C52 C35 dbm0 intermodulation distortion C4 2fa C fb psr t 0 to 30db power supply noise rejection ratio 50 mv pp measured inband *5 psr r 72 khz 3400 fd = 320 50 khz 100 khz condition (ml7001-xx: f s = 8 khz, v dd = 2.7 v to 3.3 v, ta = C30 to +85c) (ml7000-xx: f s = 8 khz, v dd = +5.0 v 5%, ta = C30 to +85c) parameter symbol min. typ. max. unit level (dbm0) freq. (hz)
? semiconductor ml7000-01/02/03/ml7001-01/02/03 15/19 timing diagram pcm data input/output timing figure 1 basic timing bclk 12345678910 xsync pcmout d8 msd t xc t xd1 t xd2 11 12 t xs t xh t cx d2 d3 d4 d5 d6 d7 transmit timing bclk 12345678910 rsync pcmin t rc t ds 11 12 t rs t rh t cr d4 d5 d6 d7 d8 msd d2 d3 t dh receive timing
? semiconductor ml7000-01/02/03/ml7001-01/02/03 16/19 application circuit pcmout xsync ainC gsx ain+ 1 m f pcm signal output 8 khz sync signal input pcm shift clock input pcm signal input control of companding law 1: a-law 0: m -law 0.1 m f 51 k w aout+ sg rsync bclk pcmin alaw aoutC pwi vfro sgc ag v dd 0 v +5 v 51 k w 10 m f + ml7000-01 pdn 0 to 20 w + 5v power down control input 1: normal operation 0: power down 600 w 600:600 600:600 300 w 300 w dg 1 k w 0.1 m f pcmout xsync ainC gsx ain+ 1 m f pcm signal output 8 khz sync signal input pcm shift clock input pcm signal input control of companding law 1: a-law 0: m -law 0.1 m f 51 k w aout+ sg rsync bclk pcmin alaw aoutC pwi vfro sgc ag v dd 0 v +3 v 51 k w 10 m f + ml7001-01 pdn 0 to 20 w +3 v power down control input 1: normal operation 0: power down 600 w 600:600 600:600 300 w 300 w dg 1 k w 0.1 m f
? semiconductor ml7000-01/02/03/ml7001-01/02/03 17/19 notes on use ? to ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. ? connect the ag pin and the dg pin as closely as possible. connect to the system ground with low impedance. ? mount the device directly on the board when mounted on pcbs. do not use ic sockets. if the use of ic socket is unavoidable, use the short lead type socket. ? when mounted on a frame, use electromagnetic shielding if any electromagnetic wave sources such as power supply transformers surrounds the device. ? keep the voltage on the v dd pin not lower than C0.3 v even instantaneously to avoid latch- up that may otherwise occur when power is turned on. ? use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
? semiconductor ml7000-01/02/03/ml7001-01/02/03 18/19 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). sop24-p-430-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.58 typ. mirror finish
? semiconductor ml7000-01/02/03/ml7001-01/02/03 19/19 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop20-p-250-0.95-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.18 typ. mirror finish

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