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? semiconductor components industries, llc, 2009 october, 2009 ? rev. 3 1 publication order number: ncp1219/d ncp1219 pwm controller with adjustable skip level and external latch input the ncp1219 represents a new, pin to pin compatible, generation of the successful 7 ? pin current mode ncp12xx product series. the controller allows for excellent standby power consumption by use of its adjustable skip mode and integrated high voltage startup fet. internal frequency jittering, ramp compensation, timer ? based fault detection and a latch input make this controller an excellent candidate for converters where ruggedness and component cost are the key constraints. the dynamic self supply (dss) drastically simplifies the transformer design in avoiding the use of an auxiliary winding to supply the ncp1219. this feature is particularly useful in applications where the output voltage varies during operation (e.g. battery chargers). due to its high voltage technology, the ic can be directly connected to the high voltage dc rail. features ? fixed ? frequency current ? mode operation with ramp compensation (65 khz and 100 khz options) ? dynamic self supply eliminates the need for an auxiliary winding ? timer ? based fault protection for improved overload detection ? cycle skip reduces input power in standby mode ? latch and auto ? recovery overload protection options ? internal high voltage startup circuit ? accurate current limit detector ( 5%) ? adjustable skip level ? latch input for easy implementation of overvoltage and overtemperature protection ? frequency modulation for softened emi signature ? 500 ma/800 ma peak source/sink current drive capability ? pin to pin compatible with the existing ncp12xx series ? these devices are pb ? free and halogen free/bfr free* typical applications ? ac ? dc adapters for notebooks, lcd monitors ? offline battery chargers ? consumer electronic appliances stb, dvd, dvdr *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soic ? 7 d suffix case 751u http://onsemi.com pin connections (top view) 1219 = specific device code x = overcurrent = (a = latch, b = auto ? retry) z = frequency = (6 = 65 khz, 1 = 100 khz) a = assembly location l = wafer lot y = year w = work week = pb ? free package 1219xz alyw 1 8 marking diagram hv v cc 1 drv gnd cs fb skip/latch see detailed ordering and shipping information in the package dimensions section on page 19 of this data sheet. ordering information
ncp1219 http://onsemi.com 2 figure 1. typical application circuit ncp1219 voltage input output emi filter + ? ac * optional latch input* r ramp * hv drv v cc cs fb skip/latch gnd
ncp1219 http://onsemi.com 3 figure 2. functional block diagram leb skip/latch cs fb 7.5%* jittering oscillator hv drv gnd pwm v fb(open) r s - + - + v fb latch ? off, reset when v cc(on) normal = v cc(min) fault = v cc(hiccup) - + i start when v cc > v inhibit i inhibit when v cc < v inhibit v cs v cc v cc r skip r cs r ramp 16.7k* uvlo latched overload (option a) v latch - skip comparator + 2 v 50 s * filter v skip/latch v skip(max) v skip 51.3k* r upper 42.0k* r lower v dd 0 i ramp(peak) i ramp - + tsd 75 s* filter v cc < v cc(reset) - + v cc(reset) ? + disable internal bias cs maximum duty ratio detect v fb / 3 tovld soft ? start set fault management double hiccup counter clamp detect time v ilim t sstart soft ? start/pwm clamp timer reset (option a) * typical values are shown q r s q r s q
ncp1219 http://onsemi.com 4 table 1. pin function description pin name description 1 skip/latch this pin provides a latch input to permanently disable the device under a fault condition. it also allows the user to adjust the skip threshold. a resistor between this pin and gnd provides noise immunity to the latch input and sets the skip threshold. the voltage on this pin is determined by the combination of the internal voltage divider and the external resistor to ground. the default skip threshold is 1.1 v (typical) if no external resistor is used. an internal clamp prevents the skip level from increasing above 1.3 v if the skip/latch pin is pulled high to latch the controller. 2 fb the voltage on this pin is proportional to the output load on the converter. an internal resistor divider sets the voltage on this pin above the regulation threshold (3 v) and an external optocoupler pulls the pin low to achieve regulation. while the fb voltage is above its regulation threshold, the overload timer is enabled. if the overload timer expires, the controller enters a double hiccup mode (option b) or is latched (option a) depending on the ver- sion of the device. the converter enters skip mode if the fb voltage is below the skip threshold. 3 cs a voltage ramp proportional to the primary current is applied to this pin. the maximum current is reached once the ramp voltage reaches 1 v (typical). a 100 a (typical) current source provides ramp compensation. the amount of ramp compensation is adjusted with a series resistor between the cs pin and the current sense resistor. 4 gnd analog ground. 5 drv main output of the pwm controller. dr v has a source resistance of 12.6 (typical) and a sink resistance of 6.7 (typical). 6 vcc positive input supply. this pin connects to an external capacitor for energy storage. an internal current source supplies current from the hv pin to this pin. once the v cc voltage reaches v cc(on) (12.7 v typical), the current source turns off and the drv is enabled. the current source turns on once v cc falls to v cc(min) (9.9 v typical). this mode of operation is known as dynamic self supply (dss). if the bias current consumption exceeds the startup current, and v cc drops 0.5 v (typical) below v cc(min) the con- verter turns off and enters a double hiccup mode. if the v cc voltage is below 0.67 v (typical) the startup current is reduced to 200 a (typical), reducing power dissipation. 8 hv this is the input of the high voltage startup regulator and connects directly to the bulk voltage. a controlled current source supplies current from this pin to the v cc capacitor, eliminating the need for an external startup resistor. the charge current is 12.8 ma (typical).
ncp1219 http://onsemi.com 5 table 2. maximum ratings (notes 1 ? 4) rating symbol value unit hv voltage v hv ? 0.3 to 500 v hv current i hv 100 ma supply v oltage v cc ? 0.3 to 20 v supply current i cc 100 ma skip/latch v oltage v skip/latch ? 0.3 to 9.5 v skip/latch current i skip/latch 100 ma fb voltage v fb ? 0.3 to 5.0 v fb current i fb 100 ma cs voltage v cs ? 0.3 to 5.0 v cs current i cs 100 ma drv voltage v drv ? 0.3 to 20 v drv current i drv ? 500 to 800 ma operating junction temperature t j ?40 to 150 c storage temperature range t stg ?60 to 150 c power dissipation (t a = 25 c, 2.0 oz cu, 1.0 sq inch printed circuit copper clad) d suffix, plastic package case 751u (soic ? 7) (note 4) p d 0.92 w thermal resistance, junction to ambient (2.0 oz cu printed circuit copper clad) d suffix, plastic package case 751u (soic ? 7) junction to air, low conductivity pcb (note 3) junction to lead, low conductivity pcb (note 3) junction to air, high conductivity pcb (note 4) junction to lead, high conductivity pcb (note 4) r ja r jl r ja r jl 177 75 136 69 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: pins 1? 6: human body model 3000 v per jedec jesd22 ? a114 ? f. pins 1? 6: machine model method 300 v per jedec jesd22 ? a115 ? a. pin 8 is the hv startup of the device and is rated to the maximum rating of the part, or 500 v. 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. 3. as mounted on a 40x40x1.5 mm fr4 substrate with a single layer of 80 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 low conductivity test pcb. test conditions were under natural convection or zero air flow. 4. as mounted on a 40x40x1.5 mm fr4 substrate with a single layer of 650 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 high conductivity test pcb. test conditions were under natural convection or zero air flow.
ncp1219 http://onsemi.com 6 table 3. electrical characteristics (v hv = 60 v, v cc = 11.3 v, v fb = 2 v, v skip/latch = 0 v, v cs = 0 v, v drv = open, c cc = 0.1 f, for typical values t j = 25 c, for min/max values, t j is ?40 c to 125 c, unless otherwise noted) characteristics conditions symbol min typ max unit startup and supply circuits supply v oltage startup threshold minimum operating v oltage undervoltage lockout double hiccup threshold logic reset voltage v cc increasing v cc decreasing v cc decreasing v cc decreasing v cc decreasing v cc(on) v cc(min) uvlo v cc(hiccup) v cc(reset) 11.2 9.0 8.4 4.9 ? 12.7 9.9 9.4 5.7 4.0 13.8 10.8 10.6 6.3 ? v uvlo filter delay t uvlo(delay) ? 50 ? s inhibit threshold v oltage i inhibit = 500 a v inhibit 0.35 0.67 0.90 v inhibit bias current v cc = 0 v i inhibit 100 200 350 a minimum startup v oltage i start = 0.5 ma, v cc = v cc(on) ? 0.5 v v start(min) ? 20 28 v startup current v cc = v cc (on) ? 0.5 v i start 5.5 12.8 18.5 ma startup circuit reverse current v hv = 0 v, v cc = 14 v i hv(reverse) ? ? 100 a off ? state leakage current v hv = 500 v, v cc = 14 v i hv(off) ? 12 50 a breakdown voltage (note 5) i hv = 50 a v br(ds) 500 ? ? v supply current device disabled/fault device enabled/no switching device switching (65 khz) device switching (100 khz) v skip/latch = 5.2 v, v fb = open v skip/latch = open, v fb = 0 v v skip/latch = open, c drv = 1000 pf v skip/latch = open, c drv = 1000 pf i cc1 i cc2 i cc3a i cc3b ? ? ? ? 0.6 1.4 2.2 2.4 0.8 2.1 2.7 3.2 ma current sense current sense voltage threshold apply voltage step on cs pin v ilim 0.95 1.0 1.05 v leading edge blanking duration t leb 100 184 330 ns propagation delay v cs > v ilim to 50% drv turns off, c drv = 1000 pf t delay ? 59 150 ns ramp compensation peak current i ramp(peak) ? 100 ? a ramp compensation valley current i ramp(valley) ? 0 ? a feedback input open feedback voltage v fb(open) 3.2 3.6 3.9 v internal pull ? up resistance r fb ? 16.7 ? k feedback pull ? up current v fb = 0 v i fb 141 280 392 a feedback to current set point ratio i ratio ? 3.0 ? soft ? start soft ? start period measured at 0.9 v ilim t sstart ? 4.8 ? ms oscillator oscillator frequency 65 khz option 100 khz option t j = 25 c t j = ? 40 c to 85 c t j = ? 40 c to 125 c t j = 25 c t j = ? 40 c to 85 c t j = ? 40 c to 125 c f osc 61.75 58 55 95 89 85 65 ? ? 100 ? ? 68.25 71 71 105 107 107 khz frequency modulation in percentage of f osc ? 7.5 ? % frequency modulation period ? 6.0 ? ms maximum duty ratio d 75 80 85 % 5. guaranteed by the i hv(off) test. 6. guaranteed by design only.
ncp1219 http://onsemi.com 7 table 3. electrical characteristics (v hv = 60 v, v cc = 11.3 v, v fb = 2 v, v skip/latch = 0 v, v cs = 0 v, v drv = open, c cc = 0.1 f, for typical values t j = 25 c, for min/max values, t j is ?40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions gate drive drive resistance drv sink drv source v fb = 0 v, v drv = 1 v v drv = v cc ? 1 v r snk r src 2.0 6.0 6.7 12.6 13 25 rise time (10% to 90%) c drv = 1000 pf (10% to 90%) t r ? 30 ? ns fall time (90% to 10%) c drv = 1000 pf (90% to 10%) t f ? 20 ? ns latch input latch voltage threshold v latch 3.4 3.9 4.6 v latch filter delay v skip/latch = 5.2 v, apply voltage step on skip/latch pin t latch(delay) ? 50 ? s cycle skip default skip threshold v fb increasing, v skip/latch = open v skip 0.9 1.1 1.3 v skip clamp voltage v fb increasing, v skip/latch = 2.0 v v skip(max) 1.1 1.3 1.5 v skip comparator hysteresis v fb decreasing, v skip/latch = 0.5 v v skip(hys1) ? 75 ? mv skip clamp comparator hysteresis v fb decreasing, v skip/latch = 2.0 v v skip(hys2) ? 75 ? mv skip current v skip/latch = 0 v i skip 30 47 56 a faults protection thermal shutdown (note 6) temperature increasing t shdn ? 155 ? c thermal shutdown hysteresis temperature decreasing t shdn(hys) ? 40 ? c thermal shutdown delay t shdn(delay) ? 75 ? s overload t imer apply voltage step on fb pin t ovld ? 118 ? ms 5. guaranteed by the i hv(off) test. 6. guaranteed by design only.
ncp1219 http://onsemi.com 8 typical characteristics figure 3. supply voltage thresholds vs. junction temperature figure 4. inhibit threshold voltage vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 5 6 7 9 10 12 14 15 125 100 75 50 25 0 ? 25 ? 50 0 0.14 0.42 0.56 0.70 0.98 1.26 1.40 figure 5. inhibit current vs. junction temperature figure 6. startup current vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 100 120 140 180 220 240 280 300 125 100 75 50 25 0 ? 25 ? 50 10.0 10.5 11.5 12.0 12.5 13.5 14.0 15.0 figure 7. startup current vs. su pply voltage figure 8. startup circuit leakage current vs. junction temperature v cc , supply voltage (v) t j , junction temperature ( c) 18 16 10 8 6 4 2 0 0 2 4 6 8 10 14 16 125 100 75 50 25 0 ? 25 ? 50 0 3 9 12 18 21 27 30 v cc , supply voltage thresholds (v) v inhibit , inhibit threshold voltage (v) i inhibit , inhibit current ( a) i start , startup current (ma) i start , startup current (ma) i start(off) , startup circuit leakage current ( a) 150 8 11 13 150 0.28 0.84 1.12 i inhibit = 500 a v cc(on) v cc(min) uvlo v cc(reset) 150 160 200 260 v cc = 0 v v hv = 60 v v cc = v cc(on) ? 0.5 v 150 11.0 13.0 14.5 12 14 20 12 v hv = 60 v 150 6 15 24 v hv = 60 v v cc = 14 v
ncp1219 http://onsemi.com 9 typical characteristics figure 9. startup circuit leakage current vs. hv voltage figure 10. supply current vs. junction temperature v hv , hv voltage (v) t j , junction temperature ( c) 450 375 300 525 225 150 75 0 0 5 10 20 30 35 40 50 figure 11. operating supply current vs. supply voltage figure 12. current sense voltage threshold vs. junction temperature v cc , supply voltage (v) t j , junction temperature ( c) 21 19 17 15 13 11 9 0 0.5 1.0 1.5 2.0 3.0 3.5 4.0 125 100 75 50 25 0 ? 25 ? 50 0.95 0.96 0.98 1.00 1.02 1.04 1.05 figure 13. leading edge blanking time vs. junction temperature figure 14. current sense propagation delay vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 100 120 140 160 180 200 220 240 125 100 75 50 25 0 ? 25 ? 50 25 35 55 65 95 105 i start(off) , startup circuit leakage current ( a) i cc , supply current (ma) i cc3 , operating supply current (ma) v ilim , current sense voltage threshold (v) t leb , leading edge blanking time (ns) t delay , current sense propagation delay (ns) 15 25 45 t j = ? 40 c t j = 125 c 2.5 t j = 25 c 150 150 150 45 75 85 i cc3 (f osc ~ 65 khz) i cc2 i cc1 20 18 16 14 12 10 0.97 0.99 1.01 1.03 260 280 300 115 125 v cc = 14 v f osc = 65 khz 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 ? 50 ? 25 0 25 50 75 100 125 150 i cc3 (f osc ~ 100 khz) f osc = 100 khz
ncp1219 http://onsemi.com 10 typical characteristics figure 15. oscillator frequency vs. junction temperature figure 16. maximum duty ratio vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 75 76 78 79 81 82 84 85 figure 17. drive sink and source resistances vs. junction temperature figure 18. latch voltage threshold vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0 2 4 8 10 14 16 20 125 100 75 50 25 0 ? 25 ? 50 3.0 3.2 3.4 3.8 4.2 4.4 4.6 5.0 figure 19. default skip threshold vs. junction temperature figure 20. skip clamp voltage vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.80 0.85 0.90 1.00 1.05 1.10 1.25 1.30 125 100 75 50 25 0 ? 25 ? 50 1.05 1.10 1.15 1.25 1.30 1.40 1.50 1.55 f osc , oscillat or frequency (khz) d, maximum duty ratio (%) r snk /r src , drive sink/source resistance ( ) v latch , latch voltage threshold (v) v skip , default skip threshold (v) v skip(max) , skip clamp voltage (v) 150 77 80 83 150 6 12 18 source, v drv = v cc ? 1 v sink, v drv = 1 v 150 3.6 4.0 4.8 0.95 1.15 1.20 150 v skip/latch = open v skip/latch = 2 v 150 1.20 1.35 1.45 v cc = 11.3 v 40 50 60 70 80 90 100 110 120 ? 50 ? 25 0 25 50 75 100 125 150 65 khz option 100 khz option
ncp1219 http://onsemi.com 11 typical characteristics figure 21. adjustable skip threshold vs. junction temperature figure 22. skip threshold vs. skip resistor t j , junction temperature ( c) r skip , external skip resistor (k ) 125 100 75 50 25 0 ? 25 ? 50 0.2 0.3 0.4 0.5 0.7 0.8 0.9 1.0 1000 100 10 1 0 0.2 0.4 0.6 0.8 1.0 1.2 figure 23. soft ? start period vs. junction temperature figure 24. overload timer period vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0 1 2 3 6 7 9 10 125 100 75 50 25 0 ? 25 ? 50 90 95 105 110 120 125 135 140 v skip2 , adjustable skip threshold (v) v skip , skip threshold (v) t sstart , soft ? start period (ms) t ovld , overload timer period (ms) 150 0.6 r skip = 48.7 k 10000 150 4 5 8 150 100 115 130 1.1 1.2
ncp1219 http://onsemi.com 12 detailed operating description the ncp1219 is part of a product family of current mode controllers designed for ac ? dc applications requiring low standby power. the controller operates in skip or burst mode at light load. its high integration reduces component count resulting in a more compact and lower cost power supply. this device family has 2 options, a and b. option a latches where as option b auto restarts after an overload fault. the internal high voltage startup circuit with dynamic self supply (dss) allows the controller to operate without an auxiliary supply, simplifying the transformer design. this feature is particularly useful in applications where the output voltage varies during operation (e.g. printer adapters). other features found in the ncp1219 are frequency jittering, adjustable ramp compensation, timer based fault detection and a dedicated latch input. high voltage startup circuit the ncp1219 internal high voltage startup circuit eliminates the need for external startup components and provides a faster startup time compared to an external startup resistor. the startup circuit consists of a constant current source that supplies current from the hv pin to the supply capacitor on the v cc pin (c cc ). the hv pin is rated at 500 v allowing direct connection to the bulk capacitor. the start ? up current (i start ) is typically 12.8 ma. the startup current source is disabled once the v cc voltage reaches v cc(on) , typically 12.7 v. the controller is then biased by the v cc capacitor. the current source is enabled once the v cc voltage decays to its minimum operating threshold (v cc(min) ) typically 9.9 v. if the supply current consumption exceeds the startup current, v cc will decay below v cc(min) . the ncp1219 has an undervoltage lockout (uvlo) to prevent operation at low v cc levels. the uvlo threshold is typically 9.4 v. the drv signal is immediately disabled upon reaching uvlo. it is re ? enabled if v cc increases above uvlo before the 50 s (typical) timer expires. otherwise, the controller enters double hiccup mode. the controller enters a double hiccup mode if an overload (option b), thermal shutdown, uvlo or latch fault is detected. a double hiccup fault disables the drv signal, sets the controller in a low current mode and allows v cc to discharge to v cc(hiccup) , typically 5.7 v. this cycle is repeated twice to minimize power dissipation in external components during a fault event. figures 25 and 26 show double hiccup mode operation with a fault occurring while the startup circuit is disabled and enabled, respectively. a soft ? start sequence is initiated the second time v cc reaches v cc(on) . if the fault is present or the controller is latched upon reaching v cc(on) , the controller stays in hiccup mode. during this mode, v cc never drops below 4 v, the controller logic reset level. this prevents latched faults from being cleared unless power to the controller is completely removed (i.e. unplugging the supply from the ac line). there are two options available in the ncp1219, options a and b. option a latches off after the overload timer expires if an overload fault is detected. in this case, v cc cycles between v cc(on) and v cc(hiccup) without enabling the drv signal until the power to the controller is reset. on the other hand, option b has auto ? retry circuitry allowing the drv signal to restart after a double hiccup sequence triggered by an overload condition. uvlo fault1 drv on off on fault figure 25. v cc double hiccup operation with a fault occurring while the startup circuit is disabled. v cc(reset) v cc(on) v cc(min) v cc(hiccup)
ncp1219 http://onsemi.com 13 on off on fault figure 26. v cc double hiccup operation with a fault occurring while the startup circuit is enabled uvlo fault2 drv v cc(reset) v cc(on) v cc(min) v cc(hiccup) an internal supervisory circuit monitors the v cc voltage to prevent the controller from dissipating excessive power if the v cc pin is accidentally grounded. a lower level current source (i inhibit ) charges c cc from 0 v to v inhibit , typically 0.67 v. once v cc exceeds v inhibit , the startup current source is enabled. this behavior is illustrated in figure 27. this slightly increases the total time to charge v cc , but it is generally not noticeable. figure 27. startup current at various v cc levels v cc v cc(on) v cc(min) v inhibit startup current i start i inhibit the start ? up circuit is rated at a maximum voltage of 500 v. if the device operates in the dss mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. if dissipation on the controller is excessive, a resistor can be placed in series with the hv pin. this will reduce power dissipation on the controller and transfer it to the series resistor. standby mode losses and normal mode power dissipation can be reduced by biasing the controller with an auxiliary winding. the auxiliary winding needs to maintain v cc above v cc(min) once the startup circuit is disabled. the power dissipation of the controller when operated in dss mode, p dss , can be calculated using equation 1, where i cc3 is the operating current of the ncp1219 during switching and v hv is the voltage at the hv pin. the hv pin is most often connected to the bulk capacitor. p dss i cc3 (v hv v cc ) (eq. 1) in comparison, the power dissipation when the startup circuit is disabled and v cc is being supplied by the auxiliary winding is a function of the v cc voltage. this is shown in equation 2. p aux i cc3 v cc (eq. 2) it is recommended that an external filter capacitor be placed as close as possible to the v cc pin to improve the noise immunity. soft ? start operation figures 28 and 29 show how the soft ? start feature is included in the pulse ? width modulation (pwm) comparator. when the ncp1219 starts up, a soft ? start voltage v sstart begins at 0 v. v sstart increases gradually from 0 v to 1.0 v in 4.8 ms and stays at 1.0 v afterward. v sstart is compared with the divided by 3 feedback pin voltage (v fb /3). the lesser of v sstart and (v fb /3) becomes the modulation voltage, v pwm , in the pwm duty ratio generation. initially, (v fb /3) is above 1.0 v because the fb pin is brought to v fb(open) , typically 3.6 v, by the internal pullup resistor. as a result, v pwm is limited by the soft ? start function and slowly ramps up the duty ratio (and therefore the primary current) for the initial 4.8 ms. this provides a greatly reduced stress on the power devices during startup. figure 28. v pwm is the lesser of v sstart and (v fb /3) ? v pwm v sstart v fb /3 01
ncp1219 http://onsemi.com 14 figure 29. soft ? start (time = 0 at v cc = v cc(on) ) time time time time must be less than t ovld to prevent fault condition time 1 v soft ? start voltage, v sstart t sstart 1 v feedback pin voltage divided by 3, v fb /3 t sstart t sstart drain current, i d 1 v pulse width modulation voltage, v pwm current ? mode pulse width modulation the ncp1219 is a current ? mode, fixed frequency pulse width modulation controller with ramp compensation. the pwm block of the ncp1219 is shown in figure 30. the drv signal is enabled by a clock pulse. at this time, current begins to flow in the power mosfet and the sense resistor. a corresponding voltage is generated on the cs pin of the device, ranging from very low to as high as the maximum modulation voltage, v pwm (maximum of 1 v). this sets the primary current on a cycle ? by ? cycle basis. equation 3 gives the maximum drain current, i d(max) , where r cs is the current sense resistor value and v ilim is the current sense voltage threshold. i d(max) v ilim r cs (eq. 3) figure 30. current ? mode implementation leb cs pwm output 180 ns + ? (1 v max. signal) clock i ramp(peak) v bulk i d r cs v cs q s 80% max duty r v pwm i ramp figure 31 shows the timing diagram for the current ? mode pulse width modulation operation. an internal clock sets the output rs latch, pulling the drv pin high. the latch is then reset when the voltage on the cs pin intersects the modulation voltage, v pwm . this generates the duty ratio of the drv pulse. the maximum duty ratio is internally limited to 80% (typical) by the output rs latch. figure 31. current ? mode timing diagram pwm output clock v pwm v cs the v pwm voltage is the scaled representation of the fb pin voltage. the scale factor, i ratio , is 3. the fb pin voltage is provided by an external error amplifier, whose output is a function of the power supply output. an fb signal between v skip and 3 v determines the duty ratio of the controller output. the fb voltage operates in a closed loop with the output voltage to regulate the power supply. it is recommended that an external filter capacitor be placed as close to the fb pin as possible to improve the noise immunity.
ncp1219 http://onsemi.com 15 ramp compensation ramp compensation is a known mean to cure subharmonic oscillations. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty ratio greater than 50%. to lower the current loop gain, one usually injects 50 to 75% of the inductor current down slope. the ncp1219 generates an internal current ramp that is synchronized with the clock. this current ramp is then routed to the cs pin. figures 32 and 33 depict how the ramp is generated and utilized. ramp compensation is simply formed by placing a resistor, r ramp , between the cs pin and the sense resistor. figure 32. internal ramp compensation current source 0 time 80% of period 100% of period i ramp(peak) ramp current, i ramp figure 33. inserting a resistor in series with the current sense information provides ramp compensation clock oscillator drv cs current ramp i ramp(peak) r ramp r cs in order to calculate the value of the ramp compensation resistor, r ramp , the off time primary current slope, s off,primary must be calculated using equation 4, s off,primary (v out v f ) n p n s l p (eq. 4) where v out is the converter output voltage, v f is the forward diode drop of the secondary diode, n p /n s is the primary to secondary turns ratio, and l p is the primary inductance of the transformer. the value of r ramp can be calculated using equation 5, r ramp s off,primary r cs %slope i ramp(peak) f osc d (eq. 5) where r cs is the current sense resistor and %slope is the percentage of the current downslope to be used for ramp compensation. the ncp1219 has a peak ramp compensation current of 100 a. a frequency of 65 khz with an 80% maximum duty ratio corresponds to an 8.1 a/ s ramp. for a typical flyback design, let?s assume that the primary inductance is 350 h, the converter output is 19 v, the v f of the output diode is 1 v and the n p :n s ratio is 10:1. the off time primary current slope is given by equation 6. (v out v f ) n p n s l p 571 ma s (eq. 6) when projected over an r cs of 0.1 (for example), this becomes 57 mv/ s. if we select 50% of the downslope as the required amount of ramp compensation, then we shall inject 28.5 mv/ s. therefore, r ramp is simply equal to equation 7. r ramp 28.5 mv s 8.1 a s 3.5 k (eq. 7) ramp compensation greater than 50% of the inductor down slope can be used if necessary; however, overcompensating will degrade the transient response of the system. the addition of ramp compensation also reduces the total available output power of the system. internal oscillator the internal oscillator of the ncp1219 provides the clock signal that sets the drv signal high and limits the duty ratio to 80% (typical). the oscillator has a fixed frequency of 65 khz or 100 khz. the ncp1219 employs frequency jittering to smooth the emi signature of the system by spreading the energy of the main switching component across a range of frequencies. an internal low frequency oscillator continuously varies the switching frequency of the controller by 7.5%. the period of modulation is 6 ms, typical. figure 34 illustrates the oscillator frequency modulation.
ncp1219 http://onsemi.com 16 figure 34. oscillator frequency modulation time oscillator frequency f osc ? 7.5% f osc + 7.5% f osc 6 ms gate drive the output drive of the ncp1219 is designed to directly drive the gate of an n ? channel power mosfet. the drv pin is capable of sourcing 500 ma and sinking 800 ma of drive current. it has typical rise and fall times of 30 ns and 20 ns, respectively, driving a 1 nf capacitive load. the power dissipation of the output stage while driving the capacitance of the power mosfet must be considered when calculating the ncp1219 power dissipation. the driver power dissipation can be calculated using equation 8, p drv f osc q g v cc (eq. 8) where q g is the gate charge of the power mosfet. external latch input board level protection functionality is often incorporated using external circuits to suit a specific application. an external fault condition can be used to disable the controller by bringing the voltage on the skip/latch pin above the latch threshold, v latch (3.9 v typical). when an external fault condition is detected, the drv signal is stopped, and the controller enters low current operation mode. the external capacitor c cc discharges and v cc drops until v cc(hiccup) is reached. the high voltage startup circuit turns on and i start charges c cc until v cc(on) is reached. v cc cycles between v cc(on) and v cc(hiccup) until v cc reaches v cc(reset) . voltage must be removed from the hv pin, disabling the startup current and allowing c cc to discharge to v cc(reset) . therefore, the controller is reset by unplugging the power supply from the wall to allow v bulk to discharge. figure 35 illustrates the timing diagram of v cc in the latch ? off condition. figure 35. latch ? off v cc timing diagram v cc(hiccup) v cc(on) startup current source is charging the v cc capacitor startup current source is off when v cc is v cc(on) startup current source turns on when v cc reaches v cc(hiccup) time the external latch feature allows the circuit designers to implement dif ferent kinds of latching protection. figure 36 shows an example circuit in which a bipolar transistor is used to pull the skip/latch pin above the latch threshold. the r lim value is chosen to prevent the skip/latch pin from exceeding the maximum rated voltage. the ncp1219 applications note (and8393/d) details several simple circuits to implement overtemperature protection (otp) and overvoltage protection (ovp). figure 36. circuit example of an external latch ? off circuit r skip c skip r lim v cc ncp1219 skip/latch fb gnd cs vcc drv fault output hv an internal blanking filter prevents fast voltage spikes caused by noise from latching the part. however, it is recommended that an external filter capacitor be placed as close as possible to the skip/latch pin to further improve the noise immunity.
ncp1219 http://onsemi.com 17 skip cycle operation during standby or light load operation the duty ratio on the controller becomes very small. at this point, a significant portion of the power dissipation is related to the power mosfet switching on and off. to reduce this power dissipation, the ncp1219 ?skips? pulses when the fb level drops below the skip threshold. the level at which this occurs is completely adjustable by setting a resistor on the skip/latch pin. by discontinuing pulses, the output voltage slowly drops and the fb voltage rises. when the fb voltage rises above the v skip level, drv is turned back on. this feature produces the timing diagram shown in figure 37. figure 37. skip operation v v fb i d skip skip skip peak current, %i csskip , is the percentage of the maximum peak current at which the controller enters skip mode. %i csskip can be any value from 0 to 43% as defined by equation 9. however, the higher %i csskip is, the greater the drain current when skip is entered. this increases acoustic noise. conversely, the lower %i csskip is, the larger the percentage of energy is expended turning the switch on and off. therefore, it is important to adjust %i csskip to the optimal level for a given application. %i csskip v skip 3v 100 (eq. 9) figure 38 shows the details of the skip/latch pin circuitry. the voltage on the skip/latch pin determines the voltage required on the fb pin to place the controller into skip mode. if the pin is left open, the default skip threshold is 1.1 v. this corresponds to a 37% %i csskip (%i csskip = 1.1 v / 3.0 v * 100% = 37%). therefore, the controller will enter skip mode when the peak current is less than 37% of the maximum peak current. figure 38. skip adjust circuit skip/latch s r q - + v fb latch-off, reset when v cc < v cc(reset) r skip v latch - skip comparator + 2 v 50 us filter v skip/latch v skip(max) v skip 51.3 k r upper 42.0 k r lower - + c skip v skip/latch to drv latch reset the skip level is reduced by placing an external resistor, r skip , between the skip/latch and gnd pins. figure 39 summarizes the operating voltage regions of the skip/latch pin.
ncp1219 http://onsemi.com 18 figure 39. ncp1219 vskip/latch pin operating regions controller is latched adjustable v skip range. 0 v (no skip) v skip(max) (maximum skip threshold) v latch 9.5 v (maximum pin voltage) v skip/latch skip threshold clamped to v skip(max) within the adjustable v skip range, the skip level changes according to equation 10. v skip 2v (r lower r skip ) (r lower r skip ) r upper (eq. 10) an internal clamp limits the skip threshold (v skip(max) ) to 1.3 v. increasing the voltage on the skip/latch pin beyond the value of the internal clamp will induce no further change in the skip level. this prevents the act of disabling the controller in the presence of an external latch event from causing it to enter skip mode. the relationship between %i csskip , v skip/latch , v skip , and r skip is summarized in table 4. table 4. %i csskip and skip threshold relationship with r skip %ics skip v skip/latch v skip r skip comment 0% 0 v 0 v 0 never skips 12% 0.36 v 0.36 v 11.8 k ? 25% 0.75 v 0.75 v 52.3 k ? 37% 1.10 v 1.10 v open default skip threshold 43% 2.00 v 1.30 v ? no further increase in skip threshold 43 % 3.00 v 1.30 v ? no further increase in skip threshold external non ? latched shutdown figure 40 summarizes the operating regions of the fb pin. an external non ? latched shutdown can be easily implemented by simply pulling fb below the skip level. this is an inherent feature of the standby skip operation, allowing additional flexibility in the smps design. figure 40. ncp1219 operation threshold fault operation when staying in this region longer than 118 ms pwm operation no drv pulses 3 v v fb 0 v v skip figure 41 shows an example implementation of a non ? latched shutdown circuit using a bipolar transistor to pull the fb pin low. figure 41. example circuit for non ? latched shutdown ncp1219 off opto coupler skip/latch cs fb gnd vcc drv hv overload protection figure 42 details the timer based fault detection circuitry. when an overload (or short circuit) event occurs, the output voltage collapses and the optocoupler does not conduct current. this opens the fb pin and v fb is internally pulled higher than 3.0 v. since v fb /3 is greater than 1 v, the controller activates an error flag and starts a timer, t ovld (118 ms typical). if the output recovers during this time, the timer is reset and the device continues to operate normally.
ncp1219 http://onsemi.com 19 however, if the fault lasts for more than 118 ms, then the driver turns off and the device enters the v cc double hiccup mode described earlier. figure 42. block diagram of timer ? based fault detection soft ? start fb 118 ms delay 1 v max fault ? + v ss v fb disable drv v fb 3 4.8 v the ncp1219 also has an internal temperature shutdown circuit. if the junction temperature of the controller reaches 155 c (typical), the driver turns off and the controller enters double hiccup mode. latched and auto ? retry options the ncp1219a offers a latched fault circuitry. an overload fault condition detected by the controller results in a latch ? off shutdown, requiring the controller to be reset by cycling v cc (removing the ac line input). ncp1219b provides an auto ? retry circuit. all fault conditions except the external latch fault result in the controller entering double hiccup mode, attempting to restart the controller every other v cc cycle, as mentioned earlier. table 5. ordering information device overcurrent frequency package shipping ? ncp1219ad65r2g latch 65 khz soic ? 7 (pb ? free) 2500 / tape & reel NCP1219BD65R2G auto ? recovery 65 khz ncp1219ad100r2g latch 100 khz ncp1219bd100r2g auto ? recovery 100 khz ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd801 1/d.
ncp1219 http://onsemi.com 20 package dimensions soic ? 7 case 751u ? 01 issue d seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? a ? ? b ? g m b m 0.25 (0.010) ? t ? b m 0.25 (0.010) t s a s m 7 pl on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1219/d the products described herein (ncp1219) may be covered by one or more of the following u.s. patents: 6,271,735, 6,362,067, 6,38 5,060, 6,597,221, 6,633,193, 6,587,351, 6,940,320. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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