2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcomputer mitsubishi description the 32182 group is a 32-bit, single-chip risc microcom- puter with built-in flash memory, which was developed for use in general industrial and household equipment. to ac- complish high-precision arithmetic operations, it incorpo- rates a fully ieee754 compliant, single-precision fpu. this microcomputer contains a variety of peripheral func- tions ranging from 12-channel a-d converters, 37-channel multijunction timers, 10-channel dmacs, 4-channel serial i/os, and 1-channel real-time debugger. also included are 2-channel full-can modules and jtag (boundary scan facility). with the software necessary to run these numerous peripheral functions stored in its large-capacity flash mem- ory, this microcomputer meets the needs of application sys- tems for high functionality, high-performance arithmetic ca- pability, and sophisticated control. with lower power consumption and low noise characteris- tics also considered, these microcomputers are ideal for embedded equipment applications. features m32r-fpu core uses the m32r family risc cpu core (m32r family common instruction set + single-precision fpu/extended instructions) five-stage pipelined processing sixteen 32-bit general-purpose registers 16-bit/32-bit instructions implemented dsp function instructions (multiply-accumulate calculation using 56-bit accumulator) built-in single-precision fpu (fully compliant with ieee754 standard: four rounding modes, etc.) bit manipulation extended instructions built-in flash memory ........................................ 384k bytes built-in flash programming boot program built-in ram ....................................................... 64k bytes pll clock generating circuit.............. built-in x 8 pll circuit oscillation stop detection function maximum operating frequency of the cpu clock type name frequency temperature rang m32182f3vfp 64mhz -40c to +125c M32182F3TFP 80mhz -40c to +85c single power supply: 5 v (+ 0.5 v) or 3.3 v (+ 0.3 v) 37-channel multijunction timers (mjt) multijunction timers are incorporated that support various purposes of use. 16-bit output related timers (top) ................... 11 channels 16-bit input/output related timers (tio)............ 10 channels 16-bit input related timers (tms) ....................... 8 channels 32-bit input related timers (tml) ....................... 8 channels flexible configuration is possible through interconnection of timers. the internal dmac and a-d converter can be started by a timer. real-time debugger includes dedicated clock-synchronized serial i/o that can read and write the contents of the internal ram independ- ently of the cpu. can look up and update the data table in real time while the program is running. can generate a dedicated interrupt based on rtd com- munication. abundant internal peripheral functions in addition to the timers and real-time debugger, the micro- computer contains the following peripheral functions. dmac ............................................................. 10 channels a-d converters (sample & hold mode, disconnection de- tector assist function, injection current bypass circuit) ..................................... 12 channels 10-bit converter serial i/o ........................................................... 4 channels interrupt controller: 23 interrupt sources, 8 priority levels wait controller full can(can specification 2.0b active).......... 2 channels virtual-flash emulation function .......... 4k bytes x 8 banks jtag (boundary scan function, mitsubishi original sdi debug function) port input threshold level select function designed to operate at high temperatures to meet the need for use at high temperatures, m32182f3vfp is designed to be able to operate in the temperature range of -40 to +125c when cpu clock oper- ating frequency = 64 mhz. M32182F3TFP is designed to be able to operate in the temperature range of -40 to +85c when cpu clock operating frequency = 80 mhz. applications automobile equipment control (e.g., engine, abs, and at), industrial equipment system control, and high-function oa equipment (e.g., ppc)
2002-07-04 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcomputer 2 m32182f3vfp M32182F3TFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 p97/to20 p117/to7 p116/to6 p115/to5 p114/to4 p113/to3 p112/to2 p111/to1 p110/to0 p127/tclk3 p126/tclk2 p125/tclk1 p124/tclk0 excvcc vcce vss vss sbi# p63 p62 p61 ad0in11 ad0in10 ad0in9 ad0in8 avss0 ad0in7 ad0in6 ad0in5 ad0in4 ad0in3 ad0in2 ad0in1 ad0in0 vref0 avcc0 p150/tin0 p153/tin3 p130/tin16 p131/tin17 p132/tin18 p133/tin19 p134/tin20 p135/tin21/rxd3 p136/tin22/crx1 p137/tin23 p220/ctx0 p221/crx0 vcce vcnt osc-vcc xin osc-vss xout reset# p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk jtdi jtdo jtrst jtck jtms p100/to8 p101/to9/txd3 p102/to10/ctx1 p103/to11 p104/to12 p105/to13 p106/to14 p107/to15 p174/txd2 p175/rxd2 fp mod0 mod1 excvdd vss excvcc vdde vss vcce p17/db15 p16/db14 p15/db13 p14/db12 p13/db11 p12/db10 p11/db9 p10/db8 p07/db7 p06/db6 p05/db5 p04/db4 p03/db3 p02/db2 p01/db1 p00/db0 p73/hack# p72/hreq# p71/wait# p70/bclk/wr# p43/rd# p42/bhw#/bhe# p41/blw#/ble# vcc-bus vss p82/txd0 p83/rxd0 p84/sclki0/sclko0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 vss vcce p44/cs0# p45/cs1# p224/a11/cs2# p225/a12/cs3# p46/a13 p47/a14 p30/a15 p31/a16 p32/a17 p33/a18 p34/a19 p35/a20 p36/a21 p37/a22 p20/a23 p21/a24 p22/a25 p23/a26 p24/a27 p25/a28 p26/a29 p27/a30 vcc-bus vss p93/to16 p94/to17 p95/to18 p96/to19 package 144p6q-a pin assignment (top view) note: it is shown that the pin (signal) with which "#" sticks to the last of a pin name (signal name) is "l" active pin (signal ). figure 1. pin layout diagram
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 3 pll clock generation circuit internal bus interface address data internal ram (64k bytes) internal flash memory (384k bytes) m32r-fpu core (max. 80mhz) multiplier accumulator (32x16+56) dmac (10 channels) input/output timer (37 channels) serial i/o (4 channels) a-d converter (a-d0 : 10-bit,12 channels) wait controller interupt controller (8 priority levels) real-time debugger (rtd) external bus interface internal 32-bit bus input/output port 97 ports full can (2 channels) single-precision fpu (fully ieee754 compliant) internal 16-bit bus internal 32-bit bus internal power supply generation circuit (vdc) figure 2. block diagram
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 4 table 1. outline performance functional block features m32r-fpu core m32r family cpu core, internally configured in 32-bit built-in multiplier-accumulator (32 x 16 + 56) basic bus cycle m32182f3vfp: 15.625 ns (cpu clock frequency at 64 mhz, internal peripheral clock frequency at 16mhz) M32182F3TFP: 12.5 ns (cpu clock frequency at 80 mhz, internal peripheral clock frequency at 20mhz) logical address space: 4g bytes, linear general-purpose register: 32-bit register x 16,control register: 32-bit register x 6 accumulator: 56-bit external data bus 16-bit data bus instruction set 16-bit/32-bit instruction formats 100 discrete instructions in six addressing modes internal flash mem- ory 384k bytes rewrite durability: 100 times internal ram 64k bytes dmac 10 channels (dma transfers between internal peripheral i/os, between internal peripheral i/o and internal ram, and between internal rams) channels can be cascaded and can operate in combination with internal peripheral i/o multijunction timer 37 channels of multijunction timers. top : 16-bit output related timer, 11 channels (single-shot, delayed single-shot, and continuous) tio : 16-bit input/output related timer, 10 channels (measure clear, measure free-run, noise processing input, pwm, single-shot, delayed single-shot, continuous output) tms : 16-bit input related timer, 8 channels (measure input) tml : 32-bit input related timer, 8 channels (measure input) flexible timer configuration is possible through interconnection of channels using the clock bus or event bus. a-d converter 10-bit multifunction a-d converters input 12 channels scan-based conversion can be switched between n (n = 1 to 12) channels capable of interrupt conversion during scan 8-bit/10-bit readout function available with sample & hold mode disconnection detector assist function injection current bypass circuit serial i/o 4 channels (the serial i/os can be set for synchronous serial i/o or uart. sio2, sio3 are uart mode only) real-time debugger (rtd) 1-channels dedicated clock-synchronized serial h?0080 4000 to h?0081 3fff: internal ram area can access the internal ram for read/rewrite from outside independently of the cpu, and also generate an exclusive-use interrupt. interrupt controller controls interrupts from internal peripheral i/os (priority can be set to one of 8 levels including interrupt disabled) wait controller controls wait when accessing external extended area (chip selects for four external extended areas each can have access extended for 0-7 wait cycles plus wait# signal entered from external source) (note1) can two channels, each having 16-channel message slots jtag boundary-scan function, built-in sdi debugger function in mitsubishi clock m32182f3vfp: cpu clock: maximum 64 mhz (for cpu, internal rom, and internal ram access) internal peripheral clock (bclk): maximum 16 mhz (for peripheral module access) external input clock (xin): maximum 8.0 mhz, built-in x8 pll circuit M32182F3TFP: cpu clock: maximum 80 mhz (for cpu, internal rom, and internal ram access) internal peripheral clock (bclk): maximum 20 mhz (for peripheral module access) external input clock (xin): maximum 10.0 mhz, built-in x8 pll circuit power supply volt- age 5v (+ 0.5v) or 3.3v (+ 0.3v) [t.b.d]: single power supply voltage (the internal logic operates with 2.5v, however) operating tempera- ture range m32182f3vfp: -40 to +125c (cpu clock 64mhz, internal peripheral clock 16mhz) (note2) M32182F3TFP: -40 to +85c (cpu clock 80mhz, internal peripheral clock 20mhz) package 0.5mm pitches / 144-pin lqfp package (144p6q-a) note 1: wait cycle by the external wait# input is not received when 0wait is selected. moreover, as for all idol setup after th e wait / strike robe / recovery / lead of cs block, only operation by "nothing" setup is guaranteed when 0wait is selected. note 2: this does not mean that the microcomputer is guaranteed for continuous operation at 125c. if 125c applications are desired, please consult mitsubishi.
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 5 m32182f3vfp , M32182F3TFP port15 port13 port12 port4 p45/cs1# xin xout vcnt osc-vcc osc-vss p70/bclk/wr# reset# mod0 mod1 fp p220/ctx0 8 p221/crx0 p224/a11/cs2# p225/a12/cs3# p150/tin0, p153/tin3 p130/tin16-p134/tin20 p137/tin23 p136/tin22/crx1 p135/tin21/rxd3 p124/tclk0-p127/tclk3 p93/to16-p97/to20 p100/to8 p101/to9/txd3 p102/to10/ctx1 p103/to11-p107/to15 p110/to0-p117/to7 ad0in0-ad0in11 avcc0 avss0 vref0 p61-p63 sbi# vcce excvcc vss p44/cs0# p43/rd# p42/bhw#/bhe# p41/blw#/ble# p71/wait# p72/hreq# p73/hack# p20/a23-p27/a30 p30/a15-p37/a22 p46/a13, p47/a14 p00/db0-p07/db7 p10/db8-p17/db15 p82/txd0 p83/rxd0 p84/sclki0/sclko0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 p174/txd2 p175/rxd2 p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk jtms jtck jtrst jtdo jtdi vdde excvdd vcc-bus bus control bus control address bus address bus bus control data bus serial i/o serial i/o serial i/o rtd port2 port3 port22 port0 port1 port8 port17 port7 jtag port11 port10 port9 multijunction timer clock reset mode can can a-d converter interrupt controller port6 8 4 5 2 7 4 2 5 5 8 8 8 3 12 2 2 note: it is shown that the pin (signal) with which "#" sticks to the last of a pin name (signal name) is "l" active pin (signal ). figure 3. pin function diagram
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 6 table 2. description of pin function (1/3) type pin name description input/output function vcce power supply - power supply (5.0v 0.5v or 3.3v 0.3v). excvcc external capaci- tance connect - external capacitance connecting pin. vcc-bus bus power supply - power supply for the bus control pins (5.0v 0.5v or 3.3v 0.3v). vdde ram power supply - internal ram backup power supply (5.0v 0.5v or 3.3v 0.3v). excvdd external capaci- tance connect - backup power supply for the internal ram, external capacitance con- necting pin. power supply vss ground - connect all vss pins to ground (gnd). xin clock input input xout clock output output clock input/output pins. these pins contain a pll-based frequency multiply-by-8, so input the clock whose frequency is 1/8 the operating frequency. (xin input = 10 mhz when cpu clock operates at 80 mhz) bclk system clock output outputs a clock twice the externally sourced clock frequency, xin (when the internal cpu memory clock is 80 mhz, bclk output = 20 mhz). use this output when external sync design is desired. osc-vcc clock power supply - power supply to the pll circuit. connect osc-vcc to the power supply osc-vss clock ground - connect osc-vss to ground. clock vcnt pll control - this pin controls the pll circuit. connect a resistor and capacitor to this pin. reset reset# reset input this pin resets the internal circuits. these pins set an operation mode. mod0 mod1 mode 0 0 single-chip mode 0 1 expanded external mode 1 0 processor mode (boot mode) (note 1) 1 1 (do not select) mode mod0, mod1 mode input note: in boot mode, the fp pin must be at the high level. flash-only fp flash protect input this pin protects the flash memory against e/w in hardware. address bus a11-a30 address bus output to allow four blocks of up to 2 mb memory space each to be added externally, 20-bit address (a11?a30) is provided. a31 is not output. data bus db0-db15 data bus input/output this is a 16-bit data bus connecting to an external device. during write cycle, the microcomputer outputs bhw# or blw# to indicate the valid byte write position of the 16-bit data bus. during read cycle, the micro- computer always reads the full 16-bit data bus. transferred to the inter- nal circuit of the m32r, however, is the data at only the valid byte posi- tion. cs0#-cs3# chip select output chip select signals for external devices. rd# read output this signal is output when reading external devices. wr# write output this signal is output when writing external devices. bhw# byte high write output blw# byte low write output indicates the byte positions to which valid are transferred when writing to external devices. bhw# / bhe# and blw# / ble# correspond to the upper address side (db0-db7 effective) and the lower address side (db8-db15 effective), respectively. bhe# byte high enable output for external device access, it indicates that the upper byte data (db0- db7) is valid. ble# byte low enable output for external device access, it indicates that the lower byte data (db8- db15) is valid. wait# wait input if wait# input is low when the m32r accesses external devices, the wait cycle extended. hreq# hold request input this pin is used by an external device to request control of the external bus. the m32r goes to a hold state when hreq# input is pulled low. bus control hack# hold acknowledge output this signal indicates to the external device that the m32r has entered a hold state and relinquished control of the external bus. note 1: in boot mode, the fp pin must be at the high level.
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 7 table 2. description of pin function (2/3) type pin name description input/output function tin0, tin3 tin16- tin23 timer input input input pin for multijunction timer to0 -to20 timer output output output pin for multijunction timer multijunction timer tclk0 -tclk3 timer clock input clock input pin for multijunction timers. avcc0 analog power sup- ply - avcc0 is the power supply for the a-d0 converter. connect avcc0 to the power supply rail. avss0 analog ground - avss0 is the analog ground for the a-d0 converters. connect avss0 to ground. ad0in0 -ad0in11 analog input input 16-channel analog input pins for the a-d0 converter in the first block. a-d converter vref0 reference voltage input input vref0 is the reference voltage input pin for the a-d0 converter. interrupt controller sbi# system break inter- rupt input system break interrupt (sbi) input pin of the interrupt controller sclki0/ sclko0 uart trans- mit/receive clock output or csio transmit/receive clock input/output input/output when channel 0 is in uart mode: clock output derived from brg output by dividing it by 2 when channel 0 is in csio mode: transmit/receive clock input when external clock is selected transmit/receive clock output when internal clock is selected sclki1/ sclko1 uart trans- mit/receive clock output or csio transmit/receive clock input/output input/output when channel 1 is in uart mode: clock output derived from brg output by dividing it by 2 when channel 1 is in csio mode: transmit/receive clock input when external clock is selected transmit/receive clock output when internal clock is selected txd0 transmit data output transmit data output pin of serial i/o channel 0 rxd0 receive data input receive data input pin of serial i/o channel 0 txd1 transmit data output transmit data output pin of serial i/o channel 1 rxd1 receive data input receive data input pin of serial i/o channel 1 txd2 transmit data output transmit data output pin of serial i/o channel 2 rxd2 receive data input receive data input pin of serial i/o channel 2 txd3 transmit data output transmit data output pin of serial i/o channel 3 serial i/o rxd3 receive data input receive data input pin of serial i/o channel 3
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 8 table 2. description of pin function (3/3) type pin name description input/output function rtdtxd transmit data output serial data output pin of the real-time debugger rtdrxd receive data input serial data input pin of the real-time debugger rtdclk clock input input serial data transmit/receive clock input pin of the real-time debugger real-time debugger rtdack acknowledge output this pin outputs a low pulse synchr onously with the real-time debug- ger?s first clock of serial data output word. the low pulse width indicates the type of the command/data the real-time debugger has received. ctx0, ctx1 transmit data output data output pin from can module. can crx0, crx1 receive data input data input pin to can module. jtms test mode input test select input for controlling the test circuit?s state transition jtck clock input clock input to the debugger module and test circuit. jtrst test reset input test reset input for initializing the test circuit asynchronously. jtdo serial output output serial output of test instruction code or test data. jtag jtdi serial input input serial input of test instruction code or test data. p00-p07 input/output port 0 input/output programmable input/output port. p10-p17 input/output port 1 input/output programmable input/output port. p20-p27 input/output port 2 input/output programmable input/output port. p30-p37 input/output port 3 input/output programmable input/output port. p41-p47 input/output port 4 input/output programmable input/output port. p61-p63 input/output port 6 input/output programmable input/output port. p70-p77 input/output port 7 input/output programmable input/output port. p82-p87 input/output port 8 input/output programmable input/output port. p93-p97 input/output port 9 input/output programmable input/output port. p100- p107 input/output port 10 input/output programmable input/output port. p110- p117 input/output port 11 input/output programmable input/output port. p124 -p127 input/output port 12 input/output programmable input/output port. p130 -p137 input/output port 13 input/output programmable input/output port. p150, p153 input/output port 15 input/output programmable input/output port. p174, p175 input/output port 17 input/output programmable input/output port. input/output port (note1) p220, p221 p224, p225 input/output port 22 input/output programmable input/output port. (however, p221 is an input-only port) note 1: input/output port 5 is reserved for future use. input/output ports 14,16,18, 20 and 21 do not exist.
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 9 outline of the cpu core the 32182 group is built around the m32r risc cpu core, and has the instruction set common to all of the m32r fam- ily microcomputers. to achieve high-precision arithmetic operation, this microcomputer additionally incorporates a fully ieee754 compliant, single-precision fpu. instructions are processed in five pipelined stages consist- ing of instruction fetch, decode, execution, memory access, and write back. thanks to its ?out-of-order-completion? mechanism, the m32r cpu allows clock cycle to realize efficient instruction execution control. the m32r-fpu internally contains sixteen 32-bit general- purpose registers. the instruction set consists of 100 dis- crete instructions, which come in either 16-bit or 32-bit in- struction format. use of the 16-bit instruction format helps to reduce the program code size. also, the availability of 32-bit instructions facilitates programming and increases the per- formance at the same clock speed, as compared to archi- tectures with segmented address spaces. multiply-accumulate instructions comparable to dsp the m32r-fpu contains a multiplier/accumulator that can execute 32-bit x 16-bit in one cycle. therefore, it executes a 32-bit x 32-bit integer multiplication instruction in three cy- cles. also, the m32r-fpu supports the following four multiply- accumulate instructions (or multiplication instructions) for dsp function use. (1) 16 high-order register bits x 16 high-order register bits (2) 16 low-order register bits x 16 low-order register bits (3) all 32 register bits x 16 high-order register bits (4) all 32 register bits x 16 low-order register bits furthermore, the m32r-fpu has instructions for rounding the value stored in the accumulator to 16 or 32-bit, and in- structions for shifting the accumulator value to adjust digits before storing in a register. because these instructions also can be executed in one cycle, dsp comparable data proc- essing capability can be obtained by using them in combi- nation with high-speed data transfer instructions such as load & address update or store & address update. fpu instructions (12 instructions) the m32r-fpu supports single-precision, floating-point arithmetic operations fully compliant with ieee754 standard. more specifically, it supports all of the following five excep- tions and four rounding modes. because the general- purpose registers are used for floating-point arithmetic, data transfer overhead is reduced. five exceptions (invalid operation, division by zero, over- flow, underflow, and inexact) four rounding modes (round toward nearest, round to- ward zero, round toward + , round toward - ) also included are the floating-point multiply and add (fmadd) and floating-point multiply and subtract (fmsub) instructions suitable for butterfly operation in fft. extended instructions (5 instructions) the m32r-fpu has several instructions implemented in it as extended instructions such as those to set, clear, and test bits, those to set and clear data in the processor status register, and those to automatically increment the address in which to store a halfword. address space the 32182 group?s logical address is always handled in width of 32-bit, providing a linear address space of up to 4g bytes. the 32182?s address space is divided into the following spaces. user space a 2g-byte area from h?0000 0000 to h?7fff ffff is the user space. located in this space are the user rom area, external extended area, internal ram area, and sfr (spe- cial function register) area (internal peripheral i/o regis- ters). of these, the user rom area and external extended area are located differently depending on mode settings. system space a 2g-byte area from h?8000 0000 to h?ffff ffff is the system area. this space is reserved for use by develop- ment tools such as an in-circuit emulator and debug monitor, and cannot be used by the user. built-in flash memory and ram the m32182f3vfp, M32182F3TFP contains 384k bytes flash memory and 64k bytes ram. the internal flash memory can be programmed while being mounted on the printed circuit board (on-board program- ming). use of flash memory allows the same chip as those used in mass production to be used beginning with the de- velopment stage. this means that system development can be proceeded without having to change the printed circuit boards during the entire course, from prototype to mass production.
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 10 user space 16m bytes sfr area (16k bytes) ram area (64k bytes) internal rom (384k) internal rom (384k bytes) reserved area (640k bytes) reserved area (640k bytes) reserved area (48k bytes) ram area (64k bytes) reserved area (48k bytes) ram area (64k bytes) reserved area (48k bytes) system space logical address single-chip mode processor mode external extended mode logical address h'0000 0000 h'8000 0000 h'7fff ffff 2g bytes 2g bytes h'ffff ffff h'000f ffff h'0000 0000 h'0010 0000 h'0005 ffff h'0006 0000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 h'005f ffff h'0060 0000 h'007f ffff h'0080 0000 h'0080 3fff h'0080 4000 h'0081 3fff h'0081 4000 h'0081 ffff ghost area in units of 16 bytes cs0 area cs1 area cs2 area cs3 area cs0 area sfr area (16k bytes) cs1 area cs2 area cs3 area sfr area (16k bytes) h'00ff ffff h'0082 0000 ghost area in units of 128k bytes figure 4. address space
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 11 internal rom (384k bytes) reserved area (640k bytes) cs0 area (1m bytes) cs1 area (2m bytes) logical address h'000f ffff h'0000 0000 h'0010 0000 h'0005 ffff h'0006 0000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 h'005f ffff h'0060 0000 h'007f ffff internal rom (384k bytes) cs1 area (1m bytes) internal rom (384k bytes) cs0 area (512k bytes) cs1 area (512k bytes) cs2 area (512k bytes) cs3 area (512k bytes) reserved area (640k bytes) cs0 area (1m bytes) cs2 area (1m bytes) reserved area (640k bytes) cs0 area (512k bytes) cs1 area (512k bytes) cs1 area (512k bytes) cs3 area (512k bytes) cs3 area (512k bytes) reserved area (640k bytes) internal rom (384k bytes) pin function (note) note: the pin functions enclosed in are effective. cs0# cs1# a11 / cs2# a12 / cs3# cs0# cs1# a11 / cs2# a12 / cs3# cs0# cs1# a11 / cs2# a12 / cs3# cs0# cs1# a11 / cs2# a12 / cs3# figure 5. internal rom and external extended area when external extended mode
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 12 cs0 area (2m bytes) cs1 area (2m bytes) h'0000 0000 pin function (note) h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 h'005f ffff h'0060 0000 h'007f ffff cs1 area (1m bytes) cs1 area (512k bytes) cs0 area (512k bytes) cs2 area (512k bytes) cs3 area (512k bytes) cs0 area (1m bytes) cs2 area (1m bytes) cs1 area (512k bytes) cs1 area (512k bytes) cs0 area (512k bytes) cs0 area (512k bytes) cs3 area (512k bytes) cs3 area (512k bytes) n o t e : t h e p i n f u n c t i o n s e n c l o s e d i n a r e e f f e c t i v e . cs0# cs1# a11 / cs2# a12 / cs3# cs0# cs1# a11 / cs2# a12 / cs3# cs0# cs1# a11 / cs2# a12 / cs3# cs0# cs1# a11 / cs2# a12 / cs3# figure 6. external extended area when processor mode
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 13 interrupt controller (icu) a-d0 converter serial i/o wait controller flash control mjt(common part) mjt(top) mjt(tio) mjt(tms) mjt(tml0) dmac dmac mjt(tml1) can0 can1 h'0080 0000 h'0080 007e h'0080 0080 h'0080 0ffe h'0080 0fe0 h'0080 1000 h'0080 11fe h'0080 1400 h'0080 15fe h'0080 3ffe h'0080 023e h'0080 0240 h'0080 02fe h'0000 0300 h'0080 03be h'0080 03c0 h'0080 03de h'0080 03e0 h'0080 03fe h'0080 0400 h'0080 0478 h'0080 0700 h'0080 0786 h'0080 0180 h'0080 0186 h'0080 01e0 h'0080 01f8 h'0080 0200 h'0080 00ee h'0080 0100 h'0080 0146 0 7 8 15 0 7 8 15 multi-junction timer (mjt) address +0 +1 address address +0 +1 address figure 7. sfr area
2002-07-12 rev.1.0 mitsubishi microcomputers 32182 group under development single-chip 32-bit cmos microcompute r 14 built-in 37-channel multijunction timers (mjt) the microcomputer contains a total of 37 channels of multi- junction timers consisting of 11 channels of 16-bit output related timers, 10 channels of 16-bit input/output related timers, 8 channels of 16-bit input related timers, 8 channels of 32-bit input related timers. each timer has multiple op- eration modes to choose from, depending on the purposes of use. also, the multijunction timers internally have a clock bus, input event bus, and an output event bus, so that multiple timers can be used in combination allowing for a flexible timer configuration. the output related timers have a cor- recting function that allows the timer?s count value to be incremented or decremented as necessary while count is in progress, making real-time output control possible. table 3. outline of the mjt name type number of channels contents top (timer output) output related 16-bit timer (down-counter) 11 one of three output modes is selected in software. single-shot output mode delayed single-shot output mode continuous output mode tio (timer input output) input/output related 16-bit timer (down- counter) 10 one of three input modes and four output modes is selected in software. measure clear input mode measure free-run input mode noise processing input mode
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