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ap160 8 - bit microcontroller data sheet with 8kb otp oc tober 2001 version 0.0 1 amic technology, inc. general description the ap160 is a wide operating voltage, low power consumption and high performance with amic high - density cmos technology. all instruction set of ap160 are fully compatible with the standard 8051. the ap160 contains 8k bytes otp epro m, 256 bytes ram, four 8 - bit bi - directional and bit addressable i/o ports, three 16 - bit timer/counter and eight interrupt sources. to reduce power consumption, idle mode and power down mode are provided to implementation. for data protection, program lock bits can be performed through programming lb1, lb2 and lb3. the amic ap160 is a useful and powerful microcontroller in many control system application. features l compatible with mcs - 51 products l 256 x 8 bit internal data ram. l 8kb on - chip otp eprom. l 2.7v~5.5v operating range. l fully static operation : 0hz to 16 mhz l 0~33mhz speed range at vcc=5v. l 32 programmable i/o pins l three 16 - bit timers/counters. l programmable clock out. l full - duplex uart l eight interrupt sources. l 2 level priority - interr upt. l power reduction control modes n idle mode n power - down mode l 3 security bits. l low emi (inhibit ale) l wake - up from power down by an external interrupt. l available in plcc and qfp44 packages.
ap160 version 0.0 2 amic technology, inc. p in con figurations n plcc ap160l p1.5 p1.4 p1.3 p1.2 p1.1 (t2ex) p1.0 (t2) nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p1.6 p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) ea/vpp nc ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) 28 27 26 25 24 23 22 21 20 19 18 44 43 42 41 40 1 2 3 4 5 6 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) (rd) p3.7 xtal2 xtal1 gnd nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 (wr) p3.6 n qfp AP160F p1.5 p1.4 p1.3 p1.2 p1.1 (t2ex) p1.0 (t2) nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p1.6 p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) ea/vpp nc ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) 22 21 20 19 18 17 16 15 14 13 12 38 37 36 35 34 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd gnd (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4
ap160 version 0.0 3 amic technology, inc. block diagram p0.0-p0.7 p2.0-p2.7 port 0 drivers port 2 drivers ram addr. register ram port0 latach port2 latach quick flash program address register buffer pc incrementer program couner dptr b register acc stack pointer tmp2 tmp1 alu interrupt, serial port, and timer blocks psw port1 latach port3 latach timing and control instruction register osc p1.0-p1.7 p3.0-p3.7 port 1 drivers port 3 drivers vcc gnd psen prog ale/ /vpp ea rst
ap160 version 0.0 4 amic technology, inc. pin descriptions symbol type descriptions vss i ground. vcc i supply voltage. p0.0 - p0.7 i/o port 0 is an 8 - bit open drain, bidirectional i/o port. when 1s are written to port 0 pins, the pins can be used as high - impedance inputs. port 0 can also be configured to be the multiplexed low - order address/data bus during accesses to external program and data memo ry. in this mode, p0 has internal pullups. port 0 also receives the code bytes during programming on - chip otp eprom and outputs the code bytes during program verification. external pullups are required during program verification. p1.0 - p1.7 i/o port 1 is an 8 - bit bidirectional i/o port with internal pullups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are ex ternally being pulled low will source current ( il i ) because of the internal pullups. in addition, p1.0 and p1.1 can be configured to be the timer/counter 2 external count input (p1.0/t2) and the timer/counter 2 trigger input (p1.1/t2ex) , respectively, as shown in the following: t2 (p1.0): timer/counter 2 external count input/clockout (see programmable clock - out) t2ex (p1.1): timer/counter 2 reload/capture/direction control. port 1 also receives the low - order address bytes during program ming on - chip otp eprom and verification. p2.0 - p2.7 i/o port 2 is an 8 - bit bidirectional i/o port with internal pullups. the port 2 output buffers can s ink/source four ttl inputs. when 1s are written to port 2 pins, they are pulled high by the internal pul lups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current ( il i ) because of the internal pullups. port 2 emits the high - order address byte during fetches from external program memory and during accesses to external data memory that use 16 - bit addresses (movx @dptr). in this application, port 2 uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8 - bit addresses (movx @ ri), port 2 emits the co ntents of the p2 special function register. port 2 also receives the high - order address bits and some control signals during programming on - chip otp eprom and verification. p3.0 - p3.7 i/o port 3 is an 8 - bit bidirectional i/o port with internal pullups. the port 3 output buffers can sink/source four ttl inputs.when 1s are written to port 3 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current ( il i ) because of the pullups. port 3 also serves the functions of various special features of the ap160, as shown below: rxd (p3.0): serial input port txd (p3.1): serial output port int0 (p3.2): external interrupt int1 (p3.3): external interrupt t 0 (p3.4): timer 0 external input t1 (p3.5): timer 1 external input wr (p3.6): external data memory write strobe rd (p3.7): external data memory read strobe port 3 also receives some control signals for programming and verification. rst i reset input. a h igh on this pin for two machine cycles while the oscillator is running resets the device.
ap160 version 0.0 5 amic technology, inc. symbol type descriptions ale/prog o/i address latch enable is an output pulse for latching the low byte of the address during accesses to external memory. this pi n is also the program pulse input (prog) during programming on - chip opt eprom. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. note, however, that one ale puls e is skipped during each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setti ng the ale - disable bit has no effect if the microcontroller is in external execution mode. psen o program store enable is the read strobe to external program memory. when the ap160 is executing code from external program memory, psen is activated twice ea ch machine cycle, except that two psen activations are skipped during each access to external data memory. ea/vpp i external access enable. ea must be strapped to gnd in order to enable the device to fetch code from external program memory locations start ing at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset. ea should be strapped to vcc for internal program executions. this pin also receives the 12 - volt programming enable voltage (v pp ) during prog ramming otp eprom. xtal1 i input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 o output from the inverting oscillator amplifier.
ap160 version 0.0 6 amic technology, inc. special function registers a map of the on - chip memory area called the special function register (sfr) space is shown in table 1. table 1. ap160 sfr map and reset values 0f8h 0ffh 0f0h b 00000000 0f7h 0e8h 0efh 0e0h acc 00000000 0e7h 0d8h 0d fh 0d0h psw 00000000 0d7h 0c8h t2con 00000000 t2mod xxxxxx00 rcap2l 00000000 tl2 00000000 th2 00000000 0cfh 0c0h 0c7h 0b8h ip xx000000 0bfh 0b0h p3 11111111 0b7h 0a8h ie 0x000000 0afh 0 a0h p2 11111111 0a7h 098h scon 00000000 sbuf xxxxxxxx 09fh 090h p1 11111111 097h 088h tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 08fh 080h p0 11111111 sp 00000111 dpl 00000 000 dph 00000000 pcon 0xxx0000 087h note that not all of the addresses are occupied. unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indet erminate effect. user software should not write 1s to these unlisted locations, since they may be used in future amic products to invoke new features. in that case the reset or inactive values of the new bits will always be 0.
ap160 version 0.0 7 amic technology, inc. timer2 timer2 is a 16 - bit timer/counter that can operate as either a timer or an event counter. the type of operation is selected by bit c/t2 in the sfr t2con (shown in table 2). timer 2 has three operating modes: capture, auto - reload (up or down counting), and baud rate generator. the modes are selected by bits in t2con, as shown in table 3. table 2. t2con ? timer/counter 2 control register t2con address = 0c8h bit 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 reset value = 00000000 bit addressable symbol function tf2 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk = 1 or tclk = 1. exf2 timer 2 external flag set when either a capture or reload is ca used by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen =1). rclk receive clock enable. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. rclk = 0 causes timer 1 overflows to be used for the receive clock. tclk transmit clock enable. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 timer 2 external enable. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 start/stop control for timer 2. tr2 = 1 starts the timer. c/t2 timer or counter select for timer 2. c /t2 = 0 for timer function. c/t2 = 1 for external event counter (falling edge triggered0. cp/rl2 capture/reload select. cp/rl2 = 1 causes captures to occur on negative transitions at t2ex if exen2 = 1. cp/rl2 = 0 causes automatic reloads to occur when tim er 2 overflows or negative transitions occur at t2ex when exen2 = 1. when either rclk or tclk = 1, this bit is ignored and the timer is forced to auto - reload on timer 2 overflow. table 3. timer 2 operating modes rclk+tclk cp/rl2 tr2 mode 0 0 1 16 - bit a uto - reload 0 1 1 16 - bit capture 1 x 1 baud rate generator x x 0 (off) timer2 consists of two 8 - bit registers, th2 and tl2. in the timer function, the tl2 register is incremented every machine cycle. since a machine cycle consists of 12 oscillator peri ods, the count rate is 1/12 of the oscillator frequency.in the counter function, the register is incremented in response to a 1 - to - 0 transition at its corresponding external input pin, t2. in this function, the external input is samples show a high in on e cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since two machine cycles (24 oscillator periods) are required to rec ognize a 1 - to - 0 transition, the maximum count rate is 1/24 of the oscillator frequency. to ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
ap160 version 0.0 8 amic technology, inc. capture mode in the captu re mode, two options are selected by bit exen2 in t2con. if exen2=0, timer 2 is a 16 - bit timer or counter which upon overflow sets bit tf2 in t2con. this bit can then be used to generate an interrupt. if exen2=1, timer 2 performs the same operation, but a 1 - to - 0 transition at external input t2ex also causes the current value in th2 and tl2 to be captured into rcap2h and rcap2l, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set. the exf2 bit, like tf2, can generate an inter rupt. the capture mode is illustrated in figure 1. timer 2 interrupt osc c/t2=0 t2 pin control th2 tf2 c/t2=1 tl2 rcap2h rcap2l exf2 t2ex pin exen2 tr2 capture control transition detector 12 ? overflow figure 1. timer in capture mode auto - reload (up or down counter) timer 2 can be programmed to count up or down when configured in its 16 - bit auto - reload mode. this feature i s invoked by the dcen (down counter enable) bit located in the sfr t2mod (see table 3). upon reset, the dcen bit is set to 0 so that timer 2 will default to count up. when dcen is set, timer 2 can count up or down, depending on the value of the t2ex pin. f igure 2 shows timer 2 automatically counting up when dcen=0. timer 2 interrupt osc c/t2=0 t2 pin control th2 tf2 c/t2=1 tl2 rcap2h rcap2l t2ex pin exen2 tr2 reload control transition detector 12 ? exf2 overflow figure 2. timer 2 auto reload mode (dcen=0)
ap160 version 0.0 9 amic technology, inc. in this mode, two options are selected by bit exen2 in t2con. if exen2=0, timer2 counts up to 0ffffh and then sets the tf2 bit upon overflow. the overflow also causes the timer registers to be reloaded with the 16 - bit value in rcap2h and rcap2l. the values in timer in capture mode rcap2h and rcap2l are preset by software. if exen2=1, a 16 - bit reload can be triggered e ither by an overflow or by a 1 - to - 0 transition at external input t2ex. this transition also sets the exf2 bit. both the tf2 and exf2 bits can generate an interrupt if enabled. setting the dcen bit enables timer2 to count up or down, as shown in figure 3. i n the mode, the t2ex pin controls the direction of the count. a logic 1 at t2ex makes timer 2 count up. the timer will overflow at 0ffffh and set the tf2 bit. the overflow also causes the 16 - bit value in rcap2h and rcap2l to be reloaded into the timer regi sters, th2 and tl2, respectively. a logic 0 at t2ex makes timer 2 count down. the timer underflows when th2 and tl2 equal the values stored in rcap2h and racp2l. the underflow sets the tf2 bit and causes 0ffffh to be reloaded into the timer registers. the exf2 bit toggles whenever timer 2 overflows or underflows and can be used as a 17 th bit of resolution. in this operating mode, exf2 does not flag an interrupt. table 3. t2mod (timer 2 mode control register) t2mod address = 0c9h reset value = xxxx xx00b not bit addressable bit 7 6 5 4 3 2 1 0 symbol - - - - - - t2oe dcen symbol function - not implemented, reserved for future t2oe timer 2 output enable bit. dcen when set, this bit allows timer 2 to be configured as an up/down counter. osc c/t2=0 t2 pin control c/t2=1 t2ex pin tr2 12 ? overflow 0ffh 0ffh rcap2h rcap2l th2 tl2 tf2 (down counting reload value) count direction 1=up 0=down timer 2 interrupt exf2 toggle (up counting reload value) figure 3. timer 2 auto reload mode (dcen=1)
ap160 version 0.0 10 amic technology, inc. baud rate generator timer 2 is selected as the baud rate generator by s etting tclk and/or rclk in t2con (table 2). note that the baud rates for transmit and receive can be different if timer 2 is used for the receiver or transmitter and timer 1 is used for the other function. setting rclk and/or tclk puts timer 2 into its bau d rate generator mode, as shown in figure 4. the baud rate generator mode is similar to the auto - reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16 - bit value in registers rcap2h and rcap2l, which are preset by so ftware. the baud rates in modes 1 and 3 are determined by timer 2?s overflow rate according to the following equation. mode 1 and 3 baud rates = 16 2 rate overflow timer the timer can be configured for either timer or counter operation. in most applicatio ns, it is configured for timer operation (cp/t2=0). the timer operation is different for timer 2 when it is used as a baud rate generator. normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). as a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). the baud rate formula is given below. )] 2 , 2 ( 65536 [ 32 3 1 l rcap h rcap frequency oscillator rate baud and modes - = where (rcap2h,rcap2l) is the content of rcap2h and rcap2l taken as a 16 - bit unsigned integer. timer 2 as a baud rat e generator is shown in figure 4. this figure is valid only if rclk or tclk=1 in t2con. note that a rollover in th2 does not ser tf2 and will not generate an interrupt. note too, that if exen2 is set, a 1 - to - 0 transition in t2ex will set exf2 but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). thus when timer 2 is in use as a baud rate generator, t2ex can be used as an extra external interrupt. note that when timer 2 is running (tr2=1) as a timer in the baud rate generator mode. th2 or tl2 shoul d not be read from or written to. under there conditions, the timer is incremented every state time, and the results of a read or write may not be accurate. the rcap2 registers may be read but should not be written to, because a write might overlap a reloa d and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 register. timer 2 interrupt osc t2 pin control th2 tl2 rcap2h rcap2l exf2 t2ex pin exen2 tr2 control transition detector rx clock tx clock "1" "1" note:osc freq. is divided by 2, not 12 "1" "0" timer 1 overflow "0" smod1 rclk tclk "0" c/t2=0 c/t2=1 2 ? 16 ? 16 ? 2 ? figure 4. timer 2 in baud rate generator mode
ap160 version 0.0 11 amic technology, inc. programmable clock out a 50% duty cycle clock c an be programmed to come out on p1.0, as shown in figure 5. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed to input the external clock for timer/counter 2 or to output a 50% duty cycle clock ranging from 61 hz to 4mhz at a 16mhz operating frequency. to configure the timer/counter 2 as a clock generator, bit c/t2 (t2con.1) must be cleared and bit t2oe (t2mod.1) must be set. bit tr2 (t2con.2) starts and stops the timer. the clock - out frequency depends on the oscil lator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l), as shown in the following equation. )] 2 , 2 ( 65535 [ 4 l rcap h rcap frequency oscillator frequency out clock - = - in the clock - out mode, timer 2 roll - overs will not generate an interrupt. this behavior is similar to when tim er 2 is used as a baud - rate generator. it is possible to use timer 2 as a baud - rate generator and a clock generator simultaneously. note, however, that the baud - rate and clock - out frequencies cannot be determined independently from one another since they b oth use rcap2h and rcap2l. timer 2 interrupt osc c/t2 bit tl2 (8 bits) th2 (8 bits) rcap2l rcap2h exf2 exen2 tr2 transition detector 2 ? 2 ? p1.0 (t2) p1.1 (t2ex) t2oe (t2mod.1) figure 5. timer 2 in clock - out mode
ap160 version 0.0 12 amic technology, inc. interrupts the ap160 has a total of six interrupt vectors: two external interrupts (int0 and int1), three timer interrupts (timers 0, 1, and 2), and the serial port interrupt. these interrupts are all shown in figure 6. each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in special function register ie. ie also contains a global disable bit, ea, whic h disables all interrupts at once. note that table 4 shows that bit position ie.6 is unimplemented. user software should not write 1s to the bit position, since they may be used in future amic products. timer 2 interrupt is generated by the logical or of b its tf2 and exf2 in register t2con. neither of these flags is cleared by hardware when the service routine is vectored to. in fact, the service routine may have to determine whether it was tf2 or exf2 that generated the interrupt, and that bit will have to be cleared in software. the timer 0 and timer 1 flags, tf0 and tf1, are set at s5p2 of the cycle in which the timers overflow. the values are then polled by the circuitry in the next cycle. however, the timer 2 flag, tf2, is set at s2p2 and is polled in t he same cycle in which the timer overflows. table 4: interrupt enable (ie) register (msb) (lsb) ea -- et2 es et1 ex1 et0 ex0 enable bit = 1 enables the interrupt. enable bit = 0 disables the interrupt. symbol position function ea ie.7 disables all interrupts. if ea = 0, no interrupt is acknowledged. if ea=1, each interrupt source is in dividually enabled or disabled by setting or clearing its enable bit. -- ie.6 reserved. et2 ie.5 timer 2 interrupt enable bit. es ie.4 serial port interrupt enable bit. et1 ie.3 timer 1 interrupt enable bit. ex1 ie.2 external interrupt 1 enable bit. et0 ie.1 timer 0 interrupt enable bit. ex0 ie.0 external interrupt 0 enable bit. user software should never write 1s to unimplemented bits, because they may be used in future amic products int0 ie0 0 1 tf0 ie1 0 1 int1 tf1 t1 r1 tf2 exf2 figure 6. interrupt sources
ap160 version 0.0 13 amic technology, inc. dat a memory the ap160 implements 256 bytes of on - chip ram. the upper 128 bytes occupy a parallel address space to the special function registers. that means the upper 128 bytes have the same addresses as the sfr space but are physically separate from sfr spa ce. when an instruction accesses an internal location above address 7fh, the address mode used in the instruction specifies whether the cpu accesses the upper 128 bytes of ram or the sfr space. instructions that use direct addressing access sfr space. for example, the following direct addressing instruction accesses the sfr at location 0a0h (which is p2). mov 0a0h, #data instructions that use indirect addressing access the upper 128 bytes of ram. for example, the following indirect addressing instruction, where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). mov @r0, #data note that stack operations are examples of indirect addressing, so the upper 128 bytes of data ram are avail - able as stack space. power management idle mode in idle mode, the cpu puts itself to sleep while all the on - chip peripherals remain active. the mode is invoked by software. the content of the on - chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal res et algorithm takes control. on - chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruc tion following the one that invokes idle mode should not write to a port pin or to external memory. power down mode in the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. the on - chi p ram and special function registers retain their values until the power down mode is terminated. the way to exit from power down mode is either hardware reset or external interrupt. reset redefines the sfrs but does not change the on - chip ram. the reset s hould not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. status of external pins during idle and power down modes mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 data data data data idle external 1 1 float data address data power down internal 0 0 data data data data power down external 0 0 float data data data reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. to insure a good power - up reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. red uced emi all port pins of the ap160 have slew rate controlled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is factory set to approximately 10 ns rise and fall times. auxr address = 8eh bit 7 6 5 4 3 2 1 0 - - - - - - - ao note: the ao bit (auxr.0) in the auxr register when set disables the ale output.
ap160 version 0.0 14 amic technology, inc. eprom programming mode the setup for programming and verification on - chip opt eprom of ap160 is shown in figure 7 and figure 8, independently. the addres s of the eprom location to be programmed is applied to ports 1 and 2. the code byte to be programmed into that location and read verified data are applied to port 0. the programming, verifying, write lock bits and read signature byte mode are selectable by the pins of rst, psen, ale/prog, p2.6, p2.7, p3.6 and p3.7, as shown in table 8. the programming and verification waveform is shown in figure 9. vcc must be rising to vcc1 during programming. a0~a7 a8~a12 addr 0000h/1fffh p1 p2.0~p2.4 p2.6 p2.7 p3.6 p3.7 xtal2 xtal1 gnd psen rst ea ale p0 vcc vcc1 pgm data prog v ih /v pp v ih see table 8. a0~a7 a8~a12 addr 0000h/1fffh p1 p2.0~p2.4 p2.6 p2.7 p3.6 p3.7 xtal2 xtal1 gnd psen rst ea ale p0 vcc vcc1 pgm data (10k pullups) v ih v ih see table 8. figure 7. programming the epro m memory figure 8. verifying the eprom memory. eprom programming and verification characteristics symbol parameter min. max. unit test conditions vpp programming voltage 11.5 12.5 v vcc1 programming supply voltage 6.0 6.5 v pp i vpp current during program 1.0 ma ale/prog = il v as t address valid to program low 2 us ds t input valid to program low 2 us vps t vpp setup time 2 us vcs t vcc setup time 2 us pw t program pulse width 95 105 us dh t data hold time 2 us vr t ea/vpp recovery time 2 us dv t data valid from p2.7 100 ns dfp t chip enable to output float delay 130 ns ah t address hold time 0 ns
ap160 version 0.0 15 amic technology, inc. prgramming and verify mode ac waveforms program verify t as valid data in data out hi-z vpp t dh t ds vcc logic 1 logic 0 t dfp t ah t dv vcc t vr t vps t vps vcc1 t vcs t pw p2.7 ale/prog vcc ea/vpp data (port 0) address (p1.0~p1.7 p2.0~p2.4) v ih v il table 8. eprom programming mode mode rst psen al e/prog ea/vpp p2.6 p2.7 p3.6 p3.7 write code data h l 12v l h h h read code data h l h h l l h h bit - 1 h l 12v h h h h bit - 2 h l 12v h h l l write lock bit - 3 h l 12v h l h l read signature byte h l h h l l l l note: the signature bytes are read by the same procedure as a normal verification of locations 30h, 31h and 32h. the values returns are as follows: (30h) = 37h indicates manufactured by amic. (31h) = 6eh indicates embedded otp device. (32h) = 7fh in dicates jedec continuation code.
ap160 version 0.0 16 amic technology, inc. program memory lock bits the ap160 has three lock bits that can be left unprogrammed(u) or can be programmed (p) to obtain the additional features listed in the following table. program lock bits lb1 lb2 l b3 protection type 1 u u u no program lock features 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the opt eprom is disabled. 3 p p u same as mode 2, but verify is also disabled. 4 p p p same as mode 3, bur external execution is also disabled. oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pi ns can be configured for use as an on - chip oscillator, as shown in the logic symbol. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external cloc k signal, because the input to the internal clock circuitry is through a divide - by - two flip - flop. however, minimum and maximum high and low times specified in the data sheet must be observed.
ap160 version 0.0 17 amic technology, inc. absolute maximum ratings paramete r rating unit operating temperature under bias - 55 to +125 c storage temperature range - 65 to +150 c voltage on ea/v pp pin to v ss 0 to +12.5 v voltage on any other pin to v ss - 0.1 to +7.0 v maximum operating voltage 6.0 v maximum i ol per i/ o pin 15.0 ma notice: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. this this is a stress rating only and functional operation of the device at these or any other conditions beyo nd those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc charactericstics the values shown in this table are valid for t a = - 40c to 85c and v cc = 2.7v to 5.5v, unless otherwise noted. symbol parameter condition min max units il v input low voltage (except ea) - 0.5 0.2 vcc - 0.1 v il1 v input low voltage (ea) - 0.5 0.2 vcc - 0.3 v ih v input high voltage (except xtal1, rst) 0.2 vcc+0.9 vcc+0.5 v ih1 v input high voltage (xtal1, rst) 0.7 vcc vcc+0.5 v ol v output low voltage (ports 1,2,3) ol i = 1.6ma 0.45 v ol1 v output low voltage (port 0, ale, psen) ol i = 3.2ma 0.45 v oh i = - 60ua, vcc=5v10% 2.4 v oh i = - 25ua 0.75 v cc v oh v output high voltage (port 1,2,3, ale, psen) oh i = - 10ua 0.9 vcc v oh i = - 800ua, vcc=5v10% 2.4 v oh i = - 300ua 0.75 vcc v oh1 v output high voltage (port 0 in external bus mode) oh i = - 80ua 0 .9 vcc v il i logical 0 input current (ports 1,2,3) in v =0.45v - 50 ua tl i logical 1 to 0 transition current (ports 1,2,3) in v =2v, vcc=5v10% - 650 ua li i input leakage current (port 0, ea) 0.45< in v < vcc 10 ua rrst reset pulldown resistor 50 300 k w io c pin capacitance test freq. =1 mhz, a t =25 c 10 pf active mode, 12 mhz 25 m a power supply current idle mode, 12mhz 6.5 ma vcc = 5.5v 100 ua cc i power down mode vcc = 3v 40 ua notes: 1. under steady state (non - transient) conditions, ol i must be externally limited as follows: maximum ol i per port pin: 10ma maximum ol i per 8 - biit port: port 0: 26ma, ports 1,2,3: 15ma maximum total ol i for all output pins: 71ma if ol i exceeds the test condition, ol v may exceed the related specification. pins are not guaranteed to sink currenr greater than the listed test condition. 2. minimum vcc for power down is 2v.
ap160 version 0.0 18 amic technology, inc. ac characteristics under operating conditions, load capacitance for port 0, ale/pro g, and psen = 100 pf; load capacitance for all other outputs = 80 pf. external program and data memory characteristics 12mhz oscillator variable oscillator symbol parameter min max min max units clcl 1/t oscillator frequency 0 16 mhz lhll t ale pulse width 127 2 clcl t - 40 ns avll t address valid to ale low 43 clcl t - 40 ns llax t address hold after ale low 48 clcl t - 35 ns lliv t ale low to valid instruction in 233 4 clcl t - 100 ns llpl t ale low to psen low 43 clcl t - 40 ns plph t psen pulse width 205 3 clcl t - 45 ns pliv t psen low to valid instruction in 145 3 clcl t - 105 ns pxix t input instruction hold after psen 0 0 ns pxiz t input instruction float after psen 59 clcl t - 25 ns pxav t psen to address valid 75 clcl t - 8 ns aviv t address to valid instruction in 312 5 clcl t - 105 ns plaz t psen low to address float 10 10 ns rlrh t rd pulse width 400 6 clcl t - 100 ns wlwh t wr pulse width 400 6 clcl t - 100 ns rldv t rd low to valid data in 252 5 clcl t - 165 ns rhdx t data ho ld after rd 0 0 ns rhdz t data float after rd 97 2 clcl t - 70 ns lldv t ale low to valid data in 517 8 clcl t - 150 ns avdv t address to valid data in 585 9 clcl t - 165 ns llwl t ale low to rd or wr low 200 300 3 clcl t - 50 3 clcl t +50 ns avwl t address to rd or wr low 203 4 clcl t - 130 ns qvwx t data v alid to wr transition 33 clcl t - 50 ns qvwh t data valid to wr high 433 7 clcl t - 150 ns whqx t data hold after wr 33 clcl t - 50 ns rlaz t rd low to address float 0 0 ns whlh t rd or wr high to ale high 43 123 clcl t - 4 0 clcl t +40 ns
ap160 version 0.0 19 amic technology, inc. external program memory read cycle a8-a15 ale t lhll t avll t llpl t plph t pliv t plaz t llax t pxav t pxiz t pxix t aviv a8-a15 a0-a7 instr in psen port 0 port 2 t lliv a0-a7 external data memory read cycle ale t lhll t whlh data in psen port 0 port 2 t rlrh t lldv t llwl rd t llax t avll t rldv t rhdx t rhdz t rlaz t avwl t avdv a0-a7 from ri or dpl a0-a7 from pcl instr in p2.0-p2.7 or a8-a15 form dph a8-a15 from pch
ap160 version 0.0 20 amic technology, inc. external clock drive waveforms 0.45v vcc-0.5v 0.7 vcc 0.2 vcc-0.1v t chcx t clcx t clcl t clch t chcl t chcx external clock drive symbol parameter min max units 1/ clcl t oscillator frequency 0 16 mhz clcl t clock period 62. 5 ns chcx t high time 20 ns clcx t low time 20 ns clch t rise time 20 ns chcl t fall time 20 ns
ap160 version 0.0 21 amic technology, inc. serial port timing: shift register mode test conditi ons the values in this table are valid for vcc = 2. 7v to 5.5v and load capacitance = 80pf 12mhz osc variable oscillator symbol parameter min max min max units xlxl t serial port clock cycle time 1.0 12 clcl t ns qvxh t output data setup to clock rising edge 700 10 clcl t - 133 ns xhqx t output data hold after clock rising edge 50 2 clcl t - 117 ns xhdx t input data hold after clock rising edge 0 0 ns xhdv t clock rising edge to input data valid 700 10 clcl t - 133 ns shift register mode timing waveforms 0 1 2 3 4 5 6 7 8 instruction t xlxl t qvxh t xhqx t xhdv t xhdx valid valid valid valid valid valid valid valid 0 1 2 3 4 5 6 7 set ti set ri ale clock output data input data write to sbuf clear ri ac testing input/output waveforms vcc-0.5v 0.45v 0.2 vcc + 0.9v test points 0.2 vcc - 0.1v note: 1. ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. timing measurements are made at v ih min. for a logic 1 and v il max. for a logic 0. float waveforms timing reference points v load + 0.1v v load - 0.1v v load v ol - 0.1v v ol + 0.1v note: 1. for timing p urposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when a 100 mv change from the loaded v oh /v ol level occurs.
ap160 version 0.0 22 amic technology, inc. ordering information part number package type operation temperature range ap160l plcc - 40 c ~ +85 c AP160F qfp - 40 c ~ +85 c note : amic technology, inc. reserves the right to make changes without prior notice.
ap160 version 0.0 23 amic technology, inc. package information plcc 44l outline dimension unit: inches /mm dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.185 - - 4.70 d 0.648 0.653 0.658 16.46 16.59 16.71 e 0.648 0.653 0.658 16.46 16.59 16.71 h d 0.680 0.690 0.700 17.27 17.53 17.78 h e 0.680 0.690 0.700 17.27 17.53 17. 78 l 0.090 0.100 0.110 2.29 2.54 2.79 q 0 - 10 0 - 10 notes: 1. dimensions d and e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only. h d d 7 17 18 28 29 39 1 6 e h e 44 40 a 1 a 2 a e g d seating plane b 1 b 0.150 ref 0.020 min l 0.630/0.590 0.050 ref 0.022/0.016 0.032/0.026 g e c 0.630/0.590 0.014/0.0008 d 0.004 y
ap160 version 0.0 24 amic technology, inc. package information qfp 44l outline dimensions unit: inches/mm b e a a 2 a 1 d 0.10 see detail a l 1.6 detail a q 12 22 33 23 34 44 1 11 e e 1 d d 1 c 0.25 gauge plane seating plane 0.20 min min 0 dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.106 - - 2.7 a 1 0.010 0.012 0.014 0.25 0.30 0.35 a 2 0.0748 0.0787 0.0866 1.9 2.0 2.2 b 0.012 typ 0.3 typ d 0.5118 0.5196 0.5274 13.00 13.20 13.40 d 1 0.3897 0 .3937 0.3977 9.9 10.00 10.10 e 0.5118 0.5196 0.5275 13.00 13.20 13.40 e 1 0.3897 0.3937 0.3977 9.9 10.00 10.10 l 0.0287 0.0346 0.0366 0.73 0.88 0.93 e 0.0315 typ 0.80 typ c 0.0021 0.0060 0.0099 0.1 0.15 0.2 q 0 - 7 0 - 7 notes: 1. dimensions d 1 and e 1 do not include mold protrusion. 2. dimension b does not include dambar protrusion.
ap160 version 0.0 25 amic technology, inc. corporation headquarters 6f, no. 5, li - shin road vi, hsin chu, hsip, taiwan, r.o.c. tel : 886 - 3 - 567 - 9966 fax : 886 - 3 - 567 - 9977 web : www.amic.com.tw asia pacific amic technology, inc. 17f - 8, no. 77, shin tai wu road, shi chi, taipei, taiwan, r.o.c. tel : 886 - 2 - 2698 - 1131 fax : 886 - 2 - 2698 - 1030 europe amic technology (europe) b.v. crown point building, de paal 1 - 6,13 351 ja, p.o box 50053,1305 ab, almere, the netherlands tel. +31 - 36 - 5359666 fax. +31 - 36 - 5401888 us and canada amic technology inc. 2518 mission college blvd., suite 102 santa clara, ca 95054, u.s.a. tel. +408 - 988 - 8818 fax. +408 - 988 - 8817 copyright ? 2001 amic technology, inc. specification subject to change without notice. all rights reserved.

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