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1 of 27 rev: 070605 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any devic e may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . features 8051-compatible microprocessor adapts to its task accesses up to 128kb of nonvolatile sram in-system programming through on-chip serial port can modify its own program or data memory accesses memory on a separate byte-wide bus performs crc-16 check of nv ram memory decodes memory and peripheral chip enables high-reliability operation ? maintains all nonvolatile resources for over 10 years ? power-fail reset ? early warning power-fail interrupt ? watchdog timer ? lithium backs user sram for program/data storage ? precision bandgap reference for power monitor fully 8051 compatible ? 128kb scratchpad ram ? two timer/counters ? on-chip serial port ? 32 parallel i/o port pins software security available with ds5002fp secure microprocessor this data sheet must be used in conjunction with the secure microcontroller user?s guide , available on our website at www.maxim-ic.com/microcontrollers . the user?s guide contains operating information, whereas the data sheet contains ordering information, pinout, and electrical specifications pin configurations ds5001fp 128k soft microprocessor chip www.maxim-ic.com p0.4ad4 ce2 pe2 ba9 p0.3/ad3 ba8 p0.2/ad2 ba13 p0.1/ad1 r/w p0.0/ad0 vcc0 vcc msel p1.0 ba14 p1.1 ba12 p1.2 ba7 p1.3 pe3 pe4 ba6 p2.6/a14 ce3 ce4 bd3 p2.5/a13 bd2 p2.4/a12 bd1 p2.3/a11 bd0 vli ba15 gnd p2.2/a10 p2.1/a9 p2.0/a8 xtal1 xtal2 p3.7/rd p3.6/wr p3.5/ti pf vrst p3.4/t0 ds5001fp 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p1.4 ba5 p1.5 ba4 p1.6 ba3 p1.7 prog ba2 rst ba1 p3.0/rxd ba0 p3.1/txd p3.2/int0 p3.3/int1 ba11 p0.5/ad5 pe1 p0.6/ad6 ba10 p0.7/ad7 ce1 n.c. ce1n bd7 ale bd6 psen bd5 p2.7/a15 bd4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 mqfp mqfp top view
ds5001fp 2 of 27 ordering information part temp range max clock speed (mhz) pin- package ds5001fp-16 0c to +70c 16 80 mqfp ds5001fp-16+ 0c to +70c 16 80 mqfp ds5001fp-16n -40c to +85c 16 80 mqfp ds5001fp-16n+ -40c to +85c 16 80 mqfp ds5001fp-12-44 0c to +70c 12 44mqfp ds5001fp-12-44+ 0c to +70c 12 44 mqfp + denotes a pb-free/rohs-compliant device. description the ds5001fp 128k soft microprocessor chip is an 8051-compatible microprocessor based on nv ram technology and designed for systems that need larg e quantities of nonvolatile memory. it provides full compatibility with the 8051 instruction set, timers, se rial port, and parallel i/ o ports. by using nv ram instead of rom, the user can program and then reprogram the microprocessor while in-system. the application software can even change its own opera tion, which allows frequent software upgrades, adaptive programs, customized systems, etc. in addition, by using nv sram, the ds5001fp is ideal for data logging applications. it also connects easily to a dallas real-time clock. the ds5001fp provides the benefits of nv ram without using i/o re sources. it uses a nonmultiplexed byte-wide address and data bus fo r memory access. this bus performs all memory access and provides decoded chip enables for sram, which leaves th e 32 i/o port pins free for application use. the ds5001fp uses ordinary sram and battery-backs th e memory contents for over 10 years at room temperature with a small external battery. a ds5001fp also provides high-reliability operation in harsh environments. these features include the ability to save the operating state, power-fail reset, power-fail interrupt, and watchdog timer. a user programs the ds5001fp through its on-chip serial bootstrap loader. the bootstrap loader supervises the loading of software into nv ram, valid ates it, and then becomes transparent to the user. software can be stored in multiple 32kb or one 128kb cmos sram(s). using its internal partitioning, the ds5001fp can divide a common ram into user-selectable program and data segments. this partition can be selected at program loading time, but can then be modified later at a ny time. the microprocessor decodes memory access to the sram and addresses me mory through its byte-wide bus. memory portions designated code or rom are automatically write-pr otected by the microproce ssor. combining program and data storage in one devi ce saves board space and cost. the ds5001fp offers several bank switches for access to even more memory. in addition to the primary data area of 64kb, a peripheral sele ctor creates a second 64kb data space with four accompanying chip enables. this area can be used for memory-mapped peripherals or more data storage. the ds5001fp can also use its expanded bus on ports 0 and 2 (like an 8051) to access an additional 64kb of data space. lastly, the ds5001fp provides one additional bank switch that chan ges up to 60kb of the nv ram program space into data memory. thus, with a sma ll amount of logic, the ds5001 accesses up to 252kb of data memory. the ds2251t is available (refer to the data sheet at www.maxim-ic.com/microcontrollers .) for users who want a preconstructed module using the ds5001fp, ram, lithium cell, and a real-time clock. for more details, refer to the secure microcontroller user?s guide . for users desiring software security, the ds5002fp is functionally identical to the ds5001fp but provides superior firmware security. the 44-pin version of the device is f unctionally identical to the 80-pin versi on but sports a reduced pin count and footprint.
ds5001fp 3 of 27 figure 1. block diagram
ds5001fp 4 of 27 pin description pin 80 pin 44 pin name function 11, 9, 7, 5, 1, 79, 77, 75 31 (p0.5) p0.0? p0.7 general-purpose i/o port 0. this port is open-drain and cannot drive a logic 1. it requires external pullups. port 0 is also the multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 15, 17, 19, 21, 25, 27, 29, 31 44 (p1.3) p1.0? p1.7 general-purpose i/o port 1 49, 50, 51, 56, 58, 60, 64, 66 ? p2.0? p2.7 general-purpose i/o port 2. also serves as the msb of the address in expanded memory accesses, and as pins of the rpc mode when used. 36 8 p3.0/rx d general-purpose i/o port pin 3.0 . also serves as the receive signal for the on board uart. this pin should not be connected directly to a pc com port. 38 10 p3.1/tx d general-purpose i/o port pin 3.1. also serves as the transmit signal for the on board uart. this pin should not be connected directly to a pc com port. 39 ? p3.2/ int0 general-purpose i/o port pin 3.2. also serves as the active-low external interrupt 0. 40 11 p3.3/ int1 general-purpose i/o port pin 3.3. also serves as the active-low external interrupt 1. 41 ? p3.4/t0 general-purpose i/o port pin 3.4. also serves as the timer 0 input. 44 12 p3.5/t1 general-purpose i/o port pin 3.5. also serves as the timer 1 input. 45 13 p3.6/ wr general-purpose i/o port pin. also serves as the write strobe for expanded bus operation. 46 ? p3.7/ rd general-purpose i/o port pin. also serves as the read strobe for expanded bus operation. 68 25 psen program store enable. this active-low signal is used to enable an external program memory when using the expanded bus. it is normally an output and should be unconnected if not used. psen also is used to invoke the bootstrap loader. at this time, psen is pulled down externally. this should only be done once the ds5001fp is already in a reset state. the device that pulls down should be open drain since it must not interfere with psen under normal operation. 34 6 rst active-high reset input. a logic 1 applied to this pi n will activate a reset state. this pin is pulled down internally so this pin can be left unconnected if not used. an rc power-on reset circuit is not needed and is not recommended. 70 27 ale address latch enable. used to demultiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a ?373 type transparent latch. 47, 48 14, 15 xtal2, xtal1 crystal connections . used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. 52 16 gnd logic ground 13 39 v cc power supply, +5v 12 38 v cco v cc output. this is switched between v cc and v li by internal circuits based on the level of v cc . when power is above the lithium input, power will be drawn from v cc . the lithium cell remains isolated from a load. when v cc is below v li , the v cco switches to the v li source. v cco should be connected to the v cc pin of an sram. 54 17 v li lithium voltage input. connect to a lithium cell greater than v limin and no greater than v limax as shown in the electrical speci fications. nominal value is +3v.
ds5001fp 5 of 27 pin description (continued) pin 80 pin 44 pin name function 53, 16, 8, 18, 80, 76, 4, 6, 20, 24, 26, 28, 30, 33, 35, 37 41, 36, 42, 32, 30, 34, 35, 43, 1, 2, 3, 4, 5, 7, 9 ba14? ba0 byte-wide address bus bits 14?0 . this bus is combined with the nonmultiplexed data bus (bd7?0) to access nv sram. decoding is performed using ce1 through ce4 . therefore, ba15 is not actually need ed. read/write access is controlled by r/ w . ba14?0 connect directly to an 8k, 32k, or 128k sram. if an 8k ram is used, ba13 and ba14 are unconnected. if a 128k sram is used, the micro converts ce2 and ce3 to serve as a16 and a15 respectively. 71, 69, 67, 65, 61, 59, 57, 55 28, 26, 24, 23, 21, 20, 19, 18 bd7?0 byte-wide data bus bits 7?0 . this 8-bit, bidirectional bus is combined with the nonmultiplexed address bus (ba14?0) to access nv sram. decoding is performed on ce1 and ce2 . read/write access is controlled by r/ w . bd7?0 connect directly to an sram, and optionally to a real-time clock or other peripheral. 10 37 r/ w read/write. this signal provides the write enable to the srams on the byte-wide bus. it is controlled by the memory ma p and partition. the blocks selected as program (rom) are write-protected. 74 29 ce1 chip enable 1. this is the primary decoded chip enable for memory access on the byte-wide bus. it connects to the chip enable input of one sram. ce1 is lithium- backed. it remains in a logic high inactive state when v cc falls below v li . 72 ? ce1n non-battery-backed version of chip enable 1. this can be used with a 32kb eprom. it should not be used with a battery-backed chip. 2 33 ce2 chip enable 2. this chip enable is provided to access a second 32k block of memory. it connects to the chip enable input of one sram. when msel = 0, the micro converts ce2 into a16 for a 128k x 8 sram. ce2 is lithium-backed and remains at a logic high when v cc falls below v li . 63 22 ce3 chip enable 3. this chip enable is provided to access a third 32k block of memory. it connects to the chip enable input of one sram. when msel = 0, the micro converts ce3 into a15 for a 128k x 8 sram. ce3 is lithium-backed and remains at a logic high when v cc falls below v li . 62 ? ce4 chip enable 4. this chip enable is provided to access a fourth 32k block of memory. it connects to the chip-enable input of one sram. when msel = 0, this signal is unused. ce4 is lithium-backed and remains at a logic high when v cc < v li . 78 ? pe1 peripheral enable 1. accesses data memory between addresses 0000h and 3 fffh when the pes bit is set to a logic 1. commonl y used to chip enable a byte-wide real- time clock such as the ds1283. pe1 is lithium-backed and remains at a logic high when v cc falls below v li . connect pe1 to battery-backed functions only. 3 ? pe2 peripheral enable 2. accesses data memory between addresses 4000h and 7 fffh when the pes bit is set to a logic 1. pe2 is lithium-backed and remains at a logic high when v cc falls below v li . connect pe2 to battery-backed functions only. 22 ? pe3 peripheral enable 3. accesses data memory between addresses 8000h and b fffh when the pes bit is set to a logic 1. pe3 is not lithium-backed and can be connected to any type of peripheral function. if connected to a battery-backed chip, it needs additional circuitry to maintain the chip enable in an inactive state when v cc < v li . 23 ? pe4 peripheral enable 4. accesses data memory between addresses c000h and ffffh when the pes bit is set to a logic 1. pe4 is not lithium-backed and can be connected to any type of peripheral function. if connected to a battery-backed chip, it needs additional circuitry to maintain the chip enable in an inactive state when v cc < v li . 32 ? prog invokes the bootstrap loader on a falling edge. this signal should be debounced so that only one edge is detected. if connected to ground, the micro enters bootstrap loading on power-up. this signal is pulled up internally.
ds5001fp 6 of 27 pin description (continued) pin 80 pin 44 pin name function 42 ? vrst this i/o pin (open drain with internal pullup) indicates that the power supply (v cc ) has fallen below the v ccmin level and the micro is in a reset state. when this occurs, the ds5001fp drives this pin to a logic 0. because the micro is lithium- backed, this signal is guaranteed even when v cc = 0v. because it is an i/o pin, it also forces a reset if pulled low externally. this allows multiple parts to synchronize their power-down resets. 43 ? pf this output goes to a logic 0 to indicate that v cc < v li and the micro has switched to lithium backup. because the micro is lithium-backed, this signal is guaranteed even when v cc = 0v. the normal application of this signal is to control lithium-powered current to isolate battery -backed functions from non-battery-backed functions. 14 40 msel memory select. this signal controls the memory size selection. when msel = +5v, the ds5001fp expects to use 32k x 8 srams. when msel = 0v, the ds5001fp expects to use a 128k x 8 sram. msel must be connected regardless of partition, mode, etc. 73 ? n.c. no connection instruction set the ds5001fp executes an instruction set that is object code-compatible with the industry standard 8051 microcontroller. as a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the ds 5001fp. a complete descrip tion of the instruction set and operation are provided in the secure microcontroller user?s guide . also note that the ds5001fp is embodied in the ds2251t module. the ds2251t co mbines the ds5001fp with between 32k and 128k of sram, a lithium cell, and a real-time clock. this is packaged in a 72-pin simm module. memory organization figure 2 illustrates the memory map accessed by the ds5001fp. the entire 64k of program and 64k of data are potentially available to the byte-wide bus. this preserves the i/o ports for application use. the user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range. any area not mapped into th e nv ram is reached by the expanded bus on ports 0 and 2. an alternate configuration allows dynamic partitioning of a 64k space as shown in figure 3. selecting pes=1 provides a nother 64k of potential data storage or memory-mapped peripheral space as shown in figure 4. these selections are made using special function registers. the memory map and its controls are covered in detail in the secure microcontroller user?s guide .
ds5001fp 7 of 27 figure 2. memory map in nonpartitionable mode (pm = 1)
ds5001fp 8 of 27 figure 3. memory map in partitionable mode (pm = 0) note: partitionable mode is not supported when msel pin = 0 (128kb mode).
ds5001fp 9 of 27 figure 4. memory map with pes = 1
ds5001fp 10 of 27 figure 5 illustrates a typical memory connection for a system using a 128kb sram. note that in this configuration, both program and data are stored in a common ram chip figure 6 shows a similar system with using two 32kb srams. the byte-wide addre ss bus connects to the sram address lines. the bidirectional byte-wide data bus conne cts the data i/o lines of the sram. figure 5. connection to 128k x 8 sram
ds5001fp 11 of 27 figure 6. ds5001fp connection to 64k x 8 sram power management the ds5001fp monitors v cc to provide power-fail reset, early warning power-fail interrupt, and switch over to lithium backup. it uses an internal bandgap re ference in determining the switch points. these are called v pfw , v ccmin , and v li , respectively. when v cc drops below v pfw , the ds5001fp performs an interrupt vector to location 2bh if the power-fail wa rning was enabled. full pro cessor operation continues regardless. when power falls further to v ccmin , the ds5001fp invokes a reset state. no further code execution is performed unless power rises back above v ccmin . all decoded chip enables and the r/ w signal go to an inactive (logic 1) state. v cc is still the power source at this time. when v cc drops further to below v li , internal circuitry switches to the lithium cell fo r power. the majority of internal circuits are disabled and the remaining nonvolatile states are retained. any devices connected v cco are powered by the lithium cell at this time. v cco is at the lithium battery voltage minus approximately 0.45v. this drop varies depending on the load. low power srams s hould be used for this reason. when using the ds5001fp, the user must select the appropriate battery to match the ram data rete ntion current and the desired backup lifetime. no te that the lithium cell is only loaded when v cc < v li . the user?s guide has more information on this topic. the trip points v ccmin and v pfw are listed in the el e ctrical specifications section.
ds5001fp 12 of 27 absolute maximum ratings voltage range on any pin relative to ground??????????..????????.-0.3v to (v cc + 0.5v) voltage range on v cc related to ground????????????????????????-0.3v to 6.0v operating temperature range???????????????????????????...-40 c to +85 c storage temperature range (note 1)????????????????????????..-55 c to +125 c soldering temperature????????????????????.see ipc/jedec j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. note 1: storage temperature is defined as the temperature of the device when v cc = 0v and v li = 0v. in this state, the contents of sram ar e not battery-backed and are undefined. dc characteristics (v cc = 5v 10%, t a = 0c to +70c.) parameter symbol min typ max units notes input low voltage v il -0.3 +0.8 v 1 input high voltage v ih1 2.0 v cc + 0.3 v 1 input high voltage (rst, xtal1, prog ) v ih2 3.5 v cc + 0.3 v 1 output low voltage at i ol = 1.6ma (ports 1, 2, 3, pf ) v ol1 0.15 0.45 v 1, 11 output low voltage at i ol = 3.2ma (ports 0, ale, psen , ba15?0, bd7?0, r/ w , ce1n , ce 1?4, pe 1?4, v rst ) v ol2 0.15 0.45 v 1 output high voltage at i oh = -80a (ports 1, 2, 3) v oh1 2.4 4.8 v 1 output high voltage at i oh = -400a (ports 0, ale, psen , pf , ba15?0, bd7?0, r/ w , ce1n , ce 1?4, pe 1?4, v rst ) v oh2 2.4 4.8 v 1 input low current v in = 0.45v (ports 1, 2, 3) i il -50 a transition current; 1 to 0 v in = 2.0v (ports 1, 2, 3) (0c to +70c) i tl -500 a transition current; 1 to 0 v in = 2.0v (ports 1, 2, 3) (-40c to +85c) i tl -600 a 10
ds5001fp 13 of 27 dc characteristics (continued) (v cc = 5v 10%, t a = 0c to +70c.) parameter symbol min typ max units notes input leakage current 0.45 < v in < v cc (port 0, msel) i il +10 a rst pulldown resistor (0c to +70c) r re 40 150 k rst pulldown resistor (-40c to +85c) r re 30 180 k 10 vrst pullup resistor r vr 4.7 k prog pullup resistor r pr 40 k power-fail warning voltage (0c to +70c) v pfw 4.25 4.37 4.50 v 1 power-fail warning voltage (-40c to +85c) v pfw 4.1 4.37 4.6 v 1, 10 minimum operating voltage (0c to +70c) v ccmin 4.00 4.12 4.25 v 1 minimum operating voltage (-40c to +85c) v ccmin 3.85 4.09 4.25 v 1, 10 operating voltage v cc v ccmin 5.5 v 1 lithium supply voltage v li 2.5 4.0 v 1 operating current at 16mhz i cc 36 ma 2 idle mode current at 12mhz (0c to +70c) i idle 7.0 ma 3 idle mode current at 12mhz (-40c to +85c) i idle 8.0 ma 3, 10 stop mode current i stop 80 a 4 pin capacitance c in 10 pf 5 output supply voltage (v cco ) v cco1 v cc -0.45 v 1, 2 output supply battery-backed mode (v cco , ce 1-4, pe 1-2) (0c to +70c) v cco2 v li -0.65 v 1, 8 output supply battery-backed mode (v cco , ce 1-4, pe 1-2) (-40c to +85c) v cco2 v li -0.9 v 1, 8, 10 output supply current at v cco = v cc - 0.45v i cco1 75 ma 6 lithium-backed quiescent current (0c to +70c) i li 5 75 na 7 lithium-backed quiescent current (-40c to +85c) i li 75 500 na 7 with bat = 3.0v (0c to +70c) 4.0 4.25 1 with bat = 3.0v (-40c to +85c) 3.85 4.25 1, 10 reset trip point in stop mode with bat = 3.0v (0c to +70c) 4.4 4.65 1
ds5001fp 14 of 27 ac characteristics: expanded bus mode timing specifications (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 1 oscillator frequency 1/ t clk 1.0 16 mhz 2 ale pulse width t alpw 2t clk - 40 ns 3 address valid to ale low t avall t clk - 40 ns 4 address hold after ale low t avaav t clk - 35 ns at 12mhz 4t clk - 150 5 ale low to valid instruction in at 16mhz t allvi 4t clk - 90 ns 6 ale low to psen low t allpsl t clk - 25 ns 7 psen pulse width t pspw 3t clk - 35 ns at 12mhz 3t clk - 150 8 psen low to valid instruction in at 16mhz t pslvi 3t clk - 90 ns 9 input instruction hold after psen going high t psiv 0 ns 10 input instruction float after psen going high t psix t clk - 20 ns 11 address hold after psen going high t psav t clk - 8 ns at 12mhz 5t clk - 150 12 address valid to valid instruction in at 16mhz t avvi 5t clk - 90 ns 13 psen low to address float t pslaz 0 ns 14 rd pulse width t rdpw 6t clk - 100 ns 15 wr pulse width t wrpw 6t clk - 100 ns at 12mhz 5t clk - 165 16 rd low to valid data in at 16mhz t rdldv 5t clk - 105 ns 17 data hold after rd high t rdhdv 0 ns 18 data float after rd high t rdhdz 2t clk - 70 ns at 12mhz 8t clk - 150 19 ale low to valid data in at 16mhz t allvd 8t clk - 90 ns at 12mhz 9t clk - 165 20 valid address to valid data in at 16mhz t avdv 9t clk - 105 ns 21 ale low to rd or wr low t allrdl 3t clk - 50 3t clk + 50 ns 22 address valid to rd or wr low t avrdl 4t clk - 130 ns 23 data valid to wr going low t dvwrl t clk - 60 ns at 12mhz 7t clk - 150 24 data valid to wr high at 16mhz t dvwrh 7t clk - 90 ns 25 data valid after wr high t wrhdv t clk - 50 ns 26 rd low to address float t rdlaz 0 ns 27 rd or wr high to ale high t rdhalh t clk - 40 t clk + 50 ns
ds5001fp 15 of 27 expanded program-memory read cycle expanded data-memory read cycle
ds5001fp 16 of 27 expanded data-memory write cycle
ds5001fp 17 of 27 ac characteristics : external clock drive (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units at 12mhz 20 28 external clock-high time at 16mhz t clkhpw 15 ns at 12mhz 20 29 external clock-low time at 16mhz t clklpw 15 ns at 12mhz 20 30 external clock-rise time at 16mhz t clkr 15 ns at 12mhz 20 31 external clock-fall time at 16mhz t clkf 15 ns external clock timing
ds5001fp 18 of 27 ac characteristics: power cycle time (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 32 slew rate from v ccmin to v li t f 130 s 33 crystal startup time t csu (note 9) 34 power-on reset delay t por 21,504 t clk power cycle timing
ds5001fp 19 of 27 ac characteristics: serial port timing?mode 0 (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 35 serial-port clock-cycle time t spclk 12t clk s 36 output-data setup to rising-clock edge t doch 10t clk - 133 ns 37 output-data hold after rising-clock edge t chdo 2t clk - 117 ns 38 clock-rising edge to input-data valid t chdv 10t clk - 133 ns 39 input-data hold after rising-clock edge t chdiv 0 ns serial port timing?mode 0
ds5001fp 20 of 27 ac characteristics : byte-wide address/data bus timing (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 40 delay to byte-wide address valid from ce1 , ce2 , or ce1n low during op code fetch t ce1lpa 30 ns 41 pulse width of ce 1-4, pe 1-4 or ce1n t cepw 4t clk - 35 ns 42 byte-wide address hold after ce1 , ce2 , or ce1n high during op code fetch t ce1hpa 2t clk - 20 ns 43 byte-wide data setup to ce1 , ce2 , or ce1n high during op code fetch t ovce1h 1t clk + 40 ns 44 byte-wide data hold after ce1 , ce2 or ce1n high during op code fetch t ce1hov 0 ns 45 byte-wide address hold after ce 1-4, pe 1-4, or ce1n high during movx t cehda 4t clk - 30 ns 46 delay from byte-wide address valid ce 1-4, pe 1-4, or ce1n low during movx t celda 4t clk - 35 ns 47 byte-wide data setup to ce 1-4, pe 1-4, or ce1n high during movx (read) t daceh 1t clk + 40 ns 48 byte-wide data hold after ce 1-4, pe 1-4, or ce1n high during movx (read) t cehdv 0 ns 49 byte-wide address valid to r/ w active during movx (write) t avrwl 3t clk - 35 ns 50 delay from r/ w low to valid data out during movx (write) t rwldv 20 ns 51 valid data-out hold time from ce 1-4, pe 1-4, or ce1n high t cehdv 1t clk - 15 ns 52 valid data-out hold time from r/ w high t rwhdv 0 ns 53 write pulse width (r/ w low time) t rwlpw 6t clk - 20 ns
ds5001fp 21 of 27 byte-wide bus timing rpc ac characteristics: dbb read (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 54 cs , a 0 setup to rd t ar 0 ns 55 cs , a 0 hold after rd t ra 0 ns 56 rd pulse width t rr 160 ns 57 cs , a 0 to data-out delay t ad 130 ns 58 rd to data-out delay t rd 0 130 ns 59 rd to data-float delay t rdz 85 ns rpc ac characteristics: dbb write (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 60 cs , a 0 setup to wr t aw 0 ns 61a cs , hold after wr t wa 0 ns 61b a 0 , hold after wr t wa 20 ns 62 wr pulse width t ww 160 ns 63 data setup to wr t dw 130 ns 64 data hold after wr t wd 20 ns
ds5001fp 22 of 27 ac characteristics: dma (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 65 dack to wr or rd t acc 0 ns 66 rd or wr to dack t cac 0 ns 67 dack to data valid t acd 0 130 ns 68 rd or wr to drq cleared t crq 110 ns ac characteristics: prog (v cc = 5v 10%, t a = 0c to +70c.) # parameter symbol min max units 69 prog low to active t pra 48 clks 70 prog high to inactive t pri 48 clks
ds5001fp 23 of 27 rpc timing mode
ds5001fp 24 of 27 notes: all parameters apply to both comme rcial and industrial temperatur e operation unless otherwise noted. 1) all voltages are referenced to ground. 2) maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10ns, v il = 0.5v; xtal2 disconnected; rst = port0 = v cc , msel = v ss . 3) idle mode, i idle , is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10ns, v il = 0.5v; xtal2 disconnected; port0 = v cc , rst = msel = v ss . 4) stop mode, i stop , is measured with all output pins disconnected; port0 = v cc ; xtal2 not connected; rst = msel = xtal1 = v ss . 5) pin capacitance is measured with a test frequency: 1mhz, t a = +25c. 6) i cco1 is the maximum average operating current that can be drawn from v cco in normal operation. 7) i li is the current drawn from v li input when v cc = 0v and v cco is disconnected. 8) v cco2 is measured with v cc < v li , and a maximum load of 10a on v cco . 9) crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit un til the first clock pulse is produced by the on-chip oscillator. the user should check with the crysta l vendor for a worst-case specification on this time. 10) this parameter applies to industrial temperature operation. 11) pf pin operation is specified with v bat 3.0v.
ds5001fp 25 of 27 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) 80-pin mqfp mm dim min max a - 3.40 a1 0.25 - a2 2.55 2.87 b 0.30 0.50 c 0.13 0.23 d 23.70 24.10 d1 19.90 20.10 e 17.70 18.10 e1 13.90 14.10 e 0.80 bsc l 0.65 0.95 56-g4005-001
ds5001fp 26 of 27 44-pin mqfp
ds5001fp 27 of 27 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. revision history the following represent the k ey differences between the 112795 an d 073096 version of the ds5001fp data sheet. please review this summary carefully. 1) change v cc02 specification from v li - 0.5 to v li - 0.65 (pcn f62501). 2) update mechanical specifications. the following represent the k ey differences between the 073096 an d 111996 version of the ds5001fp data sheet. please review this summary carefully. 1) change v cc01 from v cc - 0.3 to v cc - 0.35. the following represent the k ey differences between the 111996 an d 061297 version of the ds5001fp data sheet. please review this summary carefully. 1) pf signal moved from v ol2 test specification to v ol1 . pcn no. (d72502) 2) ac characteristics for battery-backed sdi pulse specification added. the following represent the k ey differences between the 061297 an d 051099 version of the ds5001fp data sheet. please review this summary carefully. 1) reduced absolute maximum voltage to v cc + 0.5v. 2) added note clarifying storage temperature specification is for non-battery-backed state. 3) changed r re min (industrial temp range) from 40k to 30k . 4) changed v pfw max (industrial temp ra nge) from 4.5v to 4.6v. 5) added industrial specification for i li . 6) reduced t ce1hov and t cehdv from 10ns to 0ns. the following represent the k ey differences between the 051099 an d 052499 version of the ds5001fp data sheet. please review this summary carefully. 1) minor markups and ready for approval. the following represent the k ey differences between the 052499 an d 052302 version of the ds5001fp data sheet. please review this summary carefully. 1) added information relating to 44-pin package. 2) updated v cco1 and i cco1 specifications to reflect 0.45v inte rnal voltage drop instead of 0.35v. the following represent the k ey differences between the 052302 an d 070605 version of the ds5001fp data sheet. please review this summary carefully. 1) added pb-free part to ordering information table. 2) added operating voltage specification. (this is not a new specification because operating voltage is implied in the testing limits, but rather a clarification.) 3) updated absolute maximum ratings soldering temperature to reference jedec standard.

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