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LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 0 ? revision history revision description issue date rev. 1.0 initial issue jul.25.2004 rev. 1.1 adding pkg type : 32 sop mar.3.2006 rev. 1.2 adding pkg type : 32 p-dip revised test condition of i sb1 /i dr may.14.2007 rev. 1.3 deleted l grade added sl grade added i sb1 /i dr values when t a = 25 and t a = 40 revised features & ordering information lead free and green package available to green package available added packing type in ordering information revised v term to v t1 and v t2 deleted t solder in absolute maximun ratings mar.30.2009
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 1 ? features ? fast access time : 45/55/70ns ? low power consumption: operating current : 23/20/18ma (typ.) standby current : 1 a (typ.) ll/sl -version ? single 2.7v ~ 3.6v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tri-state output ? data retention voltage : 1.5v (min.) ? green package available ? package : 32-pin 450 mil sop 32-pin 8mm x 20mm tsop-i 32-pin 8mm x 13.4mm stsop 36-ball 6mm x 8mm tfbga general description the LY62L2568 is a 2,097,152-bit low power cmos static random access memory organized as 262,144 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the LY62L2568 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. the LY62L2568 operates from a single power supply of 2.7v ~ 3.6v and all inputs and outputs are fully ttl compatible 32-pin 600 mil p-dip product family power dissipation product family operating temperature vcc range speed standby(i sb1, typ.) operating(icc,typ.) LY62L2568 0 ~ 70 2.7 ~ 3.6v 45/55/70ns 1a 23/20/18ma LY62L2568(e) -20 ~ 80 2.7 ~ 3.6v 45/55/70ns 1a 23/20/18ma LY62L2568(i) -40 ~ 85 2.7 ~ 3.6v 45/55/70ns 1a 23/20/18ma functional block diagram decoder i/o data circuit control circuit 256kx8 memory array column i/o a0-a17 vcc vss dq0-dq7 ce# we# oe# ce2 pin description symbol description a0 - a17 address inputs dq0 ? dq7 data inputs/outputs ce#, ce2 chip enable inputs we# write enable input oe# output enable input v cc power supply v ss ground nc no connection
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 2 ? pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss a14 vcc a8 a9 a11 a10 dq7 dq6 dq5 dq4 dq3 LY62L2568 sop/p-dip 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a13 ce# oe# we# a16 a17 29 32 30 31 ce2 a15 tsop-i/stsop dq3 a11 a9 a8 a13 dq2 a10 a14 a12 a7 a6 a5 vcc dq7 dq6 dq5 dq4 vss dq1 dq0 a0 a1 a2 a4 a3 LY62L2568 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 oe# we# ce# ce2 a15 a16 a17 32 31 29 30 tfbga oe# we# a12 a11 a13 ce2 nc a10 a14 a15 dq5 dq6 dq7 a9 vss a8 a16 dq4 vcc vcc dq3 a17 vss a7 a0 dq2 dq1 dq0 a6 a1 a3 a5 nc a4 a2 123456 h g c d e f a b ce#
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 3 ? absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 4.6 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v 0 to 70(c grade) -20 to 80(e grade) operating temperature t a -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. truth table mode ce# ce2 oe# we# i/o operation supply current h x x x high-z i sb ,i sb1 standby x l x x high-z i sb ,i sb1 output disable l h h h high-z i cc ,i cc1 read l h l h d out i cc ,i cc1 write l h x l d in i cc ,i cc1 note: h = v ih , l = v il , x = don't care.
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 4 ? dc electrical characteristics parameter symbol test condition min. typ. *4 max. unit supply voltage v cc 2.7 3.0 3.6 v input high voltage v ih *1 2.2 - v cc +0.3 v input low voltage v il *2 - 0.2 - 0.6 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss , output disabled - 1 - 1 a output high voltage v oh i oh = -1ma 2.2 2.7 - v output low voltage v ol i ol = 2ma - - 0.4 v - 45 - 23 40 ma - 55 - 20 35 ma i cc cycle time = min. ce# = v il and ce2 = v ih , i i/o = 0ma other pins at v il or v ih - 70 - 18 30 ma average operating power supply current i cc1 cycle time = 1 s ce# = 0.2v and ce2 R v cc -0.2v, i i/o = 0ma other pins at 0.2v or v cc - 0.2v - 4 5 ma i sb ce# = v ih or ce2 = v il, other pins at v il or v ih - 0.3 0.5 ma ll - 1 10 a lle/lli - 1 20 a 25 - 1 3 a sl *5 sle *5 sli *5 40 - 1 3 a sl - 1 10 a standby power supply current i sb1 ce# v R cc -0.2v or ce2 Q 0.2v others at 0.2v or v cc - 0.2v sle/sli - 1 15 a notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ.) and t a = 25 5. this parameter is measured at v cc = 3.0v
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 5 ? capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by devic e characterization, but not production tested. ac test conditions input pulse levels 0.2v to v cc - 0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh /i ol = -1ma/2ma ac electrical characteristics (1) read cycle LY62L2568-45 LY62L2568-55 LY62L2568-70 parameter sym. min. max. min. max. min. max. unit read cycle time t rc 45 - 55 - 70 - ns address access time t aa - 45 - 55 - 70 ns chip enable access time t ace - 45 - 55 - 70 ns output enable access time t oe - 25 - 30 - 35 ns chip enable to output in low-z t clz * 10 - 10 - 10 - ns output enable to output in low-z t olz * 5 - 5 - 5 - ns chip disable to output in high-z t chz * - 15 - 20 - 25 ns output disable to output in high-z t ohz * - 15 - 20 - 25 ns output hold from address change t oh 10 - 10 - 10 - ns (2) write cycle LY62L2568-45 LY62L2568-55 LY62L2568-70 parameter sym. min. max. min. max. min. max. unit write cycle time t wc 45 - 55 - 70 - ns address valid to end of write t aw 40 - 50 - 60 - ns chip enable to end of write t cw 40 - 50 - 60 - ns address set-up time t as 0 - 0 - 0 - ns write pulse width t wp 35 - 45 - 55 - ns write recovery time t wr 0 - 0 - 0 - ns data to write time overlap t dw 20 - 25 - 30 - ns data hold from end of write time t dh 0 - 0 - 0 - ns output active from end of write t ow * 5 - 5 - 5 - ns write to output in high-z t whz * - 15 - 20 - 25 ns *these parameters are guaranteed by device characterization, but not production tested.
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 6 ? timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and ce2 and oe# controlled) (1,3,4,5) dout data valid t oh oe# high-z high-z t clz t olz t oe t chz t ohz ce2 t ace ce# t aa address t rc notes : 1.we# is high for read cycle. 2.device is continuously selected oe# = low, ce# = low ., ce2 = high . 3.address must be valid prior to or coincident with ce# = low , ce2 = high; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz.
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 7 ? write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow ce# t aw address t wc ce2 write cycle 2 (ce# and ce2 controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc ce2 notes : 1.we#, ce# must be high or ce2 must be low during all address transitions. 2.a write occurs during the overlap of a low ce#, high ce2, low we#. 3.during a we#controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce#low transition and ce2 high transit ion occurs simultaneously with or after we# low transition, the outputs remain i n a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 8 ? data retention characteristics parameter symbo l test condition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v or ce2 Q 0.2v 1.5 - 3.6 v ll - 0.5 5 a lle/lli - 0.5 10 a 25 - 0.5 3 a sl sle sli 40 - 0.5 3 a sl - 0.5 5 a data retention current i dr v cc = 1.5v ce# v R cc - 0.2v or ce2 Q 0.2v other pins at 0.2v or v cc -0.2 v sle/sli - 0.5 10 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform low vcc data retention waveform (1) ( ce# controlled) vcc ce# v dr R 1.5v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.) low vcc data retention waveform (2) (ce2 controlled) vcc ce2 v dr R 1.5v ce2 Q 0.2v vcc(min.) v il t r t cdr v il vcc(min.)
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 9 ? package outline dimension 32 pin 450 mil sop package outline dimension unit sym. inch.(base) mm(ref) a 0.118 (max) 2.997 (max) a1 0.004(min) 0.102(min) a2 0.111(max) 2.82(max) b 0.016(typ) 0.406(typ) c 0.008(typ) 0.203(typ) d 0.817(max) 20.75(max) e 0.445 0.005 11.303 0.127 e1 0.555 0.012 14.097 0.305 e 0.050(typ) 1.270(typ) l 0.0347 0.008 0.881 0.203 l1 0.055 0.008 1.397 0.203 s 0.026(max) 0.660 (max) y 0.004(max) 0.101(max) 0 o -10 o 0 o -10 o
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 10 ? 32 pin 8mm x 20mm tsop-i package outline dimension unit sym. inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.004 0.002 0.10 0.05 a2 0.039 0.002 1.00 0.05 b 0.008 + 0.002 - 0.001 0.20 + 0.05 -0.03 c 0.005 (typ) 0.127 (typ) d 0.724 0.004 18.40 0.10 e 0.315 0.004 8.00 0.10 e 0.020 (typ) 0.50 (typ) hd 0.787 0.008 20.00 0.20 l 0.0197 0.004 0.50 0.10 l1 0.0315 0.004 0.08 0.10 y 0.003 (max) 0.076 (max) 0 o 5 o 0 o 5 o
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 11 ? 32 pin 8mm x 13.4mm stsop package outline dimension 1 16 17 32 c l hd d "a" e e 12 (2x) 12 (2x) seating plane y 32 17 16 1 c a2 a1 l a 0.254 0 gauge plane 12 (2x) 12 (2x) seating plane "a" datail view l1 b unit sym. inch(base) mm(ref) a 0.049 (max) 1.25 (max) a1 0.005 0.002 0.130 0.05 a2 0.039 0.002 1.00 0.05 b 0.008 0.01 0.20 0.025 c 0.005 (typ) 0.127 (typ) d 0.465 0.004 11.80 0.10 e 0.315 0.004 8.00 0.10 e 0.020 (typ) 0.50 (typ) hd 0.528 0.008 13.40 0.20. l 0.0197 0.004 0.50 0.10 l1 0.0315 0.004 0.8 0.10 y 0.003 (max) 0.076 (max) 0 o 5 o 0 o 5 o
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 12 ? 36 ball 6mm 8mm tfbga package outline dimension
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 13 ? 32 pin 600 mil p-dip package outline dimension note : d/e1/s dimension do not include mold flash. unit sym. inch(base) mm(ref) a1 0.001 (min) 0.254 (min) a2 0.150 0.005 3.810 0.127 b 0.018 0.005 0.457 0.127 d 1.650 0.005 41.910 0.127 e 0.600 0.010 15.240 0.254 e1 0.544 0.004 13.818 0.102 e 0.100 (typ) 2.540 (typ) eb 0.640 0.020 16.256 0.508. l 0.130 0.010 3.302 0.254 s 0.075 0.010 1.905 0.254 q1 0.070 0.005 1.778 0.127
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 14 ? ordering information LY62L2568 u v - ww xx y z z : packing type blank : tube or tray t : tape reel y : temperature range blank : (commercial) 0c ~ 70c e : (extended) -20c ~ +80c i : (industrial) -40c ~ +85c u : package type s : 32-pin 450 mil sop l : 32-pin 8 mm x 20 mm tsop-i r : 32-pin 8 mm x 13.4 mm stsop g : 36-ball 6 mm x 8 mm tfbga p : 32-pin 600 mil p-dip ww : access time(speed) xx : power type ll : ultra low power sl : special ultra low power v : lead information l : green package
LY62L2568 rev. 1.3 256k x 8 bit low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 15 ? this page is left blank intentionally.

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