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ara2017 programmable gain amplifer data sheet - rev 2.1 f eatures ? high linearity, high output power integrated amplifer with programmable gain control ? attenuation range: 0-58 db, adjustable in 2 db increments via a 3-wire serial control ? 33 db gain (at minimum attenuation) ? low distortion products at output power levels up to +64 dbmv ? low noise figure and output noise ? frequency range: 5-85 mhz ? 5 v operation ? materials set consistent with rohs directives. surface mount package applic ations ? docsis 3.0 data cable modems and e-mtas ? catv set top boxes product description the ara2017 is a highly linear, high output power, programmable gain amplifer optimized for docsis 3.0 cable modem and e-mta applications. using a low noise input amplifcation stage and an ultra linear output driver amplifer, the device generates extremely low distortion products at the high output power levels required by docsis 3.0 signals. its balanced circuit design provides superior harmonic performance and an integrated digitally-controlled, multiple-stage precision step attenuator enables system solutions to meet docsis power step accuracy requirements. s29 package 28-pin qfn 5 mm x 5 mm x 1 mm figure 1: functional block diagram the ara2017 supports output power levels of +64 dbmv while minimizing harmonic, distortion, and output noise levels. its precision attenuator provides up to 58 db of attenuation in 2 db increments, which is set by programming the register via a 3-wire serial interface. the output stage current, a feature which allows the device to be operated in reduced power modes for extended backup battery life, is also programmed through the 3-wire serial interface. the ara2017 is offered in a 28-pin 5 mm x 5 mm x 1 mm qfn package. 11/2012
2 table 1: pin description figure 2: p inout (x-ray top view) pin n ame des c r ip t ion pin n ame des c r ip t ion 1 a1 in+ amplifier a1 (+) input 28 a1 out+ amplifier a1 (+) output and supply 2 gnd ground 27 attn in+ attentuator input (+) 3 a1 in- amplifier a1 (-) input 26 gnd ground 4 gnd ground 25 v attn attenuator supply 5 a1 out- amplifier a1 (-) output and supply 24 gnd ground 6 attn in- attentuator input (-) 23 attn out+ attentuator output (+) 7 n/c no connection 22 a2 in+ amplifier a2 (+) input 8 gnd ground 21 a2 out+ amplifier a2 (+) output and supply 9 clock clock 20 gnd ground 10 d ata data 19 a2 out- amplifier a2 (-) output and supply 11 enbl enable 18 gnd ground 12 n/c no connection (reserved for future use - leave floating) 17 a2 in- amplifier a2 (-) input 13 tx_en transmit enable 16 attn out- attentuator output (-) 14 v dd supply 15 n/c no connection data sheet - rev 2.1 11/2012 ara2017
3 electrical characteristics table 2: absolute minimum and maximum ratings table 3 : operating ranges stresses in excess of the absolute ratings may cause permanent damage. f unctional operation is not implied under these conditions. exposure to absolute ratings for extended periods of time may adversely affect reliability. the device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defned in the electrical specifcations. table 4 : digital interface specifcations (v dd = +5.0 v) note: (1) logic control levels apply to the 3-wire programming bus (pins 9, 10, 11) and the transmit enable control (pin 13). p arameter m in max uni t co mme n ts supply: v dd (pins 5, 14, 19, 21, 28), v attn (pin 25) 0 +6 v rf power at inputs (pins 1, 3) - +40 dbmv differential into 200 ? digital interface (pins 9, 10, 11, 13) -0.5 v dd +0.5 v storage temperature -55 +150 c p arameter m in ty p max uni t logic high input voltage: v in , high +2.0 - v dd v logic low input voltage: v in , low 0 - +0.8 v pa ra me te r mi n ty p ma x uni t op er at in g fr equ en cy (f )5 -8 5m hz su pply : v dd (p in s 5, 14, 19 , 21 , 28) +4 .5 +5 +5 .5 v digi ta l in te rf ace (p in s 9, 10 , 11 , 13 )0 -v dd v ca se te mp er at ur e (t c )- 40 +2 5+ 95 c data sheet - rev 2.1 11/2012 ara2017
4 table 5 : electrical specifcations (v dd = +5.0 v, t x enabled (unless otherwise noted), t c = 25 8c) notes: (1) as measured in anadigics test fxture. (2) measured using the maximum current setting-see application information section. p arameter m in ty p max uni t co mme n ts gain (1) 34 36 37 db 0 db attenuation setting gain flatness (1) - - 0.5 1.0 - - db 5 to 42 mhz 5 to 85 mhz gain variation over temperature - -0.02 - db/c gain range with attenuator 58 - - db incremental attenuator step size 1.5 2.5 db nd harmonic distortion level (1) (2) - -67 -55 dbc +64 dbmv into 75 ? 3 rd harmonic distortion level (1) (2) - -72 -55 dbc +64 dbmv into 75 ? 3rd order output intercept (1) (2) +88 +93 - dbmv 2 tone, +61 dbmv/tone 1 db gain compression (1) (2) - +73 - dbmv noise figure (1) (2) - 2.5 - db full gain @ 0 db attenuator setting; includes input balun loss output noise power active / no signal / min. atten. set. active / no signal / max. atten. set. - - -38.5 -53.8 - - dbmv any 160 khz bandwidth from 5 to 85 mhz isolation (85 mhz) in tx disable mode - 60 - db differential input impedance - 200 - ? between pins 1 and 3 (tx enabled) differential output impedance - 75 - ? between pins 19 and 21 output impedance - 75 - ? with transformer output return loss (75 ohm characteristic impedance) - - -15 -12 - - db tx enabled tx disabled output voltage transient tx enable / tx disable - - 50 7 - - mvp-p 0 db attenuator setting 24 db attenuator setting total supply current (1) (2) (pins 5, 14, 19, 21, 25, 28) - - 340 10.5 400 - tx enabled (tx_en high) tx disabled (tx_en low) total power consumption - - 1.7 52.5 - - w mw tx enabled (tx_en high) tx disabled (tx_en low) thermal resistance ( ? jc ) - 30 - 8 c/w data sheet - rev 2.1 11/2012 ara2017
5 data plots figure 3: gain vs. f requency over voltage (t c = 25 8c) figure 4: noise figure vs. f requency over voltage (t c = 25 8c) 1.5 2 2.5 3 3.5 4 0 20 40 60 80 100 120 nf (db) f requency (mhz) f igure ?: n oise f igure vs f requency over voltage +5v +5.25v +5.5v +4.75v +4.5v v dd = 33 33.5 34 34.5 35 35.5 36 0 20 40 60 80 100 120 gain (db) f requency (mhz) f igure ?: gain vs f requency over voltage +5v +5.25v +5.5v +4.75v +4.5v v dd = data sheet - rev 2.1 11/2012 ara2017
6 figure 5: gain & noise f igure vs. temperature (vdd = +5v, f1 = 10 mhz) figure 6: 1db gain compression (p 1db) vs. voltage (tc = 25 8c, f1 = 10 mhz) 1 2 3 4 5 6 7 30 31 32 33 34 35 36 0 20 40 60 80 100 120 nf (db) gain(db) c ase temperature (t c ) - o c f igure ?: gain & n oise f igure vs. temperature ( v dd = + 5v, f 1 = 10mhz ) gain db nf db 73 73.5 74 74.5 75 75.5 76 76.5 77 4.4 4.6 4.8 5 5.2 5.4 5.6 p 1db (dbmv) voltage (vdc) f igure ?: 1db gain c ompression ( p 1db) vs voltage ( t c = 25 o c , f 1 = 10mhz ) data sheet - rev 2.1 11/2012 ara2017
7 figure 7: 1db gain compression (p 1db) vs. temperature (v dd = +5 v, f1 = 10 mhz) figure 8: output third order intercept point (oip 3) vs. voltage (tc = 25 8c, f1 = 10 mhz, f 2 = 11 mhz) 73 73.5 74 74.5 75 75.5 76 76.5 77 0 20 40 60 80 100 120 p 1db(dbmv) c ase temperature ( o c) f igure ?: 1db gain c ompression ( p 1db) vs. c ase temperature ( vdd = +5v, f 1 = 10mhz ) 82 83 84 85 86 87 88 89 90 91 92 4.4 4.6 4.8 5 5.2 5.4 5.6 oip 3 (dbmv) voltage (vdc) f igure ?: o utput third o rder i ntercept p oint ( oip 3) vs voltage data sheet - rev 2.1 11/2012 ara2017
8 figure 7: output third order intercept point (oip 3) vs temperature (v dd = +5 vdc, f 1 = 10 mhz, f2 = 11 mhz) f igure 10: attenuator accuracy over frequency (t c = 25 8c, v dc = +5v) 0 5 10 15 20 25 30 35 10 20 30 40 50 60 70 80 90 100 measured attenuation (db) f requency (mhz) f igure ?: attenuator accuracy over f requency 2db 4db 8db 16db 32db tc = 25 o c , vdc = +5v atte nuat o r sett in g = 85 86 87 88 89 90 91 92 93 94 95 0 20 40 60 80 100 120 oip 3(dbmv) c ase temperature( o c) f igure ?: o utput third o rder i ntercept p oint ( oip 3) vs. c ase temperature data sheet - rev 2.1 11/2012 ara2017
9 f igure 11:attenuator accuracy over voltage (t c = +25 8c, f1 = 10 mhz) f igure 12: attenuator accuracy over temperature (v dc = +5v, f1 = 10 mhz) 0 5 10 15 20 25 30 35 25 35 45 55 65 75 85 95 measured attenuation(db) c ase temperature ( o c) f igure ?: attenuator accuracy over temperature 2db 4db 8db 16db 32db ( v= +5v, f 1 = 10mhz ) atte nuat o r sett in g = 0 5 10 15 20 25 30 35 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 measured attenuation(db) supply voltage, vdd (vdc) f igure ?: attenuator accuracy over voltage 2db 4db 8db 16db 32db ( tc = +25 o c , f 1 = 10mhz ) atte nuat o r sett in g = data sheet - rev 2.1 11/2012 ara2017
10 figure 13: gain & idd vs. power control setting figure 14: p out & harmonics vs. power control setting 28.00 30.00 32.00 34.00 36.00 38.00 40.00 42.00 44.00 0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 400.00 0 2 4 6 8 gain (db) c urrent (ma) p ower c ontrol setting (1) f igure 13: gain & i dd vs p control setting current gain - 70.00 - 65.00 - 60.00 - 55.00 - 50.00 - 45.00 - 40.00 - 35.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 0 1 2 3 4 5 6 7 8 harmonics ( - dbc) p out (dbmv) p ower c ontrol setting (1) f igure ??: p out & harmonics vs p control setting pout 2nd 3rd data sheet - rev 2.1 11/2012 ara2017
11 figure 15: p1db vs. power control setting figure 16: oip3 & p out vs. power control setting notes (figures 13-16): (1) power control setting refers to the programming register bits 7, 8, and 9 (see t able 6). the power control can be set using anadigics tuner control software, version 1.2.3, in the advanced settings window. the software is used in conjunction with the anadigics ara2017 evaluation board. 40 50 60 70 80 90 0 1 2 3 4 5 6 7 8 p 1db (dbmv) p ower c ontrol setting (1) f igure 15: p 1db vs p control 25 35 45 55 65 75 85 95 105 0 1 2 3 4 5 6 7 8 oip 3 or p out (dbmv) p ower c ontrol setting (1) f igure 16: oip 3 & p out vs p control oip3 pout data sheet - rev 2.1 11/2012 ara2017
12 f igure 17: test circuit notes: (1) pin 12 is reserved for future use. do not connect (leave foating). (2) input balun is used for evaluation test purposes only in 75 ? system. actual application does not require a 4:1 balun on the input. data sheet - rev 2.1 11/2012 ara2017
13 table 6: programming register logic programming figure 18: serial data i nput timing programming instructions the programming word is set through a 10 bit shift register via the data, clock and enable lines. the data is entered in order with the most signifcant bit (msb) frst and the least signifcant bit (lsb) last. the enable line must be low for the duration of the data entry, then set high to latch the shift register. the rising edge of the clock pulse shifts each data value into the register. notes: (1) refer to application information section for current and gain bit settings. (2) data bit 0 should always be set to 1. (3) data bit 1 is reserved for future use, and should be set to 0. data b i t 9 8 7 6 5 4 3 2 1 0 func t ion current gain 0 1 data sheet - rev 2.1 11/2012 ara2017
14 applic ation info rmation transmit enable / disable the ara2017 can be switched on (t x enable) and off (t x disable) via an asynchronous input tx_en (pin 13). a logic high will turn the amplifer on. the gain and current settings are retained during tx disable and do not need to be reloaded. gain/attenuator setting the gain of the ara2017 can be controlled via the 3-wire bus. data bits d2 through d6 set the gain/ attenuator level, with 00000 being the min gain setting, and 11111 being the max gain setting. a new gain/ attenuator setting can be loaded while the pga is on (t x enable), but will not take effect until tx_en has been cycled off /on. output stage current setting the ara2017 consists of 2 gain stages. the input stage operates at a constant fxed current when t x is enabled. the current in the output stage can be controlled via the 3-wire bus. data bits d7 C d9 set the current. 111 will set the output stage to maximum current for maximum linearity. the current can be lowered for improved efficiency at lower output power levels, or lower linearity requirements. 000 will turn both stages off, the same as t x disable. a new current setting can be loaded while the pga is on (t x enable), but will not take effect until tx_en has been cycled off /on. o utput transformer matching the balanced output of the ara2017 to a single-ended 75 ? load is accomplished using a 1:1 turns ratio transformer. in addition to the balanced to single-ended conversion, this transformer provides the bias to the output amplifer stage via the center tap. the transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifers. as a result, care must be taken when selecting the transformer to be used at the output. it must be capable of handling the rf and dc power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. it also must operate over the desired frequency and temperature range for the intended application. data sheet - rev 2.1 11/2012 ara2017
15 figure 19: s29 package outline - 28 pin 5 mm x 5 mm x 1 mm qfn p ackage outline data sheet - rev 2.1 11/2012 ara2017
16 figure 20: land pattern data sheet - rev 2.1 11/2012 ara2017
17 ordering info rmation o rde r num be r tem per at ure ra ng e pa ckag e descri pt ion co mp on ent pa ckagin g ar a2 017r s2 9p 8- 40 o c to +9 5 o c 28 pi n qf n pa ckage 5 mm x 5 mm x 1 mm ta pe an d re el , 2500 pi eces per r eel warning anadigics products are not intended for use in life support appliances, devices or systems. use of an anadigics product in any such application without written consent is prohibited. import ant notice anadigics, inc. 141 mount bethel road warren, new jersey 07059, u.s.a. tel: +1 (908) 668-5000 fax: +1 (908) 668-5132 url: http://www.anadigics.com e-mail: mktg@anadigics.com anadigics, inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. the product specifcations contained in advanced product information sheets and preliminary data sheets are subject to change prior to a products formal introduction. information in data sheets have been carefully checked and are assumed to be reliable; however, anadigics assumes no responsibilities for inaccuracies. anadigics strongly urges customers to verify that the information they are using is current before placing orders. data sheet - rev 2.1 11/2012 ara2017

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