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1 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector functional diagram features ultra-low noise: -231 dbc/hz fom integer mode -227 dbc/hz fom fractional mode ultra low spurious emissions: - less than 60 dbc fractional spurious differential phase detector input 14-bit reference frequency divider lock indicator output phase measurement capability gpio (general purpose input/output) test pin cycle slip prevention support with HMC984LP4E 24 pin, 4 x 4 mm, lp4e package typical applications the HMC984LP4E is suitable for: ? test equipment ? portable instruments ? high performance fractional-n frequency synthesizers with ultra low spurious emissions ? military general description HMC984LP4E is a high-performance, ultra-low phase noise, sige bicmos phase-frequency detector and charge pump targeted to be used together with the hmc983lp5e (fractional frequency divider) to together form a high performance, low noise, ultra low spurious emission fractional-n frequency synthesizer. although best performance and maximum features are achieved when used together with the hmc983lp5e, the HMC984LP4E can also be used as a stand-alone, low phase noise phase frequency detector. the HMC984LP4E can receive differential vco input, and a reference frequency as high as 150 mhz. it features a 14-bit reference frequency r-divider, and automatic and/or confgurable lock detect indicator, as well as integrated csp (cycle slip prevention) capability, when used together with the hmc983lp5e, that signifcantly improves frequency lock time. integrated charge pump phase swap option enables seamless interfaced to vcos and active loop flters with inverted polarity. additional features include adjustable charge pump gain and offset current that improve linearity and performance, and a soft reset feature that resets all register to default values without having to perform a power-cycle. the HMC984LP4E is housed in a compact 24 pin 4x4 mm lp4 package. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
2 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 1. electrical specifcations ta = +25 c, avdd, rvdd, vddpd1, vddpd2, dvdd = 3 v; vccpd, vppcp, vddcp = 5 v; gnd = 0 v parameter conditions min. typ. max. units ref. input characteristics frequency range dc 50 350 mhz ref. input power range 50 ? source 6 12 dbm ref. input impedance 100||3 ?|| pf ref/-divider range (14-bit) 1 16383 phase detector (pd) pd input internal pull-up resistance vcop, vcon, each side 50 ? pd input current vcop, vcon, 2.5 ma steps 12.5 15 17. 5 ma pd input voltage swing single-ended peak-to-peak 625 750 875 mv fractional mode phase detector frequency 12 dbm sine-wave input, mode a & b dc 50 125 mhz 2 dbm square-wave input, mode a & b dc 50 90 mhz integer mode phase detector frequency 12 dbm sine-wave input dc 50 175 mhz 2 dbm square-wave input dc 50 150 mhz charge pump (cp) cp output current 7-bit programmable, 20 ua/step, charge pump gain = cp current/2 amps/rad 0.02 2.5 ma cp hik see charge pump high gain (hik) mode section 3.5 6 m a offset current 7-bit programmable,5 ua/step 5 635 a phase noise [1] floor figure of merit (fom) integer mode -230 dbc/hz fractional modes a & b -227 dbc/hz hik integer mode -232 dbc/hz hik fractional mode a -230 dbc/hz hik fractional mode b -229 dbc/hz flicker figure of merit (fom) integer mode -269 dbc/hz fractional modes a & b -267 dbc/hz hik integer mode -268 dbc/hz hik fractional mode a -266 dbc/hz hik fractional mode b -266 dbc/hz spurious [1] integer boundary spurs @ 2.1 ghz frequency offsets less than loop band - width f pd =50 mhz, mode a -60 -55 dbc integer boundary spurs @ 2.1 ghz frequency offsets less than loop band - width f pd =50 mhz, mode b -70 -65 dbc 1/2 integer boundary spurs f pd =50 mhz -75 -70 dbc 1/3 integer boundary spurs f pd =50 mhz -85 -80 dbc [1] measured with hmc983lp5e/HMC984LP4E as fractional-n synthesizer chip set. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 3 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 1. electrical specifcations ta = +25 c, avdd, rvdd, vddpd1, vddpd2, dvdd = 3 v; vccpd, vppcp, vddcp = 5 v; gnd = 0 v parameter conditions min. typ. max. units 1/5 integer boundary spurs fpd=50 mhz -85 dbc logic inputs vih input high voltage dvdd - 0.4 v vil input low voltage 0.4 v logic outputs voh output high voltage dvdd- 0.4 v vol output low voltage 0.4 v dc load 1.5 ma serial port serial port clock frequency 30 mhz power supplies avdd, rvdd analog supplies, avdd should equal dvdd 2.8 3 3.3 v vccpd 5 v analog supply for pd 4.5 5 5.5 v vppcp cp analog supply 4.5 5 5.5 v vddcp cp digital supply 4.5 5 5.5 v dvdd, vddpd1, vddpd2 digital supplies 2.8 3 3.3 v current consumption idd- total current consumption 123.6 ma i-avdd (3 v) avdd current 4.8 ma i-rvdd (3 v) reference path current 22 ma i-vccpd (5 v) pd current 83.5 ma i-vddpd1 (3 v) pd digital supply current 2.7 ma i-vddpd2 (3 v) pd digital supply current 2.7 ma i-vppcp (5 v) cp analog supply current 3 ma i-vddcp (5 v) cp digital supply current 2.9 ma i-dvdd (3 v) total dvdd current 2 ma bias reference voltage [2] measured with 10 g ? volt meter 1.58 1.72 1.86 v continued... [2] bias voltage cannot drive external load. it must be measured with a 10 g? voltmeter such as agilent 34410a. a typical 10 m? digital volt meter will read erroneously. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
4 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector typical performance characteristics -269.5 -269 -268.5 -268 -267.5 -267 -266.5 -266 -50 -25 0 25 50 75 100 flicker fom (dbc/hz) temperature (c) integer mode mode b hi k mode b hi k integer mode figure 1. HMC984LP4E & hmc983lp5e pll flicker fom vs temperature [1] figure 2. HMC984LP4E & hmc983lp5e pll floor fom vs temperature [1] -233 -232 -231 -230 -229 -228 -227 -226 -50 -25 0 25 50 75 100 flicker fom (dbc/hz) temperature (c) integer mode mode b hi k mode b hi k integer mode figure 3. HMC984LP4E & hmc983lp5e pll flicker fom vs frequency [1] -269.5 -269 -268.5 -268 -267.5 -267 -266.5 -266 -265.5 12345678 flicker fom (dbc/hz) frequency(ghz) integer mode mode a mode b hi k integer mode hi k mode b hi k mode a figure 4. HMC984LP4E & hmc983lp5e pll floor fom vs frequency [1] -233 -232 -231 -230 -229 -228 -227 -226 12345678 flicker fom (dbc/hz) frequency(ghz) integer mode mode a mode b hi k integer mode hi k mode b hi k mode a figure 5. HMC984LP4E & hmc983lp5e pll flicker fom vs reference power [1] -268.5 -268 -267.5 -267 -266.5 -266 -265.5 -265 -264.5 -15 -10 -5 0 5 10 15 flicker fom (dbc/hz) reference power (dbm) mode b hi k mode b integer mode hi k integer mode figure 6. HMC984LP4E & hmc983lp5e pll floor fom vs reference power [1] -233 -232 -231 -230 -229 -228 -227 -226 -225 -15 -10 -5 0 5 10 15 floor fom (dbc/hz) reference power (dbm) mode b hi k mode b integer mode hi k integer mode [1] crystal frequency = 100 mhz, pfd frequency = 50 mhz, active loop filter with 220 khz bandwidth. measured at 4101 mhz in fractional mode and 4100 mhz in integer mode. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 5 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector figure 7. HMC984LP4E & hmc983lp5e pll flicker fom vs cp current [2] -266 -265 -264 -263 -262 -261 -260 -259 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 flicker fom (dbc/hz) charge pump current (ma) figure 8. HMC984LP4E & hmc983lp5e pll floor fom vs cp current [2] -228 -226 -224 -222 -220 -218 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 floor fom (dbc/hz) charge pump current (ma) figure 9. HMC984LP4E & hmc983lp5e pll flicker fom vs cp voltage [3] -270 -265 -260 -255 -250 -245 -240 -235 -230 012345 flicker fom (dbc/hz) charge pump voltage (v) mode b hi k mode b integer mode hi k integer mode figure 10. HMC984LP4E & hmc983lp5e pll floor fom vs cp voltage [3] -235 -230 -225 -220 -215 -210 -205 -200 -195 012345 floor fom (dbc/hz) charge pump voltage (v) mode b hi k mode b integer mode hi k integer mode figure 11. HMC984LP4E & hmc983lp5e pll performance at 7000.01 mhz [4] -180 -160 -140 -120 -100 -80 -60 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset frequency (hz) figure 12. HMC984LP4E & hmc983lp5e pll performance at 4100.01 mhz [5] -180 -160 -140 -120 -100 -80 -60 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset frequency (hz) [2] pll operated in mode b, cp votage = 2.5 v, active loop filter with 220 khz bandwidth used [3] charge pump current = 2.5 ma [4] crystal frequency=100mhz, pd frequency=50mhz, cp current=2.5ma, cp offset current=255 a, loop bandwidth = 87 khz, pll in mode b. [5] reference frequency=100 mhz, pd frequency=50 mhz, cp current=2.5 ma, cp offset current=280 a, loop bandwidth = 87 khz, pll in mode b. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
6 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector figure 13. HMC984LP4E & hmc983lp5e pll performance at 2100.01 mhz [6] -180 -160 -140 -120 -100 -80 -60 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset frequency (hz) figure 14. HMC984LP4E & hmc983lp5e [6] figure 15. HMC984LP4E & hmc983lp5e pll in band fractional spurs vs. offset current [8] -120 -100 -80 -60 -40 -20 -120 -100 -80 -60 -40 -20 -800 -600 -400 -200 0 200 400 600 800 4400 mhz 4700 mhz 5000 mhz inband spur at 15 khz offset (dbc/hz) phase noise (dbc/hz) offset current (ma) figure 16. HMC984LP4E & hmc983lp5e pll floor fom vs. rf input power -233 -232 -231 -230 -229 -228 -227 -226 -30 -25 -20 -15 -10 -5 0 5 10 floor fom (dbc/hz) rf input power (dbm) hi k integer mode integer mode hi k mode a hi k mode b mode b mode a figure 17. HMC984LP4E & hmc983lp5e pll flicker fom vs. rf input power -268.5 -268 -267.5 -267 -266.5 -266 -265.5 -265 -264.5 -30 -25 -20 -15 -10 -5 0 5 10 flicker fom (dbc/hz) rf input power (dbm) hi k integer mode integer mode hi k mode a hi k mode b mode b mode a figure 18. HMC984LP4E & hmc983lp5e pll two-way auto frequency sweep [9] 6400 6500 6600 6700 6800 6900 7000 0 5 10 15 20 frequency (mhz) time (ms) -180 -160 -140 -120 -100 -80 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset frequency (hz) calculated pll integer mode calculated pll mode b measured mode b measured integer mode simulated integer mode simulated mode b [6] crystal frequency=100 mhz, pfd frequency=50 mhz, cp current=2.5 ma, cp offset current=280 a, loop bandwidth = 87 khz, pll mode [7] measured at 7 ghz in integer mode and 7.001 ghz in fractional mode b. pd frequency = 50 mhz, and loop flter bw = 87 khz. simulated results were obtained using hittite pll design software. [8] active loop flter bandwidth 150 khz, measured at 10 khz offset, pfd frequency=50 mhz. offset polarity should be positive for inverting confgurations and negative otherwise. [9] 50 mhz pfd for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 7 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector figure 19. HMC984LP4E & hmc983lp5e pll one-way triggered frequency sweep [10] 6400 6500 6600 6700 6800 6900 7000 0 200 400 600 800 1000 frequency (mhz) time (ms) figure 20. HMC984LP4E & hmc983lp5e pll floor fom vs. sine-wave ref input level [11] -230 -225 -220 -215 -210 -15 -10 -5 0 5 floor fom (dbc/hz) reference power (dbm) 100 mhz 12.5 mhz 25 mhz 50 mhz figure 21. HMC984LP4E & hmc983lp5e pll floor fom vs square-wave ref input level [11] -228 -226 -224 -222 -220 -218 -216 -15 -10 -5 0 5 floor fom (dbc/hz) reference power (dbm) 100 mhz 12.5 mhz 25 mhz 50 mhz figure 22. HMC984LP4E & hmc983lp5e pll reference input return loss [12] -16 -14 -12 -10 -8 -6 0 100 200 300 400 500 600 return loss (db) frequency (mhz) [10] using 10 hz external trigger. pfd frequency = 10 mhz. measured with hmc983lp5e/HMC984LP4E fractional-n synthesizer chip set. [11] measured with a 100 ? external resistor termination, resulting in 50 ? effective input impedance of reference. full fom performance up to maximum 3.3 vpp input voltage. [12] measured with 100 ? external termination ac coupled on HMC984LP4E & hmc983lp5e evaluation board. [13] measured with hmc983lp5e/HMC984LP4E chip set as fractional-n synthesizer. crystal input frequency = 100 mhz, cp current = 2.5 ma, cp offset current = 245 ua, loop flter bandwidth = 87 khz, dsm mode b selected. cycle slip prevention (csp) is disabled in HMC984LP4E by setting reg 01h [4] = 0. setting reg 01h [4] = 1 enables csp in the two chip pll. 6700 6750 6800 6850 6900 6950 7000 7050 0 50 100 150 200 250 300 time (us) pll output frequency (mhz) cycle slip disabled csp enabled reg0eh[18:15] = 8h csp enabled reg0eh[18:15] = 1h 6700 6750 6800 6850 6900 6950 7000 7050 0 50 100 150 200 250 300 time (us) pll output frequency (ghz) cycle slip disabled csp enabled reg0eh[18:15] = 8h csp enabled reg0eh[18:15] = 1h figure 23. HMC984LP4E & hmc983lp5e pll cycle slip prevention at 100 mhz pd [13] figure 24. HMC984LP4E & hmc983lp5e pll cycle slip prevention at 50 mhz pd [13] frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
8 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 2. pin descriptions pin number function description interface schematic 1 ref_en gate control output for tcxo clock export 2 dtsto lock detect/gpio bit 0 3 vcop positive input pin for pfd 4 vcon negative input pin for pfd 5 vccpd 5 v analog supply for differential pfd 6,7 vddpd1, vddpd2 3 v phase detector supply 1, 3 v phase detector supply 2 8 vddcp 5 v charge pump supply for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 9 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 2. pin descriptions pin number function description interface schematic 9 cp charge pump output pin 10 vppcp 5 v analog power supply pin charge pump 11 avdd 3 v analog supply 12 bias external decoupling for analog bias circuits 13 rvdd 3 v supply pin for reference circuits 14 xrefp reference/tcxo input pin 15 nc no connect pin 16 dvdd 3 v digital supply pin 17 cen chip enable pin 18 sdo serial data output pin continued... frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
10 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 2. pin descriptions pin number function description interface schematic 19, 20, 21 senb, sdi, sclk serial port enable input pin, active low, serial port data input pin, serial data clock input pin 22 chip3 chip address bit 3 23 upsat reference saturation output 24 dnsat vco saturation output flag also multiplexed with crystal oscillator clock continued... for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 11 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector outline drawing part number package body material lead finish msl rating [2] package marking [1] HMC984LP4E rohs-compliant low stress injection molded plastic 100% matte sn msl1 h984 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c package information table 19. absolute maximum ratings max vdc to paddle on supply pins 6, 7, 11, 13, 16 -0.3 to 3.6 v vccpd, vppcp, vddcp -0.3 to +5.5 v vcop, vcon common mode voltage vccpd - 1.4 v xrefp 50 source + 12 dbm digital input voltage range 0.25 to dvdd + 0.5 v digital load 1 k minimum operating temperature range -40 to +85 c operating temperature range -65 to +125 c maximum junction temperature 125 c storage temperature -65 to +125 c thermal resistance (rth) (junction to ground paddle) 12 c/w electrostatic sensitive device observe handling precautions refow soldering peak temperature time at peak temperature 260 c 40 s esd sensitivity (hbm) class 1 b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. notes: [1] package body material: low stress injection molded plastic silica and silicon impregnated. [2] lead and ground paddle material: copper alloy. [3] lead and ground paddle plating: 100% matte tin. [4] dimensions are in inches [millimeters]. [5] lead spacing tolerance is non-cumulative. [6] pad burr length shall be 0.15mm max. pad burr height shall be 0.25m max. [7] package warp shall not exceed 0.05mm [8] all ground leads and ground paddle must be soldered to pcb rf ground. [9] refer to hittite application note for suggested pcb land pat tern. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
12 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector evaluation pcb item contents part number evaluation kit HMC984LP4E and hmc983lp5e pll chipset evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluation software) ekit01-hmc983lp5e table 20. evaluation order information the circuit board used in the application should use rf circuit design techniques. signal lines should have 50 ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown unless mentioned otherwise. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 13 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector evaluation pcb block diagram frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
14 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector typical performance characteristics theory of operation primary target application of the HMC984LP4E is to be used with the hmc983lp5e as shown in figure 25 . together these two components form a high performance, low noise, ultra low spurious emissions fractional-n frequency synthesizer. the two components are separated in order to maximize isolation between them, and minimize common distortion and modulation by-products that exist in all plls. careful ic design and increased isolation between the two components result in high performance , high spectral efficiency pll, with extremely low spurious emissions. figure 25. typical application of HMC984LP4E with hmc983lp5e to form a frequency synthesizer HMC984LP4E is a high performance low noise phase detector and charge pump. it consists of the following main functional blocks; 1. reference/crystal buffer 2. reference path r divider 3. differential phase/frequency detector 4. 5 v charge pump 5. two lock detect circuits 6. serial port interface pll performance metrics (figure of merit, noise floor, and flicker noise models) the phase noise of an ideal phase locked oscillator is dependent upon a number of factors: a. frequency of the vco, and the phase detector b. vco sensitivity, kvco, and vco and reference oscillator phase noise profles c. charge pump current, loop filter and loop bandwidth d. mode of operation: integer, fractional modulator style the contributions of the pll to the output phase noise can be characterized in terms of a figure of merit (fom) for both the pll noise foor and the pll ficker (1/f) noise regions, as follows: pll phase noise ( ) 2 2 0 0 2 0 1 0 ,, p p p m pd m pd ff ff ff f ff =+ (eq 1) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 15 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector where: p 2 phase noise contribution of the pll (rads 2 /hz) f o frequency of the vco (hz) f pd frequency of the phase detector (hz) f m frequency offset from the carrier (hz) f po figure of merit (fom) for the phase noise foor f p1 figure of merit (fom) for the ficker noise region figure 26. figure of merit noise models for the pll if the free running phase noise of the vco is known, it may also be represented by a fgure of merit for both 1/f 2 , f v2 , and the 1/f 3 , f v3 , regions. vco phase noise ( ) 2 2 0 2 20 3 0 23 , m mm ff ff ff ff =+ (eq 2) the figures of merit are essentially normalized noise parameters for both the pll and vco that can allow quick estimates of the performance levels of the pll at the required vco, offset and phase detector fre quency. normally, the pll ic noise dominates inside the closed loop bandwidth of the synthesizer, and the vco dominates outside the loop bandwidth at offsets far from the carrier. hence a quick estimate of the closed loop performance of the pll can be made by setting the loop bandwidth equal to the frequency where the pll and free running phase noise are equal. the figure of merit is also useful in estimating the noise parameters to be entered into a closed loop design tool such as hittite pll design, which can give a more accurate estimate of the closed loop phase noise and pll loop flter component values. given an optimum loop design, the approximate closed loop performance is simply given by the minimum of the pll and vco noise contributions. ( ) 2 22 min , p = (eq 3) frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
16 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector an example of the use of the fom values to make a quick estimate of pll performance: estimate the phase noise of an 7 ghz closed loop pll with a 100 mhz reference operating in fractional mode b with the vco operating at 7 ghz. assume an hmc505lp4e vco has free running phase noise in the 1/f 2 region at 1 mhz offset of -130 dbc/hz and phase noise in the 1/f 3 region at 1 khz offset of -48 dbc/hz. f v1_db = -130 free running vco pn at 1 mhz offset +20*log10(1e6) pnoise normalized to 1 hz offset -20*log10(7e9) pnoise normalized to 1 hz carrier = -206.9 dbc/hz at 1 hz vco fom f v3 _db = -48 free running vco pn at 1 khz offset +30*log10(1e3) pnoise normalized to 1 hz offset -20*log10(7e9) pnoise normalized to 1 hz carrier = -154.9 dbc/hz at 1 hz vco flicker fom we can see from figure 3 and figure 4 respectively that the pll fom foor and fom ficker parameters in fractional mode a are approximately: fpo_db = -227 dbc/hz at 1 hz fp1_db = -267 dbc/hz at 1 hz each of the figure of merit equations result in straight lines on a log-frequency plot. we can see in the example below the resulting pll foor at 7 ghz = f po_db + 20log10(fvco) - 10log10(fpd) = -227+ 196.9 -80 = -110.1 dbc/hz pll flicker at 1 khz = f p1_db + 20log10(fvco) - 10log10(fm) = -267 + 196.9-30 = -100.1 dbc/hz vco at 1 mhz = f v1_db + 20log10(fvco) - 20log10(fm) = -206.9 +196.9-120 = -130 dbc/hz vco ficker at 1 khz = f v3_db +20log10(fvco)-30log10(fm)= -154.9 +196.9-90 = -48 dbc/hz these four values help to visualize the main contributors to phase noise in the closed loop pll. each falls on a linear line on the log-frequency phase noise plot shown in figure 25 . spurious performance integer operation the vco always operates at an integer multiple of the pd frequency in an integer pll. in general, spurious signals originating from an integer pll can only occur at multiples of the pd frequency. these unwanted outputs are often simply referred to as reference sidebands. spurs unrelated to the reference frequency must originate from outside sources. external spurious sources can modulate the vco indirectly through power supplies, ground, or output ports, or bypass the loop flter due to poor isolation of the flter. it can also simply add to the output of the pll. the HMC984LP4E together with the hmc983lp5e have been designed and tested for ultra-low spurious performance. reference spuri ous levels can be typically below -100 dbc with a well designed board layout. a regulator with low noise and high power supply rejection, such as the hmc860lp3e, is recommended to minimize external spurious sources. reference spurious levels of below -100 dbc require superb board isolation of power supplies, isolation of the vco from the digital switching of the synthesizer and isolation of the vco load from the pll. typical board layout, regulator design, demo boards and application information are available for very low spurious operation. operation with lower levels of isolation in the application circuit board, from those rec ommended by hittite, can result in higher spurious levels. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 17 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector of course, if the application environment contains other interfering frequencies unrelated to the pd fre quency, and if the application isolation from the board layout and regulation are insufficient, then the unwanted interfering frequencies will mix with the desired pll output and cause additional spurs. the level of these spurs is dependant upon isolation and supply regulation or rejection (psrr). fractional operation unlike an integer pll, spurious signals in a fractional pll can occur due to the fact that the vco operates at frequencies unrelated to the pd frequency. hence intermodulation of the vco and the pd harmonics can cause spurious sidebands. spurious emissions are largest when the vco operates very close to an integer multiple of the pd. when the vco operates exactly at a harmonic of the pd then, no in-close mixing products are present. interference is always present at multiples of the pd frequency, f pd , and the vco frequency, f vco . if the fractional mode of operation is used, the difference, , between the vco frequency and the nearest har monic of the reference, will create what are referred to as integer boundary spurs. depending upon the mode of operation of the pll, higher order, lower power spurs may also occur at multiples of integer fractions (sub-harmonics) of the pd frequency. that is, fractional vco frequencies which are near nf pd + f pd d/m, where n, d and m are all integers and d m (mathematicians refer to d/m as a rational num ber). we will refer to f pd d/m as an integer fraction. the denominator, m, is the order of the spurious product. higher values of m produce smaller amplitude spurious at offsets of m and usually when m > 4 spurs are small or unmeasurable. the worst case, in fractional mode, is when d =1, and the vco frequency is offset from nf pd by less than the loop bandwidth. this is the in-band fractional boundary case. figure 27. fractional spurious example characterization of the levels and orders of these products is not unlike a mixer spur chart. exact levels of the products are dependent upon isolation of the various synthesizer parts. hittite can offer guidance about expected levels of spurious with our pll and vco application boards. regulators with high power supply rejection ratios (psrr) are recommended, especially in noisy applications. when operating in fractional mode, charge pump and phase detector linearity is of paramount importance. any non- linearity degrades phase noise and spurious performance. phase detector linearity degrades when the phase error is very small and is operating back and forth between reference lead and vco lead. to mitigate these non-linearities in fractional mode it is critical to operate the phase detector with some fnite phase offset such that either the reference or vco always leads. to provide a fnite phase error, extra current sources can be enabled which provide a constant frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
18 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector dc current path to vdd (vco leads always) or ground (reference leads always). these current sources are called charge pump offset and they are controlled via reg 04h [20:14]. the time offset at the phase detector should be ~2.5 ns + 4 t ps , where t ps is the rf period at the fractional prescaler input in nanoseconds. the specifc level of charge pump offset current is determined by this time offset, the comparison frequency and the charge pump current and can be calculated from: required cp offset = (2.5 ? 10 -9 + 4 t ps ) ? ( f comparison ) ? i cp where: t ps : is the rf period at the fractional prescaler input (sec) i cp : is the full scale current setting of the switching charge pump (a) fcomparison: is the comparison frequency (hz) (eq 4) note that this calculation can be performed for the center frequency of the vco, and does not need refnement for small differences (<25%) in center frequencies. also, operation with unreasonably large charge pump offset may cause lock detect to incorrectly indicate an unlocked condition. to correct, reduce the offset to recommended levels. reference/crystal input buffer the ultra-low noise phase-detector requires the best possible reference signal. the low phase noise reference input buffer is optimized for this purpose. the input pin xrefp is dc coupled internally and there is 800 mv dc bias on the pin. the reference source should be ac coupled to the pin. the maximum input power can be up to 12 dbm from a 50 ? source. in order to achieve best phase noise performance, the reference source should have a phase noise foor of -160 dbc/hz or better. reference path r divider HMC984LP4E has 14-bit frequency divider that divides the incoming reference frequency by any number from 1 to 2 14 -1 = 16,383 inclusive. the maximum frequency at which the phase detector can work depends on the mode of operation when working as a pll with its companion chip hmc983lp5e. in integer mode, the reference buffer and divider can work up to 175 mhz, and in fractional mode the maximum frequency is typically 125 mhz. hence higher crystal frequencies need to be divided down by the r divider in order to generate phase comparison frequency that meets the limits of the phase detector. the minimum reference frequency can be as low as 100 khz provided that sharp rise and fall times (less than 500 ps) are guaranteed. internally, the reference signal is used by other circuitry, besides the phase detector. for best performance, it is recommended to use a higher reference frequency that is divided by the internal r-divider to generate the required phase comparison frequency. table 3. reference sensitivity table square input sinusoidal input frequency (mhz) slew > 0.5v/ns recommended swing (vpp) recommended power range (dbm) recommended min max recommended min max < 10 yes 0.6 2.5 x x x 10 yes 0.6 2.5 x x x 25 yes 0.6 2.5 ok 8 15 50 yes 0.6 2.5 yes 6 15 100 yes 0.6 2.5 yes 5 15 150 ok 0.9 2.5 yes 4 12 200 ok 1.2 2.5 yes 3 8 200 to 350 x x x yes 1 5 10 note: for greater than 200 mhz operation, use buffer in high frequency mode. reg 08h [11] = 1 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 19 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector differential phase-frequency detector as shown in figure 25 , the HMC984LP4E features an ultra-low noise digital differential phase detector (pd) with two differential inputs. one input comes from the reference path divider and the other from vco path divider. the reference input is internal to HMC984LP4E whereas the divided vco input is external. the output from the pd is fed to the charge pump in HMC984LP4E which converts the pd digital output to a current with programmable gain. the output of the cp is directly proportional to the phase difference between the divided reference and the vco path signals. figure 28. HMC984LP4E input interface the input of pd is a differential current-input. the input interface confgurations are shown in figure 25 and figure 25 . the HMC984LP4E is designed to work with its companion divider part, the hmc983lp5e, that provides an open collector output. the inputs are internally pulled up to vccpd with on-chip 50 ? resistors. thus, any open collector buffer can drive the pd inputs. a minimum of 750 mvpp single-ended level is needed to drive the pd inputs. figure 29. HMC984LP4E input interface with companion part hmc983lp5e frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
20 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector the pd has several features and controls including: ? phase swap ? up/dn enable ? forced outputs phase swap the input phase signals to the pd can be swapped internally by writing reg 03h [4] = 1. when swapped, the pd gain will be reversed. this feature enables the HMC984LP4E to be interfaced with reverse polarity vcos (vcos that have negative gain curve), as well as systems that use an active loop flter where the operational amplifer introduces a reverse phase polarity. forced outputs the up or dn outputs from the pd can be forced with spi control to keep constantly active in order to achieve faster lock (to force up write reg 04h [26] = 1, to force dn write reg 04h [27] = 1). this capability is used in csp (cycle slip prevention) feature when large phase errors are detected. in such a case the cp is continuously turned on the appropriate direction (up or dn) by the internal state machine to force faster phase convergence, and thus achieve faster lock. forced otput capability is also useful for testing purposes. it can be used to bring the vco tune control voltage to supply or ground, and observe the limits of the vco. cycle slip prevention when the frequency of the synthesizer is changed and the current vco frequency is far from the desired locked frequency, the phase difference at the pd varies rapidly over a range larger than 2 radians. since the gain of the pd varies linearly with phase only up to 2, the gain of conventional pds will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly more than 2 radians. this phenomena is known as cycle slipping. cycle slipping causes the pull-in rate during the phase acquisition to vary cyclically as shown in the red curve in figure 25 . cycle slipping can dramatically increase the time to lock to a value far greater than that predicted by normal small signal laplace analysis. figure 30. cycle slipping the HMC984LP4E pd features cycle slip prevention (csp) only when working in conjunction with the companion part, the hmc983lp5e. when enabled, the csp feature holds the pd gain in the appropriate polarity until such time as the frequency difference is near zero. this enables signifcantly faster lock times as shown in figure 25 . the use of csp feature is enabled with csp enable ( reg 01h [4] = 1) and csp output enable ( reg 01h [13] = 1). the csp feature may be optimized for a given set of pll dynamics by adjusting the pd sensitivity to cycle slipping. this is achieved by adjusting csp reset delay ( reg 03h [2:0]). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 21 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector the HMC984LP4E has two outputs, upsat and dnsat, which indicate to the hmc983lp5e whether the reference or the vco is leading in phase. these outputs are cmos signal with dvdd levels. when hmc983lp5e detects saturation (large phase error), it confgures itself, and the HMC984LP4E in order to eliminate or reduce cycle clipping. there are additional controls for adjusting the csp operation in hmc983lp5e. the controls for csp feature are; 1. register 0eh bits [18:15] control the step size, where step is a vco cycle. 2. register 0eh bit [29] increases the step size by a factor of 16 for operations with low reference frequencies. the actual operation of csp will depend on the reference and vco frequencies and will need to be tailored for each application. charge pump the charge pump in HMC984LP4E converts the phase detector digital outputs to appropriate current level that is proportional to phase difference between the reference and the vco. a simplifed block diagram of the charge pump is shown in figure 25 . the HMC984LP4E cp has programmable current gain and offset current. charge pump gain current cp gain current defnes the gain of phase detector vs. phase difference in amps/radians. the up and down gain currents are confgured in reg 04h [6:0] and reg 04h [13:7] respectively. both up and down currents can be programmed to provide up to 2.5 ma independently in 127 steps (20 a/step). resulting phase detector gain is the total current from one side divided by 2. for example, if both up and down currents are set 2 ma each, the gain would be 2 ma/2 = 318.31 a/radian. typically both of the gain currents are set to the same value. charge pump phase offset either of the up or down charge pumps may have a dc offset current added to it. offset current allows the phase detector to operate with a phase offset between the reference and the divided vco inputs. the phase offset is proportional to the ratio of the offset current to the main current times the period of the phase comparison clock. offset current 1 pd phase offset= cp current pd f (eq 5) it is recommended to operate the HMC984LP4E with a phase offset when using fractional mode to reduce non-linear effects from any up and dn pump mismatches that may exist. phase noise in fractional mode is strongly affected by charge pump offset. the magnitude of offset current is set in reg 04h [20:14], and can be added to the up ( reg 04h [21] = 1) or down ( reg 04h [22] = 1) pumps. as an example, if the main pump gain was set at 2 ma, an offset of 160 a ( reg 04h [20:14] = 20h) and 50 mhz pfd rate would represent a phase offset of about (160/2000)*360 = 28.8 degrees or (163.5 a/2000 a)*20 ns = 1.6 ns phase offset at the pd input. charge pump high gain (hik) mode operating the cp of the HMC984LP4E in high gain mode ( reg 04h [23] = 1) can improve pll phase noise performance by up to 3 db. in high gain mode the charge pump can deliver current of 3.5 ma + normal programmed cp current. high gain mode can be used without the normal charge pump current in which case the loop flter should be designed with a current of 3.5 ma. in the case where high gain mode is used with the normal cp current, the loop flter should be designed with a charge pump current of 3.5 ma + programmed cp current. the high gain mode current is depended on the loop flter voltage, therefore the high gain mode should be used with active loop flters to keep a constant voltage a the charge pump output. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
22 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector figure 31. charge pump block diagram pfd jitter and lock detect background in normal phase locked operation the divided vco signal arrives at the phase detector in phase with the divided crystal signal, known as the reference signal. despite the fact that the device is in lock, the phase of the vco signal and the reference signal vary in time due to the phase noise of the crystal and vco oscillators, the loop bandwidth used and the presence of fractional modulation or not. the total integrated noise on the vco path normally dominates the variations in the two arrival times at the phase detector if fractional modulation is turned off. to determine weather the vco is in lock or not, it is necessary to distinguish between normal phase jitter when in lock and phase jitter when not in lock. first, the meaning of jitter of the synthesizer that is observed at the phase detector in integer or fractional modes needs to be understood. the standard deviation of the arrival time of the vco signal, or the jitter, in integer mode may be estimated with a simple approximation if it is assumed that the locked vco has a constant phase noise, 2 (?0), at offsets less than the loop 3 db bandwidth and a 20 db per decade roll off at greater offsets. the simple locked vco phase noise approximation is shown on the left of figure 25 . figure 32. synthesizer phase noise & jitter with this simplifcation the single sideband integrated vco phase noise, 2 , in rads 2 at the phase detector is given by 22 2 () / 2 ssb o b fn ?? = ?? ?? (eq 6) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 23 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector where 2 ssb (?0) is the single sideband phase noise in rads 2 /hz inside the loop bandwidth, b is the 3 db corner frequency of the closed loop pll and n is the division ratio of the prescaler. the rms phase jitter of the vco in rads, , results from the power sum of the two sidebands: = 2 2 ssb (eq 7) since the simple integral of (eq 6) is just a product of constants, the integral in the log domain can easily be done . for example if the vco phase noise inside the loop is -100 dbc/hz at 10 khz offset and the loop bandwidth is 100 khz, and the division ratio n=100, then the integrated single sideband phase noise at the phase detector in db is given by 2 db = 10log ( 2 (? 0 )b ? n 2 ) = -100 + 50 + 5 - 40 = -85 dbrads, or equivalently = 10 -85/20 = 56 urads rms or 3.2 milli-degrees rms. while the phase noise reduces by a factor of 20log10(n) after division to the reference, the jitter is a constant. the rms jitter from the phase noise is then given by t jnp = tref / 2 in this example if the reference was 50 mhz, t ref = 20 nsec, and hence t jpn = 178 femto-sec. a normal 3 sigma peak-to-peak variation in the arrival time therefore would be 3 2t jpn = 0.756 ps if the synthesizer was in fractional mode, the fractional modulation of the vco divider will dominate the jitter. the exact standard deviation of the divided vco signal will vary based upon the modulator chosen, however a typical modulator will vary by about 3 vco periods, 4 vco periods, worst case. if, for example, a nominal vco at 5 ghz is divided by 100 to equal the reference at 50 mhz, then the worst case division ratios will vary by 1004. hence the peak variation in the arrival times caused by ds modulation of the fractional synthesizer at the reference will be ? =? * max min ( )/2 j pk vco t tn n (eq 8) in this example, t j ds pk = 200 ps (104-96)/2 = 800 psec. if it is assumed that the distribution of the delta sigma modulation is approximately gaussian, t j ds pk could be approximated as a 3 sigma jitter, and hence the rms jitter of the ds modulator could be estimated as ~ 1/3 of t j ds pk or ~ 267 psec in this example. hence the total rms jitter t j , expected from the delta sigma modulation plus the phase noise of the vco would be given by the rms sum , where ? = + 22 () 3 j pk j jpn t tt (eq 9) it is apparent that the jitter from (eq. 9) at the phase detector is dominated by the fractional modulation. in general, ~t 0.8 nsec of normal variation in the phase detector arrival times has to be expected when in fractional mode. in addition, lower vco frequencies with high reference frequencies will have much larger variations. for example, a 1 ghz vco operating at near the minimum nominal divider ratio of 36, would, according to (eq 8), exhibit about 4 nsec of peak variation at the phase detector, under normal operation. the lock detect circuit must not confuse this modulation as being out of lock. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
24 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector HMC984LP4E lock detect circuits HMC984LP4E includes two lock detect circuits. ? legacy lock detect function ? phase measurement based lock detect function reg 01h [6:8] enables the lock detect functions of the HMC984LP4E. the ld output is available either from the gpo pin d0 or through spi register reg 12h . legacy lock detect function the lock detect circuit in the HMC984LP4E places a one shot window around the reference. the one shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer. clearing lkdos one shot select ( reg 07h [22]=0) will result in a nominal 10 nsec analog window of fxed length, as shown in figure 9 . setting this bit to 1 will result in a variable length digital widow. the digital one shot window is controlled by lkdos ring oscillator speed ( reg 07h [20:19]). the resulting lock detect window period is then generated by the number of ring oscillator periods defned in lkdos one shot pulse width ( reg 07h [18:16]). the lock detect ring oscillator may be observed on the gpo port by setting reg 07h [21] =1 and confguring the reg 08h [7:0] = c1h in (gpo). lock detect does not function when this test mode is enabled. lkdos ok count ( reg 07h [15:0]) defnes the number of consecutive counts of the vco that must land inside the lock detect window to declare lock. if for example lkdos ok count = 1000 , then the vco arrival would have to occur inside the selected lock window 1000 times in a row to be declared locked. when locked the lock detect fag ( reg 12h [2]=1 ) is set, reg 12h is a read only register. a single occurrence outside of the window will result in clearing the lock detect fag. figure 33. normal lock detect window - integer mode, zero offset lock detect with phase offset when operating in fractional mode the linearity of the phase detector and charge pump is more critical than in integer mode. the phase detector linearity deteriorates when operating with zero phase offset. hence in fractional mode it is necessary to offset the phase of the reference and the vco at the phase detector. in such a case, for example with an offset delay, the mean phase of the vco will always occur after the reference, as shown in figure 10 . the lock detect circuit window can be made more selective with a fxed offset delay by setting reg 05h [0]=1 and reg 05h [1]=1. the offset can be assigned in advance of the reference by setting reg 05h [1]=0 and reg 05h [0]=1. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 25 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector figure 34. lock detect window - fractional mode with offset lock detect with phase measurement lock detect with phase measurement is based on phase error measurement at the pfd output. the phase error measurement is done in terms of the reference period at the pfd input. the period of the reference is frst measured with a delay line and this count is available in read-only register reg 10h . the phase error at the output of the pfd is then measured with the same delay line and this count is available in the read-only register re g 11h . when the pll is not locked, the measured phase error count will vary every time the re g 11h is read and will become a stable value once pll is locked. the phase error count will then be proportional to the static phase error at the pfd output. for example, assuming that pll is locked, if the reference duration count is 150 in reg 10h and re g 11h reads 35 then the approximate static phase error at the pfd output is 20*(35/150) = 4.7 ns assuming a 20 ns reference period or fpfd of 50 mhz. reg 06h [13:0] defnes the low and high thresholds for current phase error count. reg 06h [23:14] defnes the number of reference cycles that the phase error has to be within the thresholds before the lock is declared. for example, if the low threshold is set to reg 06h [6:0] = 20d and high threshold is set to reg 06h [13:7] = 50d and the ld ok count is set to reg 06h [23:14] = 512d, then the phase error count has to be between 20 and 50 for 512 consecutive reference cycles before that lock is declared. the thresholds make it easier to defne lock condition in case of fractional operation where the static phase error is expected to be larger due to charge pump offset currents. chip address pins HMC984LP4E has three programmable chip address bits, which enable the HMC984LP4E to be used in an spi bus confguration. two lsb chip address bits are internal and bond wire programmable at the time of packaging. the msb bit is available externally as pin chip3. the chip address pins are read at power-up and every time the chip is reset. by default, all chip3 is internally pulled to dvdd thus there is no need to connect the pin to dvdd if the address bit is to be set as logic high. to assign a 0 to address bit, pin should be connected to ground. the internal chip1 and chip2 bits are internally tied to ground. the chip address for the companion chip hmc983lp5e is stored in reg 09h [2:0] of HMC984LP4E. in cases when an spi command is common to both devices, it is not necessary to send separate commands to each part. both parts are always listening to the spi bus and when a common command is issued, they will take the command and update the corresponding registers. writing its own chip address to the companion chip address register reg 09h [2:0] will disable this feature. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
26 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector general purpose input output pin d0 HMC984LP4E has one gpio pin d0. this pin normally functions as the output for the lock detect. it can be programmed to test and probe several internal signals. following signals are available ( reg 08h [3:0]). 1. gpo_test_out. 2. lock detect or lock indicator output 3. pfd up output going to lock detect 4. pfd dn output going to lock detect 5. r-divider output to digital 6. r-divider output 7. saturation reset signal 8. pfd saturation dn (vco) output 9. pfd saturation up (ref) output 10. ring oscillator test output 11. one-shot pulse output 12. one-shot trigger output 13. pull up hard 14. pull down hard 15. vco divider output to digital 16. crystal oscillator buffer output see the serial port section for programming confguration, reg 08h . serial port interface the HMC984LP4E features a four wire serial port for simple communication with the host controller. typical serial port operation can be run with sck at speeds up to 30 mhz. the details of spi access for the HMC984LP4E are provided in the following sections. note that the read operation below is always preceded by a write operation to register 0 to defne the register to be queried. also note that every read cycle is also a write cycle in that data sent to the spi while reading the data will also be stored by the HMC984LP4E when sen goes high. if this is not desired then it is suggested to write to reg 00h during the read operation so that the status of the device will be unaffected. power on reset and soft reset the HMC984LP4E has a built in power on reset (por) and a serial port accessible soft reset (sr). por is accomplished when power is cycled for the HMC984LP4E while sr is accomplished via the spi by writing reg 00h = 80h, followed by writing reg 00h = 00h. all chip registers will be reset to default states approximately 250 us after power up. serial port write operation the host changes the data on the falling edge of sck and the HMC984LP4E reads the data on the rising edge. a typical write cycle is shown in figure 1 . it is 40 clock cycles long. 1. the host both asserts sen (active low serial port enable) and places the msb of the data on sdi followed by a rising edge on sck. 2. HMC984LP4E reads data on sdi (the msb) on the 1st rising edge of sck after sen. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 27 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector 3. HMC984LP4E registers the data bits, d29:d0, in the next 29 rising edges of sck (total of 30 data bits). 4. host places the 7 register address bits, a6:a0, on the next 7 falling edges of sck (msb to lsb) while the HMC984LP4E reads the address bits on the corresponding rising edge of sck. 5. host places the 3 chip address bits, ca2:ca0=[110], on the next 3 falling edges of sck (msb to lsb). note the HMC984LP4E chip address is fxed as 4d or 100b. 6. sen goes from low to high after the 40th rising edge of sck. this completes the write cycle. 7. HMC984LP4E also exports data back on the sdo line. for details see the section on read operation. serial port read operation the spi can read from the internal registers in the chip. the data is available on sdo pin. this pin itself is tri-stated when the device is not being addressed. however, when the device is active and has been addressed by the spi master, the HMC984LP4E controls the sdo pin and exports data on this pin during the next spi cycle. HMC984LP4E changes the data to the host on the rising edge of sck and the host reads the data from HMC984LP4E on the falling edge. a typical read cycle is shown in figure 1 . read cycle is 40 clock cycles long. to specifcally read a register, the address of that register must be written to dedicated reg 00h . this requires two full cycles, one to write the required address, and a 2nd to retrieve the data. a read cycle can then be initiated as follows; 1. the host asserts sen (active low serial port enable) followed by a rising edge sck. 2. HMC984LP4E reads sdi (the msb) on the 1 st rising edge of sck after sen. 3. HMC984LP4E registers the data bits in the next 29 rising edges of sck (total of 30 data bits). the lsbs of the data bits represent the address of the register that is intended to be read. 4. host places the 7 register address bits on the next 7 falling edges of sck (msb to lsb) while the HMC984LP4E reads the address bits on the corresponding rising edge of sck. for a read operation this is 0000000. 5. host places the 3 chip address bits [100] on the next 3 falling edges of sck (msb to lsb). note the HMC984LP4E chip address is fxed as 4d or 100b. 6. sen goes from low to high after the 40th rising edge of sck. this completes the frst portion of the read cycle. 7. the host asserts sen (active low serial port enable) followed by a rising edge sck. 8. HMC984LP4E places the 30 data bits, 7 address bits, and 3 chip id bits, on the sdo, on each rising edge of the sck, commencing with the frst rising edge beginning with msb. 9. the host de-asserts sen (i.e. sets sen high) after reading the 40 bits from the sdo output. the 40 bits consists of 30 data bits, 7 address bits, and the 3 chip id bits. this completes the read cycle. note that the data sent to the spi by the host during this portion of the read operation is stored in the spi when sen is de-asserted. this can potentially change the state of the HMC984LP4E. if this is undesired it is recommended that during the second phase of the read operation that reg 00h is addressed with either the same address or the address of another register to be read during the next cycle. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
28 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector figure 35. spi timing diagram dvdd = 5 v 10%, gnd = 0 v table 4. main spi timing characteristics parameter conditions min typ max units t 1 sdi to sck setup time 8 nsec t 2 sdi to sck hold time 8 nsec t 3 sck high duration [1] 10 nsec t 4 sck low duration 10 nsec t 5 sen low duration 20 nsec t 6 sen high duration 20 nsec t 7 sck to sen [2] 8 nsec t 8 sck to sdo out [3] 8 nsec [1] the spi is relatively insensitive to the duty cycle of sck. [2] sen must rise after the 32 nd falling edge of sck but before the next rising sck edge. if sck is shared amongst several devices this timing must be respected. [3] typical load to sdo is 10 pf, maximum 20 pf for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 29 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector register map table 5. reg 00h chip id, soft reset, read register bit type name w deflt description [6:0] r/w read address register 7 0 address of the register to be read in the next cycle. [7] r/w soft reset 1 0 soft reset. writing 1 generates soft reset. resets all the digital and registers to default states. writing 0 resumes normal chip operation. [31:8] r/w chid id 24 97331h part number, description. read reg00h returns chip id. table 6. reg 01h enable register bit type name w deflt description [0] r/w use spi chip enable 1 0 0 = use cen pin for chip enable. 1 = ignore cen pin and use spi chip_en bit. [1] r/w spi ce 1 1 chip enable from spi = 1 allows chip control through spi software. [2] r/w r divider enable 1 1 enable reference divider enabled [3] r/w pfd enable 1 1 1 = pfd enabled 0 = pfd disabled [4] r/w csp enable 1 1 enable cycle-slip prevention. [5] r/w charge pump enable 1 1 enable charge pump. [6] r/w lock detect enable 1 1 main lock detect enable [7] r/w lock detect watch dog enable 1 1 lock detected watch dog. declares unlock if no up/dn pulses are received from pfd. [8] r/w one shot lock detect enable 1 1 legacy lock detect enable. [9] r/w gpo enable 1 1 1 = gpio output enable, d0 pin is output. 0 = d0 pin confgured as input. [10] r/w reference buffer enable 1 1 enable reference buffer. [11] r/w test clocks enable 1 1 enable test clocks to digital (xtal, rdiv, vdiv). [12] r/w bias enable 1 1 enables the bias currents to the analog blocks. [13] r/w csp output enable 1 1 enables the output pad for [14] r/w cp op-amp enable 1 1 enables the charge pump operational amplifer. [17:15] r/w unused bits 3 111b [18] r/w vco input test clock enable 1 0 enable for vco/divider input test clock. [19] r/w unused bit 4 0 table 7. reg 02h refdiv reference divider register bit type name w deflt description [13:0] r/w r-divider ratio 14 1 reference divider division ratio r. minimum = 1, maximum = 16383d. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
30 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 8. reg 03h pfd settings register bit type name w deflt description [2:0] r/w csp reset delay 3 100b the number of reference clock cycles after which the saturation detection is reset. [3] r/w csp auto disable 1 1 when 1, pd saturation is disabled when lock detect becomes 1. [4] r/w pd phase swap 1 0 swap pd inputs when 1. [5] r/w pd short mode enable 1 0 1 = apply reference to both pfd inputs when pfd_swap_phase reg08h[4]= 0 or applies divider output to both pfd inputs when pfd_swap_phase reg08h[4] = 1. [6] r/w pd up enable 1 1 1 = enable up output from pd. 0 = disable up output from pd. [7] r/w pd down enable 1 1 1 = enable dn output from pd. 0 = disable dn output from pd. [8] r/w pd force up 1 0 1 = forces up output from the pd to stay continuously on. 0 = normal up operation. [9] r/w pd force down 1 0 1 = forces dn output from the pd to stay continuously on. 0 = normal dn operation. [10] r/w pd outputs to ld enable 1 1 1 enables pd outputs to lock detect in the digital. [11] r/w reset pd when xtal gate 1 1 1 resets the pd when crystal is exported to the companion prescaler/sigma delta chip hmc983lp5e for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 31 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 9. reg 04h charge pump settings register bit type name w deflt description [6:0] r/w up current 7 0x7h charge pump down main current, 20 a step, 127 steps 0000000 = tristate if pfd also disabled. 0000001 = 20 a 0000010 = 40 a ... 1111111 = 2. 5 4 m a [13:7] r/w down current 7 0x7h charge pump up main current, 20 a step, 127 steps 000 = tristate if pfd also disabled. 0000001 = 20 a 0000010 = 40 a ... 1111111 = 2. 5 4 m a [20:14] r/w offset current 7 0x7h charge pump offset current magnitude, 5 a step, 127 steps 0000000 = tristate if pfd also disabled. 0000001 = 5 a 0000010 = 10 a ... 1111111 = 6 3 5 a [21] r/w up offset current enable 1 0 enable for charge pump offset current in up direction. reference signal is lagging when phase swap is 0. [22] r/w down offset current enable 1 0 enable for charge pump offset current in down direction, vco/ divider is lagging when phase swap is 0. [23] r/w high gain mode enable 1 0 enables high gain mode for the charge pump with uncontrolled 1 ma - 3.5 ma of additional charge pump current. [25:24] r/w op-amp bias 2 11b charge pump op-amp bias select. 00 = 540 a 01 = 689 a 10 = 943 a 11 = 1503 a [26] r/w cp force up enable 1 0 force up current from the charge pump output. [27] r/w cp force down enable 1 0 force down current from the charge pump output. [28] r/w cp force mid rail enable 1 0 force the charge pump output to mid rail voltage. cp_force_up (reg09h[26]) or cp_force_dn (reg09h[27]) have precedence over this bit. [29] r/w ring oscillator output to cp enable 1 0 exports ring oscillator to pulluphard/pulldnhard for test purpose. table 10. reg 05h lkd_flxcpgain (lock detect) register bit type name w deflt description [0] r/w ld asymmetric window enable 1 0 enable asymmetric window for lock detect. [1] r/w ld asymmetric direction select 1 0 0 = reference is expected frst. 1 = vco/divider is expected frst. [2] r/w reference edge for ld select 1 0 0 = use falling edge. 1 = use rising edge. [4:3] r/w flex cp mode select 2 00b forces up or dn if phase error exceeds the register value. 00 = disabled 01 = force when phase error > 1 ns. 10 = force when phase error > 3 ns. 11 = force when phase error > 5 ns. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
32 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 11. reg 06h lkdos (lock detect) register bit type name w deflt description [6:0] r/w ld high threshold duration 7 7fh high threshold for measuring pfd pulse width. [13:7] r/w ld low threshold duration 7 0x00 low threshold for measuring pfd pulse width. [23:14] r/w ld ok count threshold 10 200h number of consecutive counts within the time window to declare lock. theory of operation on page 14 table 12. reg 07h lkdos (legacy lock detect) register bit type name w deflt description [15:0] r/w lkdos ok count 16 0x1000 4096d number of consecutive counts within the time window to declare lock. legacy lock detect function on page 24 [18:16] r/w lkd one shot pulse width 3 100b [20:19] r/w lkdos ring oscillator speed 2 00b set ring oscillator speed or frequency. 00 = fastest. 11 = slowest. [21] r/w lkdos ring oscillator mode 1 0 1 = force ring oscillator for test. 0 = normal operation. [22] r/w lkdos one shot select 1 1 1 = select digital one-shot. 0 = select analog one-shot. table 13. reg 08h gpio register bit type name w deflt description [3:0] r/w gpo output signal select 4 0000b select signal to be probed on the gpio output pin. 0000 = gpo_test. 0001 = locked. 0010 = pfd up output to lkd. 0011 = pfd dn output to lkd. 0100 = r-divider output to digital. 0101 = r-divider output. 0110 = pfd saturation reset. 0111 = pfd saturation dn (vco) output. 1000 = pfd saturation up (ref) output. 1001 = ring oscillator test output. 1010 = one-shot pulse output. 1011 = one-shot trigger output. 1100 = pull up hard. 1101 = pull down hard. 1110 = vco divider output to digital. 1111 = crystal oscillator buffer output. [5:4] r/w gpo static test value 2 00b static test values for gpio. [7:6] r/w gpo output enable 2 11b only lsb is used. 1 = enable gpio output. 0 = confgure gpio as input. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt
6 - 33 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector table 14. reg 09h refdivset (reference divider settings) register bit type name w deflt description [2:0] r/w hmc983lp5e chip address 3 001 chip address of the prescaler/divider hmc983lp5e. when a new refdiv value is selected through the spi, either of the two chips will take the same command. this makes it unnecessary to issue two separate write cycles to change the refdiv value. to disable this feature, write the chip address of the HMC984LP4E itself so that it will not listen to the command issued to the other chip. see chip address pins on page 25 for more information. [3] r/w force r-divider to bypass 1 0 1 = force refdiv bypass when rdiv is not equal to 1. table 15. reg 0ah spare register bit type name w deflt description [9:0] r/w not used 10 3ffh [10] r/w xtaldissat 1 0 disables saturation protection on reference (xtal) buffer. [11] r/w xtalhighfreq 1 0 extends bandwidth of the reference buffer. table 16. reg 10h meas_ref read only register bit type name w deflt description [19:0] r measured reference duration 20 0 measured duration of the reference period for lock detect calibration. [20] r reference measure overfow flag 1 0 ref measurement overfow fag. table 17. reg 11h meas_pfd read only register bit type name w deflt description [19:0] r measured phase error 20 0 measured duration of the pfd. sign is available in reg 12h , bit 0. [20] r phase error overfow flag 1 0 pfd pulse measurement overfow fag. table 18. reg 12h status read only register bit type name w deflt description [0] r phase error sign 1 0 sign of pfd duration [1] r ld output from phase error measurement 1 0 lock detect result from pulse duration based lock detect circuit. [2] r ld output from legacy lock detect 1 0 lock detect result from legacy one-shot lock detect circuit. frequency dividers & detectors - smt for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com
34 HMC984LP4E v 0 2.0112 digital phase-frequ e ncy detector notes: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com frequency dividers & detectors - smt

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