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8190738 sa14-4655-04 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 12 IBM041813PPLB 64k x 18 burst pipeline sram features ? 64k x 18 organization ? 0.5 m cmos technology ? synchronous burst mode of operation compati- ble with i486 tm and pentium tm processors ? supports pentium tm processor address pipelining ? common i/o and registered outputs ? single +3.3v 5% power supply and ground ? lvttl i/o compatible ? fast oe time: 5ns ? registered addresses, data ins, control sig- nals, and outputs ? asynchronous output enable ? self-timed write operation and byte write capability ? low power dissipation - 1.1 w active at 83 mhz - 90 mw standby ? 52 lead plcc package ? 5v tolerant i/o description ibm microelectronics 1m sram is a synchronous burstable pipelined, high performance cmos static ram that is versatile, wide i/o, and achieves 5 nsec access and 12nsec cycle time. a single clock is used to initiate the read/write operation and all inter- nal operations are self-timed. at the rising edge of the clock, all addresses, data ins and control sig- nals are registered internally. burst mode operation, compatible with the i486 tm and pentium tm proces- sors sequence, is accomplished by integrating input registers, internal 2-bit burst counter and high speed sram in a single chip. burst reads are initiated with either adsp or adsc being low with a valid address during the rising edge of clock. data from this address plus the three subsequent addresses will be output. the chip is operated with a single +3.3 v power supply and is compatible with lvttl i/o interfaces. pin description a0-a15 address input dq0-dq17 data input/output (0-8,9-17) clk clock we a write enable, byte a (0 to 8) we b write enable, byte b (9 to 17) oe output enable adsp address status processor adsc address status controller adv burst advance control cs adsp gated chip select v dd power supply (+3.3v) v ss ground x18 plcc pin array layout 46 45 44 43 42 41 38 37 36 35 34 dq8 dq7 dq6 vdd vss dq5 dq2 vss vdd dq1 dq0 39 40 dq4 dq3 8 9 10 11 12 13 16 17 18 19 20 dq9 dq10 vdd vss dq11 dq12 vss vdd dq15 dq16 dq17 15 14 dq13 dq14 7 6 5 4 3 2 51 50 49 48 47 a6 a7 cs web wea adsc clk oe a8 a9 a10 52 1 adsp adv 21 22 23 24 25 26 29 30 31 32 33 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12 a11 28 27 vss vdd ibm041813ppl64k x 18burst pipeline (pentium), plcc package.
IBM041813PPLB 64k x 18 burst pipeline sram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 12 8190738 sa14-4655-04 revised 9/97 block diagram ordering information part number organization speed leads notes IBM041813PPLB-12 64k x 18 5 ns access / 12 ns cycle 52 pin plcc 64k x 18 array a0 - a15 row address register column address register burst binary counter byte write register clear byte write register select registers dq0 - dq8 dq9 - dq17 adsp a2 - a9 a10 - a15 sa0 sa1 a0 a1 adsc clk adv cs wea web oe select register pipeline register register
IBM041813PPLB 64k x 18 burst pipeline sram 8190738 sa14-4655-04 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 12 burst sram clock truth table clk cs adsp adsc ad v we oe dq operation l ? h h x l x x x high-z deselected cycle l ? h llxxxlq read from external address, begin burst l ? h llxxxh high-z read from external address, begin burst l ? h lhlxhlq read from external address, begin burst l ? h lhlxlxd write to external address, begin burst l ? h xhhlhlq read from next add., continue burst l ? h xhhl lxd write to next add., continue burst l ? h xhhhhlq read from current add., suspend burst l ? h xhhhlxd write to current add., suspend burst l ? h hxhlhlq read from next add., continue burst l ? h hxhl lxd write to next add., continue burst l ? h hxhhhlq read from current add., suspend burst 1. for a write operation preceded by a read cycle, oe must be high early enough to allow input data setup, and must be kept high through input data hold time. 2. we refers to we a, we b. 3. adsp is gated by cs, and cs is used to block adsp when cs = v ih , as required in applications using processor address pipelin- ing. 4. all addresses, data in and control signals are registered on the rising edge of clk. 5. write cycles will put the bus into high-z on the ?rst rising clock edge according to the t chz timing. deselect cycles will put the bus into high-z on the second rising edge of clock according to the t chz timing. if a deselect cycle occurs and we is enabled within the same cycle, the part behaves as though it was in a deselect cycle. burst sequence truth table external address a15-a2 (a1,a0) notes (0,0) (0,1) (1,0) (1,1) 1st access a15-a2 (0,0) (0,1) (1,0) (1,1) 2nd access a15-a2 (0,1) (0,0) (1,1) (1,0) 3rd access a15-a2 (1,0) (1,1) (0,0) (0,1) 4th access a15-a2 (1,1) (1,0) (0,1) (0,0)
IBM041813PPLB 64k x 18 burst pipeline sram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 12 8190738 sa14-4655-04 revised 9/97 write enable truth table we a we b byte written notes h h read all bytes l l write all bytes lh write byte a (d in 0 - 8) hl write byte b (d in 9 - 17) absolute maximum ratings parameter symbol rating units notes power supply voltage v dd -0.5 to 4.6 v 1 input voltage v in -0.5 to 6.0 v 1 output voltage v out -0.5 to v dd +0.5 v1 operating temperature t opr 0 to +70 c 1 storage temperature t stg -55 to +125 c 1 power dissipation p d 1.5 w 1 short circuit output current i out 50 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. recommended dc operating conditions (t a =0 to 70 c) parameter symbol min. typ. max. units notes supply voltage v dd 3.135 3.3 3.465 v 1, 4 input high voltage v ih 2.2 5.5 v 1, 2, 4 input low voltage v il -0.3 0.8 v 1, 3, 4 output current i out 5 8ma4 1. all voltages referenced to v ss . all v dd and v ss pins must be connected. 2. v ih (max)dc = 5.5 v, v ih (max)ac = 6.0 v (pulse width 4.0ns). 3. v il (min)dc = - 0.3 v, v il (min)ac= -1.5 v (pulse width 4.0ns). 4. input voltage levels are tested to the following dc conditions: 1 microsecond cycle and 200 nanosecond set-up and hold times. capacitance (t a =0 to +70 c, v dd =3.3v 5%, f=1mhz) parameter symbol test condition max units notes input capacitance c in v in = 0v 5pf data i/o capacitance (dq0-dq17) c out v out = 0v 5pf
IBM041813PPLB 64k x 18 burst pipeline sram 8190738 sa14-4655-04 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 12 dc electrical characteristics (t a = 0 to +70 c, v dd =3.3v 5%) parameter symbol min. max. units notes operating current average power supply operating current (i out = 0, oe= v ih ,) i dd12 325 ma 2, 3 standby current power supply standby current ( cs = v ih , all other inputs = v ih or v il , i out. = 0, clk at 100mhz) i sb 25ma 1, 3 input leakage current input leakage current, any input (v in = 0 &v dd ) i li +1 m a 4 output leakage current (v out =0 &v dd , oe = v ih ) i lo +1 m a output high level output h level voltage (i oh =-8ma @ 2.4v) v oh 2.4 v output low level output l level voltage (i ol =+8ma @ 0.4v) v ol 0.4 v 1. i sb = stand-by current. 2. i dd = selected current. 3. i out = chip output current. 4. the input leakage current for 5.5v inputs is 200 m a for clk, chip selects, and output enable. other inputs have100 m a of leakage current at 5.5v. ac test conditions (t a =0 to +70 c, v dd =3.3v 5%) parameter symbol conditions units notes input pulse high level v ih 3.0 v input pulse low level v il 0v input rise time t r 2.0 ns input fall time t f 2.0 ns input and output timing reference level 1.5 v output load conditions 1 1. see ac test loading figure 1 on page 7.
IBM041813PPLB 64k x 18 burst pipeline sram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 12 8190738 sa14-4655-04 revised 9/97 ac characteristics (t a =0 to +70 c, v dd =3.3v 5%, units in nsec) parameter symbol -12 notes min. max . cycle time t cycle 12.0 clock pulse high t ch 3.0 clock pulse low t cl 3.0 clock to output valid t cq 5.0 1 address status controller setup time t adscs 2.5 address status controller hold time t adsch 0.5 address status processor setup time t adsps 2.5 address status processor hold time t adsph 0.5 advance setup time t advs 2.5 advance hold time t advh 0.5 address setup time t as 2.5 address hold time t ah 0.5 chip selects setup time t css 2.5 chip selects hold time t csh 0.5 write enables setup time t wes 2.5 write enables hold time t weh 0.5 data in setup time t ds 2.5 data in hold time t dh 0.5 data out hold time t cqx 0.75 1 clock high to output high-z t chz 5.5 1, 2, 3 clock high to output active t clz 0.5 1, 2, 3 output enable to high-z t ohz 2.0 6.5 1, 2 output enable to low-z t olz 0.25 1, 2 output enable to output valid t oq 5.0 1. see ac test loading figure 1 on page 7. 2. t ohz , t olz , t chz and t clz transitions are measured 200 mv from steady state voltage. see ac test loading ?gure 2 on page 7. 3. in depth expansion applications where one sram is selected and the other is not, bus contention will not occur because t clz is measured from the second rising clock edge while t chz is measured from the ?rst rising clock edge.
IBM041813PPLB 64k x 18 burst pipeline sram 8190738 sa14-4655-04 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 12 ac test loading 50 w vl = 1.5 v 50 w dq fig. 1 test equivalent load 0.0 0.5 1.0 1.5 2.0 2.5 3.0 015 45 30 75 105 picofarads -0.5 -1.0 60 90 nanoseconds the derating curve above is for a purely capacitive load on the output driver. for example, a part specified at 5ns access time will behave as though it has an 5.5 ns access time if a 30 pf load with no dc component was attached to the output driver. the access times guaran- teed in the datasheets are based on a 50 ohm terminated test load. for unterminated loads the derating curve should be used. this curve is based on nominal process conditions with worst case parameters v dd = 3.14 v, t a = 70 c. 30 pf output capacitive load derating curve 351 w dq fig. 2 test equivalent load 5 pf + 3.3 v 317 w
IBM041813PPLB 64k x 18 burst pipeline sram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 12 8190738 sa14-4655-04 revised 9/97 timing diagram (burst read) clk oe a1 a2 addr adv adsc adsp wea web cs dq t cycle t ch t cl t adsps t adsph t adscs t adsch t advs t advh t as t ah t ah t as t weh t wes t csh t css t css t csh t olz t oq t cq q1(a) q2(a) q2(b) q2(c) t ohz t cqx t cq notes: 1. q1(a) and q2(a) refer to output for address a1 and a2 respectively. 2. q2(b) and q2(c) refer to output from subsequent internal burst counter addresses.
IBM041813PPLB 64k x 18 burst pipeline sram 8190738 sa14-4655-04 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 12 timing diagram (burst write) clk oe a2 addr adv adsc adsp wea web cs dq t cycle t ch t cl a1 d1(a) d2(a) d2(b) d2(b) t adsps t adsph t adsch t adscs t advh t advs t advh t advs t ah t as t as t ah t weh t wes t css t csh t css t csh t ohz t dh t ds t clz t ds t dh t ds t ds t dh t dh notes: 1. d1(a) and d2(a) refer to data written to addresses a1 and a2. 2. d2(b) refers to data written to a subsequent internal burst counter address. 3. wea and web are dont cares when adsp is sampled low. t ohz
IBM041813PPLB 64k x 18 burst pipeline sram ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 12 8190738 sa14-4655-04 revised 9/97 52 pin plcc package diagram 20.07 0.127 19.1 0.05 1.067 - 1.219 lead #1 lead #52 20.07 0.127 19.1 0.05 0.660 - 0.813 1.143 dia. x 0.0 - 0.254 deep polished 4 x 2.44 - 0.07 dia. ejector pins 9.91 9.91 1.445 dia. x 0.0 - 0.254 deep polished optional 18.85 0.05 (15.24) 18.29 (+0.25/-0.76) detail k 3.86 0.10 1.27 4.37 (+.020/-0.18) 2.56 (+0.23/-0.02) 0.254 0 . 008 1.067 - 1.422 0.254 max 0.508 1.651 0.330 - 0.533 0.686 - 0.838 0.508 min 0.330 - 0.457 0.660 - 0.813 0.635 min 1.524 min r 0.635 - r 1.143 detail l 45? 1.575 - 1.727 detail k detail l 0.660 0.813 note: all measurements in millimeters scale 20/1 scale 20/1
IBM041813PPLB 64k x 18 burst pipeline sram 8190738 sa14-4655-04 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 12 revision log rev contents of modi?cation 5/94 initial release of the 64k x 18 (10/12) tqfp burst mode application spec. 3/95 updated -10, -12 specifications. 7/95 added note 5 on burst sram clock truth table & note 3 on ac characteristics for clarification purposes. updated ac characteristics as well. removed preliminary classification. 3/96 removed -10 specification. 9/97 updated part numbers to add die revision character. this new datasheet does not reflect a die revision
intern ational business machines corp.1997 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a

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