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review document - seagate - d a t a b o o k version 1.01 july 2003 inic-243 0 firewire 800 to ata bridge ic
confidential INIC-2430 data sheet revision notes for INIC-2430 data book: p/n 2430x-011ds rev 1.01, 7/03 revision history doc rev 1.00 (p/n x2430x-011ds) 06/03 doc rev 1.01 (p/n 2430x-011ds) 07/03 (current release) technical information changes in this data book release the table below lists technical information that has changed from the INIC-2430 data book revision 1.00 to the INIC-2430 data book revision 1.01 . (superficial or non-technical edits are not indicated.) section updated pages affected change description 5.4 64 table 5-4, icc values were tbd. 6.1 65 tlsu, tlh, and tlhz timings changed to 1.5 minimum, and 2.9 maximum. for tlsu, tlh, and figure 6-2: phy lclk was phy pclk. INIC-2430 data sheet confidential
INIC-2430 features copyright copyright? 2003 initio corporation. all rights reserved. no part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any, electronic, mechanical, photocopying, recording without the express written consent and authorization of initio corporation, 650 north mary ave., sunnyvale, ca 94085 trademarks initio, inic-, are registered trademarks of initio corporation. change initio corporation reserves the right to make changes in the product design without reservation and without notification to its users. the material in this publication is for information only and is subject to change without notice. ? ieee std 1394-1995 and 1394b compliant ? support industry standard firewire 800 phy ? support asynchronous transfers at 100, 200, 400 and 800 mbits/s ? perform 1394b cycle master ? implements sbp3/sbp2 stack to optimize the performance ? sbp-3 faststart support ? shadow ram for fast code fetch ? programmable wait state for cpu to access registers, external sram, and flash ? ata/atapi-7 d1532r2, vol. 1 & 2 compliant ? support ata dma modes 0-2, and udma 133/100/66/33 (note that mode 6, 133 mbytes/s, is only supported when running 1394b mode) ? support ata pio mode 0-4 ? integrated internal arm7tdmi 32-bit cpu with embedded sram ? implement the firmware download mechanism ? power management ? low power cmos operating at 3.3 and 2.5 volts ? 144-pin lqfp or 144-pin tfbga packages available ? dual ata channels ? 100 mbytes/s raw data rate read and write ? 6 gpio pins available with tfbga package version ? 4k payload size ? supports up to 32 mb of external sram and 32 mb of flash memory ? 16 kb of internal sram INIC-2430 data sheet confidential
INIC-2430 data sheet confidential i table of contents section 1 - overview ................................................................................................................................ .............. 1 1.1 introduction ................................................................................................................................ .................. 1 1.1.1 feature summary .............................................................................................................................. 1 1.1.2 firmware/software support .............................................................................................................. 1 1.1.3 devices support ................................................................................................................................ 2 1.1.4 reference documents ....................................................................................................................... 2 section 2 - pin definitions ................................................................................................................................ ..... 3 2.1 link-phy interface pins ........................................................................................................................... 5 2.2 ata interface pins ................................................................................................................................ ...... 6 2.3 mvram / gpio interface pins .................................................................................................................. 7 2.4 local microprocessor interface pins ........................................................................................................... 8 2.5 system interface pins ................................................................................................................................ ... 9 2.6 power and ground pins ............................................................................................................................... 9 section 3 - address mapping summary ............................................................................................................ 11 3.1 address mapping ................................................................................................................................ ....... 11 3.1.1 firmware shadow procedure .......................................................................................................... 12 3.2 registers ................................................................................................................................ ..................... 13 3.2.1 link block ................................................................................................................................ ....... 13 3.2.2 ata block ................................................................................................................................ ...... 14 3.2.3 data port to wr/rd s/g fifos ..................................................................................................... 14 3.2.4 bridge general registers ................................................................................................................ 14 3.3 buffers ................................................................................................................................ ....................... 17 3.3.1 cmd/data block ......................................................................................................................... 17 3.3.1.1 asynchronous receive packet formats ........................................................................ 18 3.3.1.2 asynchronous transmit packet formats ...................................................................... 21 3.3.1.3 phy receive packet format ......................................................................................... 24 3.3.1.4 synthesized bus reset packet format .......................................................................... 25 3.3.2 s/g dma block .............................................................................................................................. 26 3.3.2.1 sglist header format ................................................................................................... 26 3.4 memories ................................................................................................................................ ................... 28 3.4.1 external flash memory ................................................................................................................... 28 3.4.2 internal memory block ................................................................................................................... 28 3.4.3 external memory block .................................................................................................................. 28 INIC-2430 data sheet confidential
ii confidential INIC-2430 data sheet table of contents section 4 - register descriptions ....................................................................................................................... 29 4.1 register descriptions ................................................................................................................................ 29 4.1.1 link block registers ...................................................................................................................... 29 4.1.2 ata block registers ..................................................................................................................... 38 4.1.3 data port to wr/rd s/g fifos .................................................................................................... 40 4.1.4 bridge general registers ................................................................................................................ 41 section 5 - electrical specifications ................................................................................................................... 63 5.1 absolute maximum ratings ...................................................................................................................... 63 5.2 recommended operating conditions ....................................................................................................... 63 5.3 general dc characteristics ....................................................................................................................... 64 5.4 dc electrical characteristics for normal operation ................................................................................ 64 section 6 - timing specifications ....................................................................................................................... 65 6.1 1394 link to phy interface ...................................................................................................................... 65 6.2 flash / memory interface .......................................................................................................................... 66 6.2.1 flash memory read cycle ............................................................................................................. 66 6.2.2 flash memory write cycle ............................................................................................................ 67 6.2.3 external sram read cycle ........................................................................................................... 68 6.2.4 external sram write cycle .......................................................................................................... 69 section 7 - packaging specifications ................................................................................................................. 71 7.1 INIC-2430 lqfp packaging specifications ............................................................................................. 71 7.2 INIC-2430 tfbga packaging specifications .......................................................................................... 73
INIC-2430 data sheet confidential 1 section 1 overview 1.1 introduction the INIC-2430 provides an advanced solution to connect atapi or ata (ide/eide) devices to an ieee-1394b interface with an integrated 32-bit cpu and embedded sram. to provide high performance and a cost effective solution, the INIC-2430 integrates a 1394b link core, ata con- trol block and microprocessor into a single asic. the INIC-2430 delivers a data transfer rate of up to 800 mbits/sec on firewire 800 (1394) interface (100 mbytes/sec), while its ata interface supports ultra dma modes (33/66/100/133 mbytes/sec). 1.1.1 feature summary ? ieee std 1394-1995 and 1394b compliant ? support industry standard firewire 800 phy ? support asynchronous transfers at 100, 200, 400 and 800 mbits/s ? perform 1394b cycle master ? implements sbp3/sbp2 stack to optimize the performance ? sbp3/sbp2 faststart support ? shadow ram for fast code fetch ? programmable wait state for cpu to access registers, external sram, and flash ? ata/atapi-7 d1532r2, vol. 1 & 2 compliant ? support ata dma modes 0-2, and udma 133/100/66/33 (note that mode 6, 133 mbytes/s, is only supported when running 1394b mode) ? support ata pio mode 0-4 ? integrated internal arm7tdmi 32-bit cpu with embedded sram ? implement the firmware download mechanism ? power management ? low power cmos operating at 3.3 and 2.5 volts ? 144-pin lqfp or 144-pin tfbga packages available ? dual ata channels ? 100 mbytes/s raw data rate read and write ? 6 gpio pins available with tfbga package version ? 4k payload size ? supports up to 32 mb of external sram and 32 mb of flash memory ? 16 kb of internal sram 1.1.2 firmware/software support ? protocols supported include sbp-2, sbp-3, rbc and ata/atapi -7 ? software utilities for downloading the upgraded firmware code INIC-2430 data sheet
2 confidential INIC-2430 data sheet overview section 1 1.1.3 devices support ? hard disk drives ? cd-rw devices ? dvds ? removable media devices ? tape devices figure 1-1 INIC-2430 block diagram 1.1.4 reference documents ? ieee std 1394-1995 specification ? ieee std 1394a-2000 and ieee std 1394a-2002 ? ieee std p1212 ? ieee std 1394b local interface 32-bit cpu INIC-2430 link control block data fifo (sgbuffer) data flow control cmdtxbuf control command/status block scratch ram control registers block ata dma/ udma control block firewire 800 to ata bridge disk phy flash up to 16 mwords (16-bit access) or 32 mbytes (8-bit access) external sram (optional)
INIC-2430 data sheet confidential 3 section 2 pin definitions figure 2-1 shows the pinout of the INIC-2430. figure 2-1 INIC-2430 lqfp pin assignments 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 g p i o 0 0 g p i o 0 1 v c c _ 2 . 5 g n d p h y d 0 7 p h y d 0 6 p h y d 0 5 p h y d 0 4 v c c _ 2 . 5 g n d p h y d 0 3 p h y d 0 2 p h y d 0 1 p h y d 0 0 p h y c t l 0 1 p h y c t l 0 0 p h y l c l k v c c _ 3 . 3 p h y p c l k g n d p h y l r e q p h y l i n k o n p h y p i n t p h y l p s a t a c s 1 0 # a t a c s 1 1 # v c c _ 2 . 5 v c c _ 3 . 3 a t a i n t r q 1 a t a d m a c k 1 # a t a i o r d y 1 g n d a t a d i o r 1 # a t a d i o w 1 # a t a d m a r q 1 v c c _ 2 . 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ua22 ua21 ua20 gnd ua19 ua18 vcc_3.3 ua17 vcc_2.5 ua16 ua15 ua14 gnd ua13 ua12 ua11 vcc_2.5 ua10 ua09 ua08 gnd ua07 ua06 ua05 vcc_3.3 ua04 ua03 ua02 gnd ua01 ua00 vcc_2.5 gnd porst# vcc_3.3 gnd INIC-2430 144-pin lqfp top view 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 gnd atad09 atad06 atad10 vcc_2.5 atad05 atad11 atad04 gnd atad12 atad03 atad13 vcc_2.5 vcc_3.3 atad02 atad14 atad01 gnd atad15 atad00 atadmarq0 vcc_2.5 atadiow0# atadior0# ataiordy0 atadmack0# ataintrq0 vcc_2.5 vcc_3.3 ataa01 ataa02 ataa00 gnd atacs01# atacs00# atarst1# 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 u a 2 3 u a 2 4 a r m t e s t e n g n d e x t s r a m r d # e x t s r a m w r # v c c _ 2 . 5 e x t f l a s h r d # e x t f l a s h w r # g n d g n d u d 0 0 u d 0 1 u d 0 2 v c c _ 3 . 3 u d 0 3 u d 0 4 u d 0 5 g n d u d 0 6 u d 0 7 u d 0 8 v c c _ 2 . 5 u d 0 9 u d 1 0 u d 1 1 g n d u d 1 2 u d 1 3 u d 1 4 v c c _ 3 . 3 u d 1 5 v c c _ 2 . 5 a t a r s t 0 # a t a d 0 8 a t a d 0 7 confidential
4 confidential INIC-2430 data sheet pin definitions section 2 figure 2-2 shows the pinout of the INIC-2430 for the tfbga package. figure 2-2 INIC-2430 tfbga pin assignments a6 a1 ua16 b1 ua14 c1 ua12 d1 ua10 m1 phyd07 l1 porst# k1 ua18 j1 ua00 h1 ua02 g1 ua04 h4 vcc_3.3 g4 vcc_3.3 f4 vcc_2.5 e4 vcc_2.5 d4 vcc_2.5 f1 ua06 e1 ua08 a2 ua17 b2 ua15 c2 ua13 d2 ua11 m2 phyd06 l2 ua23 k2 ua19 j2 ua01 h2 ua03 g2 ua05 h5 gnd g5 gnd f5 gnd e5 gnd d5 vcc_2.5 f2 ua07 e2 ua09 a3 exflashrd# b3 exflashwr# c3 ud13 d3 ud14 m3 phyd05 l3 ua24 k3 ua21 j3 ua20 h3 armtesten g3 exsramre# h6 gnd g6 gnd f6 gnd e6 gnd d6 umas1 f3 exsramwe# e3 ud15 a4 ud06 b4 ud07 c4 ud12 a5 ud04 b5 ud05 c5 ud11 b6 ud03 c6 ud10 k4 ua22 l4 gpio00 m4 phyd04- k5 gpio03 l5 gpio01 m5 phyd03 k6 gpio04 l6 gpio02 m6 phyd02 a7 ud00 b7 ud01 c7 ud09 a8 atacs11# b8 atacs10# c8 ud08 a9 ataintrq1 b9 atadmack1# c9 ataiordy1 k7 gpio05 l7 phylps m7 phyd01 k8 umreq# l8 phylinkon m8 phyd00 k9 umas0 l9 phypint m9 phyctl01 a10 atacs00# b10 atadior1# c10 atadiow1# d10 atadmarq1 m10 phyctl00 l10 atad07 k10 ataintrq0 j10 atadior0# h10 atadmarq0 g10 atad01 h7 gnd g7 gnd f7 gnd e7 gnd d7 ext_test f10 atad00 e10 atarst1# a11 atacs01# b11 ataa02 c11 atad09 d11 atad10 m11 phylclk l11 atarst0# k11 atadmack0# j11 atad05 h11 atadiow0# g11 atad02 h8 gnd g8 gnd f8 gnd e8 gnd d8 vcc_3.3 f11 atad15 e11 atad03 a12 ataa00 b12 ataa01 c12 atad06 d12 atad04 m12 phypclk l12 phylreq k12 atad08 j12 ataiordy0 h12 atad11 g12 atad13 h9 vcc_2.5 g9 vcc_2.5 f9 vcc_3.3 e9 vcc_3.3 d9 vcc_3.3 f12 atad14 e12 atad12 j4 vcc_3.3 j5 vcc_3.3 j6 urw# j7 uwait# j8 vcc_2.5 j9 vcc_2.5 ud02 top view
section 2 pin definitions INIC-2430 data sheet confidential 5 2.1 link-phy interface pins table 2-1 link-phy interface pins symbol lqfp pin # tfbga pin # type description phypclk 55 m12 i phy pclock: clock from phy. phylclk 53 m11 o 4 ma phy lclock: clock to phy. phypint 59 l9 i phy interrupt: interrupt from phy to the link. phylps 60 l7 o 4 ma phy link ps: link power status. phylinkon 58 l8 i pull up phy link on: linkon from the phy to the link. pull up resistance is 40-190 k w , 75 k w typical. phylreq 57 l12 o 4 ma phy link request: link request signal. phyd[7:0] 41-44, 47-50 m1-m8 i/o 4 ma phy data: data bus between link and phy. phyctl[1:0] 51, 52 m9, m10 i/o 4 ma phy control: control bus between link and phy.
6 confidential INIC-2430 data sheet pin definitions section 2 2.2 ata interface pins ata interface pins are for 3.3 volt logic levels but are 5 volt tolerant. * note: all ata interface pin outputs a re 4 to 10 ma, programmable. table 2-2 ata interface pins symbol lqfp pin # tfbga pin # type description atad[15:0] 90, 93, 97, 99, 102, 105, 107, 110, 109, 106, 103, 101, 98, 94, 92, 89 f11, f12, g12, e12, h12, d11, c11, k12, l10, c12, j11, d12, e11, g11, g10, f10 i/o 4 ma* ata data [15:0]: ata data bus. atacs00# 74 a10 o 4 ma* ata device chip select 00 : this sig- nal is active low. atacs01# 75 a11 o 4 ma* ata device chip select 01 : this sig- nal is active low. atacs10#/ tstp06/rs232txd 61 b8 o 4 ma* ata device chip select 10 : this sig- nal is active low. atacs11#/ tstp07/rs232rxd 62 a8 i/o 4 ma* ata device chip select 11 : this sig- nal is active low. atadmarq0 88 h10 i/o 4 ma* ata dma request 0 atadmarq1/ ntrst/tstp00/ gpio[5] 71 d10 i/o 4 ma* ata dma request 1 : the gpio[5] function is brought out to a separate pin in the tfbga package. atadmack0# 83 k11 i/o 4 ma* ata dma acknowledge 0 : this sig- nal is active low. atadmack1#/ tck/tstp01 66 b9 i/o 4 ma* ata dma acknowledge 1 : this sig- nal is active low. atadiow0# 86 h11 o 4 ma* ata i/o write 0: this signal is active low. atadiow1#/ tms/tstp04/ gpio[4] 70 c10 i/o 4 ma* ata i/o write 1: the gpio[4] function is brought out to a separate pin in the tfbga package. atadior0# 85 j10 o 4 ma* ata i/o read 0: this signal is active low.
section 2 pin definitions INIC-2430 data sheet confidential 7 2.3 mvram / gpio interface pins atadior1#/ tdo/tstp03/ gpio[3] 69 b10 i/o 4 ma* ata i/o read 1: the gpio[2] function is brought out to a separate pin in the tfbga package. ataiordy0 84 j12 i ata i/o ready 0 ataiordy1/ tdi/tstp02/ gpio[2] 67 c9 i/o 4 ma* ata i/o ready 1: the gpio[2] function is brought out to a separate pin in the tfbga package. ataintrq0 82 k10 i ata interrupt request 0 ataintrq1 65 a9 i ata interrupt request 1 ataa[2:0] 78, 79, 77 b11, b12, a12 o 4 ma* ata device address [2:0] atarst0# 111 l11 o 4 ma* ata reset 0: this bit is active low. atarst1#/ tstp05/flash16 73 e10 i/o 4 ma* ata reset 1: poweron strap to select flash type: 0: 8-bit flash 1: 16-bit flash table 2-3 mvram/gpio interface pins symbol lqfp pin # tfbga pin # type description gpio[1:0] 38, 37 l5, l4 i/o 4 ma general purpose i/o [1:0] gpio[5:2] (multiplexed with other functions in lqfp pkg) k7-k5, l6 i/o 4 ma general purpose i/o [5:2]: these pins are multiplexed with other functions in the lqfp package and brought out separately (as shown here) in the tfbga package. table 2-2 ata interface pins (continued) symbol lqfp pin # tfbga pin # type description
8 confidential INIC-2430 data sheet pin definitions section 2 2.4 local microprocessor interface pins table 2-4 local microprocessor interface pins symbol lqfp pin # tfbga pin # type description ud[15:0] 113, 115-117, 119-121, 123- 125, 127-129, 131-133 e3, d3, c3-c8, b4, a4, b5, a5, b6, a6, b7, a7 i/o 8 ma local data bus [15:0] ua[24] 143 l3 o 8 ma local address bus [24] ua[23] / a1394 144 l2 i/o 8 ma local address bus [23]: output - local address bus bit 23. input - 0: 1394b mode, 1: 1394a mode. (this pin should be tied high or low with a pull up/down resistor for power-on reset.) ua[22:0] 1-3, 5, 6, 8, 10- 12, 14-16, 18- 20, 22-24, 26- 28, 30, 31 k4, k3, j3, k2, k1, a2, a1, b2, b1, c2, c1, d2, d1, e2, e1, f2, f1, g2, g1, h2, h1, j2, j1 o 8 ma local address bus [22:0] umas[1:0] n/a d6, k9 i local mas [1:0]: these pins are for manufacturing use only and must be tied low for normal operation. umreq# n/a k8 i local master request: this pin is for manufacturing use only and must be tied low for normal operation. urw# n/a j6 i local r/w: this pin is for manufactur- ing use only and must be tied low for nor- mal operation. uwait# n/a j7 i local wait: this pin is for manufactur- ing use only and must be tied low for nor- mal operation. ext_test n/a d7 i external test: this pin is for manu- facturing use only and must be tied low for normal operation. extsramrd# 140 g3 o 8 ma external sram read strobe: this bit is active low. extsramwr# 139 f3 o 8 ma external sram write strobe: this bit is active low.
section 2 pin definitions INIC-2430 data sheet confidential 9 2.5 system interface pins 2.6 power and ground pins extflashrd# 137 a3 o 8 ma local external flash read strobe: this bit is active low. extflashwr# 136 b3 o 8 ma local external flash write strobe: this bit is active low. table 2-5 system interface pins symbol lqfp # tfbga # type description porst# 34 l1 i power on reset: active low. when this signal is active, all pins on the ata interface should be tri-stated. armtesten 142 h3 i arm test enable: 0: normal, 1: test internal arm. table 2-6 power and ground pins symbol lqfp pin # tfbga pin # type description vcc_2.5 9, 17, 32, 39, 45, 63, 72, 81, 87, 96, 104, 112, 122, 138 d4, d5, e4, f4, g9, h9, j8, j9 pwr (2.5v) power for internal core logic. vcc_3.3 7, 25, 35, 54, 64, 80, 95, 114, 130 d8, d9, e9, f9, g4, h4, j4, j5 pwr (3.3v) power for i/o logic. gnd 4, 13, 21, 29, 33, 36, 40, 46, 56, 68, 76, 91, 100, 108, 118, 126, 134, 135, 141 e5-e8, f5-f8, g5-g8, h5-h8 gnd ground for internal core logic and i/o pins. table 2-4 local microprocessor interface pins (continued) symbol lqfp pin # tfbga pin # type description
10 confidential INIC-2430 data sheet pin definitions section 2 this page is intentionally left blank.
INIC-2430 data sheet confidential 11 section 3 address mapping summary 3.1 address mapping figure 3-1 INIC-2430 address mapping note: this address area is mirrored to the flash code independent of the shadow scheme. address area no shadow (poweron default) shadow to internal sram shadow to external sram flash 0000_0000 |(32 mbytes) 01ff_ffff c000_0000 |(32 mbytes) c1ff_ffff 4000_0000 |(32 mbytes) 41ff_ffff external sram (32 mbytes) 4000_0000 | 41ff-ffff 0000_0000 | 01ff-ffff mirrored flash - see note 1 - (32 mbytes) 8000_0000 | 81ff-ffff - | | | | | | | 1 gbyte | | | | | | | internal sram (16 kbytes) c000_0000 | c000-3fff 0000_0000 | 0000-3fff c000_0000 | c000-3fff reserved c000_4000 |(1/2 gbytes - 16 kbytes) dfff_ffff 0000_4000 |(1 gbyte - 16 kbytes) 3fff_ffff c000_4000 |(1/2 gbytes - 16 kbytes) dfff_ffff registers (512 bytes) e000_0000 | e000_01ff buffers (3584 bytes) e000_0200 | e000_0fff reserved e000_1000 | ffff_ffff confidential
12 confidential INIC-2430 data sheet address mapping summary section 3 3.1.1 firmware shadow procedure method a: use internal sram as shadow ram 1 after power-on, the firmware will start fetching code from the flash (code space 0000_0000), and copy the code from the flash (data space 0000_0000 ? 01ff_ffff) into the internal sram (data space c000_0000 ? c000_3fff). 2 when the copy is done, the firmware should set the register bit shadowen (reg. e000_00bah, bit 7) to 1, which will enable the shadowed sram. another register bit, shadowext (reg. e000_00bah, bit 6), needs to be set to 0, which will select internal sram as the shadow ram. 3 with shadowen = 1 & shadowext = 0, the code fetch range 0000_0000 ? 3fff_ffff will be from internal sram, and 4 the flash will be re-located to code fetch range c000_0000 ? c1ff_ffff. method b: use external sram as shadow ram 1 after power-on, the firmware will start fetching code from the flash (code space 0000_0000), and copy the code from the flash (data space 0000_0000 ? 01ff_ffff) into the external sram (data space 4000_0000 ? 41ff_ffff). 2 when the copy is done, the firmware should set the register bit shadowen (reg. e000_00bah, bit 7) to 1, which will enable the shadowed sram. another register bit, shadowext (reg. e000_00bah, bit 6), also needs to be set to 1, which will select external sram as the shadow ram. 3 with shadowen = 1 & shadowext = 1, the code fetch range 0000_0000 ? 3fff_ffff will be from external sram, and 4 the flash will be re-located to code fetch range 4000_0000 ? 41ff_ffff. note: to make firmware programming easier to access flash: with register e000_0121 bit 0 = 1?b0 (default): address range 8000-81ff is hardcoded for flash access (not affected by shadow scheme).
section 3 address mapping summary INIC-2430 data sheet confidential 13 3.2 registers note: cpu accesses the internal registers: e000_0000h - e000_007fh: use 16/32-bit mode (link registers). e000_0090h: use 16-bit mode (ata data register). e000_0091h - e000_009fh: use 8/16-bit mode (ata control registers). e000_00a0h - e000_00a7h: use 16/32-bit mode (data port to wr/rd s/g fifos). e000_00b0h - e000_0153h: use 8/16/32-bit mode (bridge general registers). note: cpu will access the ata device registers at the addresses shown in section 3.2.2: 3.2.1 link block address read value write value e000_0000h xatretries xatretries e000_0004h yatretries yatretries e000_0008h zatretries zatretries e000_000ch txackcntrl txackcntrl e000_0010h cycstartspdcntrl cycstartspdcntrl e000_0014h reserved reserved e000_0018h selfidcount selfidcount e000_001ch reserved reserved e000_0020h channelrcvhi channelrcvhi_set e000_0024h channelrcvhi channelrcvhi_clr e000_0028h channelrcvlo channelrcvlo_set e000_002ch channelrcvlo channelrcvlo_clr e000_0030h intevent intevent_set e000_0034h intevent & intenable intevent_clr e000_0038h intenable intenable_set e000_003ch intenable intenable_clr e000_0040h fairnesscntrl fairnesscntrl e000_0044h pingcntreg pingcntreg e000_0048h linkcntrl linkcntrl_set e000_004ch linkcntrl linkcntrl_clr e000_0050h nodeid nodeid e000_0054h phycntrl phycntrl e000_0058h- e000_007ch reserved reserved
14 confidential INIC-2430 data sheet address mapping summary section 3 3.2.2 ata block note: the ata device registers are part of an external ata device. these registers are accessed at the addresses shown below: 3.2.3 data port to wr/rd s/g fifos 3.2.4 bridge general registers address read value write value e000_0090h data[15:0] (16-bit access) data[15:0] (16-bit access) e000_0091h error features e000_0092h sectorcount sectorcount e000_0093h sectornumber sectornumber e000_0094h cyclinderlow cylinderlow e000_0095h cylinderhigh cylinderhigh e000_0096h device/head device/head e000_0097h status command e000_0098h-e000_009dh reserved reserved e000_009eh alternatestatus devicecontrol e000_009fh reserved reserved address read value write value e000_00a0h fifo0d[7:0] (32-bit access) fifo0d[7:0] (32-bit access) e000_00a1h fifo0d[15:8] fifo0d[15:8] e000_00a2h fifo0d[23:16] fifo0d[23:16] e000_00a3h fifo0d[31:24] fifo0d[31:24] e000_00a4h fifo1d[7:0] (32-bit access) fifo1d[7:0] (32-bit access) e000_00a5h fifo1d[15:8] fifo1d[15:8] e000_00a6h fifo1d[23:16] fifo1d[23:16] e000_00a7h fifo1d[31:24] fifo1d[31:24] address read value write value e000_00b0h sgpctrl sgpctrl e000_00b1h fifosts fifosts e000_00b2h gpiodata gpiodata e000_00b3h gpioctrl gpioctrl e000_00b4h testctrl0 testctrl0 e000_00b5h testctrl1 testctrl1 e000_00b6h drvctrl drvctrl
section 3 address mapping summary INIC-2430 data sheet confidential 15 e000_00b7h agnet0stat agent0stat e000_00b8h agent1stat agent1stat e000_00b9h agent1ofs agent1ofs e000_00bah upctrl upctrl e000_00bbh pwrmgntctrl pwrmgntctrl e000_00bch revid n/a e000_00c0h linkctrl linkctrl e000_00c1h dmactrl dmactrl e000_00c2h-e000_00c3h reserved reserved e000_00c4h atactrl (pio/dma en) atactrl (pio/dma en) e000_00c5h atamstrctrl (pio/dma mode for master device) atamstrctrl (pio/dma mode for master device) e000_00c6h ataslvctrl (pio/dma mode for slave device) ataslvctrl (pio/dma mode for slave device) e000_00c7h atastatus atastatus e000_00c8h-e000_00cfh reserved reserved e000_00d0h loginid0[7:0] (16-bit access) loginid0[7:0] (16-bit access) e000_00d1h loginid0[15:8] loginid0[15:8] e000_00d2h loginid1[7:0] (16-bit access) loginid1[7:0] (16-bit access) e000_00d3h loginid1[15:8] loginid1[15:8] e000_00e0h ata_wr_sg_threshold ata_wr_sg_threshold e000_00e1h reserved reserved e000_00e2h faststart0/1_offset faststart0/1_offset e000_00e3h-e000_00e4h reserved reserved e000_00e5h baud rate select baud rate select e000_00e6h start/stop/parity bit select start/stop/parity bit select e000_00e7h n/a rs232 wrport e000_00e8h rs232 wrport status n/a e000_00e9h rs232 rdport n/a e000_00eah rs232 rdport status n/a e000_00ebh timer_current_cnt[7:0] timer_count[7:0] e000_00ech timer_current_cnt[15:8] timer_count[15:8] e000_00edh timer timeout bit, timeout_to_int_enable bit timer timeout bit, timeout_to_int_enable bit e000_00f0h wait_state_arm_rw_reg wait_state_arm_rw_reg e000_00f1h wait_state_arm_rw_sram_ext wait_state_arm_rw_sram_ext e000_00f2h wait_state_arm_rw_flash wait_state_arm_rw_flash e000_00f3h wait_state_arm_rw_sram_int wait_state_arm_rw_sram_int e000_00f4h wait_state_arm_rw_buffer wait_state_arm_rw_buffer e000_00f5h wait_state_arm_rw_link_reg wait_state_arm_rw_link_reg e000_00f6h-e000_00ffh reserved reserved e000_0100h-010fh reserved reserved address read value write value
16 confidential INIC-2430 data sheet address mapping summary section 3 e000_0110h sgrun (32-bit access) sgrun_set e000_0111h sgrun sgrun_clr e000_0112h sgerror sgerror_clr e000_0113h sgretryexcd status sgretryexcd clear e000_0114h-e000_0117h reserved reserved e000_0118h cmdtxrun (8/16/32-bit access) cmdtxrun_set (8/16/32-bit access) e000_0119h cmdtxrun (8-bit access) cmdtxrun_clr (8-bit access) e000_011ah cmdtxerror (8/16-bit access) cmdtxerror_clr (8/16-bit access) e000_011bh cmdtxretryexcd (8-bit access) cmdtxretryexcd_clr (8-bit access) e000_011ch cmdtxreset (same as rd register 011ah) cmdtx state machine resume e000_011dh cmdtx2/0_busy status (rd) wr 1 to clear cmdtx2/0_busy (wr) e000_011eh cmdrxactivestatus cmdrxactivestatus_clr e000_0120h ackretry_en ackretry_en e000_0121h rcoderetry_en rcoderetry_en e000_0122h rereq_ch_en rereq_ch_en e000_0123h-e000_012fh reserved reserved e000_0130h tcode_rcode tcode_rcode e000_0131h-e000_013fh reserved reserved e000_0140h int0_status (8/16/32-bit access) int0_clear (8/16/32-bit access) e000_0141h int1_status (8-bit access) int1_clear (8-bit access) e000_0142h int2_status (8/16-bit access) int2_clear (8/16-bit access) e000_0143h int3_status (8-bit access) int3_clear (8-bit access) 0144h-014fh reserved reserved e000_0150h int0_en (8/16/32-bit access) int0_en (8/16/32-bit access) e000_0151h int1_en (8-bit access) int1_en (8-bit access) e000_0152h int2_en (8/16-bit access) int2_en (8/16-bit access) e000_0153h int3_en (8-bit access) int3_en (8-bit access) e000_0154h trailer0_byte0 na e000_0155h trailer0_byte1 na e000_0156h trailer0_byte2 na e000_0157h trailer0_byte3 na e000_0158h trailer1_byte0 na e000_0159h trailer1_byte1 na e000_015ah trailer1_byte2 na e000_015bh trailer1_byte3 na e000_015ch miscen miscen (internal testing) e000_0160h-e000_016f reserved reserved e000_0170h na split_timer_l e000_0171h na split_timer_h address read value write value
section 3 address mapping summary INIC-2430 data sheet confidential 17 3.3 buffers note: cpu accesses the internal buffers: e000_0200h - e000_02bfh: cmdrxbuffers: rd: use 8/16/32-bit mode. (cpu is not allowed to write cmdrxbuffers) e000_0300h - e000_0dffh: cmdtxbuffers: wr/rd: use 8/16/32-bit mode. e000_0e00h - e000_0e7fh: s/g list0-3: 8/16/32-bit mode. 3.3.1 cmd/data block address read value write value e000_0200h - e000_023fh cmdrx0buffer (64 bytes) cannot be written by cpu e000_0280h - e000_02bfh cmdrx1buffer (64 bytes) cannot be written by cpu e000_0300h - e000_03ffh cmdtx0buffer (256 bytes) cmdtx0buffer (256 bytes) e000_0500h - e000_053fh cmdtx1buffer (64 bytes) cmdtx1buffer (64 bytes) e000_0600h - e000_06ffh cmdtx2buffer (256 bytes) cmdtx2buffer (256 bytes) e000_0800h - e000_083fh cmdtx3buffer (64 bytes) cmdtx3buffer (64 bytes) e000_0900h - e000_091fh cmdtx4buffer?s header (20 bytes) cmdtx4buffer?s header (20 bytes) e000_0a00h - e000_0a7fh cmdtx4buffer?s data (128 bytes) cmdtx4buffer?s data (128 bytes) e000_0c00h - e000_0c1fh cmdtx5buffer?s header (20 bytes) cmdtx5buffer?s header (20 bytes) e000_0d00h - e000_0d7fh cmdtx5buffer?s data (128 bytes) cmdtx5buffer?s data (128 bytes)
18 confidential INIC-2430 data sheet address mapping summary section 3 note: for outgoing packets , the local link module expects a 5 quadlet-header from cmdtxbuffer or sglist, and will process this 5-quadlets header, and send out a 4-quadlets header to firewire 800 bus (complies with 1394 protocol). for incoming packets , the header always has 4 quadlets. 3.3.1.1 asynchronous receive packet formats the following are the header formats used with asynchronous receive packets. the link_core accepts only receive packets with valid "tcode" as defined by ieee std 1394a-2000; packets with undefined "tcode" are rejected. refer to table 3-1 for descriptions of the fields used. figure 3-2 rxrdreqdq - quadlet read request receive packet format figure 3-3 rxwrresp - write response receive packet format figure 3-4 rxwrreqdq - quadlet write request receive packet format 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 destinationid tlabel rt tcode (4?h4) sourceid destinationoffset [47:32] destinationoffset [31:0] r x b e t a p k t evtcode spd timestamp 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 destinationid tlabel rt tcode (4?h2) sourceid rcode r x b e t a p k t evtcode spd timestamp 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 destinationid tlabel rt tcode (4?h0) sourceid destinationoffset [47:32] destinationoffset [31:0] quadlet data r x b e t a p k t evtcode spd timestamp
section 3 address mapping summary INIC-2430 data sheet confidential 19 figure 3-5 rxrdreqdb - block read request receive packet format figure 3-6 rxrdrespdq - quadlet read response receive packet format figure 3-7 rxwrreqdq - block write request receive packet format figure 3-8 rxrdrespdb - block read response receive packet format 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 destinationid tlabel rt tcode (4?h5) sourceid destinationoffset [47:32] destinationoffset [31:0] datalength r x b e t a p k t evtcode spd timestamp 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 destinationid tlabel rt tcode (4?h6) sourceid rcode quadlet data r x b e t a p k t evtcode spd timestamp 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 destinationid tlabel rt tcode (4?h1) sourceid destinationoffset [47:32] destinationoffset [31:0] datalength block data padding (if needed) r x b e t a p k t evtcode spd timestamp 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 destinationid tlabel rt tcode (4?h7) sourceid rcode datalength block data padding (if needed) r x b e t a p k t evtcode spd timestamp
20 confidential INIC-2430 data sheet address mapping summary section 3 table 3-1 asynchronous receive packet format field definitions field name bit(s) packet type description 1st quadlet destinationid 31:16 all packets destination id: this is the concatenation of the 10-bit bus number and the 6-bit node number for the destination of this packet. this field gives the destination id of the node to which the packet was transmit- ted. tlabel 15:10 all packets transaction label: this field is used to pair up a response packet with its corresponding request packet. rt 9:8 all packets retry code: this is the retry code for this packet. the link_core ignores the software provided retry code and substi- tutes an rt as appropriate for the implemented retry mechanism unless the rtsel bit is set to 1. tcode 7:4 all packets transaction code: this is the transaction code for this packet. 2nd & 3rd quadlets sourceid 31:16 all packets source id: node-id (bus-id + physical-id of the sender of this packet. destinationoffset [47:32] destinationoffset [31:0] 15:0 (2nd) 31:0 (3rd) rxrdreqdq rxwrreqdq rxrdreqdb rxwrreqdb destination offset: the concatenation of these two fields addresses a quadlet in the destination node?s address space. for block data payload packets, the concatenation of these two fields indicates the starting address of block data payload. this address must be quadlet-aligned (modulo 4). rcode 15:12 rxwrresp rxrdrespdq rxrdrespdq response code: this is the response code field. 4th quadlet datalength 31:16 rxwrreqdb rxrdrespdb rxrdreqdb data length: the number of bytes requested in a block read request or number of bytes in a block response packet. extra quadlets block data rxwrreqdb rxrdrespdb block data payload: irrespective of the destination or source node data alignment, the first byte of the block data payload must be the most significant byte of the first quadlet in the "block data" field. padding rxwrreqdb rxrdrespdb padding: the sender of the packet pads the data block with the required number of bytes to make the block data an integral multiple of quadlets. last quadlet rxbetapkt 30 all packets receive beta packet: this bit when set, indicates that the packet was received in beta format. when clear, this bit indicates that the packet was received in legacy format. evtcode 28:24 all packets evtcode: for a non-broadcast asynchronous receive packet, the "evtcode" field carries the acknowledge code sent by the link_core prefixed by 1?b1. for a broadcast asynchronous receive packet, "evtcode" carries "ack_complete" prefixed by 1?b1. spd 23:21 all packets speed: this field indicates the speed at which this packet is to be transmitted. 3?b000 = 100 mbits/sec, 3?b001 = 200 mbits/sec, 3?b010 = 400 mbits/sec, and 3?b011 = 800 mbits/sec. other values are reserved. timestamp 15:0 all packets time stamp: this is the low order 3 bits of isochronouscy- cletimer. cycleseconds and the full 13 bits of isochronouscy- cletimer. cyclecount at the end of packet reception.
section 3 address mapping summary INIC-2430 data sheet confidential 21 3.3.1.2 asynchronous transmit packet formats the following are the header formats used with asynchronous transmit packets. refer to table 3-2 for descriptions of the fields used. figure 3-9 txrdreqdq - quadlet read request transmit packet format figure 3-10 txwrresp - write response transmit packet format figure 3-11 txwrreqdq - quadlet write request transmit packet format figure 3-12 txrdreqdb - block read request transmit packet format 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 t x b e t a p k t e h c r c r t s e l spd tcode (4?h4) destinationid tlabel rt tcode (4?h4) sourceid destinationoffset [47:32] destinationoffset [31:0] 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 t x b e t a p k t e h c r c r t s e l spd tcode (4?h2) destinationid tlabel rt tcode (4?h2) sourceid rcode 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 t x b e t a p k t e h c r c r t s e l spd tcode (4?h0) destinationid tlabel rt tcode (4?h0) sourceid destinationoffset [47:32] destinationoffset [31:0] quadlet data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 t x b e t a p k t e h c r c r t s e l spd tcode (4?h5) destinationid tlabel rt tcode (4?h5) sourceid destinationoffset [47:32] destinationoffset [31:0] datalength
22 confidential INIC-2430 data sheet address mapping summary section 3 figure 3-13 txrdrespdq - quadlet read response transmit packet format figure 3-14 txwrreqdb - block write request transmit packet format figure 3-15 txrdrespdb - block read reponse transmit packet format 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 t x b e t a p k t e h c r c r t s e l spd tcode (4?h6) destinationid tlabel rt tcode (4?h6) sourceid rcode quadlet data 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 t x b e t a p k t e h c r c e d c r c r t s e l spd tcode (4?h1) destinationid tlabel rt tcode (4?h1) sourceid destinationoffset [47:32] destinationoffset [31:0] datalength block data padding (if needed) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 t x b e t a p k t e h c r c e d c r c r t s e l spd tcode (4?h7) destinationid tlabel rt tcode (4?h7) sourceid rcode datalength block data padding (if needed)
section 3 address mapping summary INIC-2430 data sheet confidential 23 table 3-2 asynchronous transmit packet header field definitions field name bit(s) packet type description 1st quadlet txbetapkt 27 all packets transmit beta packet: this bit if set, the link_core sets the "rfmt" bit in the asynchronous packet transmit request pattern. set this bit to explicitly request the phy to use the beta packet format for packet transmission. ehcrc 26 all packets header crc error: this bit if set, the link_core sends the packet with header crc error. edcrc 25 txwrreqdb txrdrespdb data crc error: this bit if set, the link_core sends the packet with data crc error. rtsel 24 all packets retry code select: this is the retry code select bit for this packet. the link_core ignores the software provided retry code and substitutes an rt as appropriate for the implemented retry mech- anism unless the rtsel bit is set to 1. spd 18:16 all packets speed: this field indicates the speed at which this packet is to be transmitted. 3?b000 = 100 mbits/sec, 3?b001 = 200 mbits/sec, 3?b010 = 400 mbits/sec, and 3?b011 = 800 mbits/sec. other values are reserved. tcode 7:4 all packets transaction code: this is the transaction code for this packet. 2nd quadlet destinationid 31:16 all packets destination id: concatenation of the 10-bit bus number and the 6-bit node number for the destination of this packet. this field gives the destination id of the node to which the packet was transmitted. tlabel 15:10 all packets transaction label: this field is used to pair up a response packet with its corresponding request packet. rt 9:8 all packets retry code: this is the retry code for this packet. the link_core ignores the software provided retry code and substi- tutes an rt as appropriate for the implemented retry mechanism unless the rtsel bit is set to 1. tcode 7:4 all packets transaction code: this is the transaction code for this packet. 3rd & 4th quadlets sourceid 31:16 all packets source id: this is the concatenation of the 10-bit bus number and the 6-bit physical id for the transmitting node, as supplied by the host. destinationoffset [47:32] destinationoffset [0:31] 15:0 (2nd) 31:0 (3rd) txrdreqdq txwrreqdq txrdreqdb txwrreqdb destination offset: the concatenation of these two fields addresses a quadlet in the destination node?s address space. for block data payload packets, the concatenation of these two fields indicates the starting address of block data payload. this address must be quadlet-aligned (modulo 4). rcode 15:12 txwrresp txrdrespdq txrdrespdb response code: this is the response code field. 5th quadlet quadlet data 31:0 txwrreqdq txrdrespdq quadlet data: for quadlet write requests, this field holds the data to be written. for quadlet read responses, this fields holds the data quadlet read from the host address space. datalength 31:16 txwrreqdb txrdrespdb txrdreqdb data length: the number of bytes requested in a block read request or the number of bytes present in a block write request or block read response packet. if the "datalength" field value is 16?h0, the header crc quadlet will be the last quadlet of the packet. extra quadlets block data rxwrreqdb rxrdrespdb block data payload: irrespective of the destination or source node data alignment, the first byte of the block data payload must be the most significant byte of the first quadlet in the "block data" field. padding rxwrreqdb rxrdrespdb padding: if datalength ( datalength field value mod 4 ) is not equal to zero, then zero-value bytes have to be added to make the packet length an integral multiple of quadlets. link_core will accept and transmit only packets that contain intergral multiple of quadlets.
24 confidential INIC-2430 data sheet address mapping summary section 3 3.3.1.3 phy receive packet format the following is the header format used with phy receive packets. all unspecified bits are reserved and have a value of ?0?. refer to table 3-3 for descriptions of the fields used. figure 3-16 phy receive packet format table 3-3 phy receive packet format field definitions 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 tcode (4?he) phy packet quadlet 1 phy packet quadlet 2 spd timestamp field name bit(s) description 1st quadlet tcode 7:4 transaction code: this is the transaction code for this packet. set to 4?he to indicate a phy packet. 2nd quadlet phy packet (1st quadlet) 31:0 phy packet 1st quadlet: this is the first quadlet of the received phy packet. 3rd quadlet phy packet (2nd quadlet) 31:0 phy packet 2nd quadlet: this is the second quadlet of the received phy packet; it is the logical inverse (ones-complement) of "phy packet first quadlet". 4th quadlet spd 23:21 speed: this field indicates the speed at which this packet is to be transmitted. 3?b000 = 100 mbits/sec, 3?b001 = 200 mbits/sec, 3?b010 = 400 mbits/sec, and 3?b011 = 800 mbits/sec. other values are reserved. timestamp 15:0 time stamp: this is the low order 3 bits of isochronouscy- cletimer. cycleseconds and the full 13 bits of isochronouscy- cletimer. cyclecount at the end of packet reception.
section 3 address mapping summary INIC-2430 data sheet confidential 25 3.3.1.4 synthesized bus reset packet format the following is the header format used with synthesized bus reset packets. all unspecified bits are reserved and have a value of ?0?. refer to table 3-4 for descriptions of the fields used. figure 3-17 synthesized bus reset packet format table 3-4 synthesized bus reset packet format field definitions 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 tcode (4?he) selfidgeneration evtcode (5?h09) field name bit(s) description 1st quadlet tcode 7:4 transaction code: this is the transaction code for this packet. set to 4?he to indicate a phy packet. 3rd quadlet selfidgeneration 23:16 self id generation: this is the selfidcount.selfidgeneration value at the time this packet was created. 4th quadlet evtcode 28:24 evtcode: a value of 5?h09 identifies it as a bus-reset packet.
26 confidential INIC-2430 data sheet address mapping summary section 3 3.3.2 s/g dma block note: s/g list0-3 are for channel sg0-3?s headers. s/g fifo0-1 are ping-pong buffers for sg channel?s data. s/g fifos can be accessed by cpu through the data ports: wr access: fifo0: 32-bit wr to port adderss e000_00a0 or 16-bit wr to port address e000_00a0 16-bit wr to port address e000_00a2 fifo1: 32-bit wr to port adderss e000_00a4 or 16-bit wr to port address e000_00a4 16-bit wr to port address e000_00a6 rd access: fifo0: 32-bit rd from port adderss e000_00a0 or 16-bit rd from port address e000_00a0 16-bit rd from port address e000_00a2 fifo1: 32-bit rd from port adderss e000_00a4 or 16-bit rd from port address e000_00a4 16-bit rd from port address e000_00a6 3.3.2.1 sglist header format for outgoing packets , the local link module expects a 5 quadlet-header from cmdtxbuffer or sglist, and will process this 5-quadlets header, and send out a 4-quadlets header to firewire 800 bus (complies with 1394 protocol). for incoming packets , the header always has 4 quadlets. refer to table 3-5 for descriptions of the fields used. figure 3-18 sglist header format address read value write value e000_0e00h - e000_0e1fh s/g list0 (20 bytes) s/g list0 (20 bytes) e000_0e20h - e000_0e3fh s/g list1 (20 bytes) s/g list1 (20 bytes) e000_0e40h - e000_0e5fh s/g list2 (20 bytes) s/g list2 (20 bytes) e000_0e60h - e000_0e7fh s/g list3 (20 bytes) s/g list3 (20 bytes) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 t x b e t a p k t e h c r c e d c r c s r c i d l . s e g m o r e d i r spd tcode destinationid tlabel rt tcode sourceid destinationoffset [47:32] destinationoffset [31:0] datalength
section 3 address mapping summary INIC-2430 data sheet confidential 27 table 3-5 sglist header format field definitions field name bit(s) description 1st quadlet reserved 31:28 reserved: these bits should be cleared to 0 by firmware during the initialization process. txbetapkt 27 transmit beta packet: this bit if set, the link_core sets the "rfmt" bit in the asynchronous packet transmit request pattern. set this bit to explicitly request the phy to use the beta packet format for packet transmission. ehcrc 26 header crc error: if this bit is set to 1, the link_core sends the packet with a header crc error. edcrc 25 header data error: if this bit is set to 1, the link_core sends the packet with a data crc error. reserved 24 reserved: this bit should be cleared to 0 by firmware during the initialization process. srcid 23 source bus id selector: if cleared to 0, the high order 10 bits of the source_id field of the transmitted packet will be 10?h3ff. if set to 1, the high order 10 bits of the source_id field of the transmit- ted packet will be node_id. busnumber . reserved 22 reserved: this bit should be cleared to 0 by firmware during the initialization process. l. seg 21 last segment: if the command is the last one of s/g segments, this bit should be set to 1 by firmware. more 20 more: if the number of commands in sgcmd buffer is more than one, this bit should be set to 1 by firmware. dir 19 direction: when 0, the dma data are transferred from the firewire 800 bus to an ata device. when 1, the dma data are transferred from an ata device to the firewire 800 bus. spd 18:16 speed: this field indicates the speed at which this packet is to be transmitted. 3?b000 = 100 mbits/sec, 3?b001 = 200 mbits/sec, 3?b010 = 400 mbits/sec, and 3?b011 = 800 mbits/sec. other values are reserved. tcode 7:4 transaction code: this is the transaction code for this packet. 2nd quadlet destinationid 31:16 destination id: this is the concatenation of the 10-bit bus num- ber and the 6-bit node number for the destination of this packet. tlabel 15:10 transaction label: this field is the transaction label, which is used to pair up a response packet with its corresponding request packet. rt 9:8 retry code: this is the retry code for this packet. the link_core ignores the software provided retry code and substi- tutes an rt as appropriate for the implemented retry mechanism unless the rtsel bit is set to 1. tcode 7:4 transaction code: this is the transaction code for this packet. 3rd & 4th quadlets sourceid 31:16 source id: this is the concatenation of the 10-bit bus number and the 6-bit node number for the source of this packet. destinationoffset [47:32] destinationoffset [31:0] 15:0 (2nd) 31:0 (3rd) destination offset: the concatenation of these two fields addresses a quadlet in the destination node?s address space. this address must be quadlet-aligned (modulo 4). 5th quadlet datalength 31:16 data length: the number of bytes requested in a block read request or number of bytes in a block response packet.
28 confidential INIC-2430 data sheet address mapping summary section 3 3.4 memories notes: to provide easy firmware programming and maximum flexibility, the decoding logic does not dis- tinguish code space and data space. therefore, no write protection to code space is provided. the firm- ware programmer needs to be aware, and only write to firmware area when intended to do so. in the tables below, shadowen is reg. e000-00bah, bit 7 and shadowext is reg. e000-00bah, bit 6. 3.4.1 external flash memory cpu accesses flash: using 8-bit or 16-bit modes. refer to section 3.1.1 for firmware shadow procedure. 3.4.2 internal memory block cpu accesses internal sram(16 kbytes): c000_0000h - c000_3fffh: wr/rd: use 8/16/32-bit mode. 3.4.3 external memory block cpu accesses external sram: wr/rd: using 16-bit mode . address read value write value 0000_0000h- 01ff_ffffh (32 mbytes) ~nrw && ( ~shadowen ) initial power on, start the code fetch from here (32 mbytes) nrw && ( ~shadowen ) c000_0000h- c1ff_ffffh (32 mbytes) ~nrw && ( shadowen && ~shadowext ) partially shadowed by internal sram. (32 mbytes) nrw && ( shadowen && ~shadowext ) 4000_0000h- 41ff_ffffh (32 mbytes) ~nrw && ( shadowen && shadowext ) partially shadowed by external sram. (32 mbytes) nrw && ( shadowen && shadowext ) address read value write value c000_0000h- c000_3fffh (16 kbytes) ~nrw && ~ ( shadowen && ~shadowext ) (16 kbytes) nrw && ~ ( shadowen && ~shadowext ) 0000_0000h- 0000_3fffh (16k bytes) ~nrw && ( shadowen && ~shadowext ) mainly used as shadow ram. (16k bytes) nrw && ( shadowen && ~shadowext ) address read value write value 4000_0000h- 40ff_ffffh (16m bytes) ~nrw && ~ ( shadowen && shadowext ) (16m bytes) nrw && ~ ( shadowen && shadowext ) 0000_0000h- 00ff_ffffh (16m bytes) ~nrw && ( shadowen && shadowext ) mainly used as shadow ram. (16m bytes) nrw && ( shadowen && shadowext )
INIC-2430 data sheet confidential 29 section 4 register descriptions 4.1 register descriptions note: all registers have a base address of 0xe000-0000h . cpu accesses the internal registers using 8-bit or 16-bit or 32-bit modes. cpu accesses internal buffers, sram using 32-bit mode. cpu accesses flash using 8-bit or 16-bit modes. 4.1.1 link block registers 0x0000-0x0003 x asynchronous transmit retries (xat_retry) bit(s) rscu reset acronym definition 31:29 rwu 3?h0 (secondlimit) second limit: 28:16 rwu 13?h0 (cyclelimit) cycle limit: together the secondlimit and cyclelimit fields define a time limit for retry attempts when the outbound dual-phase retry protocol is enabled. the secondlimit field represents a count in seconds modulo 8, and cycle- limit represents a count in cycles modulo 8000. a value of zero written to both fields disables the outbound dual phase retry protocol and enables outbound single phase retry protocol. 15-4 r 12?h0 reserved reserved 3:0 rw 4?h0 (maxatretries) max async transmit retries: the retrycountlimit field tells the 1394b_link core how many times to attempt to retry the transmit operation for an asynchronous packet. 0x0004-0x0007 y asynchronous transmit retries (yat_retry) bit(s) rscu reset acronym definition 31:29 rwu 3?h0 (secondlimit) second limit: 28:16 rwu 13?h0 (cyclelimit) cycle limit: together the secondlimit and cyclelimit fields define a time limit for retry attempts when the outbound dual-phase retry protocol is enabled. the secondlimit field represents a count in seconds modulo 8, and cycle- limit represents a count in cycles modulo 8000. a value of zero written to both fields disables the outbound dual phase retry protocol and enables outbound single phase retry protocol. 15-4 r 12?h0 reserved reserved 3:0 rw 4?h0 (maxatretries) max async transmit retries: the retrycountlimit field tells the 1394b_link core how many times to attempt to retry the transmit operation for an asynchronous packet. confidential
30 confidential INIC-2430 data sheet register descriptions section 4 0x0008-0x000b z asynchronous transmit retries (zat_retry) bit(s) rscu reset acronym definition 31:29 rwu 3?h0 (secondlimit) second limit: 28:16 rwu 13?h0 (cyclelimit) cycle limit: together the secondlimit and cyclelimit fields define a time limit for retry attempts when the outbound dual-phase retry protocol is enabled. the secondlimit field represents a count in seconds modulo 8, and cycle- limit represents a count in cycles modulo 8000. a value of zero written to both fields disables the outbound dual phase retry protocol and enables outbound single phase retry protocol. 15-4 r 12?h0 reserved reserved 3:0 rw 4?h0 (maxatretries) max async transmit retries: the retrycountlimit field tells the 1394b_link core how many times to attempt to retry the transmit operation for an asynchronous packet. 0x000c-0x000f txack control (txackcntrl) bit(s) rscu reset acronym definition 31 rw 3?h0 (1?b0) external acknowledge code enable: 30-28 r 3?b0 reserved reserved 27:24 rw 4?h0 (extackcode) external acknowledge code: when extackcodeen is set, the 1394b_link core sends extackcode[0:3] value as the acknowledge code for any non-broadcast asynchronous receive packet. 23-0 r 24?h0 reserved reserved 0x0010-0x0013 cycle start speed control (cycstartspdctrl) bit(s) rscu reset acronym definition 31:28 rw 4?h0 (cycstrttxspd) cycle start transmit speed: when the 1394b_link core is the cycle master, it will transmit csp according the speed value written into ?cycstrttxspd? field. the mapping is as follows: 4?b0000 s100 4?b0010 s200 4?b0100 s400 4?b0110 s800 27:24 ru 4?h0 (cycstrtrxspd) cycle start receive speed: when the 1394b_link core is the cycle slave, ?cycstrtrxspd? field will indicate the speed at which the 1394b_link core received the last csp. 23-0 r 24?h0 reserved reserved
section 4 register descriptions INIC-2430 data sheet confidential 31 0x0018-0x001b self id count (selfidcnt) bit(s) rscu reset acronym definition 31 ru 1?b0 (selfiderror) self id error: this bit is set in the following situations: ? ?rxbufferfull? signal is asserted during self-id packet reception. ? self-id packet reception starts before the 1394b_link core writes all the quadlets of the synthesized bus reset packet into the receive interface. ? a ?selfiderr? signal is asserted. ? a parity error is detected in one of the receive self-id packets. 30-24 r 7?b0 reserved reserved 23:16 ru 8?h00 (selfidgeneration) self id generation: the value in this field increments each time a receive self-id packet is written into the receive interface. this field rolls over to 0 after reaching 255. 15-13 r 3?b0 reserved reserved 12:2 ru 11?h0 (selfidsize) self id size: this field indicates the number of quadlets present in the last receive self-id packet written by the 1394b_link core to the receive interface. it includes the self-id header, self-id trailer and all the self-id packet quadlets received. 1-0 r 2?b0 reserved reserved 0x001c-0x001f reserved 0x0020-0x0023: set channel receive hi (chnlrcvhi_set) 0x0024-0x0027: clr channel receive hi (chnlrcvhi_clr) bit(s) rscu reset acronym definition 31:0 rsu 32?h0 (channelrcvhi) channel receive hi: if channelrcvhi[n] is set, the 1394b_link core will accept receive stream packets with channel number ?n? and if channelrcvhi[n] is cleared, the 1394b_link core will reject receive stream packets with channel number ?n? where ?n? can be 1, 2, 3, ? and 31. 0x0028-0x002b: set channel receive lo (chnlrcvlo_set) 0x002c-0x002f: clr channel receive lo (chnlrcvlo_clr) bit(s) rscu reset acronym definition 31:0 rsu 32?h0 (channelrcvlo) channel receive lo: if channelrcvlo[n] is set, the 1394b_link core will accept receive stream packets with channel number ?(n + 32)? and if channelrcvlo[n] is cleared, the 1394b_link core will reject receive stream packets with channel number ?(n + 32)? where ?n? can be 1, 2, 3, ? and 31.
32 confidential INIC-2430 data sheet register descriptions section 4 0x0030-0x0033: set interrupt event (intevent_set) 0x0034-0x0037: clr interrupt event (intevent_clr) this register reflects the state of the various interrupt sources from the 1394b_link core. reading the intevent_set register returns the current state of the intevent register. reading the intevent_clr register returns the enabled ver- sion of the intevent register; i.e. the result of (intevent & intenable). bit(s) rscu reset acronym definition 31 rscu 1?b0 (asyxtxcompint) asyxtxcomp interrupt: the asyxtxcompint bit is set when the 1394b_link core issues an asyxtxcomp pulse. 30 rscu 1?b0 (asyytxcompint) asyytxcomp interrupt: the asyytxcompint bit is set when the 1394b_link core issues an asyytxcomp pulse. 29 rscu 1?b0 (asyztxcompint) asyztxcomp interrupt: the asyztxcompint bit is set when the 1394b_link core issues an asyztxcomp pulse. 28 rscu 1?b0 ( reserved ) reserved 27 rscu 1?b0 ( reserved ) reserved 26 rscu 1?b0 (asyxtxtcodeerrint) asyxtxcodeerr interrupt: the asyxtxcodrerrint bit is set when the 1394b_link core detects a reserved ?tcode? value in the first quadlet of the packet in the asynchronous transmit queue x. 25 rscu 1?b0 (asyytxtcodeerrint) asyytxcodeerr interrupt: the asyytxcodrerrint bit is set when the 1394b_link core detects a reserved ?tcode? value in the first quadlet of the packet in the asynchronous transmit queue y. 24 rscu 1?b0 (asyztxtcodeerrint) asyztxcodeerr interrupt: the asyztxcodrerrint bit is set when the 1394b_link core detects a reserved ?tcode? value in the first quadlet of the packet in the asynchronous transmit queue z. 23 rscu 1?b0 ( reserved ) reserved 22 rscu 1?b0 ( reserved ) reserved 21 rscu 1?b0 (cycdatainvalidint) cycle data invalid interrupt: the cycledatainvalidint bit is set if the 1394b_link core detects invalid cycle timer contents in the received csp (without header crc error). 20 rscu 1?b0 (selfidcompleteint) self id complete interrupt: the selfidcompleteint bit is set after the 1394b_link core detects the first ?subactiongap? event indica- tion from phy following a ?busreset? event indication and after it has completely wrote the receive self-id packet to the receive interface. 19 rscu 1?b0 (ackmissing) acknowledge missing: the ackmissing bit is set, after the trans- mission of a non-broadcast asynchronous primary packet if: ? phy indicates a ?subactiongap? event before an ack is received. ? a parity error is detected in the ack received. ? a reserved acknowledge code is detected in the ack received. 18 rscu 1?b0 (asyxretryexcd) asynchronous x retrys exceeded: the asyxretryexcd bit is set, if the last ack received for the non-broadcast primary packet trans- mitted from asynchronous transmit queue x is ack_busy_* and ? if outbound single phase retry protocol is enabled, the number of retries attempted has reached the retry count limit set by asyxatre- tries.asyxretrycountlimit field, or...
section 4 register descriptions INIC-2430 data sheet confidential 33 ? if outbound dual phase retry protocol is enabled, the retry time has reached the time limit set by asyxatretries.asyxsecondlimit and asyxatretries.asyxcyclelimit fields together. 17 rscu 1?b0 (asyyretryexcd) asynchronous y retrys exceeded: the asyyretryexcd bit is set, if the last ack received for the non-broadcast primary packet trans- mitted from asynchronous transmit queue y is ack_busy_* and ? if outbound single phase retry protocol is enabled, the number of retries attempted has reached the retry count limit set by asyyatre- tries.asyyretrycountlimit field, or... ? if outbound dual phase retry protocol is enabled, the retry time has reached the time limit set by asyyatretries.asyysecondlimit and asyyatretries.asyycyclelimit fields together. 16 rscu 1?b0 (asyzretryexcd) asynchronous z retrys exceeded: the asyzretryexceeded bit is set, if the last ack received for the non-broadcast primary packet transmitted from asynchronous transmit queue z is ack_busy_* and ? if outbound single phase retry protocol is enabled, the number of retries attempted has reached the retry count limit set by asyzatre- tries.asyzretrycountlimit field, or... ? if outbound dual phase retry protocol is enabled, the retry time has reached the time limit set by asyzatretries.asyzsecondlimit and asyzatretries.asyzcyclelimit fields together. 15 rscu 1?b0 (phyinterruptint) phy_interrupt interrupt: the phyinterruptint bit is set when the 1394b_link core detects an out-of-band status transfer of type ?phy_interrupt? over the pint signal. 14 rscu 1?b0 (interfaceerrint) interface error interrupt: the interfaceerrorint bit is set when the 1394b_link core detects an out-of-band status transfer of type ?interface_error? over the pint signal. 13 rscu 1?b0 (rxtcodeerrint) rx tcode error interrupt: the rxtcodeerrint bit is set when the 1394b_link core detects a reserved ?tcode? value in the first qua- dlet of the receive packet. 12 rscu 1?b0 (datacrcerrint) data crc error interrupt: the datacrcerrint is set when the 1394b_link core detects a data crc error in the receive packet. 11 rscu 1?b0 (hdrcrcerrint) header crc error interrupt: the hdrcrcerrint is set when the 1394b_link core detects a header crc error in the receive packet. 10 rscu 1?b0 (phyregrcvdint) phy register received interrupt: the phyregrcvdint bit is set, when the 1394b_link core detects an out-of-band status transfer of type ?phy_register_sol? or ?phy_register_unsol? over the pint signal. 9 rscu 1?b0 (phyresetint) phy reset interrupt: the phyresetint bit is set, when the 1394b_link core detects an in-band status transfer of type ?phy inter- face reset? over the din[0:7] signal lines. 8 rscu 1?b0 (busresetint) bus reset interrupt: the busresetint bit is set when the 1394b_link core detects an in-band status transfer of type ?bus reset? over the din[0:7] signal lines.
34 confidential INIC-2430 data sheet register descriptions section 4 7 rscu 1?b0 (restorenoresetint) restore_no_reset interrupt: the restorenoresetint bit is set when the 1394b_link core detects an out-of-band status transfer of type ?ph_restore_no_reset? over the pint signal. 6 rscu undef (restoreresetint) restore_reset interrupt: the restoreresetint bit is set when the 1394b_link core detects an out-of-band status transfer of type ?ph_restore_reset? over the pint signal. 5 rscu undef (cyclelostint) cycle lost interrupt: the cyclelostint bit is set when the 1394b_link core detects two consecutive ?cyclesynch? events without receiving any csp in between. 4 rscu undef ( reserved ) reserved 3 rscu 1?b0 (subactiongapint) subaction gap interrupt: the subactiongapint bit is set when the 1394b_link core detects an in-band status transfer of type ?subac- tion gap? over the din[0:7] signal lines. 2 rscu 1?b0 (arbresetgapint) arbitration reset gap interrupt: the arbresetgapint bit is set when the 1394b_link core detects an in-band status transfer of type ?arbitration reset gap - odd? or ?arbitration reset gap - even? over the din[0:7] signal lines. 1 rscu 1?b0 (cycletoolongint) cycle too long interrupt: the cycletoolongint bit is set if the 1394b_link core does not detect an in-band status transfer of type ?subaction gap? over the din[0:7] signal lines even after 118 m s have elapsed after it last detected an in-band status transfer of type ?cycle start - odd? or ?cycle start - even? over the din[0:7] signal lines. this indi- cates that the isochronous cycle lasted longer than 118 m s. 0 rscu 1?b0 (commandrstint) command reset interrupt: the commandrstint bit is set if the 1394b_link core detects a valid write request for data quadlet packet addressed to the ?reset_start? register (destinationoffsethigh = 16?hffff and destinationoffsetlow = 32?hf000_000c). 0x0038-0x003b: set interrupt enable (intenable_set) 0x003c-0x003f: clr interrupt enable (intenable_clr) all the bits in the intenable register can be set and cleared. only those bits, which are valid in the intevent register, are valid in intenable register also. for example, bit position 11 is reserved in both intevent and intenable registers. any bit that is set in the intenable register will enable the interrupt event that occupies the same bit position in intevent register. for example, if bit [30] in intenable register is set, the interrupt event ?cycletoolongint? (bit [30] in intevent register) will be enabled. any bit that is cleared in the intenable register will disable the interrupt event that occupies the same bit position in intevent register. there are two addresses for this register: intenableset and intenableclr. on read, both addresses return the contents of the intenable register. 0x0040-0x0043 fairness control (fairnesscntrl) bit(s) rscu reset acronym definition 31-6 r 26?h0 reserved reserved 5:0 rw 6?h0 (prireqin) priority request in: this field specifies the maximum number of ?cur_async? arbitration requests for asynchronous request packets that the 1394b_link core is permitted to make of the phy during a fair- ness interval. a prireqin value of 6?h0 is equivalent to the behaviour specified by ieee 1394-1995 standard.
section 4 register descriptions INIC-2430 data sheet confidential 35 0x0044-0x0047 ping count (pingcntreg) bit(s) rscu reset acronym definition 31 rwu 1?b0 (pingcountvalid) ping count valid: when asserted, ?pingcountvalid? indicates that the contents of ?pingcount? field are valid and were generated for the pre- vious transmit phy packet. the 1394b_link core clears this bit when it starts transmission of a phy packet. 30-10 r 26?h0 reserved reserved 9:0 r 10?h0 (pingcount) ping count: this field specifies the number of 24.576 mhz clock cycles elapsed from the end of transmission of a phy packet to either the start of reception of a new packet or detecting of ?subactiongap? or a ?busreset? indication by the the 1394b_link core. if no response is received for a phy packet before the ?pingcount? reaches a value of 10?h3ff, this counter will not roll over to 10?h00, but will saturate. it is cleared by hardware when a next phy packet is transmitted by link. this field is valid only if the ?pingcountvalid? signal is asserted. 0x0048-0x004b: set link control (linkctl_set) 0x004c-0x004f: clr link control (linkctl_clr) the linkcontrol register provides the control flags that enable and configure the link core protocol portions of the link_core. it contains controls for the receiver, and cycle timer. there are two addresses for this register: lincon- trolset and linkcontrolclr. when read, both addresses return the contents of the linkcontrol register. when write, the two addresses have different behavior: a ?1? written to the linkcontrolset causes the corresponding bit in the linkcontrol register to be set, while a ?0? written to the linkcontrolset leaves the corresponding bit in the linkcontrol register unaffected. on the other hand, a ?1? written to the linkcontrolclr causes the corresponding bit in the linkcontrol register to be cleared, while a ?0? written to the linkcontrolclr leaves the corresponding bit in the linkcontrol register unaffected. bit(s) rscu reset acronym definition 31 rsc 1?b0 (cyclemstrcapable) cycle master capable: if set, this bit indicates that the 1394b_link core is capable of becoming a cycle master. 30 r 1?b0 (preroot) preroot: this bit indicates whether the 1394b_link core was root or not before the last ?busreset? event; set if it was the root and clear, if it was not the root. 29 rscu 1?b1 (cyclemaster) cycle master: when this bit is set, the 1394b_link core will trans- mit a csp on every cyclesynch event. when this bit is clear, the 1394b_link core will receive csp from firewire 800 (1394) serial bus to maintain synchronisation with the node, which is sending them. this bit is automatically cleared when the intevent.cycletoolongint occurs and cannot be set until the intevent.cycletoolongint bit is cleared. this bit can be set only if nodeid.root is set. after a bus reset, this bit is automati- cally activated by hardware. after the bus reset, if (nodeid.root == 1) { if (linkcontrol.preroot) {linkcontrol.cyclemaster retain its prior value} else {linkcontrol.cyclemaster = cyclemastercapable} } else {linkcontrol.cyclemaster = 0}
36 confidential INIC-2430 data sheet register descriptions section 4 28 rsc 1?b0 ( reserved ) reserved 27 rsc 1?b0 (rcvphypkt) receive phy packet enable: when set, the 1394b_link core will accept incoming phy packets. this does not control either the receipt of self-id packets during the self-id phase or the queuing of synthesised bus reset packets. this does control receipt of any self-id packets received outside the self-id phase. 26 rsc 1?b0 (rcvselfid) receive self id enable: when set, the 1394b_link core will accept the self-id packets received during bus initialisation phase. 25-8 r 18?b0 reserved reserved 7 rsc 1?b1 (inboundretrymode) inbound retry mode: when inboundretrymode is set, inbound single-phase retry protocol is enabled. when cleared, inbound dual-phase retry mode is enabled. 6-2 r 5?b0 reserved reserved 1 rsc 1?b0 (interfacereset) interface reset: when interfacereset is set, the 1394b_link core will initiate a phy-link interface reset operation by driving lps low as per p1394b draft 1.2 specifications. this bit is set by the hardware if the ?lpsreg? input signal is de-asserted for at least one clock period. this bit is cleared by the hardware when the phy-link interface reset operation is over. 0 r 1?b0 reserved reserved 0x0050-0x0053 node id (nodeid) this register contains the firewire 800 address for the node on which this chip resides . the 16-bit combination of busnumber and nodenumber is referred to as the node-id. this register is updated autonomously by the hardware whenever the 1394b_link core receives an out-of-band status transfer of type ?phy_register_unsol? or ?phy_register_sol?, addressed to phy register 0. bit(s) rscu reset acronym definition 31 ru 1?b0 (idvalid) id valid: this bit indicates whether the 1394b_link core has a valid nodenumber. it is cleared when a ?busreset? event is detected and set again when the 1394b_link core receives a valid nodenumber ( 1 63) from the phy through an out-of-band status transfer. 30 ru 1?b0 (root) root: this bit indicates whether the attached phy is root. it is cleared when ?busreset? event is detected and set again if bit 6 is set in the phy register data received during the out-of-band status transfer. 29-28 r 2?b0 reserved reserved 27 ru 1?b0 (cps) cable power status: this bit indicates whether the phy is report- ing that cable power status is ok (vp 8v). it is cleared when a ?busreset? event is detected and set again if bit 7 is set in the phy register data received during the out-of-band status transfer. 26-14 r 2?b0 reserved reserved 15:6 rwu 10?h3ff (busnumber) bus number: this number is used to identify the specific firewire 800 bus this node belongs to when multiple firewire 800-compatible busses are connected via a bridge. the reset value of 10?h3ff is a specifically reserved value:
section 4 register descriptions INIC-2430 data sheet confidential 37 5:0 ru 6?h3f (nodenumber) node number: this number is the physical node number established by the phy during self-id phase. it is automatically set to bits [0:5] in the phy register data received during the out-of-band status transfer. the 1394b_link core will not receive any packets if the nodenumber is 63. 0x0054-0x0057 phy control (phyctl) the phycontrol register is used to read or write a phy register. to read a phy register, the address of that phy reg- ister is written to the regaddr field of phycontrol register and the rdphyreg bit is set. when the read request has been sent to the phy (through the lreqout pin), the rdphyreg bit is cleared to ?0?. when the phy returns the register content (through a status transfer), the phyregrddone and then the intevent.phyre- grcvd bit are set. the address of the received phy register is placed in the rdaddr fields. the contents of the received phy register is placed in the phyregrddata fields. software shall serialise all phy register read and write requests. only after the current phy register read or write operation completes, software can issue another phy register read or write request. also software shall not try to set rdphyreg and wrphyreg at the same time. if so, rdphyreg will have priority and wrphyreg will be ignored. bit(s) rscu reset acronym definition 31 rwu 1?b0 (rddone) read done: this bit is set to ?1? by hardware when a phy register transfer from phy to link is done. this bit will be cleared to ?0? by soft- ware when either rdreg or wrreg is set to ?1?. 30 rwu 1?b0 (unsolicited) unsolicited: the unsolicited bit is set whenever the 1394b_link core receives an out-of-band status transfer of type ?phy_register_unsol? over the pint signal. 29-28 r 2?h0 reserved reserved 27:24 ru 4?h0 (rdaddr) read address: this is the phy register address received along with the last out-of-band status transfer of type ?phy_register_sol? or ?phy_register_unsol? over the pint signal . 23:16 ru 8?h0 (rddata) read data: this is the phy register address received along with the last out-of-band status transfer of type ?phy_register_sol? or ?phy_register_unsol? over the pint signal . 15 rwu 1?b0 (rdreg) read phy register: set this bit to ?1? to initiate a read request to a phy register. this bit is cleared when the 1394b_link core receives an out-of-band status transfer of type ?phy_register_sol? over pint signal. 14 rwu 1?b0 (wrreg) write phy register: set this bit to ?1? to initiate a write request to a phy register. this bit is cleared when the write request has been sent. 13-12 r 2?b0 reserved reserved 11:8 rw 4?h0 (regaddr) register address: this is the address of the phy register to be writ- ten to or read from. 7:0 rw 8?h0 (wrdata) write data: this is the contents to be written to a phy register. it is ignored when doing a read phy register request. 0x0058-0x005f reserved
38 confidential INIC-2430 data sheet register descriptions section 4 4.1.2 ata block registers note: the INIC-2430 cpu will access the ata device registers at the addresses shown below. check the device reg- ister specifications for the actual register and bit definitions. 0x0090 ata data (data[15:0]) the data register is 16 bits wide. bit(s) rscu reset acronym definition 15:0 rw 16?h0 (data[15:0]) data [15:0]: these are the ata data bits [15:0]. 0x0091 ata error/features (error/features[15:0]) if this address is read by the host, the error register is read. if this address is written by the host, the features register is written. bit(s) rscu reset acronym definition 15-3 r 13?h0 reserved reserved 2 rw 2?b0 (abrt) abort: when set, this bit indicates that the requested command has been command aborted. 1-0 r 2?b0 reserved reserved 0x0092 ata sector count (sectorcount) the contents of this register are command dependent. bit(s) rscu reset acronym definition 15:0 rw 16?h0 (sectcnt[15:0) sector count [15:0]: these are the ata sector count bits [15:0]. 0x0093 ata sector number (sectornumber) the contents of this register are command dependent. bit(s) rscu reset acronym definition 15:0 rw 16?h0 (sectnum[15:0]) sector number [15:0]: these are the ata sector number bits [15:0]. 0x0094 ata cylinder low (cylinderlow) the contents of this register are command dependent. bit(s) rscu reset acronym definition 15:0 rw 16?h0 (cyllow[15:0) cylinder low [15:0]: these are the ata cyclinder low bits [15:0]. 0x0095 ata cylinder high (cylinderhigh) the contents of this register are command dependent. bit(s) rscu reset acronym definition 15:0 rw 16?h0 (cylhigh[15:0) cylinder high [15:0]: these are the ata cylinder high bits [15:0].
section 4 register descriptions INIC-2430 data sheet confidential 39 0x0096 ata device (device) bit 4 selects the device. the other bits in this register are command dependent. bit(s) rscu reset acronym definition 15-5 r 11?h0 reserved reserved 4 rw 1?b0 (dev) device: when cleared, this bit indicates that device 0 has been selected and when set to ?1?, device 1 is selected. 3-0 r 4?b0 reserved reserved 0x0097 ata status/command (status/command) if this address is read by the host, the status register is read. if this address is written by the host, the command regis- ter is written. bit(s) rscu reset acronym definition 15-8 r 8?h0 reserved reserved 7 rw 1?b0 (bsy) busy: when set, this bit indicates that the device is busy. 6 rw 1?b0 (drdy) device ready: when set, this bit indicates that the device is ready. 5-4 r 2?b0 reserved reserved 3 rw 1?b0 (drq) data request: when set, this bit indicates that the device is ready to transfer a word of data between the host and the device. 2-1 r 2?b0 reserved reserved 0 rw 1?b0 (err) error: when set, this bit indicates that an error has occurred during exe- cution of the previous command. 0x0098-0x009d reserved 0x009e ata alternatestatus / devicecontrol (altsts/devcntrl) if this address is read by the host, the alternate status register is read. if this address is written by the host, the device control register is written. bit(s) rscu reset acronym definition 15-8 r 8?h0 reserved reserved 7 rw 1?b0 (hob) high order byte: this bit is defined by the 48-bit address feature set. a write to any command block register shall clear the hob bit to zero. 6-3 r 4?b0 reserved reserved 2 rw 1?b0 (srst) host software reset: when set, this bit is the host software reset bit. 1 r 1?b0 (nien) interrupt enable: this bit is the enable bit for the device assertion of intrq to the host. 0 rw 1?b0 (0) bit ?0? shall be cleared to zero. 0x009f reserved
40 confidential INIC-2430 data sheet register descriptions section 4 4.1.3 data port to wr/rd s/g fifos 0x00a0 fifo 0 data (fifo0d[7:0]) bit(s) rscu reset acronym definition 7:0 rw 8?h0 (fifo0data[7:0]) dma fifo 0 data [7:0]: software can access dma fifo 0 through this reg- ister 0x0a3-0a0 (using 32-bit or 16-bit mode access). 0x00a1 fifo 0 data (fifo0d[15:8]) bit(s) rscu reset acronym definition 7:0 rw 8?h0 (fifo0data[15:8]) dma fifo 0 data [15:8]: software can access dma fifo 0 through this register 0x0a3-0a0. 0x00a2 fifo 0 data (fifo0d[23:16]) bit(s) rscu reset acronym definition 7:0 rw 8?h0 (fifo0data[23:16]) dma fifo 0 data [23:16]: software can access dma fifo 0 through this register 0x0a3-0a0 (using 16-bit mode access). 0x00a3 fifo 0 data (fifo0d[31:24]) bit(s) rscu reset acronym definition 7:0 rw 8?h0 (fifo0data[31:24]) dma fifo 0 data [31:24]: software can access dma fifo 0 through this register 0x0a3-0a0. 0x00a4 fifo 1 data (fifo1d[7:0]) bit(s) rscu reset acronym definition 7:0 rw 8?h0 (fifo1data[7:0]) dma fifo 1 data [7:0]: software can access dma fifo 0 through this reg- ister 0x0a3-0a0 (using 32-bit or 16-bit mode access). 0x00a5 fifo 1 data (fifo1d[15:8]) bit(s) rscu reset acronym definition 7:0 rw 8?h0 (fifo1data[15:8]) dma fifo 1 data [15:8]: software can access dma fifo 0 through this register 0x0a3-0a0. 0x00a6 fifo 1 data (fifo1d[23:16]) bit(s) rscu reset acronym definition 7:0 rw 8?h0 (fifo1data[23:16]) dma fifo 1 data [23:16]: software can access dma fifo 0 through this register 0x0a3-0a0 (using 16-bit mode access). 0x00a7 fifo 1 data (fifo1d[31:24]) bit(s) rscu reset acronym definition 7:0 rw 8?h0 (fifo1data[31:24]) dma fifo 1 data [31:24]: software can access dma fifo 0 through this register 0x0a3-0a0.
section 4 register descriptions INIC-2430 data sheet confidential 41 4.1.4 bridge general registers 0x00b0 sgpiocmd control (sgpctrl) bit(s) rscu reset acronym definition 7-4 rw 1?b0 (piox3-0run) pioxnrun [3:0]: these run bits are used in conjunction with sgrun reg- ister bits [3:0]. these bits are self cleared by hardware after being set. before setting them, firmware needs to disable atadmaen and enable pioxen bit in ata enable register (reg 0x00c4). fill the package header into sglist, set the sgrun bit on sgrun register and the set the cor- responding pioxrun bit. the hardware will start transmitting the fifo data to/from ata using pio transfer mechanism. 3-0 rw 1?b0 (pio3-0run) pionrun [3:0]: start transfer for pio mode. when these bits are set, the hardware will start transmitting data from dma fifo to firewire 800 or receiving data from firewire 800 to dma fifo, based on the dir bit set- ting. these bits are self-cleared by hardware after set. before set this bit, the firmware needs to disable atadmaen bit on dma control register, write the package header into the segment of sgcmd buffer, set run bit on sgcmd control register, and fill data into fifo data register. 0x00b1 fifo status (fifosts) read: ?1? means the corresponding channel?s transaction is failed. writing a ?1? will clear the corresponding status bit. bit(s) rscu reset acronym definition 7 r 1?b0 ( reserved ) reserved 6 r 1?b0 (fifo1full) dma fifo 1 full: this bit is used to indicate the dma fifo 1 full status. 5 r 1?b1 (fifo1empty) dma fifo 1 empty: this bit is used to indicate that the dma fifo 1 empty status. 4 rw 1?b0 (fifo1rst) dma fifo 1 reset: this bit is used to reset dma fifo 1. this bit is self-cleared by hardware after set. 3 r 1?b0 ( reserved ) reserved 2 rw 1?b0 (fifo0full) dma fifo 0 full: this bit is used to indicate the dma fifo 0 full status. 1 r 1?b1 (fifo0empty) dma fifo 0 empty: this bit is used to indicate that the dma fifo 0 empty status. 0 rw 1?b0 (fifo0rst) dma fifo 0 reset: this bit is used to reset dma fifo 0. this bit is self-cleared by hardware after set. 0x00b2 gpio data (gpiodata) bit(s) rscu reset acronym definition 7 rw 1?b1 (atarst1#) ata channel 1 reset: this bit, when clear, will reset the ata device. 6 rwu 1?b0 (atarst0#) ata channel 0 reset: this bit, when clear, will reset the ata device. 5:0 rwu 1?b0 (gpiod[5:0]) gpio data [5:0]: these bits are general purpose i/o data bits [5:0].
42 confidential INIC-2430 data sheet register descriptions section 4 0x00b3 gpio control (gpioctrl) bit(s) rscu reset acronym definition 7-6 r 2?b0 ( reserved ) reserved 5:0 rw 6?hd (gpioctrl[5:0]) gpio control [5:0]: when set, the gpio data is output. 0x00b4 test control 0 (testctrl0) bit(s) rscu reset acronym definition 7 rw 1?b0 (rstatareq) ata request reset: when set, this bit will reset the current ata request (not used in INIC-2430). 6 r 1?b0 (alink) link select: 0: system uses blink. 1: system uses alink. 5 r 1?b1 reserved reserved 4 rw 1?b0 (rs232en) rs232 mode enable: when set, the rs232 test mode is enabled. 3 rw 1?b0 (testen) test mode enable: when set, the device is in test mode. 2:0 rw 3?h0 (testsel2-0) test mode select: these 3 bits select specific internal signals to be routed to the device?s outputs during test mode. 0x00b5 test control 1 (testctrl1) bit(s) rscu reset acronym definition 7 r 1?b0 (mbisten) memory bist enable: when set, memory built-in-self-test enabled. 6 r 1?b0 (mbistrst) memory bist reset: when set, memory built-in-self-test reset. 5-3 r 3?h000 reserved reserved 2:0 rw 3?b000 (retrydly[2:0]) firewire 800 retry delay enable [2:0]: when set, the hard- ware will wait for the selected time interval and then send the request packet out after receiving ack_busy. 000: no delay 001: 125 us (1394b), 250 us (1394a) 010: 250 us (1394b), 500 us (1394a) 011: 500 us (1394b), 1 ms (1394a) 100: 1 ms (1394b), 2 ms (1394a) 101: 2 ms (1394b), 4 ms (1394a) 110: 4 ms (1394b), 8 ms (1394a) 111: reserved
section 4 register descriptions INIC-2430 data sheet confidential 43 0x00b6 ata i/o cell driving control (drvctrl) bit(s) rscu reset acronym definition 7-5 r 3?h0 reserved reserved 4 rw 1?b0 (gpiosel) ata ch1 pin select: 0: use ata ch1?s pins for ata ch1. 1: use ata ch1?s pins for gpio[5:2]. 3 rw 1?b0 (atatsen1) ata ch1 enable: when set, ata ch1?s outputs are enabled. 2 rw 1?b0 (atatsen0) ata ch0 enable: when set, ata ch0?s outputs are enabled. 1:0 rw 3?b000 (drvsel[1:0]) ata output drive select [1:0]: when set, the ata output drives : 00: 4 ma 01: 6 ma 10: 8 ma 11: 10 ma 0x00b7 agent 0 state (agent0stat) bit(s) rscu reset acronym definition 7 rw 1?b0 (heartbeat_0) heartbeat 0: when this bit is set, it will generate a interrupt to indi- cate that chip received a wrreqqb packet for lun0 heartbeat. when firmware write ?1?, will clear it. 6 rw 1?b0 (faststart_0) faststart 0: when this bit is set, it will generate a interrupt to indicate that chip received a wrreqdb packet for lun0 faststart. when firmware write ?1?, will clear it. 5 rw 1?b0 (usn_0) unsolicited status enable 0: when this bit is set, it will gener- ate a interrupt to indicate that chip received a wrreqqb packet for lun0 unsolicited_status_enable. when firmware write ?1?, will clear it. 4 rw 1?b0 (doorbell_0) doorbell 0: when this bit is set, it will generate a interrupt to indicate that chip received a wrreqqb packet for lun0 doorbell. when firm- ware write ?1?, will clear it. 3 r 1?b0 reserved reserved 2 rw 1?b0 (orb_pointer_0) orb pointer 0: when this bit is set, it will generate a interrupt to indi- cate that chip received a wrreqdb packet for lun0 orb pointer and two quadlets of orb pointer will be re-route to cmdtx0 buffer. when firmware write ?1?, will clear it. 1 rw 1?b0 (agent_reset_0) agent reset 0: when this bit is set, it will generate a interrupt to indi- cate that chip received a wrreqqb packet for lun0 reset fetch agent. when firmware write ?1?, will clear it. 0 rw 1?b0 (agent_state_0) agent state 0: when this bit is set, it will generate a interrupt to indi- cate that chip received a wrreqqb packet for lun0 report fetch agent state. when firmware write ?1?, will clear it.
44 confidential INIC-2430 data sheet register descriptions section 4 0x00b8 agent 1 state (agent1stat) bit(s) rscu reset acronym definition 7 rw 1?b0 (heartbeat_1) heartbeat 1: when this bit is set, it will generate a interrupt to indi- cate that chip received a wrreqqb packet for lun1 heartbeat. when firmware write ?1?, will clear it. 6 rw 1?b0 (faststart_1) faststart 1: when this bit is set, it will generate a interrupt to indicate that chip received a wrreqdb packet for lun1 faststart. when firmware write ?1?, will clear it. 5 rw 1?b0 (usn_1) unsolicited status enable 1: when this bit is set, it will gener- ate a interrupt to indicate that chip received a wrreqqb packet for lun1 unsolicited_status_enable. when firmware write ?1?, will clear it. 4 rw 1?b0 (doorbell_1) doorbell 1: when this bit is set, it will generate a interrupt to indicate that chip received a wrreqqb packet for lun1 doorbell. when firm- ware write ?1?, will clear it. 3 r 1?b0 reserved reserved 2 rw 1?b0 (orb_pointer_1) orb pointer 1: when this bit is set, it will generate a interrupt to indi- cate that chip received a wrreqdb packet for lun1 orb pointer and two quadlets of orb pointer will be re-route to cmdtx0 buffer. when firmware write ?1?, will clear it. 1 rw 1?b0 (agent_reset_1) agent reset 1: when this bit is set, it will generate a interrupt to indi- cate that chip received a wrreqqb packet for lun1 reset fetch agent. when firmware write ?1?, will clear it. 0 rw 1?b0 (agent_state_1) agent state 1: when this bit is set, it will generate a interrupt to indi- cate that chip received a wrreqqb packet for lun1 report fetch agent state. when firmware write ?1?, will clear it. 0x00b9 agent 1 offset (agent1ofs) bit(s) rscu reset acronym definition 7:0 rw 8?h80 (agentofs[7:0]) fetch agent offset: fetch agent offset for lun1. this offset will be added to the base addesss of fetch agent (ffff f001 0000h) for point- ering to lun1 fetch agent registers. 0x00ba up control (upctrl) bit(s) rscu reset acronym definition 7 rw 1?b0 (shadowen) shadow enable: after power on, firmware will copy the code into shadow ram. then, firmware should set this bit to enable the shadow ram to provide code to cpu. 6 rw 1?b0 (shadowext) external shadow ram: 0: use internal sram as the shadow ram (shadowen needs to be 1). 1: use external sram as the shadow ram (shadowen needs to be 1). 5-0 r 6?h0 reserved reserved
section 4 register descriptions INIC-2430 data sheet confidential 45 0x00bb power management control (pwrmgntctrl) the power management mechanism works as follows: 1 cpu writes 1 to register 0xbb bit 0 to shut down the clocks on most parts of the bridge. clocks on/off switch- ing will occurs when clocks are at low voltage level. 2 cpu will enter its low power mode when its pipeline instruction queue is idle for 5 clks. 3 the system is now in ?sleep?. 4 4. an incoming ?phy resume packet? will wake up the bridge, restore the clocks, set the wakeup bit (register 0xbb bit 1), clear the sleep bit (register 0xbb bit 0), and optionally generate the sysint to cpu (if register 0xbb bit 2 has been set to 1). bit(s) rscu reset acronym definition 7-2 r 6?h0 reserved reserved 1 rw 1?b0 (wakeup) wakeup: the incoming ?phy resume packet? will set this bit to 1, firm- ware may read this register to determine the cause of the sysint. rd: wakeup status wr: write a ?1? to force wakeup (resume clock) 0 rw 1?b0 (regsleep) register sleep mode: firmware sets this bit to 1 to stop the clock. incoming ?phy resume packet? will clear this bit to 0 to restore the clocks. firmware may also write a 0 to this bit to clear it. 0x00bc revision id (revid) bit(s) rscu reset acronym definition 7:0 rw 8?h80 (revid[7:0]) revision id: this register is read only . 0x00c0 link control (linkctrl) bit(s) rscu reset acronym definition 7 rwu 1?b1 (databyteswap) data byte swap: a soft reset and a bus reset shall not affect this bit. 0: data quadlets are sent/received in big endian order. 1: data quadlets are sent/received in little endian order. 6 rwu 1?b0 (corehardrst) core hard reset: when 1, this bit will do the ?async reset? to all linkcore?s flip-flops which use ?coreclk? as the clock input. 5 rwu 1?b0 (phyhardrst) phy hard reset: when 1, this bit will do the ?async reset? to all linkcore?s flip-flops which use ?phyclk? as the clock input. 4 rwu 1?b0 (blockackdataerr) block ack data error: when 1, linkcore will send an ack_busy_* instead of ack_data_error if a data crc is detected for the incoming packet. 3 rwu 1?b1 lps link power status control: this bit is used to control the link power status. software must set lps to 1 to permit link ? phy communi- cation. once set, the link can use lreqs to perform phy reads and writes. an lps value of 0 prevents link ? phy communication. in this state, the only accessible host controller registers are version, vendorid, hccon- trol, guid_rom, guidhi and guidlo. access to other registers is not defined. hardware and software resets clear lps to 0. software shall not clear lps.
46 confidential INIC-2430 data sheet register descriptions section 4 2 rwu 1?b0 (postedwren) posted write enable: when set to ?1?, physical posted writes. when ?0?, physical writes shall not be posted. 1 rwu 1?b0 (linkenable) link enable: software must set this bit to ?1? when the system is ready to begin operation and then force a bus reset. this bit is necessary to keep other nodes from sending transactions before the local system is ready. when this bit is cleared the host controller is logically and immediately disconnected from the firewire 800 bus. the link shall not process or interpret any packets received from the phy, nor shall the link generate any bus requests. however, the link may access phy registers via the phy control register. this bit is cleared to ?0? by hardware reset or soft- ware reset, and shall not be cleared by software. software should not set the linkenable bit until the configuration rom mapping register is valid. 0 rwu 1?b0 (softrst) soft reset: when set to ?1?, all host controller state is reset, all fifo?s are flushed, and host controller registers is reset. the read value of this bit is ?1? while a soft reset or hard reset is in progress. the read value of this bit is ?0? when neither soft reset nor hard reset is in progress. software can use the value of his bit to determine when a reset has completed and the host controller is safe to operate. 0x00c1 dma control (dmactrl) bit(s) rscu reset acronym definition 7-4 r 4?h0 reserved reserved 3 rw 1?b1 (diow#) diow: when dma fifo is underrun, this bit is used by firmware to tog- gle diow# signal. 2 rw 1?b1 (dior#) dior: when dma fifo is underrun, this bit is used by firmware to tog- gle dior# signal. 1 rw 1?b1 (dmack#) dmack: when dma fifo is underrun, this bit is used by firmware to toggle dmack# signal. 0 rw 1?b0 (flushabort) flush / abort: when dma fifo is overrun, this bit is used by firm- ware to flush data out for outgoing data or abort the dma operation for incoming data. this bit is self-cleared by hardware. 0x00c2-0x00c3 reserved 0x00c4 dma control (dmactrl) bit(s) rscu reset acronym definition 7 rw 1?b1 (atadmaen) ata dma enable: this bit when set enables atadma. 6 rw 1?b0 (pioreqgrnt) pio req/grant: write a 1 for pio request. pio grant status when read. 5 rw 1?b0 (pioxen) piox engine enable: this bit when set enables piox engine. (atad- maen should be disabled when piox engine is enabled.) 4 rw 1?b0 (cfen) compact flash enable: when set to ?1?, this bit enables the com- pact flash. 3-0 r 4?h0 reserved reserved
section 4 register descriptions INIC-2430 data sheet confidential 47 0x00c5 ata master device control (atamstrctrl) bit(s) rscu reset acronym definition 7:4 rw 4?h0 (dmamode[3:0]) dma mode [3:0 ] : note - udma mode 6 is only supported when running 1394b mode. 0000: dma mode 0 (11 mb/s) 0001: dma mode 1 (13 mb/s) 0010: dma mode 2 (16 mb/s) 1010: udma mode 2 (33 mb/s) 1100: udma mode 4 (66 mb/s) 1101: udma mode 5 (100 mb/s) 1110: udma mode 6 (133 mb/s) all other values: reserved 3:0 rw 4?h0 (piomode[3:0]) pio mode [3:0 ] : 0000: pio mode 0 0001: pio mode 1 0010: pio mode 2 0011: pio mode 3 0100: pio mode 4 all other values: reserved 0x00c6 ata slave device control (ataslvctrl) bit(s) rscu reset acronym definition 7:4 rw 4?h0 (dmamode[3:0]) dma mode [3:0 ] : note - udma mode 6 is only supported when running 1394b mode. 0000: dma mode 0 (11 mb/s) 0001: dma mode 1 (13 mb/s) 0010: dma mode 2 (16 mb/s) 1010: udma mode 2 (33 mb/s) 1100: udma mode 4 (66 mb/s) 1101: udma mode 5 (100 mb/s) 1110: udma mode 6 (133 mb/s) all other values: reserved 3:0 rw 4?h0 (piomode[3:0]) pio mode [3:0 ] : 0000: pio mode 0 0001: pio mode 1 0010: pio mode 2 0011: pio mode 3 0100: pio mode 4 all other values: reserved 0x00c7 ata control/status (atastatus) bit(s) rscu reset acronym definition 7 rw 1?b0 (atach1en) ata channel 1 enable: when set, the ata channel is switched to 1. 6 rw 1?b0 (atach01en) ata channel 0 &1 enable: when set, dma writes to channels 0 and 1 will be executed simultaneously. 5 ru 1?b0 (atach1status) ata channel 1 status: read only
48 confidential INIC-2430 data sheet register descriptions section 4 4 ru 1?b0 (atach0status) ata channel 0 status: read only 3 ru 1?b0 (ataiordy1) ata channel 1 iordy: read only 2 ru 1?b0 (ataiordy0) ata channel 0 iordy: read only 1 ru 1?b0 (ataintrq1) ata channel 1 intrq: read only 0 ru 1?b0 (ataintrq0) ata channel 0 intrq: read only 0x00d0 login id0l (loginid0l) bit(s) rscu reset acronym definition 7:0 rw 8?hff (loginid0[7:0]) login id 0 [7:0]: these bits are the login id for lun 0. this id low byte is used by the hardware to recognize the incoming requests for lun 0. 0x00d1 login id0h (loginid0h) bit(s) rscu reset acronym definition 7:0 rw 8?hff (loginid0[15:8]) login id 0 [15:8]: these bits are the login id for lun 0. this id high byte is used by the hardware to recognize the incoming requests for lun 0. 0x00d2 login id1l (loginid1l) bit(s) rscu reset acronym definition 7:0 rw 8?hff (loginid1[7:0]) login id 1 [7:0]: these bits are the login id for lun 1. this id low byte is used by the hardware to recognize the incoming requests for lun 1. 0x00d3 login id1h (loginid1h) bit(s) rscu reset acronym definition 7:0 rw 8?hff (loginid1[15:8]) login id 1 [15:8]: these bits are the login id for lun 1. this id high byte is used by the hardware to recognize the incoming requests for lun 1. 0x00e0 ata sg write threshold (atawrsgthrshld) bit(s) rscu reset acronym definition 7:0 rw 8?h00 (atawrsgthrshld[7:0]) ata sg write threshold [7:0]: this register defines the threshold value when ata writes data into the s/g buffer. when the writepointer reaches this value, the s/g buffer starts transferring data to firewire 800. bit[7:0] corresponds to adr[11:4], for example: a value of 0x01 means threshold is 16 bytes. a value of 0xff means 255 x 16 bytes. when the value is 0, it will disable this feature. for best performance, the faster node may have a small threshold. to avoid rdpointer outruns of the writepointer, the slower node should have a larger threshold value. however, if an outrun occurs, the inic- 2430 will trigger a retry on the firewire 800 bus.
section 4 register descriptions INIC-2430 data sheet confidential 49 0x00e1 reserved 0x00e2 faststart 0/1 offset (faststart0/1ofs) bit(s) rscu reset acronym definition 7:4 rw 4?h2 (faststart1ofs[3:0]) faststart 1 offset [3:0]: these bits correspond to adr[11:8]. 3:0 rw 4?h1 (faststart0ofs[3:0]) faststart 0 offset [3:0]: these bits correspond to adr[11:8]. 0x00e3-0x00e4 reserved 0x00e5 rs232 baud rate (baudratesel) bit(s) rscu reset acronym definition 7:3 r 5?h0 reserved reserved 2:0 rw 3?h0 (baudratesel[2:0]) baud rate select [2:0]: 1394b_mode 1394a_mode 000: 9600 4800 001: 19200 9600 010: 38400 19200 011: 57600 --- 100: 115200 --- 101: --- 110: --- 111: --- 0x00e6 rs232 transfer select (rs232xfrsel) bit(s) rscu reset acronym definition 7-6 r 2?h0 reserved reserved 5:4 rw 2?h0 (startbitsel[1:0]) start bit select [1:0]: 00: 1 start bit 01: 1 start bit 10: 2 start bits 11: 3 start bits 3:2 rw 2?h0 (stopbitsel[1:0]) stop bit select [1:0]: 00: 1 stop bit 01: 1 stop bit 10: 2 stop bits 11: 3 stop bits 1:0 rw 2?h0 (paritybitsel[1:0]) parity bit select [1:0]: 00: no parity 01: odd parity 10: even parity 11: reserved
50 confidential INIC-2430 data sheet register descriptions section 4 0x00e7 rs232 wrport (rs232wrport) bit(s) rscu reset acronym definition 7:0 rw 8?h00 (wrrs232data[7:0]) rs232 write port data [7:0]: for debugging purpose, the firmware will write debugging messages (in asci codes) to this port, and inic- 2430 will convert it to the serial data, and send it out through rs232 pro- tocol. 0x00e8 rs232 wrport status (rs232wrctrl) bit(s) rscu reset acronym definition 7 ru 1?b0 (rs232datardy) rs232 data ready: after firmware write asci data to the rs232wrport, the hardware will set this bit to indicate that the rs232wrport (reg 0x00e7) is occupied, and firmware should wait until this bit is cleared by hardware (after rs232wrport send out its data) before try to write next data to rs232wrport. the firmware should check this bit, make sure it is 0 before write data to rs232wrport. 6-0 r 7?h0 reserved reserved 0x00e9 rs232 rdport (rs232rdport) bit(s) rscu reset acronym definition 7:0 r 8?h00 (rdrs232data[7:0]) rs232 read port data [7:0]: this register will latch the data which echos back from the other end?s rs232. 0x00ea rs232 rdport status (rs232rdctrl) bit(s) rscu reset acronym definition 7 ru 1?b0 (rs232rdportsts) rs232rdport full/empty status: this bit will be set by hard- ware when incoming data is in rs232rdport. this bit will be cleared by hardware after the firmware read the data out from rs232rdport. 6-3 r 4?h0 reserved reserved 2 ru 1?b0 (startbiterr) start bit error: this bit this bit indicates ths incoming data has a start-bit error. 1 ru 1?b0 (stopbiterr) stop bit error: this bit this bit indicates ths incoming data has a stop-bit error. 0 ru 1?b0 (paritybiterr) parity bit error: this bit this bit indicates ths incoming data has a parity-bit error. 0x00eb: timer_count [7:0] (timercnt[7:0]) bit(s) rscu reset acronym definition 7:0 rw 8?h00 (timercnt[7:0]) timer count [7:0]: wr: timer_count[7:0] rd: will read out the ?current_timer_count[7:0]?, value after reset is 8?hff.
section 4 register descriptions INIC-2430 data sheet confidential 51 0x00ec: timer_count [15:8] (timercnt[15:8]) 7:0 rw 8?h00 (timercnt[15:8]) timer count [15:8]: wr: timer_count[15:8] rd: will read out the ?current_timer_count[15:8]?, value after reset is 8?hff. the unit of timer count is 125us. for example: timer_count[15:0] with a value of 0x000a means 1250us to timeout. a value of timer_count[15:0] = 0will disable the timer. timer_count[15:0] value after reset: 16?h0000 current_timer_count[15:0] value after reset: 16?hffff when timeout occurs, it will automatically set the timeout bit (register 0xed bit 0), and optionally generate the sysint to the cpu (if register 0xed bit 1 is set). also, the timer will automatically reload the timer_count[15:0] and start the count down again. 0x00ed: timer timeout (timertimeout) bit(s) rscu reset acronym definition 7 rw 1?b0 (timer_sim) timer simulation: this bit when set enables the timer simulation using a much faster clock. (this bit is for internal use only.) 6 r 1?b0 reserved reserved 5:4 rw 2?b0 (waitdly) wait delay: insert delay after an incoming resp packet. 00: no delay 01: 5 us 10: 10 us 11: 20 us 3-1 r 3?h0 reserved reserved 0 rwu 1?b0 (timeout) timeout: timeout status when read (wr 1 to clear status). 0x00f0 wait state cpu r/w reg (wait_state_arm_r/w_reg) bit(s) rscu reset acronym definition 7:4 rw 4?hf (ws_cpu_rd_reg) wait state for cpu to access internal registers/buffers/sram (rd cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 3:0 rw 4?hf (ws_cpu_wr_reg) wait state for cpu to access internal registers/buffers/sram (wr cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 0x00f1 wait state cpu r/w external sram (wait_state_arm_r/w_sram_ext) bit(s) rscu reset acronym definition 7:4 rw 4?hf (ws_cpu_rd_ext_sram) wait state for cpu to access external sram (rd cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states.
52 confidential INIC-2430 data sheet register descriptions section 4 3:0 rw 4?hf (ws_cpu_wr_ext_sram) wait state for cpu to access external sram (wr cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 0x00f2 wait state cpu r/w flash (wait_state_arm_r/w_flash) bit(s) rscu reset acronym definition 7:4 rw 4?hf (ws_cpu_rd_flash) wait state for cpu to access external flash (rd cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 3:0 rw 4?hf (ws_cpu_wr_flash) wait state for cpu to access external flash (wr cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 0x00f3 wait state cpu r/w internal sram (wait_state_arm_r/w_sram_int) bit(s) rscu reset acronym definition 7:4 rw 4?hf (ws_cpu_rd_int_sram) wait state for cpu to access internal sram (rd cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 3:0 rw 4?hf (ws_cpu_wr_int_sram) wait state for cpu to access internal sram (wr cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 0x00f4 wait state cpu r/w internal buffers (wait_state_arm_r/w_int_buffers) bit(s) rscu reset acronym definition 7:4 rw 4?hf (ws_cpu_rd_int_buffers) wait state for cpu to access internal buffers (rd cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 3:0 rw 4?hf (ws_cpu_wr_int_buffers) wait state for cpu to access internal buffers (wr cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 0x00f5 wait state cpu r/w link (wait_state_arm_r/w_link) bit(s) rscu reset acronym definition 7:4 rw 4?hf (ws_cpu_rd_link_buffers) wait state for cpu to access link registers (rd cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states. 3:0 rw 4?hf (ws_cpu_wr_link_buffers) wait state for cpu to access link registers (wr cycle). the value defines the number of wait states. for example: a value of 0x5 means 5 wait states (minimum value should be > 2).
section 4 register descriptions INIC-2430 data sheet confidential 53 0x00f6-0x00ff reserved 0x0100-0x010f reserved 0x0110: set sg run (sgrun_set) 0x0111: clr sg run (sgrun_clr) bit(s) rscu reset acronym definition 7-5 r 3?h0 reserved reserved 4 rw 1?b0 (wait_for_dmarq) wait for dmarq: when set, there will be a wait until atadmarq asserted to send out rdreq packet. 3 rwu 1?b0 (sg3run) sg run bits 3-0: when set register is set by software, the correspond 2 rwu 1?b0 (sg2run) ing channel is ready to be transmitted. the hardware clears the run bit 1 rwu 1?b0 (sg1run) when the transfer of the corresponding channel is completed or completed 0 rwu 1?b0 (sg0run) with error. software can set one of bit[3:0] on clear register to clear the corresponding bit. 0x0112: clr sg error/clear (sgerr_clr) bit(s) rscu reset acronym definition 7 w 1?b0 (sgchrst) sg channel reset: writing a 1 to this bit will reset the dma chan- nel, and the state machine will be reset to idle. 6-4 r 3?h0 reserved reserved 3 rwu 1?b0 (sg3error) sg error bits 3-0: when hardware detects an interrupt or an error, 2 rwu 1?b0 (sg2error) these bits will be set. software should read the intevent register to deter- 1 rwu 1?b0 (sg1error) mine the problem and set one of bits [3:0] on the clear register to clear the 0 rwu 1?b0 (sg0error) corresponding error bit. 0x0113: clr sg retry exceeded/clear (sgrtryexcd_clr) bit(s) rscu reset acronym definition 7 rw 1?b0 (infinite_retry) infininte retry: writing a 1 to this bit will enable the infinite_retry mode, which will prevent the generation of retryexceeded. 6 rw 1?b0 (resend_rdresp) resend rdresp: when 0, if rereqevent occurs, hardware will re-gen- erate rdreq packet to request the same packet again. when 1, if rereqevent occurs, hardware assumes the source node will re- send the rdresp packet. 5-4 r 2?h0 reserved reserved 3 rwu 1?b0 (sg3rtryexcd) sg retry exceeded bits 3-0: reading these bits returns the bit 2 rwu 1?b0 (sg2rtryexcd) status. writing a 1 to these bits clears the bits. 1 rwu 1?b0 (sg1rtryexcd) 0 rwu 1?b0 (sg0rtryexcd) 0x0114-0x0117 reserved
54 confidential INIC-2430 data sheet register descriptions section 4 0x0118: set command tx run (cmdtxrun_set) 0x0119: clr command tx run (cmdtxrun_clr) bit(s) rscu reset acronym definition 7-6 r 2?b0 reserved reserved 5 rwu 1?b0 (cmdtx5run) command transfer run bits 5-0: the set register is set by 4 rwu 1?b0 (cmdtx4run) software and cleared by hardware when transfer of the corresponding 3 rwu 1?b0 (cmdtx3run) channel is completed or completed with error. when the clear register is 2 rwu 1?b0 (cmdtx2run) set by software, the corresponding command transmit out channel is reset. 1 rwu 1?b0 (cmdtx1run) cmdtx0 (lun0) and cmdtx2 (lun1) are used for requesting orb. 0 rwu 1?b0 (cmdtx0run) cmdtx1 (lun0) and cmdtx3 (lun1) are used for sending status. cmdtx4, 5 are for general purposes. 0x011a: clr command tx error/clear (cmdtxerr_clr) bit(s) rscu reset acronym definition 7-6 r 2?b0 reserved reserved 5 rwu 1?b0 (cmdtx5err) command transfer error bits 5-0: when one of these bits are 4 rwu 1?b0 (cmdtx4err) set by hardware, it indicates that the transaction of the corresponding 3 rwu 1?b0 (cmdtx3err) channel is failed. when the bit is set by software, the corresponding 2 rwu 1?b0 (cmdtx2err) error bit will be cleared. 1 rwu 1?b0 (cmdtx1err) 0 rwu 1?b0 (cmdtx0err) 0x011b: clr command tx retry exceeded/clear (cmdtxrtryexcd_clr) bit(s) rscu reset acronym definition 7-6 r 2?b0 reserved reserved 5 rwu 1?b0 (cmdtx5rtryexcd) command transfer retry exceeded bits 5-0: reading 4 rwu 1?b0 (cmdtx4rtryexcd) these bits returns the bit status. writing a 1 to these bits clears the bits. 3 rwu 1?b0 (cmdtx3rtryexcd) 2 rwu 1?b0 (cmdtx2rtryexcd) 1 rwu 1?b0 (cmdtx1rtryexcd) 0 rwu 1?b0 (cmdtx0rtryexcd) 0x011c: command tx channel reset (cmdtxchrst) bit(s) rscu reset acronym definition 7-6 r 2?b0 reserved reserved 5 rwu 1?b0 (cmdtx5chrst) command transfer channel reset bits 5-0: reading 4 rwu 1?b0 (cmdtx4chrst) these bits returns cmdtxerr (same as read register 0x011a). writing a 3 rwu 1?b0 (cmdtx3chrst) 1 to these bits will reset the corresponding channel to the idle state. 2 rwu 1?b0 (cmdtx2chrst) 1 rwu 1?b0 (cmdtx1chrst) 0 rwu 1?b0 (cmdtx0chrst)
section 4 register descriptions INIC-2430 data sheet confidential 55 0x011d: clr command tx 2/0 busy status (cmdtx2/0_busy) bit(s) rscu reset acronym definition 7-2 r ?h0 reserved reserved 1 rwu 1?b0 (cmdtx2_busy) cmdtx2 busy: reading this bit reads cmdtx2_busy status. write a ?1? to this bit clear cmdtx2_busy. 0 rwu 1?b0 (cmdtx0_busy) cmdtx0 busy: reading this bit reads cmdtx0_busy status. write a ?1? to this bit clear cmdtx0_busy. note: any of the following conditions will set cmdtx2_busy to 1: 1. cmdtx2run bit is set or 2. incoming wrreq packet is an orb_ptr or faststart to lun1. any of the following conditions will set cmdtx0_busy to ?1?: 1. cmdtx0run bit is set or 2. incoming wrreq packet is an orb_ptr or faststart to lun0. note: once these bits are set, any further faststart will be treated as a doorbell (will set doorbell (bit 4), not faststart (bit 6), in registers 0x00b7h, 0x00b8h). these busy bits can only be cleared by writing 1 to the corresponding bit of this register. 0x011e: clr command rx active (cmdrxactive_clr) bit(s) rscu reset acronym definition 7- 3 r 5? h0 reserved reserve d 2 r 1?b0 (rx_to_be_handled) cmdrxbuffer select: this bit indicates which cmdrxbuffer has the older incoming packet, and should be handled by firmware first (this bit is read only ). when ?0?, the firmware should handle cmdrx0 first, and when ?1?, the firmware should handle cmdrx1 first. this bit will be cleared when cmdrx1active (bit 1) is cleared. 1 rwu 1?b0 (cmdrx1active) cmdrx1, 0 active: when these bits are set by hardware, they indicate 0 rwu 1?b0 (cmdrx0active) that data is available in the corresponding cmdrx buffer. when these bits are set by software, the corresponding command rx channel is reset. write a ?1? to clear each of these bits. 0x011f reserved 0x0120: ack retry enable (ackrtry_en) bit(s) rscu reset acronym definition 7 rw 1?b0 (ack_adrerr_rtryen) ack address error retry enable: write a 1 to enable an ack_adrerr to trigger a retry. 6 rw 1?b1 (ack_typeerr_rtryen) ack type error retry enable: write a 1 to enable an ack_typeerr to trigger a retry.
56 confidential INIC-2430 data sheet register descriptions section 4 5 rw 1?b1 (ack_dataerr_rtryen) ack data error retry enable: write a 1 to enable an ack_dataerr to trigger a retry. 4 rw 1?b0 (ack_cnflcterr_rtryen) ack conflict error retry enable: write a 1 to enable an ack_cnflcterr to trigger a retry. 3 rw 1?b0 (ack_trdy_rtryen) ack trdy retry enable: write a 1 to enable an ack_trdy to trigger a retry. 2 rw 1?b1 (ack_missing_rtryen) ack missing retry enable: write a 1 to enable an ack_missing to trigger a retry. 1-0 r 2?b0 reserved reserved 0x0121: rcode retry enable (rcodertry_en) bit(s) rscu reset acronym definition 7 rw 1?b0 (rcode_adrerr_rtryen) rcode address error retry enable: write a 1 to enable an rcode_adrerr to trigger a rereqevent. 6 rw 1?b1 (rcode_typeerr_rtryen) rcode type error retry enable: write a 1 to enable an rcode_typeerr to trigger a rereqevent. 5 rw 1?b1 (rcode_dataerr_rtryen) rcode data error retry enable: write a 1 to enable an rcode_dataerr to trigger a rereqevent. 4 rw 1?b0 (rcode_cnflcterr_rtryen) rcode conflict error retry enable: write a 1 to enable an rcode_cnflcterr to trigger a rereqevent. 3 rw 1?b1 (splittimeouten) split timeout enable: write a 1 to enable a splittimeout to trigger a rereqevent. 2 rw 1?b1 (datacrcerr_rtryen) data crc error retry enable: write a 1 to enable a datacrcerr to trigger a rereqevent. 1 rw 1?b1 (hdrcrcerr_rtryen) hardware crc error retry enable: write a 1 to enable an hdrcrcerr to trigger a rereqevent. 0 r 1?b0 reserved reserved: this bit is for manufacturing use only. 0x0122: rereq channel enable (rereq_ch_en) bit(s) rscu reset acronym definition 7 rw 1?b1 (en_rereqsg) sg channel resend enable: write a 1 to enable the sg channel to re-send the previous request packet if an rereqevent occurs. 6 r 1?b1 reserved reserved 5 rw 1?b1 (en_rereqtx5) cmdtx5 channel resend enable: write a 1 to enable the cmdtx5 channel to re-send the previous request packet if an rereqevent occurs. 4 rw 1?b1 ( en_rereqtx4 ) cmdtx4 channel resend enable: write a 1 to enable the cmdtx4 channel to re-send the previous request packet if an rereqevent occurs. 3 rw 1?b1 (en_rereqtx3) cmdtx3 channel resend enable: write a 1 to enable the cmdtx3 channel to re-send the previous request packet if an rereqevent occurs. 2 rw 1?b1 (en_rereqtx2) cmdtx2 channel resend enable: write a 1 to enable the cmdtx2 channel to re-send the previous request packet if an rereqevent occurs.
section 4 register descriptions INIC-2430 data sheet confidential 57 1 rw 1?b1 (en_rereqtx1) cmdtx1 channel resend enable: write a 1 to enable the cmdtx1 channel to re-send the previous request packet if an rereqevent occurs. 0 rw 1?b1 (en_rereqtx0) cmdtx0 channel resend enable: write a 1 to enable the cmdtx0 channel to re-send the previous request packet if an rereqevent occurs. 0x0123-0x012f reserved 0x0130: rcode / rcode (rcode/tcode) bit(s) rscu reset acronym definition 7-4 r 4?h0 (tcode[3:0]) tcode [3:0]: these bits indicate the latest incoming packet?s tcode value. 3-0 r 4?h0 (rcode[3:0]) rcode [3:0]: these bits indicate the latest incoming packet?s rcode value. 0x0131-0x013f reserved 0x0140: interrupt 0 status (int0_status) a read each of these bits returns the status of that bit. a write to a bit clears that bit. bit(s) rscu reset acronym definition 7 ruw 1?b0 (busrst_int) bus reset interrupt: busrst_int status from link. 6 rwu 1?b0 (rxdatardy_int) rxdatardy interrupt: rxdatardy_int status from rs232 when incoming rs232 data is ready. 5 rwu 1?b0 (wakeup_int) wakeup interrupt: wakeup_int status from the power management logic. 4 rwu 1?b0 ( timeout_int ) timeout interrupt: timeout_int status from the timer. 3 rwu 1?b0 (sg3rtryexcd_int) sg3 retry exceeded interrupt: sg3rtryexcd_int status from sg3 channel. 2 rwu 1?b0 (sg2rtryexcd_int) sg2 retry exceeded interrupt: sg2rtryexcd_int status from sg2 channel. 1 rwu 1?b0 (sg1rtryexcd_int) sg1 retry exceeded interrupt: sg1rtryexcd_int status from sg1 channel. 0 rwu 1?b0 (sg0rtryexcd_int) sg0 retry exceeded interrupt: sg0rtryexcd_int status from sg0 channel. 0x0141: interrupt 1 status (int1_status) a read each of these bits returns the status of that bit. a write to a bit clears that bit. bit(s) rscu reset acronym definition 7 rwu 1?b0 (cmdrx1actv_int) cmdrx1actv interrupt: cmdrx1actv_int status from cmdrx1 channel. 6 rwu 1?b0 (cmdrx0actv_int) cmdrx0actv interrupt: cmdrx0actv_int status from cmdrx0 channel.
58 confidential INIC-2430 data sheet register descriptions section 4 5 rwu 1?b0 (cmdtx5rtryexcd_int) cmdtx5 retry exceeded interrupt: cmdtx5 rtryexcd_int status from cmdtx5 channel. 4 rwu 1?b0 (cmdtx4rtryexcd_int) cmdtx4 retry exceeded interrupt: cmdtx4 rtryexcd_int status from cmdtx4 channel. 3 rwu 1?b0 (cmdtx3rtryexcd_int) cmdtx3 retry exceeded interrupt: cmdtx3 rtryexcd_int status from cmdtx3 channel. 2 rwu 1?b0 (cmdtx2rtryexcd_int) cmdtx2 retry exceeded interrupt: cmdtx2 rtryexcd_int status from cmdtx2 channel. 1 rwu 1?b0 (cmdtx1rtryexcd_int) cmdtx1 retry exceeded interrupt: cmdtx1 rtryexcd_int status from cmdtx1 channel. 0 rwu 1?b0 (cmdtx0rtryexcd_int) cmdtx0 retry exceeded interrupt: cmdtx0 rtryexcd_int status from cmdtx0 channel. 0x0142: interrupt 2 status (int2_status) a read each of these bits returns the status of that bit. a write to a bit clears that bit. bit(s) rscu reset acronym definition 7 rwu 1?b0 (heartbeat0_int) heartbeat 0 interrupt: heartbeat0_int status. 6 rwu 1?b0 (faststart0_int) faststart0 interrupt: faststart0_int status. 5 rwu 1?b0 (usn0_int) usn0 interrupt: usn0_int status. 4 rwu 1?b0 ( doorbell0_int ) doorbell0 interrupt: doorbell0_int status. 3 rwu 1?b0 (gpio0_int) gpio0 interrupt: gpio0_int status. 2 rwu 1?b0 (orb_ptr0_int) orb_ptr0 interrupt: orb_ptr0 _int status. 1 rwu 1?b0 (agent0rst_int) agent0 reset interrupt: agent0rst _int status. 0 rwu 1?b0 (agent0state_int) agent0 state interrupt: agent0state _int status. 0x0143: interrupt 3 status (int3_status) a read each of these bits returns the status of that bit. a write to a bit clears that bit. bit(s) rscu reset acronym definition 7 rwu 1?b0 (heartbeat1_int) heartbeat 1 interrupt: heartbeat1_int status. 6 rwu 1?b0 (faststart1_int) faststart 1 interrupt: faststart1_int status. 5 rwu 1?b0 (usn1_int) usn 1 interrupt: usn1_int status. 4 rwu 1?b0 ( doorbell1_int ) doorbell 1 interrupt: doorbell1_int status. 3 rwu 1?b0 ( linkon_ int) link on i nterrupt: linkon_ int status. 2 rwu 1?b0 (orb_ptr1_int) orb_ptr 1 interrupt: orb_ptr1 _int status. 1 rwu 1?b0 (agent1rst_int) agent1 reset interrupt: agent1rst _int status. 0 rwu 1?b0 (agent1state_int) agent1 state interrupt: agent1state _int status. 0x0144-0x014f reserved
section 4 register descriptions INIC-2430 data sheet confidential 59 0x0150: interrupt 0 enable (int0_enable) writing a 1 to a bit enables that bit?s interrupt while writing a 0 to the bit masks that bit. a read of each of these bits returns the status of each bit. bit(s) rscu reset acronym definition 7 rw 1?b0 (busrst_int_en) bus reset interrupt enable: busrst_int enable. 6 rw 1?b0 (rxdatardy_int_en) rxdatardy interrupt enable: rxdatardy_int enable. 5 rw 1?b0 (wakeup_int_en) wakeup interrupt enable : wakeup_int enable. 4 rw 1?b0 ( timeout_int_en ) timeout interrupt enable : timeout_int enable. 3 rw 1?b0 (sg3rtryexcd_int_en) sg3 retry exceeded interrupt enable : sg3rtryexcd_int enable. 2 rw 1?b0 (sg2rtryexcd_int_en) sg2 retry exceeded interrupt enable : sg2rtryexcd_int enable. 1 rw 1?b0 (sg1rtryexcd_int_en) sg1 retry exceeded interrupt enable : sg1rtryexcd_int enable. 0 rw 1?b0 (sg0rtryexcd_int_en) sg0 retry exceeded interrupt enable : sg0rtryexcd_int enable. 0x0151: interrupt 1 enable (int1_enable) writing a 1 to a bit enables that bit?s interrupt while writing a 0 to the bit masks that bit. a read of each of these bits returns the status of each bit. bit(s) rscu reset acronym definition 7 rw 1?b0 (cmdrx1actv_int_en) cmdrx1actv interrupt enable: cmdrx1actv_int enable. 6 rw 1?b0 (cmdrx0actv_int_en) cmdrx0actv interrupt enable: cmdrx0actv_int enable. 5 rwu 1?b0 (cmdtx5rtryexcd_int_en) cmdtx5 retry exceeded interrupt enable : cmdtx5 rtryexcd_int enable. 4 rw 1?b0 (cmdtx4rtryexcd_int_en) cmdtx4 retry exceeded interrupt enable : cmdtx4 rtryexcd_int enable. 3 rw 1?b0 (cmdtx3rtryexcd_int_en) cmdtx3 retry exceeded interrupt enable : cmdtx3 rtryexcd_int enable. 2 rw 1?b0 (cmdtx2rtryexcd_int_en) cmdtx2 retry exceeded interrupt enable : cmdtx2 rtryexcd_int enable. 1 rw 1?b0 (cmdtx1rtryexcd_int_en) cmdtx1 retry exceeded interrupt enable : cmdtx1 rtryexcd_int enable. 0 rw 1?b0 (cmdtx0rtryexcd_int_en) cmdtx0 retry exceeded interrupt enable : cmdtx0 rtryexcd_int enable.
60 confidential INIC-2430 data sheet register descriptions section 4 0x0152: interrupt 2 enable (int2_enable) writing a 1 to a bit enables that bit?s interrupt while writing a 0 to the bit masks that bit. a read of each of these bits returns the status of each bit. bit(s) rscu reset acronym definition 7 rw 1?b0 (heartbeat0_int_en) heartbeat 0 interrupt enable: heartbeat0_int enable. 6 rw 1?b0 (faststart0_int_en) faststart0 interrupt enable: faststart0_int enable. 5 rw 1?b0 (usn0_int_en) usn0 interrupt enable : usn0_int enable. 4 rw 1?b0 ( doorbell0_int_en ) doorbell0 interrupt enable : doorbell0_int enable. 3 rw 1?b0 (gpio0_int_en) gpio0 interrupt enable : gpio0_int enable. 2 rw 1?b0 (orb_ptr0_int_en) orb_ptr0 interrupt enable : orb_ptr0 _int enable. 1 rw 1?b0 (agent0rst_int_en) agent0 reset interrupt enable : agent0rst _int enable. 0 rw 1?b0 (agent0state_int_en) agent0 state interrupt enable : agent0state _int enable. 0x0153: interrupt 3 enable (int3_enable) writing a 1 to a bit enables that bit?s interrupt while writing a 0 to the bit masks that bit. a read of each of these bits returns the status of each bit. bit(s) rscu reset acronym definition 7 rw 1?b0 (heartbeat1_int_en) heartbeat 1 interrupt enable: heartbeat1_int enable. 6 rw 1?b0 (faststart1_int_en) faststart 1 interrupt enable: faststart1_int enable. 5 rw 1?b0 (usn1_int_en) usn 1 interrupt enable : usn1_int enable. 4 rw 1?b0 ( doorbell1_int_en ) doorbell 1 interrupt enable : doorbell1_int enable. 3 rw 1?b0 ( linkon_ int_en) link on i nterrupt enable : linkon_ int enable. 2 rw 1?b0 (orb_ptr1_int_en) orb_ptr 1 interrupt enable : orb_ptr1 _int enable. 1 rw 1?b0 (agent1rst_int_en) agent1 reset interrupt enable : agent1rst _int enable. 0 rw 1?b0 (agent1state_int_en) agent1 state interrupt enable : agent1state _int enable. 0x0154: trailer 0 byte 0 (trailer0_byte0) the bits in this register are read only . bit(s) rscu reset acronym definition 7-0 r 8?h0 (time0stamp00) trailer 0 quadlet byte 0: read the incoming packet?s trailer 0 quadlet?s byte 0. the incoming packet itself is put into cmdrx0buffer. 0x0155: trailer 0 byte 1 (trailer0_byte1) the bits in this register are read only . bit(s) rscu reset acronym definition 7-0 r 8?h0 (time0stamp01) trailer 0 quadlet byte 1: read the incoming packet?s trailer 0 quadlet?s byte 1. the incoming packet itself is put into cmdrx0buffer.
section 4 register descriptions INIC-2430 data sheet confidential 61 0x0156: trailer 0 byte 2 (trailer0_byte2) the bits in this register are read only . bit(s) rscu reset acronym definition 7-0 r 8?h0 (time0stamp10) trailer 0 quadlet byte 2: read the incoming packet?s trailer 0 quadlet?s byte 2. the incoming packet itself is put into cmdrx0buffer. 0x0157: trailer 0 byte 3 (trailer0_byte3) the bits in this register are read only . bit(s) rscu reset acronym definition 7-0 r 8?h0 (time0stamp11) trailer 0 quadlet byte 3: read the incoming packet?s trailer 0 quadlet?s byte 3. the incoming packet itself is put into cmdrx0buffer. 0x0158: trailer 1 byte 0 (trailer1_byte0) the bits in this register are read only . bit(s) rscu reset acronym definition 7-0 r 8?h0 (time1stamp00) trailer 1 quadlet byte 0: read the incoming packet?s trailer 1 quadlet?s byte 0. the incoming packet itself is put into cmdrx1buffer. 0x0159: trailer 1 byte 1 (trailer1_byte1) the bits in this register are read only . bit(s) rscu reset acronym definition 7-0 r 8?h0 (time1stamp01) trailer 1 quadlet byte 1: read the incoming packet?s trailer 1 quadlet?s byte 1. the incoming packet itself is put into cmdrx1buffer. 0x015a: trailer 1 byte 2 (trailer1_byte2) the bits in this register are read only . bit(s) rscu reset acronym definition 7-0 r 8?h0 (time1stamp10) trailer 1 quadlet byte 2: read the incoming packet?s trailer 1 quadlet?s byte 2. the incoming packet itself is put into cmdrx1buffer. 0x015b: trailer 1 byte 3 (trailer1_byte3) the bits in this register are read only . bit(s) rscu reset acronym definition 7-0 r 8?h0 (time1stamp11) trailer 1 quadlet byte 3: read the incoming packet?s trailer 1 quadlet?s byte 3. the incoming packet itself is put into cmdrx1buffer.
62 confidential INIC-2430 data sheet register descriptions section 4 0x015c: miscellanous enable (miscen) the bits in this register are reserved . bit(s) rscu reset acronym definition 7-0 rw 8?h03 reserved reserved: these bits are used for internal testing purposes and are reserved. 0x015d-0x015f reserved 0x0160-0x016f reserved 0x0170: split timer lo (split_timer_l) bit(s) rscu reset acronym definition 7-0 w 8?h0 (split_timer_l) split timer [7:0]: bits 7-0 of split_timer[15:0]. split_timer[15:0] specifies the timeout value. if the request packet has received ack_pending and waits for more than the time duration specified by split_timer[15:0] without receiving its response packet, a split_timeout event will occur, which will t rigger the hardware to re-send the request packet. the resolution is 125us, a value of split_timer[15:0] = 16?h0005 means 5x 125us = 575us. a value of 16?h0000 will disable this timer, and will not generate any split_timer event. 0x0171: split timer hi (split_timer_h) bit(s) rscu reset acronym definition 7-0 w 8?h0 (split_timer_h) split timer [15:8]: bits 15-8 of split_timer[15:0]. split_timer[15:0] specifies the timeout value. if the request packet has received ack_pending and waits for more than the time duration specified by split_timer[15:0] without receiving its response packet, a split_timeout event will occur, which will trigger the hardware to re-send the request packet. the resolution is 125us, a value of split_timer[15:0] = 16?h0005 means 5x 125us = 575us. a value of 16?h0000 will disable this timer, and will not generate any split_timer event.
INIC-2430 data sheet confidential 63 section 5 electrical specifications 5.1 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.2 recommended operating conditions ta = 0 c to + 115 c v cc_3.3 = 3.3v 5% v cc_2.5 = 2.5 v 5% gnd = 0v table 5-1 absolute maximum ratings parameter minimum maximum units environment storage temperature -40 150 c operating temperature 0 115 c esd immunity 2.0 kv human model voltage levels i/o logic power supply (3.3v) -0.3 3.9 v core logic power supply (2.5v) -0.3 3.0 v inputs -0.3 vcc+0.3 v outputs -0.3 vcc+0.3 v table 5-2 device recommended operating conditions symbol parameter minimum typical maximum units vcc_3.3 i/o logic supply voltage 3. 0 3. 3 3.6 v vcc_2.5 core logic supply voltage 2.25 2.5 2.75 v t j commercial junction operating temperature 0 25 115 c t j in dustrial junction operating temperature -40 25 125 c confidential
64 confidential INIC-2430 data sheet electrical specifications section 5 5.3 general dc characteristics ta = 0 c to +115 c v cc_3.3 = 3.3v 5% v cc_2.5 = 2.5 v 5% gnd = 0v 5.4 dc electrical characteristics for normal operation ta = 0 c to +115 c v cc = 3.3v 5% v cc_2.5 = 2.5 v 5% gnd = 0v table 5-3 general dc characteristics symbol parameter minimum typical maximum units i il input leakage current -10 - 10 m a i oz tri-state leakage current -10 - 10 m a c in input capacitance 3.1 pf c out output capacitance 2.7 3.1 4.9 pf c bid bi-directional buffer capacitance 2.7 3.1 4.9 pf table 5-4 dc electrical characteristics for normal operation symbol parameter conditions minimum typical maximum units v il input low voltage cmos 0.3*vcc v v ih input high voltage cmos 0.7*vcc v v ol output low voltage i oh = 2-24 ma 0.4 v v oh output high voltage i oh = 2-24 ma 2.4 v ri input pull up/down resistance v il = 0 / v ih = vcc 40 75 190 k w i cc operating supply current vcc = 3.3v vcc_2.5 = 2.5v 30 50 ma
INIC-2430 data sheet confidential 65 section 6 timing specifications 6.1 1394 link to phy interface figure 6-1 phy to link interface figure 6-2 link to phy interface symbol parameter minimum maximum units t psu ctl and d setup time to phy pclk 2 - ns t ph ctl and d hold time after phy pclk 2 - ns t lsu delay time of driving ctl and d from phy l clk 1 . 5 2 .9 ns t lh delay time of driving ctl and d after phy l clk 1 . 5 2 .9 ns t lhz delay time of driving ctl and d to high z 1.5 2.9 ns t psu t ph phy pclk d, ctl valid t lh t lhz d, ctl, t lsu lreq valid phy lclk INIC-2430 data sheet confidential
66 confidential INIC-2430 data sheet timing specifications section 6 6.2 flash / memory interface 6.2.1 flash memory read cycle figure 6-3 flash memory read cycle symbol parameter minimum maximum units t pa phypclk to ua address valid time 7.0 9.0 ns t pf phypclk to flashrd active time 5.5 8.0 ns t pn phypclk to flashrd negated time 5.5 8.0 ns t pd phypclk to ud read data valid time see flash memory spec ns t fd ud read data hold time from flashrd negated see flash memory spec ns rd data ud flashrd# ua phypclk t fd t pf t pn t pa t pd
section 6 timing specifications INIC-2430 data sheet confidential 67 6.2.2 flash memory write cycle figure 6-4 flash memory write cycle symbol parameter minimum maximum units t pa phypclk to ua address valid time 7 . 0 9.0 ns t pf phypclk to flashwr active time 5.5 8.0 ns t pn phypclk to flashwr negated time 5.5 8.0 ns t pw phypclk to ud write data valid time 0 1.0 ns t pwh phypclk to ud write data hold time 6.0 9.0 ns wr data ud flashwr# ua phypclk t pw t pf t pn t pa t pwh
68 confidential INIC-2430 data sheet timing specifications section 6 6.2.3 external sram read cycle figure 6-5 external sram read cycle symbol parameter minimum maximum units t pa phypclk to ua address valid time 7.0 9.0 ns t ps phypclk to extsramrd active time 4.9 7.4 ns t pn phypclk to extsramrd negated time 5.0 7.5 ns t pd phypclk to ud read data valid time see sram memory spec ns t ds ud read data hold time from extsramrd negated see sram memory spec ns rd data ud extsramrd# ua phypclk t ds t ps t pn t pa t pd
section 6 timing specifications INIC-2430 data sheet confidential 69 6.2.4 external sram write cycle figure 6-6 external sram write cycle symbol parameter minimum maximum units t pa phypclk to ua address valid time 7.0 9.0 ns t ps phypclk to extsramwr active time 5.4 8.1 ns t pn phypclk to extsramwr negated time 5.5 8.3 ns t pw phypclk to ud write data valid time 1.6 2.4 ns t pwh phypclk to ud write data hold time 6.0 9.0 ns wr data ud extsramwr# ua phypclk t pw t ps t pn t pa t pwh
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INIC-2430 data sheet confidential 71 section 7 packaging specifications 7.1 INIC-2430 lqfp packaging specifications figure 7-1 shows the physical outline of the 144-pin lqfp package. table 7-1 shows the package?s dimensions. figure 7-1 144 pin lqfp package outline seating plane a d 1 d pin 1 b base metal with plating lead cross-section e 1 e e see detail a all tips a a a c a-b d b b b h a-b d 4x . . . . . . c c c - c - c d d d s m s a-b c d . . . . . . . . . - a - - d - - b - a 1 l a 2 l1 detail a - c - gauge plane 0.25 - h - d 2 e 2 confidential
72 confidential INIC-2430 data sheet packaging specifications section 7 *notes: 1. reference documents: jedec ms-026 faraday dwg no. lq144-20x20-01 2. controlling dimensions are in millimeters (mm). 2. the top package body size may be smaller than the bottom package body size by as much as 0.15 mm. 3. datums a-b and -d- to be determined at datum plane -h-. 4. reference plane -h- is located at mold parting line and is coincident with bottom of lead where it exits plastic body. 5. dimensions d and e to be determined at seating plane -c-. 6. dimensions d1 and e1 do not include mold protrusion. allowable protru- sion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. dimension b does not include dambar protrusion. allowable dambar pro- trusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm. 8. the dimensions shown in lead cross-section apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 9. dimension a1 is defined as the distance from the seating plane to the lowest point of the package body. 10. solder plate thickness shall be 200 microinches minimum. table 7-1 144-pin lqfp package dimensions mm inch symbol min nom max min nom max a - - - - - - 1.60 - - - - - - 0.063 a1 0.05 - - - - - - 0.002 - - - - - - a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.12 - - - 0.20 0.005 - - - 0.008 d 21.85 22.00 22.15 0.860 0.866 0.872 d1 19.90 20.00 20.10 0.783 0.787 0.791 e 21.85 22.00 22.15 0.860 0.866 0.872 e1 19.90 20.00 20.10 0.783 0.787 0.791 e 0.50 bsc 0.020 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 bsc 0.039 bsc ? 0 deg 3.5 deg 7 deg 0 deg 3.5 deg 7 deg aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.07 0.003
section 7 packaging specifications INIC-2430 data sheet confidential 73 7.2 INIC-2430 tfbga packaging specifications figure 7-2 shows the physical outline of the 144-pin tfbga package. table 7-2 shows the package?s dimensions. figure 7-2 144-pin tfbga package outline d1 e1 ddd z bbb z a3 a2 a1 a e b 3 eee fff m m z z x y a b c d e f g j k l m h 1 2 3 4 5 6 7 8 9 10 11 12 z d e notes: 1. 2. dimensioning and tolerancing per asme y14.5m-1994. all dimensions in mm. 3. solder balls are typically 63/37 tin lead. 4. referance document: jedec code mo-216. 5. primary datum z and seating plane are defined by the spherical crowns of the solder balls. 6. the pattern of pin 1 fiducial is for reference only. 7. there shall be a minimum clearance of 0.25mm between the edge of the solder ball and the body edge. 8. dimension b is measured at the maximum solder ball diameter, parallel to primary datum z. aaa aaa
74 confidential INIC-2430 data sheet packaging specifications section 7 *notes: 1. reference documents: jedec mo-216 faraday dwg no. tf144-13x13-01 2. controlling dimensions are in millimeters (mm). 3. dimension a is defined as the distance from the seating plane to the high- est point of the package body. table 7-2 144-pin tfbga package dimensions mm inch symbol min nom max min nom max a - - - - - - 1.30 - - - - - - 0.051 a1 0.25 0.30 0.35 0.010 0.012 0.014 a2 0.84 0.89 0.94 0.033 0.035 0.037 a3 0.32 0.36 0.40 0.013 0.014 0.016 b 0.35 0.40 0.45 0.014 0.016 0.018 d 12.90 13.00 13.10 0.508 0.512 0.516 d1 - - - 11.00 - - - - - - 0.433 - - - e 12.90 13.00 13.10 0.508 0.512 0.516 e1 - - - 11.00 - - - - - - 0.433 - - - e - - - 1.00 - - - - - - 0.039 - - - aaa - - - 0.10 - - - - - - 0.004 - - - bbb - - - 0.10 - - - - - - 0.004 - - - ddd - - - 0.12 - - - - - - 0.005 - - - eee - - - 0.15 - - - - - - 0.006 - - - fff - - - 0.08 - - - - - - 0.003 - - -

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