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features applications description pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 16/20-bit single-ended analog input/output stereo audio codecs single 3-v power supply monolithic 20-bit d s adc and dac small package: ssop-24 16/20-bit input/output data software control: pcm3002 dvc applications hardware control: pcm3003 dsc applications stereo adc: portable/mobile audio applications ? single-ended voltage input ? antialiasing filter ? 64 oversampling the pcm3002 and pcm3003 are low-cost, ? high performance single-chip stereo audio codecs (analog-to-digital and digital-to-analog converters) with single-ended analog thd+n: ?86 db voltage input and output. snr: 90 db the adcs and dacs employ delta-sigma modulation dynamic range: 90 db with 64-times oversampling. the adcs include a stereo dac: digital decimation filter, and the dacs include an ? single-ended voltage output 8-times oversampling digital interpolation filter. the dacs also include digital attenuation, de-emphasis, ? analog low-pass filter infinite zero detection, and soft mute to form a ? 64 oversampling complete subsystem. the pcm3002 and pcm3003 ? high performance operate with left-justified (adc) and right-justified (dac) formats, while the pcm3002 also supports thd+n: ?86 db other formats, including the i 2 s data format. snr: 94 db the pcm3002 and pcm3003 provide a power-down dynamic range: 94 db mode that operates on the adcs and dacs indepen- special features (pcm3002, pcm3003) dently. ? digital de-emphasis: 32 khz, 44.1 khz, the pcm3002 and pcm3003 are fabricated using a 48 khz highly advanced cmos process, and are available in ? power down: adc/dac independent a 24-pin ssop package. the pcm3002 and special features (pcm3002) pcm3003 are suitable for a wide variety of cost-sensitive consumer applications where good per- ? digital attenuation (256 steps) formance is required. ? soft mute the pcm3002 programmable functions are controlled ? digital loopback by software. the pcm3003 functions, which are ? four alternative audio data formats controlled by hardware, include de-emphasis, sampling rate: 4 khz to 48 khz power-down, and audio data format selections. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. system two, audio precision are trademarks of audio precision, inc. all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2000?2004, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
lch in rch in analog front-end delta-sigma modulator digital decimation filter serial interface and mode control digital outmode control system clock b0006-01 digital in digital interpolation filter lch out rch out low-pass filter and output buffer multilevel delta-sigma modulator * * pcm3002 only
electrical characteristics pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. all specifications at t a = 25 c, v dd = v cc = 3 v, f s = 44.1 khz, sysclk = 384 f s , and 16-bit data, unless otherwise noted pcm3002e/3003e parameter conditions min typ max units digital input/output input logic v ih (1) (2) (3) 0.7 v dd input logic level vdc v il (1) (2) (3) 0.3 v dd i in (2) 1 input logic current m a i in (1) (3) 100 output logic v oh (4) i out = ?1 ma v dd ? 0.3 v ol (4) output logic level i out = 1 ma 0.3 vdc v ol (5) i out = 1 ma 0.3 clock frequency f s sampling frequency 4 (6) 44.1 48 khz 256 f s 1.024 11.2896 12.288 system clock frequency 384 f s 1.536 16.9344 18.432 mhz 512 f s 2.048 22.5792 24.576 adc characteristics resolution 20 bits dc accuracy gain mismatch, channel- 1 3 % of fsr to-channel gain error 2 5 % of fsr gain drift 20 ppm of fsr/ c bipolar zero error high-pass filter bypassed (7) 1.7 % of fsr bipolar zero drift high-pass filter bypassed (7) 20 ppm of fsr/ c dynamic performance (8) v in = ?0.5 db ?86 ?80 thd+n db v in = ?60 db ?28 dynamic range a-weighted 86 90 db signal-to-noise ratio a-weighted 86 90 db channel separation 84 88 db (1) pins 7, 8, 17 and 18: rst, ml, md, and mc for the pcm3002; pdad, pdda, dem1, and dem0 for pcm3003 (schmitt-trigger input with 100-k w typical internal pulldown resistor) (2) pins 9, 10, 11, 15: sysclk, lrcin, bckin, din (schmitt-trigger input) (3) pin 16: 20bit for pcm3003 (schmitt-trigger input, 100-k w typical internal pulldown resistor) (4) pin 12: dout (5) pin 16: zflg for pcm3002 (open-drain output) (6) see application bulletin sbaa033 for information relating to operation at lower sampling frequencies. (7) high-pass filter for offset cancel (8) f in = 1 khz, using the system two? audio measurement system by audio precision? in rms mode with 20-khz lpf, 400-hz hpf used for performance calculation. 2 www .ti.com
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 electrical characteristics (continued) all specifications at t a = 25 c, v dd = v cc = 3 v, f s = 44.1 khz, sysclk = 384 f s , and 16-bit data, unless otherwise noted pcm3002e/3003e parameter conditions min typ max units digital filter performance pass band 0.454 f s hz stop band 0.583 f s hz pass-band ripple 0.05 db stop-band attenuation ?65 db delay time 17.4/f s s hpf frequency response ?3 db 0.019 f s mhz analog input voltage range 0.6 v cc vp-p center voltage 0.5 v cc vdc input impedance 30 k w antialiasing filter frequency ?3 db 150 khz response dac characteristics resolution 20 bits dc accuracy gain mismatch, channel- 1 3 % of fsr to-channel gain error 1 5 % of fsr gain drift 20 ppm of fsr/ c bipolar zero error 2.5 % of fsr bipolar zero drift 20 ppm of fsr/ c dynamic performance (9) v out = 0 db (full scale) ?86 ?80 thd+n db v out = ?60 db ?32 dynamic range eiaj, a-weighted 88 94 db signal-to-noise ratio eiaj, a-weighted 88 94 db channel separation 86 91 db digital filter performance pass band 0.445 f s hz stop band 0.555 f s hz pass-band ripple 0.17 db stop-band attenuation ?35 db delay time 11.1/f s s analog output voltage range 0.6 v cc vp-p center voltage 0.5 v cc vdc load impedance ac coupling 10 k w lpf frequency response f = 20 khz ?0.16 db (9) f out = 1 khz, using the system two audio measurement system by audio precision in rms mode with 20-khz lpf, 400-hz hpf used for performance calculation. 3 www .ti.com
absolute maximum ratings pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 electrical characteristics (continued) all specifications at t a = 25 c, v dd = v cc = 3 v, f s = 44.1 khz, sysclk = 384 f s , and 16-bit data, unless otherwise noted pcm3002e/3003e parameter conditions min typ max units power supply requirements ?25 c to 85 c 2.7 3 3.6 vdc v cc , v dd supply voltage 0 c to 70 c (10) 2.4 3 3.6 vdc operation, v cc = v dd = 3 v 18 24 ma supply current power down, v cc = v dd = 3 v 50 m a operation, v cc = v dd = 3 v 54 72 mw power dissipation power down (11) , v cc = v dd = 150 m w 3 v temperature range t a operation ?25 85 c t stg storage ?55 125 c q ja thermal resistance 100 c/w (10) applies for voltages between 2.4 v and 2.7 v for 0 c to 70 c and 256 f s /512 f s operation (384 f s not available) (11) sysclk, bckin, and lrcin are stopped. package/ordering information package package package ordering transport product quantity type code marking number media pcm3002e rails 58 pcm3002e 24-pin ssop db pcm3002e pcm3002e/2k tape and reel 2000 pcm3003e rails 58 pcm3003e 24-pin ssop db pcm3003e pcm3003e/2k tape and reel 2000 supply voltage v dd , v cc 1, v cc 2 ?0.3 v to 6.5 v supply voltage differences 0.1 v gnd voltage differences 0.1 v digital input voltage ?0.3 v to v dd + 0.3 v, < 6.5 v analog input voltage ?0.3 v to v cc 1, v cc 2 + 0.3 v, < 6.5 v power dissipation 300 mw input current (any pins except supplies) 10 ma operating temperature ?25 c to 85 c storage temperature ?55 c to 125 c lead temperature, soldering 260 c, 5 s package temperature (ir reflow, peak) 235 c 4 www .ti.com
recommended operating conditions pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 over operating free-air temperature range min nom max unit analog supply voltage, v cc 1, v cc 2 2.7 3 3.6 v digital supply voltage, v dd 2.7 3 3.6 v analog input voltage, full scale (?0 db) v cc = 3 v 1.8 vp-p digital input logic family cmos system clock 8.192 24.576 mhz digital input clock frequency sampling clock 32 48 khz analog output load resistance 10 k w analog output load capacitance 30 pf digital output load capacitance 10 pf operating free-air temperature, t a ?25 85 c pin assignments?pcm3002 name pin i/o description agnd1 23 ? adc analog ground agnd2 22 ? dac analog ground bckin 11 i bit clock input (1) dgnd 13 ? digital ground din 15 i data input (1) dout 12 o data output lrcin 10 i sample rate clock input (f s ) (1) mc 18 i bit clock for mode control (1) (2) md 17 i serial data for mode control (1) (2) ml 8 i strobe pulse for mode control (1) (2) rst 7 i reset, active low (1) (2) sysclk 9 i system clock input (1) v cc 1 1, 2 ? adc analog power supply v cc 2 24 ? dac analog power supply v com 21 ? adc/dac common v dd 14 ? digital power supply (1) schmitt-trigger input (2) with 100-k w typical internal pulldown resistor 5 www .ti.com 12 3 4 5 6 7 8 9 10 1 1 12 2423 22 21 20 19 18 17 16 15 14 13 v c c 1 v c c 1 v i n r v r e f 1 v r e f 2 v i n l rst ml sysclk lrcin bckin dout v c c 2 agnd1agnd2 v c o m v o u t r v o u t l mcmd zflg dinv d d dgnd pcm3002 (t op view) p0004-02 12 3 4 5 6 7 8 9 10 1 1 12 2423 22 21 20 19 18 17 16 15 14 13 v c c 1 v c c 1 v i n r v r e f 1 v r e f 2 v i n l pdad pdda sysclk lrcin bckin dout v c c 2 agnd1agnd2 v c o m v o u t r v o u t l dem0dem1 20bit din v d d dgnd pcm3003 (t op view)
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 pin assignments?pcm3002 (continued) name pin i/o description v in l 6 i adc analog input, lch v in r 3 i adc analog input, rch v out l 19 o dac analog output, lch v out r 20 o dac analog output, rch v ref 1 4 ? adc reference 1 v ref 2 5 ? adc reference 2 zflg 16 o zero flag output, active low (3) (3) open-drain output pin assignments?pcm3003 name pin i/o description agnd1 23 ? adc analog ground agnd2 22 ? dac analog ground bckin 11 i bit clock input (1) dem0 18 i de-emphasis control 0 (1) (2) dem1 17 i de-emphasis control 1 (1) (2) dgnd 13 ? digital ground din 15 i data input (1) dout 12 o data output lrcin 10 i sample rate clock input (f s ) (1) pdad 7 i adc power down, active low (1) (2) pdda 8 i dac power down, active low (1) (2) sysclk 9 i system clock input (1) v cc 1 1, 2 ? adc analog power supply v cc 2 24 ? dac analog power supply v com 21 ? adc/dac common v dd 14 ? digital power supply v in l 6 i adc analog input, lch v in r 3 i adc analog input, rch v out l 19 o dac analog output, lch v out r 20 o dac analog output, rch v ref 1 4 ? adc reference 1 v ref 2 5 ? adc reference 2 20bit 16 i 20-bit format select (1)(2) (1) schmitt-trigger input (2) with 100-k w typical internal pulldown resistor 6 www .ti.com
typical performance curves adc section pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, f sysclk = 384 f s , and f signal = 1 khz, unless otherwise noted thd+n dynamic range and snr vs vs temperature temperature figure 1. figure 2. thd+n dynamic range and snr vs vs supply voltage supply voltage figure 3. figure 4. note: all characteristics at supply voltages from 2.4 v to 2.7 v are measured at sysclk = 256 f s . 7 www .ti.com 86 88 90 92 94 ?25 0 25 50 75 100 t a ? free-air t emperature ? c dynamic range ? db snr 9492 90 86 88 snr ? signal-to-noise ratio ? db g002 dynamic range 0.002 0.004 0.006 0.008 0.010 ?25 0 25 50 75 100 t a ? free-air t emperature ? c thd+n ? t otal harm. dist. + noise at ?0.5 db ? % ?0.5 db 54 3 1 2 ?60 db g001 thd+n ? t otal harm. dist. + noise at ?60 db ? % 86 88 90 92 94 2.1 2.4 2.7 3.0 3.3 3.6 3.9 v c c ? supply v oltage ? v dynamic range ? db 9492 90 86 88 snr ? signal-to-noise ratio ? db g004 dynamic range snr 0.002 0.004 0.006 0.008 0.010 2.1 2.4 2.7 3.0 3.3 3.6 3.9 v c c ? supply v oltage ? v thd+n ? t otal harm. dist. + noise at ?0.5 db ? % 54 3 1 2 thd+n ? t otal harm. dist. + noise at ?60 db ? % g003 ?60 db ?0.5 db
dac section pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 typical performance curves (continued) all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, f sysclk = 384 f s , and f signal = 1 khz, unless otherwise noted thd+n dynamic range and snr vs vs sampling frequency sampling frequency figure 5. figure 6. thd+n dynamic range and snr vs vs temperature temperature figure 7. figure 8. 8 www .ti.com 86 88 90 92 94 dynamic range ? db 9492 90 86 88 snr ? signal-to-noise ratio ? db g006 dynamic range snr f s ? sampling frequency ? khz 48 32 44.1 0.002 0.004 0.006 0.008 0.010 f s ? sampling frequency ? khz thd+n ? t otal harm. dist. + noise at ?0.5 db ? % 54 3 1 2 g005 thd+n ? t otal harm. dist. + noise at ?60 db ? % 48 32 44.1 ?60 db ?0.5 db 90 92 94 96 98 ?25 0 25 50 75 100 t a ? free-air t emperature ? c dynamic range ? db snr 9896 94 90 92 snr ? signal-to-noise ratio ? db g008 dynamic range 0.002 0.004 0.006 0.008 0.010 ?25 0 25 50 75 100 t a ? free-air t emperature ? c thd+n ? t otal harm. dist. + noise at fs ? % fs 43 2 0 1 ?60 db g007 thd+n ? t otal harm. dist. + noise at ?60 db ? %
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 typical performance curves (continued) all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, f sysclk = 384 f s , and f signal = 1 khz, unless otherwise noted thd+n dynamic range and snr vs vs supply voltage supply voltage figure 9. figure 10. note: all characteristics at supply voltages from 2.4 v to 2.7 v are measured at sysclk = 256 f s . thd+n dynamic range and snr vs vs sampling frequency and system clock sampling frequency and system clock figure 11. figure 12. 9 www .ti.com 90 92 94 96 98 2.1 2.4 2.7 3.0 3.3 3.6 3.9 v c c ? supply v oltage ? v dynamic range ? db 9896 94 90 92 snr ? signal-to-noise ratio ? db g010 dynamic range snr 0.002 0.004 0.006 0.008 0.010 2.1 2.4 2.7 3.0 3.3 3.6 3.9 v c c ? supply v oltage ? v thd+n ? t otal harm. dist. + noise at fs ? % 43 2 0 1 thd+n ? t otal harm. dist. + noise at ?60 db ? % g009 ?60 db fs 90 92 94 96 98 dynamic range ? db 9896 94 90 92 snr ? signal-to-noise ratio ? db g012 dynamic range snr f s ? sampling frequency ? khz 48 32 44.1 256 f s , 512 f s 384 f s 0.002 0.004 0.006 0.008 0.010 f s ? sampling frequency ? khz thd+n ? t otal harm. dist. + noise at fs ? % 43 2 0 1 g01 1 thd+n ? t otal harm. dist. + noise at ?60 db ? % 48 32 44.1 384 f s 256 f s , 512 f s 384 f s 256 f s , 512 f s fs ?60 db
output spectrum adcs pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 typical performance curves (continued) all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, f sysclk = 384 f s , and f signal = 1 khz, unless otherwise noted output spectrum (?0.5 db, n = 8192) output spectrum (?60 db, n = 8192) figure 13. figure 14. thd+n vs signal level figure 15. 10 www .ti.com f ? frequency ? khz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 20 25 amplitude ? db g015 signal level ? db ?96 ?84 ?72 ?60 ?48 ?36 ?24 ?12 0 thd+n ? t otal harmonic distortion + noise ? % g017 0.001 0.1 100 0.01 1 10 f ? frequency ? khz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 20 25 amplitude ? db g013
dacs pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 typical performance curves (continued) all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, f sysclk = 384 f s , and f signal = 1 khz, unless otherwise noted output spectrum (0 db, n = 8192) output spectrum (?60 db, n = 8192) figure 16. figure 17. thd+n vs signal level figure 18. 11 www .ti.com f ? frequency ? khz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 20 25 amplitude ? db g014 f ? frequency ? khz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 20 25 amplitude ? db g016 signal level ? db ?96 ?84 ?72 ?60 ?48 ?36 ?24 ?12 0 thd+n ? t otal harmonic distortion + noise ? % g018 0.001 0.1 100 0.01 1 10
typical performance curves supply current pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, f sysclk = 384 f s , din = bpz, and v in = bpz, unless otherwise noted i cc + i dd i cc + i dd vs vs supply voltage temperature figure 19. figure 20. all characteristics at supply voltages from 2.4 v to 2.7 v are measured at sysclk = 256 f s . i cc + i dd vs sampling frequency figure 21. 12 www .ti.com v c c ? supply v oltage ? v 0 5 10 15 20 25 2.1 2.4 2.7 3.0 3.3 3.6 3.9 i c c + i d d ? ma adc and dac adc dac power down and off 2.52.0 1.5 0 1.0 i c c + i d d : power down and off ? ma g020 0.5 t a ? free-air t emperature ? c 0 5 10 15 20 25 ?50 ?25 0 25 50 75 100 i c c + i d d ? ma adc and dac adc dac power down and off 2.52.0 1.5 0 1.0 i c c + i d d : power down and off ? ma g019 0.5 15 16 17 18 19 20 i c c + i d d ? ma adc and dac f s ? sampling frequency ? khz 48 32 44.1 g021 512 f s 256 f s
typical performance curves of internal filters (adcs) decimation filter pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, and f sysclk = 384 f s , unless otherwise noted overall characteristics stop-band attenuation characteristics figure 22. figure 23. pass-band ripple characteristics transition band characteristics figure 24. figure 25. 13 www .ti.com normalized frequency [ f s hz] ?200 ?150 ?100 ?50 0 0 8 16 24 32 amplitude ? db g022 normalized frequency [ f s hz] ?100 ?80 ?60 ?40 ?20 0 0.0 0.2 0.4 0.6 0.8 1.0 amplitude ? db g023 normalized frequency [ f s hz] ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.0 0.2 0.0 0.1 0.2 0.3 0.4 0.5 amplitude ? db g024 normalized frequency [ f s hz] ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 0.45 0.47 0.49 0.51 0.53 0.55 amplitude ? db g025 ?4.13 db at 0.5 f s
high-pass filter antialiasing filter pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 typical performance curves of internal filters (adcs) (continued) all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, and f sysclk = 384 f s , unless otherwise noted high-pass filter response high-pass filter response figure 26. figure 27. antialiasing filter overall antialiasing filter pass-band frequency response frequency response figure 28. figure 29. 14 www .ti.com normalized frequency [ f s /1000 hz] ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.0 0.2 0 1 2 3 4 amplitude ? db g027 normalized frequency [ f s /1000 hz] ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.0 0.1 0.2 0.3 0.4 0.5 amplitude ? db g026 ?50 ?40 ?30 ?20 ?10 0 f ? frequency ? hz amplitude ? db 1 10 100 10m 1k 10k g028 100k 1m ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.0 0.2 f ? frequency ? hz amplitude ? db 1 10 100 100k 1k 10k g029
typical performance curves of internal filters (dacs) digital filter de-emphasis filter pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, and f sysclk = 384 f s , unless otherwise noted overall frequency characteristics pass-band ripple characteristics (f s = 44.1 khz) (f s = 44.1 khz) figure 30. figure 31. de-emphasis frequency response (32 khz) de-emphasis error (32 khz) figure 32. figure 33. 15 www .ti.com ?100 ?80 ?60 ?40 ?20 0 level ? db f ? frequency ? hz 75k 25k 50k g030 0 175k 100k 125k 150k ?1.00 ?0.80 ?0.60 ?0.40 ?0.20 0.00 level ? db f ? frequency ? hz 5k g031 0 20k 10k 15k ?12 ?10 ?8 ?6 ?4 ?2 0 level ? db f ? frequency ? hz 5k g032 0 25k 10k 15k 20k ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 error ? db f ? frequency ? hz 3628 g033 0 14512 7256 10884
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 typical performance curves of internal filters (dacs) (continued) all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, and f sysclk = 384 f s , unless otherwise noted de-emphasis frequency response (44.1 khz) de-emphasis error (44.1 khz) figure 34. figure 35. de-emphasis frequency response (48 khz) de-emphasis error (48 khz) figure 36. figure 37. 16 www .ti.com ?12 ?10 ?8 ?6 ?4 ?2 0 level ? db f ? frequency ? hz 5k g034 0 25k 10k 15k 20k ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 error ? db f ? frequency ? hz 4999.8375 g035 0 19999.35 9999.675 14999.5125 ?12 ?10 ?8 ?6 ?4 ?2 0 level ? db f ? frequency ? hz 5k g036 0 25k 10k 15k 20k ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 error ? db f ? frequency ? hz 5442 g037 0 21768 10884 16326
analog low-pass filter pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 typical performance curves of internal filters (dacs) (continued) all specifications at t a = 25 c, v cc = v dd = 3 v, f s = 44.1 khz, and f sysclk = 384 f s , unless otherwise noted internal analog filter frequency response internal analog filter frequency response (1 hz?10 mhz) (1 hz?100 khz) figure 38. figure 39. 17 www .ti.com ?100 ?80 ?60 ?40 ?20 0 20 f ? frequency ? hz level ? db 1 10 100 10m 1k 10k g038 100k 1m ?0.15 ?0.10 ?0.05 0.00 0.05 0.10 0.15 f ? frequency ? hz level ? db 1 10 100 100k 1k 10k g039
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 block diagram (1) mc, md, ml, rst, and zflg are for pcm3002 only. (2) dem0, dem1, 20bit, pdad, and pdda are for pcm3003 only. 18 www .ti.com ml ( 1 ) 20bit ( 2 ) analog front-end circuit lrcin v i n l reference v r e f 1 v r e f 2 v i n r delta-sigma modulator delta-sigma modulator decimation and high-pass filter power supply reset and power down serial data interface dout mc ( 1 ) /dem0 ( 2 ) v c o m (+) (?)(?) (+) mode control interface analog front-end circuit decimation and high-pass filter adc bckindin analog low-pass filter v o u t l multilevel delta-sigma modulator interpolation filter 8 oversampling analog low-pass filter v o u t r multilevel delta-sigma modulator interpolation filter 8 oversampling dac md ( 1 ) /dem1 ( 2 ) pdda ( 2 ) rst ( 1 ) /pdad ( 2 ) zero detect ( 1 ) clock sysclk zflg ( 1 ) agnd2 v c c 2 agnd1 v c c 1 dgnd v d d b0004-03
pcm audio interface pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 figure 40. analog front-end (single-channel) the four-wire digital audio interface for the pcm3002/3003 comprises lrcin (pin 10), bckin (pin 11), din (pin 15), and dout (pin 12). the pcm3002 can be used with any of the four input/output data formats (formats 0?3), while the pcm3003 can only be used with selected input/output formats (formats 0?1). for the pcm3002, these formats are selected through program register 3 in the software mode. for the pcm3003, data formats are selected by the 20bit input (pin 16). figure 41 , figure 42 , and figure 43 illustrate audio data input/output formats and timing. the pcm3002/3003 can accept 32, 48, or 64 bit clocks (bckin) in one clock of lrcin. only the 16-bit data format can be selected when 32-bit clocks/lrcin are applied. 19 www .ti.com 30 k w v i n r v c o m 3 21 5 delta-sigma modulator (+) v r e f v r e f 2 + 1.0 m f 4.7 m f + + ? (?) + ? s001 1-03 v r e f 1 4 4.7 m f + 4.7 m f +
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 figure 41. audio data input/output format 20 www .ti.com dac: 16-bit, msb-first, right-justified forma t 0: pcm3002/3003 lrcin right-channel left-channel bckin din msb lsb msb lsb 3 2 1 16 15 14 16 3 2 1 16 15 14 bckin lrcin right-channel left-channel dout 1 14 15 16 3 2 1 msb lsb msb lsb 14 15 16 3 2 1 adc: 16-bit, msb-first, left-justified lrcin right-channel left-channel bckin din msb lsb msb lsb 18 19 20 3 2 1 18 19 20 3 2 1 20 dac: 20-bit, msb-first, right-justified forma t 1: pcm3002/3003 bckin lrcin right-channel left-channel dout 1 18 19 20 3 2 1 msb lsb msb lsb 18 19 20 3 2 1 adc: 20-bit, msb-first, left-justified t0016-04
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 figure 42. audio data input/output format (pcm3002) 21 www .ti.com dac: 20-bit, msb-first, left-justified forma t 2: pcm3002 only bckin lrcin right-channel left-channel din 1 18 19 20 3 2 1 msb lsb msb lsb 18 19 20 3 2 1 adc: 20-bit, msb-first, left-justified bckin lrcin right-channel left-channel dout 1 18 19 20 3 2 1 msb lsb msb lsb 18 19 20 3 2 1 lrcin right-channel left-channel bckin din msb lsb msb lsb 18 19 20 3 2 1 18 19 20 3 2 1 dac: 20-bit, msb-first, i 2 s forma t 3: pcm3002 only lrcin right-channel left-channel bckin dout msb lsb msb lsb 18 19 20 3 2 1 18 19 20 3 2 1 adc: 20-bit, msb-first, i 2 s t0016-05
system clock pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 bckin pulse cycle time t (bcy) 300 ns (min) bckin pulse duration, high t (bch) 120 ns (min) bckin pulse duration, low t (bcl) 120 ns (min) bckin rising edge to lrcin edge t (bl) 40 ns (min) lrcin edge to bckin rising edge t (lb) 40 ns (min) lrcin pulse duration t (lrp) t (bcy) (min) din setup time t (dis) 40 ns (min) din hold time t (dih) 40 ns (min) dout delay time to bckin falling edge t (bdo) 40 ns (max) dout delay time to lrcin edge t (ldo) 40 ns (max) rising time of all signals t (rise) 20 ns (max) falling time of all signals t (fall) 20 ns (max) figure 43. audio data input/output timing the system clock for the pcm3002/3003 must be either 256 f s , 384 f s , or 512 f s , where f s is the audio sampling frequency. the system clock should be provided at the sysclk input (pin 9). the pcm3002/3003 also has a system-clock detection circuit that automatically senses if the system clock is operating at 256 f s , 384 f s , or 512 f s . when a 384-f s or 512-f s system clock is used, the clock is divided to 256 f s automatically. the 256-f s clock is used to operate the digital filters and the delta-sigma modulators. table 1 lists the relationship of typical sampling frequencies and system clock frequencies; figure 44 illustrates the system clock timing. table 1. system clock frequencies sampling rate frequency (khz) system clock frequency (mhz) 256 f s 384 f s 512 f s 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 22 www .ti.com bckin lrcin din t ( b c h ) t ( b c l ) t ( l r p ) t ( l b ) t ( b c y ) 0.5 v d d t ( b l ) dout t ( b d o ) t ( l d o ) 0.5 v d d t ( d i s ) t ( d i h ) 0.5 v d d 0.5 v d d t0021?01
power-on reset pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 figure 44. system clock timing system clock pulse duration, high t (sckh) 12 ns (min) system clock pulse duration, low t (sckl) 12 ns (min) both the pcm3002 and pcm3003 have internal power-on reset circuitry. power-on reset occurs when the system clock (sysclk) is active and v dd > 2.2 v. for the pcm3003, the sysclk must complete a minimum of three complete cycles prior to v dd > 2.2 v to ensure proper reset operation. the initialization sequence requires 1024 sysclk cycles for completion, as shown in figure 45 . figure 46 shows the state of the dac and adc outputs during and after the reset sequence. figure 45. internal power-on reset timing 23 www .ti.com t ( s c k h ) sysclk 0.3 v d d 0.7 v d d t ( s c k l ) 1/256 f s , 1/384 f s , or 1/512 f s h l t0005-05 1024 system clock periods reset reset removal 2.4 v2.2 v 2.0 v v d d internal reset system clock t0014-03 3 clocks minimum
external reset synchronization with the digital audio system pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 (1) the hpf transient response (exponentially attenuated signal from 0.2% dc of fsr with 200-ms time constant) appears initially. figure 46. dac output and adc output for reset and power down the pcm3002 includes a reset input, rst (pin 7), while the pcm3003 uses both pdad (pin 7) and pdda (pin 8) for external reset control. as shown in figure 47 , the external reset signal must drive rst or pdad and pdda low for a minimum of 40 nanoseconds while sysclk is active in order to initiate the reset sequence. initialization starts on the rising edge of rst or pdad and pdda, and requires 1024 sysclk cycles for completion. figure 46 shows the state of the dac and adc outputs during and after the reset sequence. figure 47. external forced-reset timing the pcm3002/3003 operates with lrcin synchronized to the system clock. the pcm3002/3003 does not require any specific phase relationship between lrcin and the system clock, but there must be synchronization of lrcin and the system clock. if the synchronization between the system clock and lrcin changes more than 6 bit clocks (bckin) during one sample (lrcin) period because of phase jitter on lrcin, internal operation of the dac stops within 1/f s , and the analog output is forced to bipolar zero (0.5 v cc ) until the system clock is resynchronized to lrcin followed by t (dacdly2) delay time. internal operation of the adc also stops within 1/f s , and the digital output codes are set to bipolar zero until resynchronization occurs followed by t (adcdly2) delay time. if lrcin is synchronized within 5 or fewer bit clocks to the system clock, operation is normal. figure 48 illustrates the effects on the output when synchronization is lost. before the outputs are forced to bipolar zero (<1/f s seconds), the outputs are not defined and some noise may occur. during the transitions between normal data and undefined states, the output has discontinuities, which cause output noise. 24 www .ti.com t0019-02 reset ready/operation internal reset or power down dac v o u t t ( d a c d l y 1 ) (16384/f s ) reset removal or power down off power down adc dout zero data normal data ( 1 ) v c o m (0.5 v c c ) t ( a d c d l y 1 ) (18432/f s ) zero data gnd t ( r s t ) reset removal 1024 system clock periods rst or pdad and pdda internal reset system clock t ( r s t ) = 40 ns (min) reset t0015-02 rst pulse duration
zero flag output: pcm3002 only operational control pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 (1) the hpf transient response (exponentially attenuated signal from 0.2% dc of fsr with 200-ms time constant) appears initially. figure 48. dac output and adc output for loss of synchronization pin 16 is an open-drain output, used as the infinite zero detection flag on the pcm3002 only. when input data is continuously zero for 65,536 bckin cycles, zflg is low; otherwise, zflg is in a high-impedance state. the pcm3002 can be controlled in a software mode with a three-wire serial interface on mc (pin 18), md (pin 17), and ml (pin 8). table 2 indicates selectable functions, and figure 49 and figure 50 illustrate the control data input format and timing. the pcm3003 only allows for control of 16/20-bit data format, digital de-emphasis, and power-down control by hardware pins. table 2. selectable functions (o = user selectable; x = not available) function adc/dac pcm3002 pcm3003 audio data format adc/dac four selectable formats two selectable formats lrcin polarity adc/dac o x loopback control adc/dac o x left-channel attenuation dac o x right-channel attenuation dac o x attenuation control dac o x infinite zero detection and mute dac o x dac output control dac o x soft mute control dac o x de-emphasis (off, 32 khz, 44.1 khz, 48 khz) dac o o adc power-down control adc o o dac power-down control dac o o high-pass filter operation adc o x 25 www .ti.com within 1/f s t ( d a c d l y 2 ) (32/f s ) normal data v c o m (0.5 v c c ) undefined data normal data synchronous asynchronous synchronous resynchronization synchronization lost dac v o u t state of synchronization t0020-03 normal data ( 1 ) zero data normal data adc dout t ( a d c d l y 2 ) (32/f s ) undefined data
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 figure 49. control data input format mc pulse cycle time t (mcy) 100 ns (min) mc pulse duration, low t (mcl) 40 ns (min) mc pulse duration, high t (mch) 40 ns (min) md setup time t (mds) 40 ns (min) md hold time t (mdh) 40 ns (min) ml low-level time t (mll) 40 ns + 1 sysclk (1) (min) ml high-level time t (mhh) 40 ns + 1 sysclk (1) (min) ml setup time (3) t (mls) 40 ns (min) ml hold time (2) t (mlh) 40 ns (min) sysclk: 1/256 f s or 1/384 f s or 1/512 f s (1) sysclk: system clock cycle (2) mc rising edge of lsb to ml rising edge (3) ml rising edge to the next mc rising edge figure 50. control data input timing 26 www .ti.com b8 b15 ml mcmd b9 b10 b1 1 b12 b13 b14 b0 b7 b1 b2 b3 b4 b5 b6 t0023-01 t ( m c h ) ml lsb t ( m c l ) t ( m h h ) t ( m c y ) t ( m d h ) t ( m d s ) mcmd t ( m l s ) t ( m l l ) t ( m l h ) t0024-02 0.5 v d d 0.5 v d d 0.5 v d d
mapping of program registers software control (pcm3002) program register 0 pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 0 res res res res res a1 a0 ldl al7 al6 al5 al4 al3 al2 al1 al0 register 1 res res res res res a1 a0 ldr ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 register 2 res res res res res a1 a0 pdad byps pdda atc izd out dem1 dem0 mut register 3 res res res res res a1 a0 res res res lop res fmt1 fmt0 lrp res note: res indicates a reserved bit that should be set to 0. the pcm3002 special functions are controlled using four program registers which are each 16 bits long. there are four distinct registers, with bits 9 and 10 determining which register is in use. table 3 describes the functions of the four registers. table 3. functions of the registers register name register bit(s) bit name description register 0 15?11 res reserved, should be set to 0 10?9 a[1:0] register address 00 8 ldl dac attenuation data load control for lch 7?0 al[7:0] dac attenuation data for lch register 1 15?11 res reserved, should be set to 0 10?9 a[1:0] register address 01 8 ldr dac attenuation data load control for rch 7?0 ar[7:0] dac attenuation data for rch register 2 15?11 res reserved, should be set to 0 10?9 a[1:0] register address 10 8 pdad adc power-down control 7 byps adc high-pass filter bypass control 6 pdda dac power-down control 5 atc dac attenuation data mode control 4 izd dac infinite zero detection and mute control 3 out dac output enable control 2?1 dem[1:0] dac de-emphasis control 0 mut dac lch and rch soft mute control register 3 15?11 res reserved, should be set to 0 10?9 a[1:0] register address 11 8?6 res reserved, should be set to 0 5 lop adc/dac digital loopback control 4 res reserved, should be set to 0 3?2 fmt[1:0] adc/dac audio data format selection 1 lrp adc/dac polarity of lr-clock selection 0 res reserved, should be set to 0 res: bits 15?11: reserved these bits are reserved and should be set to 0. 27 www .ti.com
program register 1 program register 2 pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 a[1:0] bits 10, 9: register address these bits define the address for register 0: a1 a0 register 0 0 register 0 ldl bit 8: dac attenuation data load control for left channel this bit is used to set analog outputs of the left and right channels simultaneously. the output level is controlled by al[7:0] attenuation data when this bit is set to 1. when set to 0, the new attenuation data is ignored, and the output level remains at the previous attenuation level. the ldr bit in register 1 has the equivalent function as ldl. when either ldl or ldr is set to 1, the output levels of the left and right channels are controlled simultaneously. al (7:0) bits 7?0: dac attenuation data for left channel al7 and al0 are the msb and lsb, respectively. the attenuation level (att) is given by: att = 20 log 10 (al[7:0]/256) [db], except al[7:0] = ffh al[7:0] attenuation level 00h ? db (mute) 01h ?48.16 db : : feh ?0.07 db ffh 0 db (default) res: bits 15?11: reserved these bits are reserved and should be set to 0. a[1:0] bits 10, 9: register address these bits define the address for register 1: a1 a0 register 0 1 register 1 ldr bit 8: dac attenuation data load control for right channel this bit is used to set analog outputs of the left and right channels simultaneously. the output level is controlled by ar[7:0] attenuation data when this bit is set to 1. when set to 0, the new attenuation data is ignored, and the output level remains at the previous attenuation level. the ldl bit in register 0 has the equivalent function as ldr. when either ldl or ldr is set to 1, the output levels of the left and right channels are controlled simultaneously. ar[7:0] bits 7?0: dac attenuation data for right channel ar7 and ar0 are the msb and lsb, respectively. att = 20 log 10 (ar[7:0]/256) [db], except ar[7:0] = ffh ar[7:0] attenuation level 00h ? db (mute) 01h ?48.16 db : : feh ?0.07 db ffh 0 db (default) res: bits 15?11: reserved these bits are reserved and should be set to 0. 28 www .ti.com
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 a[1:0] bits 10, 9: register address these bits define the address for register 2: a1 a0 register 1 0 register 2 pdad: bit 8: adc power-down control this bit places the adc section in the lowest power-consumption mode. the adc operation is stopped by cutting the supply current to the adc section, and dout is fixed to zero during adc power-down mode enable. figure 46 illustrates the adc dout response for adc power-down on/off. this does not affect the dac operation. pdad dac power-down status 0 power-down mode disabled (default) 1 power-down mode enabled byps: bit 7: adc high-pass filter bypass control this bit enables or disables the high-pass filter for the adc. byps filter bypass status 0 high-pass filter enabled (default) 1 high-pass filter disabled (bypassed) pdda: bit 6: dac power-down control this bit places the dac section in the lowest power-consumption mode. the dac operation is stopped by cutting the supply current to the dac section, and vout is fixed to gnd during dac power-down mode enable. figure 46 illustrates the dac vout response for dac power-down on/off. this does not affect the adc operation. pdda adc power-down status 0 power-down mode disabled (default) 1 power-down mode enabled atc: bit 5: dac attenuation data mode control when set to 1, the register 0 attenuation data can be used for both dac channels. in this case, the register 1 attenuation data is ignored. atc attenuation control 0 individual channel attenuation data control (default) 1 common channel attenuation data control izd: bit 4: dac infinite zero detection and mute control this bit enables the infinite zero detection circuit in the pcm3002. when enabled, this circuit disconnects the analog output amplifier from the delta-sigma dac when the input is continuously zero for 65,536 consecutive cycles of bckin. izd infinite zero detect status 0 infinite zero detection and mute control disabled (default) 1 infinite zero detection and mute control enabled out: bit 3: dac output enable control when set to 1, the outputs are forced to v cc /2 (bipolar zero). in this case, all registers in the pcm3002 hold the present data. therefore, when set to 0, the outputs return to the previous programmed state. out dac output status 0 dac outputs enabled (default normal operation) 1 dac outputs disabled (forced to bpz) 29 www .ti.com
program register 3 pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 dem[1:0]: bits 2, 1: dac de-emphasis control these bits select the de-emphasis mode as shown below: dem1 dem0 de-emphasis status 0 0 de-emphasis 44. 1 khz on 0 1 de-emphasis off (default) 1 0 de-emphasis 48 khz on 1 1 de-emphasis 32 khz on mut: bit 0: dac soft mute control when set to 1, both left- and right-channel dac outputs are muted at the same time. this muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on. mut mute status 0 mute disabled (default) 1 mute enabled res: bits 15?11: reserved these bits are reserved and should be set to 0. a[1:0] bits 10, 9: register address these bits define the address for register 3: a1 a0 register 1 1 register 3 res: bits 8?6: reserved these bits are reserved and should be set to 0. lop: bit 5: adc to dac loopback control when this bit is set to 1, the adc audio data is sent directly to the dac. the data format defaults to i 2 s; dout is still available in loopback mode. lop loopback status 0 loopback disabled (default) 1 loopback enabled res: bit 4: reserved this bit is reserved and should be set to 0. fmt[1:0] bits 3?2: audio data format select these bits determine the input and output audio data formats. fmt1 fmt0 dac data format adc data format name 0 0 16-bit, msb-first, right-justified 16-bit, msb-first, left-justified format 0 (default) 0 1 20-bit, msb-first, right-justified 20-bit, msb-first, left-justified format 1 1 0 20-bit, msb-first, left-justified 20-bit, msb-first, left-justified format 2 1 1 20-bit, msb-first, i 2 s 20-bit, msb-first, i 2 s format 3 lrp: bit 1: adc to dac lrcin polarity select polarity of lrcin applies only to formats 0 through 2. lrp left/right polarity 0 left channel is h, right channel is l (default). 1 left channel is l, right channel is h. 30 www .ti.com
pcm3003 data format control power-down control (pin 7 and pin 8) de-emphasis control (pin 17 and pin 18) 20bit audio data selection (pin 16) pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 res: bit 0: reserved this bit is reserved and should be set to 0. the pcm3003 has hardware functional control using pdad (pin 7) and pdda (pin 8) for power-down control; dem0 (pin 18) and dem1 (pin 17) for de-emphasis; and 20bit (pin 16) for 16/20-bit format selection. both the adc and dac power-down control pins place the adc or dac section in the lowest power-consumption mode. the adc/dac operation is stopped by cutting the supply current to the adc/dac section. dout is fixed to zero during adc power-down mode enable and v out is fixed to gnd during dac power-down mode enable. figure 46 illustrates the adc and dac output response for power-down on/off. pdad pdda power down low low reset (adc/dac power down enabled) low high adc power-down/dac operates high low adc operates/dac power down high high adc and dac normal operation dem0 (pin 18) and dem1 (pin 17) are used as de-emphasis control pins. dem1 demo de-emphasis low low de-emphasis enabled for 44.1 khz low high de-emphasis disabled high low de-emphasis enabled for 48 khz high high de-emphasis enabled for 32 khz 20bit format low adc: 16-bit msb-first, left-justified dac: 16-bit msb-first, right-justified high adc: 20-bit msb-first, left-justified dac: 20-bit msb-first, right-justified 31 www .ti.com
application and layout considerations power-supply bypassing grounding voltage input v ref inputs v com input system clock reset control external mute control typical connection diagram pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 the digital and analog power supply lines to pcm3002/3003 should be bypassed to the corresponding ground pins with both 0.1- m f ceramic and 10- m f tantalum capacitors as close to the device pins as possible. although the pcm3002/3003 has three power-supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power-supply sequencing problems. if separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems. in order to optimize the dynamic performance of the pcm3002/3003, the analog and digital grounds are not connected internally. the pcm3002/3003 performance is optimized with a single ground plane for all returns. it is recommended to tie all pcm3002/3003 ground pins to the analog ground plane using low-impedance connections. the pcm3002/3003 should reside entirely over this plane to avoid coupling high-frequency digital switching noise into the analog ground plane. a tantalum or aluminum electrolytic capacitor, between 1 m f and 10 m f, is recommended as an ac-coupling capacitor at the inputs. combined with the 30-k w characteristic input impedance, a 1- m f coupling capacitor establishes a 5.3-hz cutoff frequency for blocking dc. the input voltage range can be increased by adding a series resistor on the analog input line. this series resistor, when combined with the 30-k w input impedance, creates a voltage divider and enables larger input ranges. a 4.7- m f to 10- m f tantalum capacitor is recommended between v ref 1, v ref 2, and agnd1 to ensure low source impedance for the adc references. these capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the adc reference. a 4.7- m f to 10- m f tantalum capacitor is recommended between v com and agnd1 to ensure low source impedance of the adc and dac common voltage. this capacitor should be located as close as possible to the v com pin to reduce dynamic errors on the dc common-mode voltage. the quality of the system clock can influence dynamic performance of both the adc and dac in the pcm3002/3003. the duty cycle and jitter at the system-clock input pin should be carefully managed. when power is supplied to the part, the system clock, bit clock (bckin), and word clock (lcrin) also must be supplied simultaneously. failure to supply the audio clocks results in a power-dissipation increase of up to three times normal dissipation and can degrade long-term reliability if the maximum power-dissipation limit is exceeded. if capacitors larger than 22 m f are used on v ref and v com , external reset control ( rst = low for the pcm3002, pdad = low and pdda = low for the pcm3003) is required after the v ref , v com transient response is settled. for power-down on/off control without click noise, which is generated by a dc level change on the dac output, use of the external mute control is recommended. the control sequence, which is external mute on, codec power-down on, sysclk stop and resume if necessary, codec power-down off, and external mute off is recommended. a typical connection diagram for the pcm3002/3003 is shown in figure 51 . 32 www .ti.com
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 (1) 0.1- m f ceramic and 10- m f tantalum, typical, depending on power supply quality and pattern layout (2) 4.7- m f, typical, gives settling time with 30-ms (4.7 m f 6.4 k w ) time constant in the power on and power-down off periods. (3) 1- m f, typical, gives 5.3-hz cutoff frequency for the input hpf in normal operation and gives settling time with 30-ms (1 m f 30 k w ) time constant in the power on and power-down off periods. (4) 4.7- m f, typical, gives 3.4-hz cutoff frequency for the output hpf in normal operation and gives settling time with 47-ms (4.7 m f 10 k w ) time constant in the power on and power-down off periods. (5) post low-pass filter with r in > 10 k w , depending on system performance requirements (6) mc, md, ml, zflg, rst, and 10-k w pullup resistor are for the pcm3002. (7) dem0, dem1, 20bit, pdad, pdda are for the pcm3003. figure 51. typical connection diagram for pcm3002/3003 33 www .ti.com v r e f 2 2019 18 17 16 15 14 13 56 7 8 9 10 1 1 12 v i n l rst /pdad ml/pdda sysclklrcin bckin dout v o u t r dgnd v o u t l mc/dem0md/dem1 zflg /20bit v d d din rch in audio interface v c c 1 2423 22 21 12 3 4 v c c 1 v i n r v r e f 1 v c c 2 agnd1 agnd2 v c o m ++ 0.1 m f and 10 m f ( 1 ) mc ( 6 ) /dem0 ( 7 ) zflg ( 6 ) /20bit ( 7 ) controlinterface pcm3002/3003 + + 1 m f ( 3 ) 4.7 m f ( 2 ) 4.7 m f ( 2 ) lch in + 1 m f ( 3 ) sysclk l/r clkbit clk da t a out da t a in s0014-01 +3 v analog v c c + + 0.1 m f and 10 m f ( 1 ) 4.7 m f ( 2 ) + 4.7 m f ( 4 ) rch out ( 5 ) lch out ( 5 ) md ( 6 ) /dem1 ( 7 ) 0.1 m f and 10 m f ( 1 ) ml ( 6 ) /pdda ( 7 ) rst ( 6 ) /pdad ( 7 ) 4.7 m f ( 4 ) 10 k w +
theory of operation adc section dac section pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 the pcm3002/3003 adc consists of two reference circuits, a stereo single-to-differential converter, a fully differential fifth-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. the block diagram in this data sheet illustrates the architecture of the adc section, figure 40 shows the single-to-differential converter, and figure 52 illustrates the architecture of the fifth-order delta-sigma modulator and transfer functions. an internal reference circuit with three external capacitors provides all reference voltages required by the adc, which defines the full-scale range for the converter. the internal single-to-differential voltage converter saves the space and extra parts needed for the external circuitry required by many delta-sigma converters. the internal full-differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. the input signal is sampled at a 64 oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying antialias filtering requirements. the fifth-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit dac. the delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. the high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. the 64-f s , one-bit data stream from the modulator is converted to 1-f s , 16/20-bit data words by the decimation filter, which also acts as a low-pass filter to remove the shaped quantization noise. the dc components are removed by a high-pass filter function contained within the decimation filter. the delta-sigma dac section of the pcm3002/3003 is based on a 5-level amplitude quantizer and a third-order noise shaper. this section converts the oversampled input data to a 5-level delta-sigma format. a block diagram of the 5-level delta-sigma modulator is shown in figure 53 . this 5-level delta-sigma modulator has the advantage of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. the combined oversampling rate of the delta-sigma modulator and the internal 8 interpolation filter is 64 f s for a 256-f s system clock. the theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in figure 54 . figure 52. simplified fifth-order delta-sigma modulator 34 www .ti.com 1 s t sw -cap integrator analogin x(z) + ? + ? 2 n d sw -cap integrator 3 r d sw -cap integrator + ? 4 t h sw -cap integrator + + + + + + + + 5 t h sw -cap integrator digitalout y(z) comparator qn(z) h(z) 1-bit dac stf(z) = h(z) / [1 + h(z)]ntf(z) = 1 / [1 + h(z)] y(z) = stf(z) * x(z) + ntf(z) * qn(z)signal t ransfer function noise t ransfer function b0005-01
pcm3002 pcm3003 sbas079a ? october 2000 ? revised october 2004 theory of operation (continued) figure 53. five-level delta-sigma modulator block diagram figure 54. quantization noise spectrum 35 www .ti.com + + ? z ? 1 + + + + ? z ? 1 in 8 f s 21-bit out 64 f s + + z ? 1 b0008-01 + 5-level quantizer 0 1 2 3 4 f ? frequency ? khz ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 5 10 15 20 25 30 gain ? db g040
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) pcm3002e active ssop db 24 58 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm3002e/2k active ssop db 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm3002e/2kg4 active ssop db 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm3002eg active ssop db 24 58 pb-free (rohs) cu snbi level-2-260c-1 year pcm3002eg/2k active ssop db 24 2000 pb-free (rohs) cu snbi level-2-260c-1 year pcm3002eg/2ke6 active ssop db 24 2000 pb-free (rohs) cu snbi level-2-260c-1 year pcm3002eg4 active ssop db 24 58 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm3002ege6 active ssop db 24 58 pb-free (rohs) cu snbi level-2-260c-1 year pcm3003e active ssop db 24 58 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm3003e/2k active ssop db 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm3003e/2kg4 active ssop db 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pcm3003eg4 active ssop db 24 58 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. package option addendum www.ti.com 12-jan-2007 addendum-page 1
in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 12-jan-2007 addendum-page 2
mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. cu stomers should obtain the latest relevant information before placing orders and should verify that such info rmation is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and othe r quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by governm ent requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti component s. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implie d, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are us ed. information published by ti regarding third-party products or services does not consti tute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the pat ents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, lim itations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements diffe rent from or beyond the parameters stated by ti for that product or service voids all express and any imp lied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.c om audio www.ti.com/audio data converters dataconverter.ti.co m automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 6553 03 dallas, texas 75265 copyright ? 2007, texas instruments incorporated

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