power architecture ? mcus pxs30 family built on power architecture ? technology overview psx30 32-bit power architecture ? based dual-core mcus are designed specifically for use in industrial safety applications. all devices in this family are built around a dual-core safety platform with an innovative safety concept targeting systems with international electrotechnical commission (iec) 61508 sil3 safety integrity levels. to minimize additional software and module-level features, on-chip redundancy is offered for the critical components of the mcu. critical components include the cpu core, dma controller, interrupt controller, crossbar bus system, memory protection unit, flash memory and ram controllers, peripheral bus bridge, system timers and watchdog timer. lock step redundancy checking units are implemented at each output of this sphere of replication. the performance of the pxs30 family is rarely experienced in an mcu with over 600 possible dmips, up to 2 mb of flash and ethernet communication. the pxs30 family is part of the safeassure program, which is designed to help system manufacturers more easily achieve compliance with functional safety standards. safety with performance target applications factory automation ? programmable logic control ? input/output (i/o) control ? process control, temperature control ? robotic arm ? robotic manipulator smart grid and smart metering ? residential solar power inverters ? commercial solar power inverters ? off-grid solar power inverters diagnostic and therapy ? anesthesia unit monitors ? ventilators and respirators crossbar masters vreg pxs30 block diagram spe2 e200 core edma interrupt controller vle mmu flexray? controller pdi spe2 e200 core vle mmu vreg edma interrupt controller debug jtag nexus memory protection unit crossbar switch memory protection unit crossbar switch i/o bridge ebi rc flash (ecc) i/o bridge mddr1 rc rc flash (ecc) fccu 3x linflex 3x dspi iic 4 flexcan 3x etimer 2x flexpwm ctu 2 atd communications i/o system pxs30 block diagram
freescale, the freescale logo and codewarrior are trademarks of freescale?semiconductor,?inc., reg. u.s. pat. & tm. off. safeassure and the safeassure logo are trademarks of freescale semiconductor, inc. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. all other product or service names are the property of their respective owners. ??2012?freescale?semiconductor,?inc. document number: pxs30fs rev 1 for current information about pxs30 family products and documentation, please visit freescale.com/pxs30 and freescale.com/tower temperature range: -40oc to +105oc: select parts +125c product number speed (mhz) flash/ram package PXS3010 150 1 mb/256 kb 257 mapbga pxs3015 180 1.5 mb/384 kb 473 mapbga pxs3020 180 2 mb/512 kb 473 mapbga selector guide challenges and solutions system challenges pxs30 solutions reduce system costs and simplify design ? reduces design complexity and component count by putting key functional safety features on a single chip ? dual processing spheres, including cpu, dma, interrupt controller, crossbar and mpu for logic level fault detection ? dual z7 cpu architecture provides performance to address real-time applications and cross-checking functions common in many safety strategies, which reduces hardware and software complexity used in multiple mcu designs. the architecture can be run in two statistically configurable modes of operation. ? lockstep operation provides a software environment for redundant processing and calculations ? independent core operation (dual parallel mode) provides a software environment for diverse processing and calculations to increase performance or to cross check for reliable operation ? built-in flexible hardware self-test capabilities provide diagnostic coverage both at logic and memory level ? fault collection and control unit manages mcu behavior in the event internal mcu logic faults and signals these to external system components ? flexray? protocol and safety ports for robust communications ? probability of undetected failure per hour (pfh) = 0.1 fit (one failure per every 10 billion hours) ? designed to target safety requirements outlined in iec61511 and iec61508 (sil3), which reduces system cost and effort precise control for real-time applications ? e200 z7 cpu at 180 mhz provides computational performance targeted at vector-oriented control of motor applications ? dual-core architecture provides computation ability for complex applications or cross-checking requirements of safety applications ? precise control of integrated electric motor control periphery ? advanced pwm for specialized multi-phase motor control requirements ? configurable alignment ? high frequency above 100 mhz ? dead time insertion ? skew correction ? cross-triggering unit coordinates adc, timer and pwm generation and minimizes cpu interrupt load etimer units handle rotor position and speed acquisition and offer six dual-action ic/oc channels with incremental/quadrature encoder mode ? two 12-bit adcs offer precise conversion for an improved driving experience ? flexray protocol for fault-tolerant communications with other networked modules within the vehicle ? up to 2 mb flash ? up to 512 kb sram ? motor control library of common functions ? ability to control two three-phase motors the pxs30 dual-core architecture can be statically switched from lockstep mode to decoupled parallel mode (independent core operation) for applications needing maximum performance or software diversity. a wide variety of industrial applications can be supported, such as motion and power control. for example, the new cross-triggering unit allows control of up to two brushless dc motors or multiple actuators with a minimum interrupt load. additional features include ethernet, a fault collection unit, multiple communication modules, two 12-bit adcs, etimer units and a built-in hardware self test. safeassure program: functional safety. simplified. freescales safeassure functional safety program is designed to help system manufacturers more easily achieve system compliance with functional safety standards: international standards organization (iso) 26262 and iec 61508. the program highlights freescale solutionshardware and softwarethat are optimally designed to support functional safety implementations and come with a rich set of enablement collateral. for more information, visit freescale.com/safeassure . development tools ? mqx? ? rappid ? freemaster ? codewarrior ? green hills software ? tower system
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