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6 pll
contents pll2013x ....................................................................................................................... ..... 6-1
samsung asic 6-1 stdm110 pll2013x block diagram figure 6-1 phase locked loop block diagram note: x-tal oscillator and lock detector are optional block. if customer concerns about this block - xtal buffer or lock detector, refer to next chapter. charge fout pump pre-divider p pfd vco post scaler s main divider m loop filter (external) fin general description the pll2013x is a phase-locked loop (pll) fre- quency synthesizer constructed in cmos on single monolithic structure. the pll macrofunctions pro- vide frequency multiplication capabilities. the out- put clock frequency fout is related to the reference input clock frequency fin (xtalin) by the following equation: fout = (m fin) / (p 2 s ) where, fout is the output clock frequency. fin is the reference input clock frequency. m, p and s are the values for programmable dividers. pll2013x con- sists of a phase/frequency detector (pfd), a charge pump, an external loop filter, a voltage controlled oscillator (vco), a 6-bit pre-divider, an 8-bit main divider and a 2-bit post scaler as shown in figure 6-1 features ? 0.25 m m cmos device technology ? 2.5v single power supply ? output frequency range: 20-170mhz ? jitter: 150 ps at 170mhz ? duty ratio: 45% to 55% (all tuned range) ? frequency changed by programmable dividers ? provision for 14.318mhz crystal oscillator buffer (option) ? lock detector (option) ? power down mode
pll2013x 20 mhz-170mhz fspll stdm110 6-2 samsung asic pin description figure 6-2 core con?guration name i/o type i/o pad pin description vddd digital power vddd digital power supply vssd digital ground vssd digital ground vdda analog power vdda analog power supply vssa analog ground vssa analog ground vbb analog sub bias /digital sub bias vbba analog / digital sub bias fin digital input pic_bb reference frequency input filter analog output poa_bb pump out is connected to filter. a capacitor is connected between the pin and analog ground. fout digital output pot8_bb 20mhz~170mhz clock output pwrdn digital input pic_bb fspll clock power down. - when pwrdn is high, pll do not operate. - if pwrdn is not used, it should be tied to vss. p[5:0] digital input pic_bb the values for 6bit programmable pre-divider. m[7:0] digital input pic_bb the values for 8bit programmable main divider. s[1:0] digital input pic_bb the values for 2bit programmable post scaler. fout filter m[7:0] fin pwrdn pll2013x m[0] m[1] m[2] m[3] m[4] m[5] m[6] m[7] p[5:0] p[0] p[1] p[2] p[3] p[4] p[5] s[1:0] s[0] s[1]
20 mhz-170mhz fspll pll2013x samsung asic 6-3 stdm110 absolute maximum ratings (ta=25 c) notes : 1. absolute maximum rating specifies the values beyond which the device may be damaged permanently. exposure to absolute maximum rating conditions for extended periods may affect reliability. each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. all voltages are measured with respect to vss unless otherwise specified. 3. 100pf capacitor is discharged through a 1.5k w resistor (human body model) recommended operating conditions note: it is strongly recommended that all the supply pins (vdda, vddd) be powered from the same operating supply voltage to avoid power latch-up. characteristics symbol value unit applicable pin supply voltage vddd, vdda 3.3 v vddd,vdda,vssd, vssa,vbb voltage on any digital pin vin vssd-0.25 to vddd+0.25 v p[5:0],m[7:0],s[1:0] pwrdn operating temperature topr 0 to 70 c- storage temperature tstg -45 to 125 c- characteristics symbol min typ max unit supply voltage vddd - vdda -0.1 +0.1 v oscillator frequency fosc 14.318 mhz external loop ?lter capacitance lf 820 pf operating temperature topr 0 70 c
pll2013x 20 mhz-170mhz fspll stdm110 6-4 samsung asic dc electrical characteristics ac electrical characteristics note: it is strongly recommended that input signal is not generated glitch, but if customer cannot help generating glitch, customer must carefully considerate the specification. characteristics symbol min typ max unit operating voltage vddd/vdda 2.375 2.5 2.625 v digital input voltage high v ih 2.0 v digital input voltage low v il 0.8 v dynamic current idd 3 ma power down current ipd 50 m a characteristics symbol min typ max unit crystal frequency f xtal 14.318 mhz input frequency f in 5 40 mhz output clock frequency f out 20 170 mhz input clock duty cycle t id 40 60 % output clock duty cycle (at 170mhz) t od 45 55 % input glitch pulse width t igp 1ns locking time t lt 150 m s jitter, cycle to cycle t jcc -150 + 150 ps
20 mhz-170mhz fspll pll2013x samsung asic 6-5 stdm110 functional description a pll is the circuit synchronizing an output signal (generated by an vco) with a reference or input signal in frequency as well as in phase. in this application, it includes the following basic blocks. the voltage-controlled oscillator to generate the output frequency the divider p divides the reference frequency by p the divider m divides the vco output frequency by m the divider s divides the vco output frequency by s the phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. the loop filter removes the high frequency components in charge pump voltage and gives smooth and clean control to vco the m, p, s values can be programmed by 16bit digital data from the external source. so the pll can be locked in the desired frequency. fout = (m fin) / (p s) where fin = 14.318 mhz, m = m + 8, p = p + 2, s = 2 s table 6-1 digital data format notes: 1. s[1]-s[0]: output frequency scaler 2. m[7]-m[0]: vco frequency divider 3. p[5]-p[0]: reference frequency input divider main divider pre divider post scaler m7, m6, m5, m4, m3, m2, m1, m0 p5, p4, p3, p2, p1, p0 s1, s0
pll2013x 20 mhz-170mhz fspll stdm110 6-6 samsung asic output frequency equation & table frequency equation: table 6-2 example of divider ratio core evaluation guide for the embedded pll, we must consider the test circuits for the embedded pll core in multiple applications. hence the following requirements should be satisfied. the filter and fout pins must be bypassed for external test. for pll test (below 2 examples), it is needed to control the dividers - m[7:0], p[5:0] and s[1:0] - that generate multiple clocks. #1. registers can be used for easy control of divider values. #2. n sample bits of 16-bit divider pins can be bypassed for test using mux. figure 6-3 pll functional block diagram m7 m6 m5 m4 m3 m2 m1 m0 m m(m+8) s1 s0 2 s 01010101 85 93 001 p6 p5 p4 p3 p2 p1 p0 p p(p+2) 010101042 44 f out m8 + () p2 + () 2 s ---------------------------- - f in = fout filter m[7:0] fin pwrdn pll2013x p[5:0] s[1:0] external clock source #1. 16-bit register block #2. mux select pin test pins of n sample bits internal divider signal line gnd 2.5v digital power gnd 2.5v analog power 820pf vssa vddd vssd vdda vssa vbb : 10 m f electronic capacitor, unless otherwise speci?ed : 104 ceramic capacitor, unless otherwise speci?ed
20 mhz-170mhz fspll pll2013x samsung asic 6-7 stdm110 figure 6-4 the example of pll block with dedicated 14.318 mhz xtal-osc xtal buffer cell figure 6-5 xtal pad symbol - a xtal buffer cell for pll is supported mdl111 databook of sec - the xtal must be located between pada and padb. enable pin (e) must be high in normal operation. - pi pin must be connected to vddd and the po pin ?oated. lock detector figure 6-6 lock detector block the built-in lock detector circuit will only work, when it is used in conjunction with pfd block output up/down xtalin ldout fout xtalout glue logic filter mux xtal osc fin pfd p[5:0] lf divider m scaler s m[7:0] s[1:0] divider p vco ld & cp up down pwrdn * optional test pin *divider bus e pa da padb pi yn po internal up signal internal down signal ls ldout lo lock state detector
pll2013x 20 mhz-170mhz fspll stdm110 6-8 samsung asic signal. (refer to figure 6-6) we represent the output of lock detector in the timing diagram. (refer to figure 6-7) figure 6-7 lock detector timing diagram package configuration up/down ldout lo lock unlock pll2013x 48 47 44 46 45 43 42 41 40 39 38 37 36 35 34 33 30 32 31 29 28 27 26 25 12 5 34 6789101112 p4 p5 tst3 tst1 tst2 nc nc nc nc ldout vssa vssa 24 23 20 22 21 19 18 17 16 15 14 13 nc fout vbb nc nc vbb pwrdn filter xtalout xtalin vdda vdda p3 p2 m7 p1 p0 m6 m5 m4 m3 m2 m1 m0 vddd vddd vssd vssd s1 vddo vsso nc nc so tst4 tst5 lh lh lh lh lh lh lh lh lh lh lh lh 8-bit main divider 6-bit pre divider input h l h l c 2.5v analog power c h l h l c c 2.5v digital power 2-bit post scaler 2.5v i/o power hl c 2.5v analog power 820pf 25pf 25pf external source clock c 104 10 m f
20 mhz-170mhz fspll pll2013x samsung asic 6-9 stdm110 package pin description notes: 1. i/o type pp and pg denote pad power and pad ground respectively. 2. xtalin, xtalout, ldout is test pin for pll in samsung. name pin no. i/o type pin description vddd 35,36 dp digital power supply vssd 33,34 dg digital ground vbb 19,20 ab/db analog / digital sub bias pwrdn 18 di fspll clock power down. - when pwrdn is high, pll do not operate. - if pwrdn is not used, it should be tied to vss. p[0]~p[5] 45~48,1,2 di pre-divider input vdda 13,14 ap analog power supply vssa 11,12 ag analog ground xtalin 15 ai crystal external clock input xtalout 16 ao xtal buffer output clock fout 23 do 20mhz~170mhz clock output ldout 10 do lock detector output filter 17 ao pump out is connected to the filter. a 900pf capacitor is con- nected between the pin and analog pin s[0]~s[1] 32,31 di post scaler input m[0]~m[7] 37~44 di 8-bit main divider input vddo 28 pp i/o pad power vsso 27 pg i/o pad power
pll2013x 20 mhz-170mhz fspll stdm110 6-10 samsung asic pll components figure 6-8 is the block diagram of the components of a pll: the phase detector, charge pump, voltage con- trolled oscillator, and loop filter. in samsung technology, the loop filter is implemented as external components close to the chip. figure 6-8 pll functional block diagram n phase detector: the phase detector monitors the phase difference between the fref and fvco, and generates a control signal when it detects difference between the two. if the fref frequency is higher then the fvco frequency, its falling edge occurs before (lead) the falling edge of the fvco output. when this occurs the phase detector signals the vco to increase the frequency of the on-chip clock. if the falling edge of the fref occurs after (lag) the falling edge of the fvco output, the detector signals the vco to decrease on-chip clock frequency. figure 6-9 illustrates the lead and lag conditions. if the frequencies of the fref and fvco are the same, the detect or does not generate a control signal, so the frequencies remain the same. figure 6-9 lead and lag clocking relationship n charge pump: the charge pump converts the phase detector control signal to a charge in voltage across the external filter that drives the vco. as the voltage controlled oscillator decreases, or increases, if the voltage remains con- stant, the frequency of the oscillator remains constant. xtalin pfd xtalout p[5:0] pump voltage controlled oscillator divider m divider s m[7:0] s[1:0] filter r c1 c2 r,c2: internal c1: external divider p xtal osc fref fvco fout pwrdn fref clk fvco clk up down
20 mhz-170mhz fspll pll2013x samsung asic 6-11 stdm110 n loop filter: the control signal that the phase detector generates for the charge pump may generate large excursions (rip- ples) each time the vco output is compared to the system clock. to avoid overloading the vco, a low pass filter samples and filters the high-frequency components out of the control signal. the filter is typically a sin- gle-pole rc filter consisting of a resistor and capacitor. n voltage controlled oscillator (vco): the output voltage from the loop filter drives the vco, causing its oscillation frequency to increase or de- crease as a function of variations in voltage. when the vco output matches the system clock in frequency and phase, the phase detector stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter. the vco frequency then remains constant, and the pll remains locked onto the system clock. frequency synthesis frequency synthesis uses the system clock as a base frequency to generate higher/lower frequency clocks for internal logic. for high speed applications in high-end designs, transmission line effects cause problems because of para- sitic and impedance mismatch among various on-board components. these problems can be eliminated by moving the high frequency to the chip level. on-chip clocks that are faster than the external system clock can be synthesized by inserting a divider in the feedback path. the divider is placed after voltage controlled os- cillator, as illustrated in figure 6-11. the signal is running at m times the system clock frequency, so the pll matches the divider signal output to the system clock. this configuration reduces the problem of interfacing to the system clock on the board, and it reduces the noise generated by the system clock oscillator and driver for all the components in the system. design considerations the following design considerations apply: ? phase tolerance and jitter are independent of the pll frequency. ? jitter is affected by the noise frequency in the power (vddd/vssd, vdda/vssa). it increases when the noise level increases. ? a cmos-level input reference clock is recommend for signal compatibility with the pll circuit. other levels such as ttl may degrade the tolerances. ? the used of two, or more plls requires special design considerations. please consult your application engineer for more information. ? the following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - use wide pcb traces for power (vddd/vssd, vdda/vssa, vbb) connections to the pll core. - separate the traces from the chips vddd/vssd, vdda/vssa supplies. - use proper vddd/vssd, vdda/vssa de-coupling. - use good power and ground sources on the board. - use power vbb for minimize substrate noise. ? the pll core should be placed as close as possible to the dedicated loop ?lter and analog power and ground pins. ? it is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the pll i/o cells. ? other related i/o signals should be placed near the pll i/o but do not have any pre-de?ned placement restriction.
20 mhz-170mhz fspll pll2013x samsung asic 6-12 stdm110 pll speci?cation we appreciate your interest in our products. if you have further questions, please specify in the attached form. thank you very much. ? do you need xtal driver buffer in pll core? if you need it, what is the crystal frequency range? if not, what is the input frequency range? ? do you need the lock detector? ? do you need the i/o cell of samsung? ? do you need the external pin for pll test? ? what is the main frequency and frequency range? ? how many fsplls do you use in your system? ? what is output loading? ? could you internal/external pin configurations as required? ? specially requested function list: parameter min typ max unit remarks supply voltage output frequency range input frequency range cycle-to-cycle jitter lock up time dynamic current standby current output clock duty ratio long term jitter output slew rate

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