functional block diagram rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos parallel loading dual 12-bit dac AD7547 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 general description the AD7547 contains two 12-bit current output dacs on one monolithic chip. also on-chip are the level shifters, data regis- ters and control logic for easy microprocessor interfacing. there are 12 data inputs. csa , csb , wr control dac selection and loading. data is latched into the dac registers on the rising edge of wr . the device is speed compatible with most micro- processors and accepts ttl, 74hc and 5 v cmos logic level inputs. the d/a converters provide 4-quadrant multiplication capabili- ties with separate reference inputs and feedback resistors. monolithic construction ensures that thermal and gain error tracking is excellent. 12-bit monotonicity is guaranteed for both dacs over the full temperature range. the AD7547 is manufactured using the linear compatible cmos (lc 2 mos) process. this allows fast digital logic and precision linear circuitry to be fabricated on the same die. features two 12-bit dacs in one package dac ladder resistance matching: 0.5% space saving skinny dip and surface mount packages 4-quadrant multiplication low gain error (1 lsb max over temperature) fast interface timing applications automatic test equipment programmable filters audio applications synchro applications process control product highlights 1. dac to dac matching since both dacs are fabricated on the same chip, precise matching and tracking is inherent. many applications which are not practical using two discrete dacs are now possible. typical matching: 0.5%. 2. small package size the AD7547 is available in 0.3" wide 24-pin dips and soics and in 28-terminal surface mount packages. 3. wide power supply tolerance the device operates on a +12 v to +15 v v dd , with 10% tolerance on this nominal figure. all specifications are guar- anteed over this range.
rev. a C2C AD7547Cspecifications 1 parameter j, a versions k, b versions l, c versions s version t version u version units test conditions/comments accuracy resolution 12 12 12 12 12 12 bits relative accuracy 1 1/2 1/2 1 1/2 1/2 lsb max differential nonlinearity 1 1 1 1 1 1 lsb max all grades guaranteed monotonic over temperature. gain error 6 3 l 6 3 2 lsb max both dac registers loaded with all 1s. gain temperature coefficient 2 ; d gain/ d temperature 5 5 5 5 5 5 ppm/ c max typical value is 1 ppm/ c output leakage current i outa +25 c 10 10 10 10 10 10 na max dac a register loaded t min to t max 150 150 150 250 250 250 na max with all 0s. i outb +25 c 10 10 10 10 10 10 na max dac b register loaded t min to t max 150 150 150 250 250 250 na max with all 0s. reference input input resistance 9 9 9 999k w min typical input resistance = 14 k w 20 20 20 20 20 20 k w max v refa , v refb input resistance match 3 3 1 3 3 1 % max typically 0.5% digital inputs v ih (input high voltage) 2.4 2.4 2.4 2.4 2.4 2.4 v min v il (lnput low voltage) 0.8 0.8 0.8 0.8 0.8 0.8 v max i in (input current) +25 c 1 1 1 1 1 1 m a max v in = v dd t min to t max 10 10 10 10 10 10 m a max c in (input capacitance) 2 10 10 10 10 10 10 pf max power supply 3 v dd 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 v min/v max i dd 2 2 2 2 2 2 ma max ac performance characteristics these characteristics are included for design guidance only and are not subject to test. (v dd = +12 v to +15 v; v refa = v refb = +10 v, i outa = i outb = agnd = 0 v. output amplifiers are ad644 except where noted.) parameter t a = +25 8 ct a = t min , t max units test conditions/comments output current settling time 1.5 m s max to 0.01 % of full-scale range. i out load = 100 w , c ext = 13 pf. dac output measured from rising edge of wr . typical value of settling time is 0.8 m s. digital-to-analog glitch impulse 7 nv-s typ measured with v refa = v refb = 0 v. i outa , i outb load = 100 w , c ext = 13 pf. dac registers alternately loaded with all 0s and all 1s. ac feedthrough 4 v refa to i outa C70 C65 db max v refa , v refb = 20 v p-p, 10 khz sine wave. dac v refb to i outb C70 C65 db max registers loaded with all 0s. power supply rejection d gain/ d v dd 0.01 0.02 % per % max d v dd = v dd max C v dd min output capacitance c outa 70 70 pf max dac a, dac b loaded with all 0s. c outb 70 70 pf max c outa 140 140 pf max dac a, dac b loaded with all 1s. c outb 140 140 pf max channel-to-channel isolation v refa to i outb C84 db typ v refa = 20 v p-p 10 khz sine wave, v refb = 0 v. both dacs loaded with all 1s. v refb to i outa C84 db typ v refb = 20 v p-p 10 khz sine wave, v refa = 0 v. both dacs loaded with all 1s. digital crosstalk 7 nv-s typ measured for a code transition of all 0s to all 1s. i outa , i outb load = 100 w , c ext = 13 pf output noise voltage density 25 nv/ ? hz typ measured between r fba and i outa or r fbb and i outb . (10 hzC100 khz) frequency of measurement is 10 hzC100 khz. total harmonic distortion C82 db typ v in = 6 v rms, 1 khz. both dacs loaded with all 1s. notes 1 temperature range as follows: j, k, l versions, C40 c to +85 c; a, b, c versions, C40 c to +85 c; s, t, u versions, C55 c to +125 c. 2 sample tested at +25 c to ensure compliance. 3 functional at v dd = 5 v with degraded specifications. 4 pin 12 (dgnd) on ceramic dips is connected to lid. specifications subject to change without notice. (v dd = +12 v to +15 v, 6 10%, v refa = v refb = 10 v; i outa = i outb = agnd = o v. all specifications t min to t max unless otherwise noted.)
AD7547 rev. a C3C timing characteristics limit at limit at limit at t a = C40 8 ct a = C55 8 c parameter t a = +25 8 c to +85 8 c to +125 8 c units test conditions/comments t 1 60 80 80 ns min data setup time t 2 25 25 25 ns min data hold time t 3 80 80 100 ns min chip select to write setup time t 4 0 0 0 ns min chip select to write hold time t 5 80 80 100 ns min write pulse width specifications subject to change without notice. (v dd = 10.8 v to 16.5 v, v refa = v refb = +10 v, i outa = i outb = agnd = 0 v) absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +17 v v refa , v refb to agnd . . . . . . . . . . . . . . . . . . . . . . . . . 25 v v rfba , v rfbb to agnd . . . . . . . . . . . . . . . . . . . . . . . . . 25 v digital input voltage to dgnd . . . . . . . C0.3 v, v dd +0.3 v i outa , i outb to dgnd . . . . . . . . . . . . . . C0.3 v, v dd +0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . C0.3 v, v dd +0.3 v power dissipation (any package) to +75 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mw derates above +75 c . . . . . . . . . . . . . . . . . . . . . . 6 mw/ c operating temperature range commercial plastic (j, k, l versions) . . . . C40 c to +85 c industrial hermetic (a, b, c versions) . . . C40 c to +85 c extended hermetic (s, t, u versions) . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table i. AD7547 truth table csa csb wr function x x 1 no data transfer 1 1 x no data transfer gg 0 a rising edge on csa or csb loads data to the respective dac from the data bus 01 g dac a register loaded from data bus 10 g dac b register loaded from data bus 00 g dac a and dac b registers loaded from data bus notes 1. x = dont care. 2. g means rising edge triggered. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7547 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. figure 1. timing diagram ordering guide 1 temperature relative gain package model 2 range accuracy error option 3 AD7547jn C40 c to +85 c 1 lsb 6 lsb n-24 AD7547kn C40 c to +85 c 1/2 lsb 3 lsb n-24 AD7547ln C40 c to +85 c 1/2 lsb 1 lsb n-24 AD7547jp C40 c to +85 c 1 lsb 6 lsb p-28a AD7547kp C40 c to +85 c 1/2 lsb 3 lsb p-28a AD7547lp C40 c to +85 c 1/2 lsb 1 lsb p-28a AD7547jr C40 c to +85 c 1 lsb 6 lsb r-24 AD7547kr C40 c to +85 c 1/2 lsb 3 lsb r-24 AD7547lr C40 c to +85 c 1/2 lsb 1 lsb r-24 AD7547aq C40 c to +85 c 1 lsb 6 lsb q-24 AD7547bq C40 c to +85 c 1/2 lsb 3 lsb q-24 AD7547cq C40 c to +85 c 1/2 lsb 1 lsb q-24 AD7547sq C55 c to +125 c 1 lsb 6 lsb q-24 AD7547tq C55 c to +125 c 1/2 lsb 3 lsb q-24 AD7547uq C55 c to +125 c 1/2 lsb 2 lsb q-24 AD7547se C55 c to +125 c 1 lsb 6 lsb e-28a AD7547te C55 c to +125 c 1/2 lsb 3 lsb e-28a AD7547ue C55 c to +125 c 1/2 lsb 2 lsb e-28a notes 1 analog devices reserves the right to ship ceramic packages (d-24a) in lieu of cerdip packages (q-24). 2 to order mil-std-883, class b processed parts, add /883b to part number. contact your local sales office for military data sheets. 3 e = leadless ceramic chip carrier; n = plastic dip; p = plastic leaded chip carrier; q = cerdip; r = soic.
AD7547 rev. a C4C pin configurations dip, soic lccc plcc pin function description (dip) pin mnemonic description 1 1 agnd analog ground. 1 2i outa current output terminal of dac a. 1 3r fba feedback resistor for dac a. 1 4v refa reference input to dac a. 1 5 csa chip select input for dac a. active low. 6C18 db0Cdb11 12 data inputs, db0 (lsb)Cdb11 (msb). 12 dgnd digital ground. 19 wr write input. data transfer occurs on rising edge of wr . see table i. 20 csb chip select input for dac b. active low. 21 v dd power supply input. nominally +12 v to +15 v with 10% tolerance. 22 v refb reference input to dac b. 23 r fbb feedback resistor of dac b. 24 i outb current output terminal of dac b. equivalent circuit analysis figure 3 shows the equivalent circuit for one of the d/a con- verters (dac a) in the AD7547. a similar equivalent circuit can be drawn for dac b. note that agnd is common to both dac a and dac b. figure 3. equivalent analog circuit for dac a c out is the output capacitance due to the n-channel switches and varies from about 50 pf to 150 pf with digital input code. the current source i lkg is composed of surface and junction leakages and approximately doubles every 10 c. r o is the equivalent output resistance of the device which varies with input code. digital circuit information the digital inputs are designed to be both ttl and 5 v cmos compatible. all logic inputs are static-protected mos gates with typical input currents of less than 1 na. circuit information d/a section the AD7547 contains two identical 12-bit multiplying d/a con- verters. each dac consists of a highly stable r-2r ladder and 12 n-channel current steering switches. figure 2 shows a simpli- fied d/a circuit for dac a. in the r-2r ladder, binary weighted currents are steered between i outa and agnd. the current flowing in each ladder leg is constant, irrespective of switch state. the feedback resistor r fba is used with an op amp (see figures 4 and 5) to convert the current flowing in i outa to a voltage output. figure 2. simplified circuit diagram for dac a
AD7547 rev. a C5C bipolar operation (4-quadrant multiplication) the recommended circuit diagram for bipolar operation is shown in figure 5. offset binary coding is used. with the appropriate dac register loaded to 1000 0000 0000, adjust r1 (r3) so that v outa (v outb ) = 0 v. alternatively, r1, r2 (r3, r4) may be omitted and the ratios of r6, r7 (r9, r10) varied for v out a (v outb ) = 0 v. full-scale trimming can be accomplished by adjusting the amplitude of v in or by vary- ing the value of r5 (r8). if r1, r2 (r3, r4) are not used, then resistors r5, r6, r7 (r8, r9, r10) should be ratio matched to 0.01% to ensure gain error performance to the data sheet specification. when operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. the code table for figure 5 is given in table iii. figure 5. bipolar operation (offset binary coding) table iii. bipolar code table for offset binary circuit of figure 5 binary number in dac register analog output, msb lsb v outa or v outb 1111 1111 1111 + v in 2047 2048 ? ? ? ? 1000 0000 0001 + v in 1 2048 ? ? ? ? 1000 0000 0000 0 v 0111 1111 1111 v in 1 2048 ? ? ? ? 0000 0000 0000 v in 2048 2048 ? ? ? ? = v in unipolar binary operation (2-quadrant multiplication) figure 4 shows the circuit diagram for unipolar binary operation. with an ac input, the circuit performs 2-quadrant multiplica- tion. the code table for figure 4 is given in table ii. operational amplifiers a1 and a2 can be in a single package (ad644, ad712) or separate packages (ad544, ad711, ad op27). capacitors c1 and c2 provide phase compensation to help prevent overshoot and ringing when high speed op amps are used. for zero offset adjustment, the appropriate dac register is loaded with all 0s and amplifier offset adjusted so that v outa or v outb is 0 v. full-scale trimming is accomplished by loading the dac register with all 1s and adjusting r1 (r3) so that v outa (v outb ) = C v in (4095/4096). for high temperature operation, resistors and potentiometers should have a low tem- perature coefficient. in many applications, because of the excel- lent gain t.c. and gain error specifications of the AD7547, gain error trimming is not necessary. in fixed reference applica- tions, full-scale can also be adjusted by omitting r1, r2, r3, r4 and trimming the reference voltage magnitude. figure 4. unipolar binary operation table ii. unipolar binary code table for circuit of figure 4 binary number in dac register analog output, msb lsb v outa or v outb 1111 1111 1111 v in 4095 4096 ? ? ? ? 1000 0000 0000 v in 2048 4096 ? ? ? ? = 1/ 2 v in 0000 0000 0001 v in 1 4096 ? ? ? ? 0000 0000 0000 0 v
programmable state variable filter the circuit shown in figure 6 provides three filter outputs: low pass, high pass and bandpass. it is called a state variable filter and the particular version shown in figure 6 uses two AD7547s to control the critical parameters f o , q and a o . instead of sev- eral fixed resistors, the circuit uses the dac equivalent resis- tances as circuit elements. thus, r1 in figure 6 is controlled by the 12-bit digital word loaded to dac a of the AD7547. this is also the case with r2, r3 and r4. the fixed resistor r5 is the feedback resistor, r fbb . dac equivalent resistance, req = 4096 r lad n where r lad = dac ladder resistance where n = dac digital code in decimal. (0AD7547 have termination resistors which are tied to the agnd line within the device. this ar- rangement is ideal for single supply operation because agnd may be biased at any voltage between dgnd and v dd . fig- ure 7 shows a circuit which provides two +5 v to +10 v analog outputs by biasing agnd to +5 v with respect to dgnd, which in this case is also the system ground. the two dac ref- erence inputs are also tied to system ground. AD7547Capplications rev. a C6C figure 7. AD7547 single supply operation the transfer function for each channel is: v out = 5 v 1 + r fb r eq ? ? ? ? with all 0s loaded to the dac, r eq = and v out = +5 v. with all 1s loaded r eq = r ladder = r fb and v out = +10 v. figure 8 shows both dacs of the AD7547 connected in the voltage switching mode. for further information on this mode of operation see the cmos dac application guide from ana- log devices, publication number g872a-15-4/86. to optmize performance when using this circuit, v in must be in the range 0 v to +1.25 v and the output buffered. v in must be driven from a low impedance source (e.g., a buffer amplifier). figure 9 shows how differential linearity degrades with increasing v in . figure 8. AD7547 operated in single supply, voltage switching mode
AD7547 rev. a C7C figure 9. differential nonlinearity vs. reference voltage for circuit of figure 8. v dd = 15 v. shaded area shows range of values of differential nonlinearity that typically occur for l, c and u grades application hints output offset: cmos d/a converters in circuits such as fig- ures 4 and 5 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier. the maximum amplitude of this error, which adds to the d/a converter nonlinearity, depends on v os , where v os is the amplifier input offset voltage. to maintain specified operation, it is recommended that v os be no greater than (25 10 C6 )(v ref ) over the temperature range of operation. suitable op amps are the ad711c and its dual version, the ad712c. these op amps have a wide bandwidth and high slew rate and are recommended for wide bandwidth ac applications. ad711/ ad712 settling time to 0.01% is typically 1 m s. temperature coefficients: the gain temperature coefficient of the AD7547 has a maximum value of 5 ppm/ c and typical value of 1 ppm/ c. this corresponds to worst case gain shifts of 2 lsbs and 0.4 lsbs respectively over a 100 c temperature range. when trim resistors r1(r3) and r2(r4) are used to ad- just full-scale range as in figure 4, the temperature coefficient of r1(r3) and r2(r4) should also be taken into account. for further information see gain error and gain temperature coefficient of cmos multiplying dacs, application note, publication number e630c-5-3/86 available from analog devices. high frequency considerations: AD7547 output capaci- tance works in conjunction with the amplifier feedback resis- tance to add a pole to the open loop response. this can cause ringing or oscillation. stability can be restored by adding a phase compensation capacitor in parallel with the feedback re- sistor. this is shown as c1 and c2 in figures 4 and 5. feedthrough: the dynamic performance of the AD7547 de- pends upon the gain and phase stability of the output amplifier, together with the optimum choice of pc board layout and de- coupling components. a suggested printed circuit layout for figure 4 is shown in figure 10 which minimizes feedthrough from v refa , v refb to the output in multiplying applications. figure 10. suggested layout for circuit of figure 4 microprocessor interfacing the AD7547 is designed for easy interfacing to 16-bit micro- processors. figures 11 and 12 show the interface circuits for two of the most popular 16-bit microprocessors; the 8086 and the 68000. note that the amount of external logic needed is minimal. since data is loaded into the dac registers on the rising edge of wr, the possibility of invalid data being loaded temporarily to the dac is removed. this considerably eases the interface cir- cuit design. figure 11. AD7547-mc68000 interface figure 12. AD7547-8086 interface
AD7547 rev. a C8C outline dimensions dimensions shown in inches and (mm). c977bC5C6/88 printed in u.s.a. 24-pin plastic dip (n-24) 28-terminal plastic leaded chip carrier (p-28a) 24-pin cerdip (q-24) 24-pin ceramic dip (d-24a) 28-terminal leadless ceramic chip carrier (e-28a)
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