asahi kasei [akd5702-a] 2007 / 04 - 1 - general description akd5702-a is an evaluation board for the portable digital audio 16bit a/d converter with mic-amp, AK5702. akd5702-a also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. ? ordering guide akd5702-a --- AK5702 evaluation board (cable for connecting with printer port of ibm-at compatible pc and control software are packed with this. this control software does not support windows nt.) function ? dit with optical output ? bnc connector for an external clock input ? 10pin header for serial control interface ak4114 (dit) 10pin header control data 10pin header dgnd opt out AK5702 vd avdd dsp 2 dvdd agnd mic3/4/5 5v regulator 3.0v 10pin header tdm ext_bclk lin3/4/5 ext_lrck clock gen rin3/4/5 mic1/2/5 lin1/2/5 rin1/2/5 ext_mclk opt in 10pin header dsp 1 figure 1. akd5702-a block diagram * circuit diagram and pcb layout are attached at the end of this manual. AK5702 evaluation board rev.1 a kd5702- a
asahi kasei [akd5702-a] 2007 / 04 - 2 - evaluation board manual ? operation sequence 1) set up the power supply lines. 1-1) when avdd, dvdd and vd are supplied from the regulator. (default) [reg] (red) = 5v [avdd] (orange) = open (3.0v, supply from regulator, for avdd of AK5702) [dvdd] (orange) = open (3.0v, supply from regulator, for dvdd of AK5702) [vd] (orange) = 2.7 3.6v (typ. 3.0v, for logic of digital part) [agnd] (black) = 0v (for analog ground) [dgnd] (black) = 0v (for digital ground) 1-2) when avdd, dvdd and vd are not supplied from the regulator. [reg] (red) = open [avdd] (orange) = 2.4 3.6v (typ. 3.0v, for avdd of AK5702) [dvdd] (orange) = 1.6 3.6v (typ. 3.0v, for dvdd of AK5702) [vd] (orange) = 2.7 3.6v (typ.3.0v, for logic of digital part) [agnd] (black) = 0v (for analog ground) [dgnd] (black) = 0v (for digital ground) each supply line should be distributed from the power supply unit. 2) set up the evaluation mode, jumper pins and dip switches. (see the followings.) 3) power on. the AK5702 and ak4114 should be reset once by bringing sw1, 2 ?l? upon power-up. ? evaluation mode in case of AK5702 evaluation using ak4114, same audio interface format should be set for both AK5702 and ak4114. about AK5702?s audio interface format, refer to datasheet of AK5702. about ak4114?s audio interface format, refer to table 2 in this manual. applicable evaluation mode (1) pll master mode (default) (2) pll slave mode 1 (pll reference clock: mcki pin) (3) pll slave mode 2 (pll reference clock: bclk or lrck pin) (4) ext slave mode (5) ext master mode
asahi kasei [akd5702-a] 2007 / 04 - 3 - (1) pll master mode (default) * connect port4 (dsp1) with dsp. figure below shows port4 pin assign. port4 gnd gnd nc nc sdtob vd sdtoa lrck bclk mcko a) set up jumper pins of mcki clock when using x?tal as mcki clock, x?tal of 11.2896mhz, 12mhz, 12.288mhz, 13mhz, 24mhz or 27mhz can be set to x1. x?tal of 11.2896mhz (default) is set on the akd5702-a. when an external clock (11.2896mhz, 12mhz, 12.288mhz, 13mhz, 24mhz or 27mhz) is supplied through a bnc connector j1 (ext_mcki), select ext_mclk on jp16 (xti) and select ext on jp7 (mclk_sel). jp12 (ext) and r19 should be properly selected in order to match the output impedance of the clock generator. jp7 mcki_sel jp5 tdmmclk_sel jp8 mkfs dit ext 256fs 512fs jp16 xti ext_mclk mcko 1024fs 384/768fs mcko ext_mclk 384fs-768 jp32 mclk_sel mcko ext_mclk *the setting of jp8(mkfs) is invalid in this mode,but if jp8( mkfs) is open, the input of the buffer will be unstable. so jp8(mkfs) should set up any. b) set up jumper pins of bclk clock output frequency (32fs/64fs) of bclk should be set by ?bcko1-0 bit? in the AK5702. there is no necessity for set up jp9(bclkfs). jp10 bclk_sel jp9 bclkfs 64fs-384 32fs-384 64fs 32fs dit bclkfs bnc_bclk jp28 m/s m s c) set up jumper pins of lrck clock jp13 lrck_sel jp11 lrckfs 2fs-384 1fs-384 2fs 1fs dit lrckfs bnc_lrck
asahi kasei [akd5702-a] 2007 / 04 - 4 - d) set up jumper pins of sdto jp29 sdtob jp30 sdto_sel b a (2) pll slave mode 1 (pll reference clock: mcki pin) * connect port4 (dsp1) with dsp. figure below shows port4 pin assign. port4 gnd gnd nc nc sdtob vd sdtoa lrck bclk mcki a) set up jumper pins of mcki clock x?tal of 11.2896mhz (default) is set on the akd5702-a. in this case, the AK5702 corresponds to pll reference clock of 11.2896mhz. in this evaluation mode, the output clock from mcko pin of the AK5702 is supplied to a divider (u3: 74vhc4040), ext_bclk and ext_lrck clocks are generated by the divider. then ?mcko bit? in the AK5702 should be set to ?1?. when an external clock is supplied through a bnc conn ector j1 (ext_mcki), select ext_mclk on jp16 (xti) and select ext on jp7 (mcki_sel). jp12 (ext) and r19 shoul d be properly selected in order too match the output impedance of the clock generator. jp7 mcki_sel jp5 tdmmclk_sel jp8 mkfs dit ext 256fs 512fs jp16 xti ext_mclk mcko 1024fs 384/768fs mcko ext_mclk 384fs-768 jp32 mclk_sel mcko ext_mclk b) set up jumper pins of bclk clock jp10 bclk_sel jp9 bclkfs 64fs-384 32fs-384 64fs 32fs dit bclkfs bnc_bclk jp28 m/s m s
asahi kasei [akd5702-a] 2007 / 04 - 5 - c) set up jumper pins of lrck clock jp13 lrck_sel jp11 lrckfs 2fs-384 1fs-384 2fs 1fs dit lrckfs bnc_lrck d) set up jumper pins of sdto jp29 sdtob jp30 sdto_sel b a (2-a) in the case of using ak4114. * in this mode, mclk of AK5702 should be supplied from j1 (ext_mcki), and x1 should be open. this mode is bclk=64fs, lrck=1fs only. set up jumper pins of mcki clock jp7 mcki_sel jp5 tdmmclk_sel jp8 mkfs dit ext 256fs 512fs jp16 xti ext_mclk mcko 1024fs 384/768fs mcko ext_mclk 384fs-768 jp32 mclk_sel mcko ext_mclk *the setting of jp8(mkfs) is invalid in this mode,but if jp8(mkfs) is open, the input of the buffer will be unstable. so jp8(mkfs) should set up any. set up jumper pins of bclk clock jp10 bclk_sel jp9 bclkfs 64fs-384 32fs-384 64fs 32fs dit bclkfs bnc_bclk jp28 m/s m s set up jumper pins of lrck clock jp13 lrck_sel jp11 lrckfs 2fs-384 1fs-384 2fs 1fs dit lrckfs bnc_lrck
asahi kasei [akd5702-a] 2007 / 04 - 6 - set up jumper pins of sdto jp29 sdtob jp30 sdto_sel b a (3) pll slave mode 2 (pll reference clock: bclk or lrck pin) * connect port4 (dsp1) with dsp. figure below shows port4 pin assign. port4 gnd gnd nc nc sdtob vd sdtoa lrck bclk mcki a) set up jumper pins of mcki clock jp7 mcki_sel jp5 tdmmclk_sel jp8 mkfs dit ext 256fs 512fs jp16 xti ext_mclk mcko 1024fs 384/768fs mcko ext_mclk 384fs-768 jp32 mclk_sel mcko ext_mclk b) set up jumper pins of bclk clock when an external clock is supplied through a bnc co nnector j2 (ext/bclk), j3 (ext/lrck), jp14 (ext1) and r20, jp15 (ext2) and r21 should be properly selected in order to much the output impedance of the clock generator. jp10 bclk_sel jp9 bclkfs 64fs-384 32fs-384 64fs 32fs dit bclkfs bnc_bclk jp28 m/s m s
asahi kasei [akd5702-a] 2007 / 04 - 7 - c) set up jumper pins of lrck clock jp13 lrck_sel jp11 lrckfs 2fs-384 1fs-384 2fs 1fs dit lrckfs bnc_lrck d) set up jumper pins of sdto jp29 sdtob jp30 sdto_sel b a (4) ext slave mode * connect port4 (dsp1) with dsp. figure below shows port4 pi n assign. in this mode, mcki, bclk and lrck should be supplied from port4. port4 gnd gnd nc nc sdtob vd sdtoa lrck bclk mcki a) set up jumper pins of mcki clock jp7 mcki_sel jp5 tdmmclk_sel jp8 mkfs dit ext 256fs 512fs jp16 xti ext_mclk mcko 1024fs 384/768fs mcko ext_mclk 384fs-768 jp32 mclk_sel mcko ext_mclk b) set up jumper pins of bclk clock jp10 bclk_sel jp9 bclkfs 64fs-384 32fs-384 64fs 32fs dit bclkfs bnc_bclk jp28 m/s m s
asahi kasei [akd5702-a] 2007 / 04 - 8 - c) set up jumper pins of lrck clock jp13 lrck_sel jp11 lrckfs 2fs-384 1fs-384 2fs 1fs dit lrckfs bnc_lrck d) set up jumper pins of sdto jp29 sdtob jp30 sdto_sel b a (4-a) in the case of using ak4114. *this mode is bclk=64fs, lrck=1fs only. the setting of jp16(xti) is open, the clock of ak4114 use x?tal of x1. the signal of mcko, bclk and lrck outputted from ak4114 is inputted into AK5702. set up jumper pins of mcki clock jp7 mcki_sel jp5 tdmmclk_sel jp8 mkfs dit ext 256fs 512fs jp16 xti ext_mclk mcko 1024fs 384/768fs mcko ext_mclk 384fs-768 jp32 mclk_sel mcko ext_mclk *the setting of jp8(mkfs) is invalid in this mode,but if jp8( mkfs) is open, the input of the buffer will be unstable. so jp8(mkfs) should set up any. set up jumper pins of bclk clock jp10 bclk_sel jp9 bclkfs 64fs-384 32fs-384 64fs 32fs dit bclkfs bnc_bclk jp28 m/s m s
asahi kasei [akd5702-a] 2007 / 04 - 9 - set up jumper pins of lrck clock jp13 lrck_sel jp11 lrckfs 2fs-384 1fs-384 2fs 1fs dit lrckfs bnc_lrck set up jumper pins of sdto jp29 sdtob jp30 sdto_sel b a (5) ext master mode * connect port4 (dsp1) with dsp. figure below shows port4 pi n assign. in this mode, mcki should be supplied from port4, but bclk and lrck should not be supplied. port4 gnd gnd nc nc sdtob vd sdtoa lrck bclk mcki a) set up jumper pins of mcki clock jp7 mcki_sel jp5 tdmmclk_sel jp8 mkfs dit ext 256fs 512fs jp16 xti ext_mclk mcko 1024fs 384/768fs mcko ext_mclk 384fs-768 jp32 mclk_sel mcko ext_mclk *the setting of jp8(mkfs) is invalid in this mode,but if jp8( mkfs) is open, the input of the buffer will be unstable. so jp8(mkfs) should set up any. b) set up jumper pins of bclk clock jp10 bclk_sel jp9 bclkfs 64fs-384 32fs-384 64fs 32fs dit bclkfs bnc_bclk jp28 m/s m s
asahi kasei [akd5702-a] 2007 / 04 - 10 - c) set up jumper pins of lrck clock jp13 lrck_sel jp11 lrckfs 2fs-384 1fs-384 2fs 1fs dit lrckfs bnc_lrck d) set up jumper pins of sdto jp29 sdtob jp30 sdto_sel b a ? dip switch set up [sw1] (mode): mode setting of ak4114 on is ?h?, off is ?l?. no. name on (?h?) off (?l?) 1 i2s 2 m/s ak4114 audio format setting see table 2 3 ocks0 4 ocks1 master clock fr equency select see table 3 5 cad1 6 cad0 chip address pin 7 test ?l? 8 i2c p control mode select pin ?h?: i2c, ?l?: 3-wire serial table 1. mode setting resistor for AK5702 set up for ak4114 sw1 m/s dif1 dif0 dif1 dif0 daux 0 1 0 0 0 24bit, left justified master 0 1 1 0 1 24bit, i 2 s master default 1 1 0 1 0 24bit, left justified slave 1 1 1 1 1 24bit, i 2 s slave table 2. setting for AK5702 and ak4114 audio interface format no. ocks1 ocks0 mcko1 x?tal 0 0 0 256fs 256fs default 2 1 0 512fs 512fs table 3. master clock frequency select for ak4114 (stereo mode)
asahi kasei [akd5702-a] 2007 / 04 - 11 - ? other jumper pins set up 1. jp1, jp3 (mpwrb) : connect to mpwrb open : no connect short : connect to mpwrb 2. jp2, jp4 (mpwra) : connect to mpwra open : no connect short : connect to mpwra 3. jp17 (lin125_sel) : select input pin from j4 lin1 : enable to input to lin1 from j4 lin2 : enable to input to lin2 from j4 lin5 : enable to input to lin5 from j4 4. jp18 (rin125_sel) : select input pin from j6 rin1 : enable to inpu t to rin1 from j6 rin2 : enable to input to rin2 from j6 rin5 : enable to input to rin5 from j6 5. jp19 (lin5_sel) : select input connecter to lin5 lin125 : enable to input to lin5 from j4 lin345 : enable to input to lin5 from j7 6. jp20 (rin5_sel) : select input connecter to rin5 rin125 : enable to inpu t to rin5 from j6 rin345 : enable to input to rin5 from j9 7. jp21 (lin345_sel) : select input pin from j7 lin3 : enable to input to lin3 from j7 lin4 : enable to input to lin4 from j7 lin5 : enable to input to lin5 from j7 8. jp22 (rin345_sel) : select input pin from j9 rin3 : enable to inpu t to rin3 from j9 rin4 : enable to input to rin4 from j9 rin5 : enable to input to rin5 from j9 9. jp35 (sdtob_sel) : select input pin to tdmin pdown : connect to gnd sdtob : connect to sdtob 10. jp36 (ctrl_sel) : select for p control mode 3-wire : select to 3-wire i2c : select to i2c 11. jp37 (gnd) : analog ground and digital ground open : separated. short : common. (the connector ?dgnd? should be open.) 12. jp38 (avdd_sel) : avdd of the AK5702 reg : avdd is supplied from the regula tor (?avdd? jack should be open). < default > avdd : avdd is supplied from ?avdd ? jack.
asahi kasei [akd5702-a] 2007 / 04 - 12 - 13. jp39 (dvdd_sel) : dvdd of the AK5702 avdd : dvdd is supplied from ?avdd?. < default > dvdd : dvdd is supplied from ?dvdd ? jack. 14. jp40 (lvc_sel) : supply line selection of logic block of lvc. dvdd : logic block of lvc is supplied from ?dvdd?. < default > vd : logic block of lvc is supplied from ?vd ? jack. ? the function of the toggle sw [sw2] (pdn): power control of AK5702. keep ?h? during normal operation. [sw3] (dit): power control of ak4114. keep ?h? during normal operation. keep ?l? when ak4114 is not used. ? indication for led [led1] (erf): monitor int0 pin of the ak4114. led turns on when some error has occurred to ak4114. ? serial control the AK5702 can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port3 (ctrl) with pc by 10-wire flat cable packed with the akd5702-a 10pin header csn 10 wire flat cable cclk cdti 10pin connector pc connect akd5702-a figure 2. connect of 10 wire flat cable
asahi kasei [akd5702-a] 2007 / 04 - 13 - ? analog input / output circuits (1) input circuits a) lin, rin, mic input circuit lin1 lin5 rin5 rin1 rin1 rin2 rin2 rin5 lin125 lin5 lin3 rin5 rin4 rin3 rin3 rin4 lin345 lin4 jp20 rin5_sel jp21 lin345_sel jp22 rin345_sel lin3 lin4 rin345 lin2 6 4 3 j8 mic345 2 3 1 j7 mr-552ls 2 3 1 j9 mr-552ls r26 (open) r27 (open) jp19 lin5_sel jp17 lin125_sel jp18 rin125_sel lin2 lin1 rin125 6 4 3 j5 mic125 2 3 1 j4 mr-552ls 2 3 1 j6 mr-552ls r24 (open) r25 (open) lin5 figure 3. lin, rin, mic input circuit ? akm assumes no responsibility for the trouble when using the above circuit examples.
asahi kasei [akd5702-a] 2007 / 04 - 14 - 2. control software manual ? set-up of evaluation board and control software 1. set up the akd5702-a according to previous term. 2. connect ibm-at compatible pc with akd5702-a by 10-line type flat cable (packed with akd5702-a). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of c ontrol software driver by akm device control software?. in case of windows95/98/me, this installation is not needed. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?AK5702 ev aluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd5702-a.exe? to set up the control program. ? operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?port reset? button. 3. click ?write default? button ? explanation of each buttons 1. [port reset]: set up the usb interface board (akdusbif-a) when using the board. 2. [write default]: initialize the register of AK5702. 3. [all write]: write all registers that is currently displayed. 4. [function1]: dialog to write data by keyboard operation. 5. [function2]: dialog to write data by keyboard operation. 6. [function3]: the sequence of regi ster setting can be set and executed. 7. [function4]: the sequence that is created on [f unction3] can be assigned to buttons and executed. 8. [function5]: the register setting that is created by [save] function on main window can be assigned to buttons and executed. 9. [save]: save the current register setting. 10. [open]: write the saved values to all register. 11. [write]: dialog to write data by mouse operation. ? indication of data input data is indicated on the register map. red letter indicat es ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet.
asahi kasei [akd5702-a] 2007 / 04 - 15 - ? explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corresponding to each register. click the [write] button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to AK5702, click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers ad dress in 2 figures of hexadecimal. data box: input registers da ta in 2 figures of hexadecimal. if you want to write the input data to AK5702, click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate ivol there are dialogs corresponding to register of 18h and 19h. address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is written to AK5702 by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not return to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to AK5702, click [ok] button. if not, click [cancel] button.
asahi kasei [akd5702-a] 2007 / 04 - 16 - 4. [save] and [open] 4-1. [save] all of current register setting values displayed on the main window are saved to the file. the extension of file name is ?akr?. (1) click [save] button. (2) set the file name and click [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting values saved by [save] are written to the AK5702. the file type is the same as [save]. (1) click [open] button. (2) select the file (*.akr) and click [open] button.
asahi kasei [akd5702-a] 2007 / 04 - 17 - 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. the following is displayed. (2) set the control sequence. set the address, data and interval time. set ?-1? to the address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval="-1". click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 1. [f3] window
asahi kasei [akd5702-a] 2007 / 04 - 18 - 6. [function4 dialog] the sequence file (*.aks) saved by [function3] can be list ed up to 10 files, assigned to buttons and then executed. when [f4] button is clicked, the window as shown in figure 2 opens. figure 2. [f4] window
asahi kasei [akd5702-a] 2007 / 04 - 19 - 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the sequence file (*.aks) saved by [function3]. the sequence file name is displayed as shown in figure 3. ( in case that the selected sequence file name is ?dac_stereo_on.aks?) figure 3. [f4] window (2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save] : the name assign of sequence file displayed on [fun ction4] window can be saved to the file. the file name is ?*.ak4?. [open] : the name assign of sequence file(*.ak4) saved by [save] is loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files used by [save] and [open] function on right side need to be in the same folder. (3) when the sequence is changed in [function3], the sequence fi le (*.aks) should be loaded again in order to reflect the change.
asahi kasei [akd5702-a] 2007 / 04 - 20 - 7. [function5 dialog] the register setting file(*.akr) saved by [save] function on main window can be listed up to 10 files, assigned to buttons and then executed. when [f5] button is clicked, the window as shown in figure 4 opens. figure 4. [f5] window 7-1. [open] buttons on left side and [write] button (1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 5. (in case that the selected file name is ?dac_output.akr?) (2) click [write] button, then the register setting is executed.
asahi kasei [akd5702-a] 2007 / 04 - 21 - figure 5. [f5] window (2) 7-2. [save] and [open] buttons on right side [save] : the name assign of register setting file displaye d on [function5] window can be saved to the file. the file name is ?*.ak5?. [open] : the name assign of register sett ing file(*.ak5) saved by [save] is loaded. 7-3. note (1) all files used by [save] and [open] function on right side need to be in the same folder. (2) when the register setting is changed by [save] button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
asahi kasei [akd5702-a] 2007 / 04 - 22 - revision history date manual revision board revision reason contents 2006/11/28 km086500 0 first edition error correct p2. operation sequence 1) set up the power supply lines 1-1) add (default) to the end of sentence. avdd: open ? open (3.0v, supply from regulator, for avdd of AK5702) dvdd: open ? open (3.0v, supply from regulator, for dvdd of AK5702) vd: for logic ? (typ 3.0v, for logic of digital part) 1-2) ?reg? jack should be open ? open avdd: for avdd of AK5702 (typ.3.0v) ? (typ.3.0v, for avdd of AK5702) dvdd: for dvdd of AK5702 (typ.3.0v) ? (typ.3.0v, for dvdd of AK5702) vd: for logic ? (typ 3.0v, for logic of digital part) p2. evaluation mode applicable evaluation mode (1) evaluation of pll, master mode ? pll master mode (2) evaluation of pll, slave mode ? pll slave mode 1 (3) evaluation of pll, slave mode ? pll slave mode 2 (4) evaluation of ext, slave mode ? ext slave mode (5) ext, master mode ? ext master mode p3-p10 (1) evaluation of pll, master mode ? pll master mode a) set up jumper pins of mcki clock (j1: ext_mcki) ? j1 (ext_mcki) jp8 ? jp8 (mkfs) b) set up jumper pins of bclk clock jp9 ? jp9 (bclkfs) (2) evaluation of pll, slave mode ? pll slave mode 1 a) set up jumper pins of mcki clock (j1: mclk_sel) ? j1 (ext_mcki) (2-a) in the case of using ak4114 j1 ? j1 (ext_mclk) jp8 ? jp8 (mkfs) (3) evaluation of pll, slave mode ? pll slave mode 2 (4) evaluation of ext, slave mode ? ext slave mode connect port4 (dsp1) with dsp in this mode, bclk and lrck should be supplied from port4, but mcki should not be supplied. ? in this mode, mcki, bclk and lrck should be supplied from port4. (4-a) in the case of using ak4114 jp16 ? jp16 (xti) jp8 ? jp8 (mkfs) (5) ext, master mode ? ext master mode a) set up jumper pins of mcki clock jp8 ? jp8 (mkfs) b) set up jumper pins of bclk clock the direction of jumper setup of jp28 (m/s): s (slave) ? m (master) p11. other jumper pins set up 12. jp38 (avdd_sel) open ? reg short ? avdd 2007/04/09 km086501 1 circuit change resistance value, capacitance value change: mcki: r13: 51 ? r100:100, c100: open ? 22p bick: r101: short ? 100, c101: open ? 22p lrck: r102: short ? 100, c102: open ? 22p
asahi kasei [akd5702-a] 2007 / 04 - 23 - important notice ? these products and their specific ations are subject to change without notice. before considering any use or application, consult the asahi kasei mi crosystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or syst ems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for us e as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written cons ent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who dist ributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or dist ributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
a a b b c c d d e e e e d d c c b b a a lin2 rin2 pdn dvdd cad0 rin3 lin3 rin4 lin4 rin5 lin5 rin1 lin1 test 5702_tdmin cdti/sda cclk/scl csn/cad1 5702_mcko i2c 5702_mcki avdd 5702_sdtoa 5702_sdtob 5702_lrck 5702_bclk title size document number rev date: sheet of AK5702 1 akd5702-a a3 16 monday, april 09, 2007 title size document number rev date: sheet of AK5702 1 akd5702-a a3 16 monday, april 09, 2007 title size document number rev date: sheet of AK5702 1 akd5702-a a3 16 monday, april 09, 2007 r10 51 r10 51 1 2 + c15 10u + c15 10u r4 2.2k r4 2.2k 1 2 + c7 1u + c7 1u c16 0.1u c16 0.1u r101 100 r101 100 1 2 3 4 5 6 7 8 cn1 32pin_1 cn1 32pin_1 c14 4.7n c14 4.7n r9 51 r9 51 r6 2.2k r6 2.2k 1 2 + c10 1u + c10 1u r11 10k r11 10k 9 10 11 12 13 14 15 16 cn2 32pin_2 cn2 32pin_2 r8 (open) r8 (open) 1 2 + c4 1u + c4 1u 1 2 + c1 1u + c1 1u jp4 mpwar jp4 mpwar 1 2 + c11 2.2u + c11 2.2u r7 (open) r7 (open) r14 51 r14 51 jp3 mpwbr jp3 mpwbr 1 2 + c6 1u + c6 1u jp1 mpwbr jp1 mpwbr c100 22p c100 22p 1 2 + c2 1u + c2 1u r18 51 r18 51 c101 22p c101 22p r5 2.2k r5 2.2k r15 51 r15 51 r102 100 r102 100 r2 (open) r2 (open) r17 51 r17 51 r3 2.2k r3 2.2k r12 51 r12 51 1 2 + c8 1u + c8 1u jp2 mpwar jp2 mpwar r1 (open) r1 (open) 1 2 + c18 10u + c18 10u 1 2 + c5 1u + c5 1u 17 18 19 20 21 22 23 24 cn3 32pin_3 cn3 32pin_3 r100 100 r100 100 1 2 + c9 1u + c9 1u mpwrb 1 vcom 2 pdn 3 cad0 4 dvdd 5 vss2 6 lrck 7 sdtob 9 sdtoa 10 mcko 11 test 12 tdmin 13 cdti 14 cclk 15 mcki 17 i2c 18 vss1 19 avdd 20 vcoc 21 mpwra 22 lin2 23 rin1 26 lin5 27 rin5 28 lin4 29 rin4 30 lin3 31 rin3 32 bclk 8 csn 16 rin2 24 lin1 25 u1 AK5702 u1 AK5702 c102 22p c102 22p c17 0.1u c17 0.1u c13 (open) c13 (open) c12 0.1u c12 0.1u 25 26 27 28 29 30 31 32 cn4 32pin_4 cn4 32pin_4 1 2 + c3 1u + c3 1u r16 (short) r16 (short)
a a b b c c d d e e e e d d c c b b a a ext_bclk mcko 4114_mcko ext_lrck ext_mclk vd 4114_lrck 4114_bick title size document number rev date: sheet of clock 1 akd5702-a a3 26 monday, april 09, 2007 title size document number rev date: sheet of clock 1 akd5702-a a3 26 monday, april 09, 2007 title size document number rev date: sheet of clock 1 akd5702-a a3 26 monday, april 09, 2007 1024fs 32fs-384 512fs 256fs 64fs 32fs 1fs mcko 2fs 384/768fs 64fs-384 1fs-384 2fs-384 dit ext bnc_bclk bnc_lrck dit dit bclkfs lrckfs 256fs 128fs 384fs-768 ext_mclk jp7 mcki_sel jp7 mcki_sel 1pr 4 1ck 3 1d 2 1clr 1 2pr 10 2ck 11 2d 12 2clr 13 vcc 14 gnd 7 1q 5 1q 6 2q 9 2q 8 u2 74ac74 u2 74ac74 1 2 3 4 5 j3 ext_lrck j3 ext_lrck jp10 bclk_sel jp10 bclk_sel 1 2 3 4 5 j2 ext_bclk j2 ext_bclk c20 0.1u c20 0.1u jp9 bclkfs jp9 bclkfs jp8 mkfs jp8 mkfs c19 0.1u c19 0.1u r19 51 r19 51 a 3 qa 14 b 4 qb 13 c 5 qc 12 d 6 qd 11 rco 15 enp 7 ent 10 clk 2 load 9 clr 1 vcc 16 gnd 8 u4 74ac163 u4 74ac163 c21 0.1u c21 0.1u r21 51 r21 51 jp6 tdmbclk_sel jp6 tdmbclk_sel jp12 ext jp12 ext r20 51 r20 51 jp13 lrck_sel jp13 lrck_sel clk 10 rst 11 q1 9 q2 7 q3 6 q4 5 q5 3 q6 2 q7 4 q8 13 q9 12 q10 14 q11 15 q12 1 vdd 16 vss 8 u3 74hc4040 u3 74hc4040 c22 0.1u c22 0.1u jp15 ext jp15 ext jp5 tdmmclk_sel jp5 tdmmclk_sel jp11 lrckfs jp11 lrckfs jp14 ext jp14 ext 1 2 3 4 5 j1 ext_mcki j1 ext_mcki gnd 7 1a 1 3a 5 5a 11 5y 10 3y 6 1y 2 2y 4 4y 8 6y 12 6a 13 4a 9 2a 3 vcc 14 u5 74hcu04 u5 74hcu04
a a b b c c d d e e e e d d c c b b a a daux vd vd vd ocks0 ocks1 vd vd int0 vd ocks1 ocks0 4114_mcko ext_mclk mcko 4114_bick 4114_lrck cad0 test i2c dvdd cad1 vd 4114_pdn title size document number rev date: sheet of dit 1 akd5702-a a3 36 monday, april 09, 2007 title size document number rev date: sheet of dit 1 akd5702-a a3 36 monday, april 09, 2007 title size document number rev date: sheet of dit 1 akd5702-a a3 36 monday, april 09, 2007 i2s ocks1 m/s ocks0 i2c cad0 test cad1 r22 470 r22 470 1 2 + c32 10u + c32 10u out 1 vcc 3 gnd 2 port1 torx141 port1 torx141 c25 0.1u c25 0.1u c26 0.47u c26 0.47u ips0 1 nc 2 dif0 3 test2 4 dif1 5 nc 6 dif2 7 ips1 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 dvss 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0 32 cm1 33 ocks1 34 ocks0 35 int0 36 avdd 38 r 39 vcom 40 avss 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 nc 47 rx3 48 vin 12 lrck 24 sdto 25 int1 37 u6 ak4114 u6 ak4114 c28 5p c28 5p 1 2 + c31 10u + c31 10u gnd 1 vcc 2 in 3 port2 totx141 port2 totx141 c30 0.1u c30 0.1u 1 2 + c24 10u + c24 10u c29 0.1u c29 0.1u 1 2 l1 (short) l1 (short) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sw1 sw dip-8 sw1 sw dip-8 1 2 3 4 5 6 7 8 9 rp1 47k rp1 47k jp16 xti jp16 xti c27 5p c27 5p c33 0.1u c33 0.1u 1 2 x1 11.2896mhz x1 11.2896mhz r23 18k r23 18k c23 0.1u c23 0.1u
a a b b c c d d e e e e d d c c b b a a lin1 lin2 lin5 rin1 rin2 rin5 lin3 rin3 rin4 lin4 title size document number rev date: sheet of input 1 akd5702-a a3 46 monday, april 09, 2007 title size document number rev date: sheet of input 1 akd5702-a a3 46 monday, april 09, 2007 title size document number rev date: sheet of input 1 akd5702-a a3 46 monday, april 09, 2007 lin125 lin1 lin2 rin125 lin5 rin5 rin1 rin2 lin5 rin5 rin3 rin4 lin345 lin3 lin4 rin345 2 3 1 j9 mr-552ls j9 mr-552ls jp20 rin5_sel jp20 rin5_sel jp18 rin125_sel jp18 rin125_sel 2 3 1 j4 mr-552ls j4 mr-552ls r24 (open) r24 (open) jp21 lin345_sel jp21 lin345_sel r27 (open) r27 (open) r26 (open) r26 (open) r25 (open) r25 (open) 2 3 1 j6 mr-552ls j6 mr-552ls 6 4 3 j8 mic345 j8 mic345 jp19 lin5_sel jp19 lin5_sel jp22 rin345_sel jp22 rin345_sel 6 4 3 j5 mic125 j5 mic125 2 3 1 j7 mr-552ls j7 mr-552ls jp17 lin125_sel jp17 lin125_sel
a a b b c c d d e e e e d d c c b b a a vd vd 5702_mcki csn/cad1 cclk/scl pdn daux ext_mclk ext_lrck cad1 lvc vd vd vd int0 4114_pdn vd ext_bclk vd lvc 5702_tdmin 5702_bclk 5702_lrck vd lvc lvc vd 5702_sdtob 5702_mcko mcko 5702_sdtoa vd vd cdti/sda title size document number rev date: sheet of logic 1 akd5702-a a2 56 monday, april 09, 2007 title size document number rev date: sheet of logic 1 akd5702-a a2 56 monday, april 09, 2007 title size document number rev date: sheet of logic 1 akd5702-a a2 56 monday, april 09, 2007 cclk/sci cdti/sda csn/cad1 lh mcki bclk lrck vd sdtoa sdtob cdto/sda(ack) i2c 3-wire sdto mcko bclk lrck vcc h l pdn mcki bclk lrck tdmin vd sdtob p_down tdmin c43 0.1u c43 0.1u c36 0.1u c36 0.1u 2 1 3 sw3 4114_pdn sw3 4114_pdn gnd 7 1a 1 3a 5 5a 11 5y 10 3y 6 1y 2 2y 4 4y 8 6y 12 6a 13 4a 9 2a 3 vcc 14 u12 74hc14 u12 74hc14 1 2 3 4 5 6 7 8 9 10 port6 ctrl port6 ctrl r37 100k r37 100k jp36 ctrl_sel jp36 ctrl_sel jp32 mclk_sel jp32 mclk_sel c41 0.1u c41 0.1u r29 10k r29 10k k a d2 hsu119 d2 hsu119 jp28 m/s jp28 m/s c34 0.1u c34 0.1u r38 (short) r38 (short) r36 470 r36 470 c35 0.1u c35 0.1u c40 0.1u c40 0.1u 1 2 3 4 5 6 7 8 9 10 port5 tdm port5 tdm r28 (open) r28 (open) 2 1 3 sw2 pdn sw2 pdn 6 5 4 3 2 1 7 rp3 r-pack6r rp3 r-pack6r r34 470 r34 470 r31 10k r31 10k a1 3 a2 4 a4 6 a5 7 a6 8 a7 9 a8 10 oe 22 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 vccb 24 gnd 13 a3 5 dir 2 vccb 23 vcca 1 gnd 11 gnd 12 u7 74avc8t245 u7 74avc8t245 1 2 3 4 5 6 7 8 9 10 port3 dsp2 port3 dsp2 k a led1 erf led1 erf r33 10k r33 10k a1 3 a2 4 a4 6 a5 7 a6 8 a7 9 a8 10 oe 22 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 vccb 24 gnd 13 a3 5 dir 2 vccb 23 vcca 1 gnd 11 gnd 12 u9 74avc8t245 u9 74avc8t245 jp30 sdto_sel jp30 sdto_sel a1 3 a2 4 a4 6 a5 7 a6 8 a7 9 a8 10 oe 22 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 vccb 24 gnd 13 a3 5 dir 2 vccb 23 vcca 1 gnd 11 gnd 12 u10 74avc8t245 u10 74avc8t245 6 5 4 3 2 1 7 rp2 r-pack6r rp2 r-pack6r r35 10k r35 10k r42 1k r42 1k r39 10k r39 10k k a d1 hsu119 d1 hsu119 c44 0.1u c44 0.1u 1a 1 1b 2 1y 3 2a 4 2b 5 2y 6 4b 13 4a 12 4y 11 3b 10 3a 9 3y 8 vcc 14 gnd 7 u8 74lvc32 u8 74lvc32 jp35 sdtob_sel jp35 sdtob_sel 1 2 3 4 5 6 7 8 9 10 port4 dsp1 port4 dsp1 1a 1 1y 2 vcc 14 gnd 7 2a 3 3a 5 4a 9 5a 11 6a 13 2y 4 3y 6 4y 8 5y 10 6y 12 u11 74lvc07 u11 74lvc07 r32 470 r32 470 r40 1k r40 1k c39 0.1u c39 0.1u jp29 sdtob jp29 sdtob c38 0.1u c38 0.1u c42 0.1u c42 0.1u r30 (open) r30 (open) r41 10k r41 10k c37 0.1u c37 0.1u
a a b b c c d d e e e e d d c c b b a a avdd1 reg_in vd1 dvdd1 vd1 reg_in avdd1 dvdd1 avdd lvc vd avdd dvdd title size document number rev date: sheet of power 1 akd5702-a a3 66 monday, april 09, 2007 title size document number rev date: sheet of power 1 akd5702-a a3 66 monday, april 09, 2007 title size document number rev date: sheet of power 1 akd5702-a a3 66 monday, april 09, 2007 reg dvdd vd dvdd avdd avdd1 1 avdd1 t45_o avdd1 t45_o tp1_agnd1 tp1_agnd1 1 vd1 t45_o vd1 t45_o jp38 avdd_sel jp38 avdd_sel 1 2 + c48 47u + c48 47u jp40 lvc_sel jp40 lvc_sel in out gnd t1 ta48m03f t1 ta48m03f 1 2 + c46 47u + c46 47u tp3_agnd1 tp3_agnd1 1 2 + c49 47u + c49 47u tp2_dgnd1 tp2_dgnd1 1 2 l2 (short) l2 (short) c47 0.1u c47 0.1u 1 dgnd1 t45_bk dgnd1 t45_bk tp3_dgnd1 tp3_dgnd1 1 dvdd1 t45_o dvdd1 t45_o 1 2 l3 (short) l3 (short) jp37 gnd jp37 gnd r43 5.1 r43 5.1 1 2 l4 (short) l4 (short) 1 agnd1 t45_bk agnd1 t45_bk tp2_agnd1 tp2_agnd1 jp39 dvdd_sel jp39 dvdd_sel 1 reg1 t45_r reg1 t45_r 1 2 + c50 47u + c50 47u tp1_dgnd1 tp1_dgnd1 c45 0.1u c45 0.1u
|
