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ltc4216 4216f 1 allows safe board insertion and removal from a live backplane controls load voltages from 0v to 6v fast response limits peak fault current adjustable analog current limit adjustable soft-start with inrush current limiting adjustable response time for overcurrent protection low circuit breaker trip threshold: 25mv no external gate capacitor required gate drive for external n-channel mosfet adjustable supply voltage power-up rate ? r ? e ? s ? e ? t and ? f ? a ? u ? l ? t output 10-lead msop and 12-lead (4mm 3mm) dfn packages ultralow voltage hot swap controller the ltc ? 4216 is a positive low-voltage hot swap tm controller that allows a board to be safely inserted and removed from a live backplane. it controls load voltages ranging from 0v to 6v and isolates a severe fault with instantaneous analog current limiting. an internal high side switch driver controls the gate of an external n-channel mosfet. an adjustable soft-start limits the rate of change of the inrush current at start-up for a large load capacitor. together with an analog current limit ampli? er, an electronic circuit breaker with adjustable response time provides dual level overcurrent protection. no external gate capacitor is required for the analog cur- rent limit loop compensation. the fb pin monitors the output supply voltage and signals the ? r ? e ? s ? e ? t output pin. an on pin provides on/off control and a ? f ? a ? u ? l ? t pin indicates the fault status. the ltc4216 is available in the 10-lead msop and 12-lead (4mm 3mm) dfn packages. single channel 1.8v hot swap controller electronic circuit breaker live board insertion and removal industrial high side switch/circuit breaker optical networking normal power-up with soft-start applicatio s u features descriptio u typical applicatio u 4216 ta01b 0.5ms/div v gate 5v/div i out 2.5a/div v out 1v/div sensep sensen gate v cc on timer fb fault reset ss filter ltc4216 330nf 20k 1% 17.4k 1% 10k 10k 1% 15k 1% long backplane connector (female) pcb edge connector (male) gnd long short 10nf 10nf 18nf v out 1.8v 5a v in 1.8v v cc 3.3v gnd si4864dy 0.004 ? 22 ? 3.3v 10k + 1000 f fault reset p logic 4216 ta01 long , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
ltc4216 4216f 2 symbol parameter conditions min typ max units v cc bias supply range 2.3 6 v v sensep v sensep supply range 0 6 v i cc bias supply current v on = 2v, v fb = 2v 1.6 3 ma v cc(uvl) bias supply undervoltage lockout v cc rising 1.97 2.12 2.23 v v cc(uvl,hyst) bias supply undervoltage 50 120 190 mv lockout hysteresis v cb(th) circuit breaker trip voltage threshold 22.5 25 27.5 mv (v sensep C v sensen ) 21.5 25 28.5 mv v acl(th) analog current limit voltage threshold 32 40 48 mv (v sensep C v sensen ) i sensep(in) sensep pin input current v sensep = v sensen = v cc = 6v 20 70 250 a v sensep = v sensen = 0v, v cc = 6v C7 C20 a i sensen(in) sensen pin input current v sensen = v sensep = v cc = 6v 10 15 a v sensen = v sensep = 0v, v cc = 6v C5 C 10 C 15 a 12 11 10 9 8 7 1 2 3 4 5 6 13 fault v cc sensep sensen gate fb reset on filter timer ss gnd top view de package 12-lead (4mm 3mm) plastic dfn bias supply voltage (v cc ) ............................C 0.3v to 9v input voltages fb, on, ss, sensep, sensen .................C 0.3v to 9v timer, filter ............................ C 0.3v to v cc + 0.3v output voltages ? r ? e ? s ? e ? t, ? f ? a ? u ? l ? t ......................................... C 0.3v to 9v gate ...................................................... C 0.3v to 15v order part number de part* marking consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is indicated by a label on the shipping container. 4216 ltc4216cde ltc4216ide (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 3.3v, unless otherwise noted. (note 2) operating temperature range ltc4216c ................................................ 0c to 70c ltc4216i .............................................C 40c to 85c storage temperature range ms .....................................................C 65c to 150c de ......................................................C 65c to 125c lead temperature (soldering, 10sec) ms package ...................................................... 300c order part number ms part* marking ltbkv ltc4216cms ltc4216ims electrical characteristics absolute axi u rati gs w ww u package/order i for atio uu w 1 2 3 4 5 reset on filter timer gnd 10 9 8 7 6 v cc sensep sensen gate fb top view ms package 10-lead plastic msop t jmax = 125c, ja = 160c/w t jmax = 125c, ja = 43c/w, jc = 4.3c/w exposed pad (pin 13) internally connected to gnd (pcb connection optional)
ltc4216 4216f 3 symbol parameter conditions min typ max units i gate(up) gate pull up current gate drive on, v gate = 0v, v on = 2v C 16 C 20 C 26 a i gate(dn) gate pull down current gate drive off, v gate = 5v, v on = 0.6v 100 600 1500 a v sensep - v sensen = 55mv, v gate = 5v 1 5 20 ma v sensep - v sensen = 100mv, v gate = 5v 15 50 100 ma v gate external n-channel gate drive 2.3v v cc < 3v 4.0 5.0 7.9 v (v gate C v sensen ) 3v v cc 6v 4.5 6.2 7.9 v v gate(th) gate pin threshold voltage v gate falling 0.15 0.2 0.3 v v ss(clp) ss pin clamp voltage after end of ss timing cycle 1.3 1.65 2.0 v v ss(th) ss pin threshold voltage v ss falling 0.15 0.2 0.35 v i ss(up) ss pull up current v on = 2v, v ss = 1.2v, v fb = 2v C7 C 10 C 13 a v on = 2v, v fb = 0v C0.3 C1 C2 a i ss(dn) ss pull down current v on = 0v, v ss = 2v 8 ma v fb(th) fb pin threshold voltage v fb falling 0.593 0.602 0.611 v v fb(linereg) fb pin threshold line regulation 2.3v v cc 6v 0.2 3 mv v fb(hyst) fb pin hysteresis 3 mv i fb(in) fb pin input current v fb = 1.2v, v cc = 6v 0 1 a v on(th) on pin threshold voltage v on rising 0.77 0.8 0.83 v v on(hyst) on pin hysteresis 40 80 130 mv v on(fc) on pin fault clear threshold voltage v on falling 0.36 0.4 0.44 v i on(in) on pin input current v on = 1.2v, v cc = 6v 0 1 a v tmr(th) timer pin threshold voltage v timer rising 1.216 1.253 1.291 v v timer falling 0.15 0.2 0.35 v i tmr(up) timer pull up current timer on, v on = 2v, v timer = 1v C1.5 C2 C2.5 a i tmr(dn) timer pull down current timer off, v on = 0v, v timer = 2v 8 ma v filt(th) filter pin threshold voltage v filter rising 1.216 1.253 1.291 v v filter falling 0.15 0.2 0.35 v i filt(up) filter pull up current v on = 2v, v filter = 1v, in fault mode C 45 C 60 C 75 a i filt(dn) filter pull down current v on = 2v, v filter = 1v, no faults 1.5 2.4 3.3 a v on = 0v, v filter = 2v, in reset mode 8 ma v ? f ? a ? u ? l ? t(th) ? f ? a ? u ? l ? t pin threshold voltage v ? f ? a ? u ? l ? t falling 1.216 1.253 1.291 v v ? f ? a ? u ? l ? t(hyst) ? f ? a ? u ? l ? t pin hysteresis 10 mv i ? f ? a ? u ? l ? t(up) ? f ? a ? u ? l ? t pin current v on = 0v, v ? f ? a ? u ? l ? t = 1.5v C3 C5 C7 a v ol output low voltage ( ? r ? e ? s ? e ? t, ? f ? a ? u ? l ? t) i ? r ? e ? s ? e ? t = i ? f ? a ? u ? l ? t = 1.6ma 0.15 0.4 v i ? r ? e ? s ? e ? t(leak) ? r ? e ? s ? e ? t pin input leakage current v ? r ? e ? s ? e ? t = v cc = 6v 0 10 a t cb(trip) circuit breaker trip to gate (v sensep - v sensen ) = step 0v to 30mv, 120 240 360 s discharging v sensep = v cc , filter = 10nf to gnd t ? f ? a ? u ? l ? t(ext) ? f ? a ? u ? l ? t low to gate discharging v ? f ? a ? u ? l ? t = step 2v to 0v 10 20 s t filter filter high to gate discharging v filter = step 0v to 2v 20 40 s t rst(onlo) circuit breaker reset delay time, v on = step 2v to 0v 30 60 s on low to ? f ? a ? u ? l ? t high t rst(vcclo) circuit breaker reset delay time, v on = 2v, v cc = step 3.3v to 1.8v 50 100 s v cc low to ? f ? a ? u ? l ? t high t off turn-off time, on low to gate discharging v on = step 2v to 0.6v 15 s the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 3.3v, unless otherwise noted. (note 2) electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of the device pins are negative; all voltages are referenced to gnd unless otherwise speci? ed.
ltc4216 4216f 4 temperature ( c) ?0 v fb(th) (v) 125 4216 g09 ?5 0 25 50 75 100 0.611 0.608 0.605 0.602 0.599 0.596 falling rising temperature ( c) ?0 i gate(up) ( a) 125 4216 g08 ?5 0 25 50 75 100 ?2 ?1 ?0 ?9 ?8 temperature ( c) ?0 ? v acl(th) (mv) 125 4216 g07 ?5 0 25 50 75 100 42 41 40 39 38 temperature ( c) ?0 ? v cb(th) (mv) 125 4216 g04 ?5 0 25 50 75 100 27 26 25 24 23 v sensen (v) 0 v gate (v) 14 12 10 8 6 4 2 1 234 4216 g06 56 v cc = 6v temperature ( c) ?0 ? v gate (v) 125 4216 g05 ?5 0 25 50 75 100 7.0 6.5 6.0 5.5 5.0 4.5 v cc = 5v v cc = 3.3v v sensep = v sensen = v cc v cc = 2.5v v cc (v) 2.0 i cc (ma) 6.0 4216 g01 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.0 2.5 2.0 1.5 1.0 0.5 temperature ( c) ?0 i cc (ma) 125 4216 g02 ?5 0 25 50 75 100 3.0 2.5 2.0 1.5 1.0 0.5 v cc = 6v v cc = 3.3v v cc = 2.3v temperature ( c) ?0 v cc(uvl) (v) 125 4216 g03 ?5 0 25 50 75 100 2.20 2.15 2.10 2.05 2.00 1.95 1.90 falling rising i cc vs v cc i cc vs temperature v cc(uvl) vs temperature v cb(th) vs temperature v gate vs temperature v gate vs v sensen v acl(th) vs temperature i gate(up) vs temperature v fb(th) vs temperature speci? cations are at t a = 25c. v cc = 3.3v, unless otherwise noted. typical perfor a ce characteristics uw
ltc4216 4216f 5 temperature ( c) ?0 i filt(dn) ( a) 125 4216 g17 ?5 0 25 50 75 100 2.8 2.6 2.4 2.2 2.0 temperature ( c) ?0 i filt(up) ( a) 125 4216 g16 ?5 0 25 50 75 100 ?0 ?5 ?0 ?5 ?0 temperature ( c) ?0 v ss(clp) (v) 125 4216 g15 ?5 0 25 50 75 100 1.9 1.8 1.7 1.6 1.5 1.4 temperature ( c) ?0 v filt(th) (v) 125 4216 g14 ?5 0 25 50 75 100 1.27 1.26 1.25 1.24 1.23 temperature ( c) ?0 v fault(th) (v) 125 4216 g12 ?5 0 25 50 75 100 1.27 1.26 1.25 1.24 1.23 temperature ( c) ?0 v on(th) (v) 125 4216 g11 ?5 0 25 50 75 100 0.90 0.85 0.80 0.75 0.70 0.65 0.60 falling rising temperature ( c) ?0 v tmr(th) (v) 125 4216 g10 ?5 0 25 50 75 100 1.27 1.26 1.25 1.24 1.23 temperature ( c) ?0 i ss(up) ( a) 125 4216 g18 ?5 0 25 50 75 100 ?2 ?0 ? ? ? ? 0 v fb = 2v v fb = 0v v tmr(th) vs temperature v on(th) vs temperature v fault(th) vs temperature i tmr(up) vs temperature v filt(th) vs temperature v ss(clp) vs temperature i filt(up) vs temperature i filt(dn) vs temperature i ss(up) vs temperature typical perfor a ce characteristics uw temperature ( c) ?0 i tmr(up) ( a) 125 4216 g13 ?5 0 25 50 75 100 ?.2 ?.1 ?.0 ?.9 ?.8
ltc4216 4216f 6 ? r ? e ? s ? e ? t (pin 1/pin 1): reset or power-good output. open drain output that pulls low if the fb pin voltage falls below its threshold (0.6v). if an undervoltage lockout condition occurs, the ? r ? e ? s ? e ? t pin pulls low and ignores the fb pin voltage. on (pin 2/pin 2): on control input. a rising edge above the on pin threshold (0.8v) initiates the start-up cycle and turns on the external n-channel mosfet. a falling edge below 0.72v (80mv on pin hysteresis) turns it off. if this pin is pulled below 0.4v, following a circuit breaker trip, it resets the electronic circuit breaker and fault latch. filter (pin 3/pin 3): fault filter input. connect a capacitor between this pin and ground to set up the fault ? lter delay. this pin sources 60a or sinks 2.4a when the voltage across the sense resistor exceeds 25mv or drops below 25mv respectively. timer (pin 4/pin 4): timer input. connect a capacitor between this pin and ground to set up the start-up timing cycle duration. it also de? nes the ? r ? e ? s ? e ? t power-good delay from the instant the fb pin voltage exceeds 0.6v. this pin sources 2a pull-up current during ramp up. ss (pin 5/not available): soft-start control input. con- nect a capacitor between this pin and ground for soft-start during power-up. it controls the gate ramp up, limiting the rate of change of the inrush current when the external mosfet turns on. if soft-start function is not used, leave this pin unconnected. gnd (pin 6/pin 5): device ground. fb (pin 7/pin 6): output monitor for reset output. a resis- tive divider from the external mosfets source terminal is tied to this pin. when the voltage at this pin drops below 0.6v, the ? r ? e ? s ? e ? t pin pulls low. gate (pin 8/pin 7): gate drive for external n-channel mosfet. an internal charge pump provides 20a gate pull-up current and suf? cient gate overdrive to the exter- nal mosfet. an internal shunt regulator limits the gate pin voltage to about 6.2v (typ) above the sensen pin voltage. sensen (pin 9/pin 8): circuit breaker negative sense input. connect this pin to the sense resistor terminal wired to the drain of the external n-channel mosfet. the sense resistor is placed in the power path between sensep and sensen pins to sense the output current. the electronic circuit breaker trips if the voltage across the sense resistor exceeds 25mv for more than a fault ? lter delay. sensep (pin 10/pin 9): circuit breaker positive sense input. connect this pin to the sense resistor terminal wired to the positive supply input for the external output load. this positive supply range extends from 0v to 6v. v cc (pin 11/pin 10): bias supply input. operates from 2.3v to 6v. an internal undervoltage lockout circuit disables the device until the input supply voltage at v cc exceeds 2.12v typically. ? f ? a ? u ? l ? t (pin 12/not available): fault input and output. as an input, driving this pin low (<1.253v) will latch-off the device to fault mode. as an output, it is either pulled high by an internal 5a pull-up or an external pull-up resistor to positive supply under normal operating condition. it pulls low when the circuit breaker is tripped due to an overcurrent fault. exposed pad (pin 13/not available): exposed pad may be left open or connected to device ground. (de12 package/ms package) pi fu ctio s uuu
ltc4216 4216f 7 the ltc4216 is a hot swap controller residing either on a removable circuit board or on the backplane. it moni- tors the current and protects the load with an external n-channel mosfet and a current sensing resistor (see typical application). both inrush current limiting and short-circuit protection are provided by the ltc4216. the device is powered via the bias supply input (v cc ) and it has a separate sense pin, sensep, to monitor the load supply (v in ). the load supply can extend from 0v to 6v, with a minimum bias supply voltage of 2.3v. when the on pin is pulled from low to high, timer begins the ? rst timing cycle by sourcing 2a into c1 once these conditions are met: bias supply voltage out of undervolt- age lockout (> 2.12v); timer, ss, filter and gate pin voltages < 0.2v. when the c1 voltage rises above the timer pin threshold (1.253v), timer pulls low and releases both the ss and gate pins. c2 starts to ramp up at the ss pin, controlling the rate of gate ramp. this limits the rate of change of the inrush current ? owing into the output load capacitance. ? r ? e ? s ? e ? t pin goes high after the second timing cycle when the fb pin voltage exceeds 0.6v and its hysteresis. when the external mosfet is fully turned on, the output will ramp to load supply voltage if the inrush into the load capacitance is low. however, if the inrush current exceeds the analog current limit of v acl(th) /r sense , the ltc4216 will ramp the output by sourcing the limited current into the load capacitance. the ltc4216 provides protection against output short- circuits or current overload through an internal electronic circuit breaker with trip threshold of 25mv and an analog current limit circuit. the circuit breaker response time is set by c3 at the filter pin. + + + + + + + + + + 0.2v 2.12v 0.4v 0.8v 0.6v 2 a 2.4 a 1.253v cp1 cp6 cp7 cp5 cp4 v cc v cc v cc sensep sensen gate ss** reset on fb 4216 bd fault** gnd timer filter normal uvlo ecb acl note 1: filter delay is set by filter pin capacitor ** only available in the de12 package v cc v cc cp2 cp3 1.253v 1.253v 6 s delay fault latch reset device reset fault latch-off out of uvlo cb trips or uvlo gate on gate off m4 m3 m2 m1 m5 m6 r1 m7 m9 m10 m8 z1 d1 d2 charge pump 100 a 20 a 40mv 25mv 10 a1 a 5 a gate on gate off device reset, uvlo or power bad cb trips filter function of overdrive filter delay (see note 1) 30 s delay 60 a v cc logic 3 s delay + + block diagra w operatio u
ltc4216 4216f 8 hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient current from the power bus as they charge. potentially, the ? ow of current could damage the connector pins and glitch the power bus, causing other boards in the system to reset. the ltc4216 is designed to turn on or off a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. overview of ltc4216 features 1. allows safe board insertion and removal from a live backplane. 2. controls load voltages from 0v to 6v. 3. high side gate drive for external n-channel mosfet. 4. adjustable soft-start with inrush current limiting for large load capacitor during start-up. 5. adjustable analog current limit (acl) with circuit breaker fault time-out during an overcurrent fault condi- tion. no external gate capacitor is required for the acl loop compensation. 6. electronic circuit breaker tripping at 25mv across the sense resistor. the response time is adjustable through an external capacitor at the filter pin. 7. provides an on pin to turn on and off the device. this can also be used to reset the device after a circuit breaker trip. 8. provides output supply voltage monitoring through the fb pin and signals the ? r ? e ? s ? e ? t pin output. 9. provides fault status output. on control the on pin has two hysteretic comparators with differ- ent threshold levels (0.8v and 0.4v) and they serve two purposes: 1. turn on the device if the on pin voltage > 0.8v for more than 6s and turn it off if the on pin voltage < 0.72v for more than 15s. 2. reset the device if the on pin voltage < 0.4v for more than 30s after a circuit breaker trip. there are various methods of setting the on pin voltage: 1. tie the on pin to the load supply (v in ) through a 10k pull-up resistor. 2. drive the on pin with an on/off logic signal from the system controller. 3. connect an external resistive divider at the on pin. this divider can be used to set a higher value for the load supply undervoltage lockout voltage than the internal v cc undervoltage lockout circuit. for example, as shown in figure 17, if both v cc and sensep pins are connected to a 5v load supply, choosing the resistive divider values, r1 = 20k, r2 = 80.6k, turns on the device when the load supply voltage reaches around 80% of its ? nal value. v cc undervoltage lockout a hysteretic comparator, uvlo, monitors bias supply (v cc ) for undervoltage. the thresholds are de? ned by v cc(uvl) (2.12v) and its hysteresis, v cc(uvl,hyst) (120mv). when v cc rises above v cc(uvl) , the device is enabled. when v cc falls below (v cc(uvl) C v cc(uvl,hyst) ), the device is disabled and gate is pulled low. if v cc cycles below this threshold for more than 200s, following a circuit breaker trip, it clears the fault latch. any bias sup- ply glitches that last less than 10s will be rejected by the uvlo glitch ? lter. timer an external capacitor, c1, is used at timer pin to provide two timing cycles for the ltc4216. the ? rst timing cycle is the debounce cycle when the on pin is ? rst turned on, both the gate and ss pins are held low and any short- circuit faults are ignored by the electronic circuit breaker. second timing cycle is the power-good delay before the ? r ? e ? s ? e ? t pin goes high when the fb pin voltage exceeds 0.6v and its hysteresis. the timer pin sources 2a into c1 during the two timing cycles and is then pulled low by an internal n-channel applicatio s i for atio wu u u
ltc4216 4216f 9 + logic timer timer ltc4216** sensep 0.6v v cc v in on fb r4 r3 r sense r5 m2 m1 reset sensen gate + c1 c load **additional details omitted for clarity reset p v out + 4216 f02 switch when the timer pin voltage exceeds its threshold. the timer period for c1 to charge up to the timer pin threshold, v tmr(th) (1.253v), is given by: t vc a timer = 1 253 1 2 . (1) for example, if c1 = 10nf, t timer = 6.2ms. fb glitch filtering the fb pin is used to monitor the output voltage of the external mosfet through a resistive divider. any tran- sients on the fb pin due to the output low spikes will pull ? r ? e ? s ? e ? t low. to prevent ? r ? e ? s ? e ? t from generating an unwanted system reset, the fb comparator has a glitch ? lter to ride out these glitches. the ? lter time is 20s for large transients (greater than 150mv) and up to 100s for small transients. the relationship between glitch ? lter time and the fb pin transient voltage or fb overdrive is shown in figure 1. fb pin voltage rises above 0.6v, the fb comparator output goes low and a new timing cycle starts. after a complete timing cycle at time point 6, ? r ? e ? s ? e ? t is pulled high by the external pull-up resistor, r5. the timer period given by equation (1) sets the power-good delay for ? r ? e ? s ? e ? t going high. if the fb pin voltage stays above 0.6v for less than a timing cycle at time point 4, the ? r ? e ? s ? e ? t output remains low. any overcurrent fault detected by the electronic circuit breaker or ? f ? a ? u ? l ? t pin driven low externally during the timing cycle, will also pull the timer pin low and ? r ? e ? s ? e ? t output remains low. when the device enters an undervoltage lockout condition or the on pin voltage drops below 0.4v, ? r ? e ? s ? e ? t is pulled low, ignoring the fb pin voltage. figure 2. output voltage monitor block diagram figure 3. output voltage monitor waveforms in normal operation 12 v out v tmr(th) v fb < 0.6v v fb > 0.6v v fb < 0.6v v fb > 0.6v timer reset glitch filter delay 345 6 power-good delay 2? 2? 4216 f03 applicatio s i for atio wu u u figure 1. fb comparator glitch filter time vs fb overdrive output voltage monitor as shown in figure 2, the output voltage is monitored through a resistive divider, r3 and r4, connected at the fb pin, and a fb comparator with 0.6v threshold. the normal operation of the output voltage monitor after a start-up cycle is shown in figure 3. at time point 1, when the fb pin voltage falls below 0.6v, the fb comparator output goes high. ? r ? e ? s ? e ? t is pulled low by an internal n-channel switch after a glitch ? lter delay at time point 2. when the fb overdrive (mv) 0 100 120 140 160 120 80 60 40 80 200 40 20 0 glitch filter time ( s) t a = 25 c
ltc4216 4216f 10 electronic circuit breaker the ltc4216 features an electronic circuit breaker function that protects the external mosfet against short-circuits or excessive load current conditions on the supply. an external sense resistor connected between sensep and sensen pins is used to measure the load current. if the voltage across the sense resistor exceeds the circuit breaker trip threshold of 25mv for more than a fault ? lter delay, the gate of the mosfet is pulled low, turning it off. the fault ? lter delay is determined by a capacitor, c3, con- nected between the filter pin and ground as in equation (2). the filter pin sources 60a pull-up current when the sense voltage across the sense resistor exceeds 25mv. otherwise, it pulls down with 2.4a. when the filter pin voltage exceeds v filt(th) threshold (1.253v), there is an internal 20s delay before the gate pulls low and the ? f ? a ? u ? l ? t pin will be pulled low. if no filter capacitor is used, the ? lter fault delay defaults to 20s. the circuit breaker response time or fault ? lter delay with the filter capacitor, c3, is given by: t vc a s cb trip () . = + 1 253 3 60 20 (2) the filter capacitor, c3, should be chosen so that the fault ? lter delay is not too short to trip the circuit breaker as the mosfet current charges up a large output load capacitance in analog current limit during power-up. it also should not be too long to exceed the safe operating area (soa) of the external mosfet. intermittent overloads may exceed the current limit as in figure 5, but if the duration is suf? ciently short, the filter pin voltage may not reach the v filt(th) threshold and the device will not shut off. to handle this situation, the filter discharges with 2.4a whenever voltage across the sense resistor is below 25mv. any intermittent overload with an aggregate duty cycle of more than 4% will eventually trip the circuit breaker. figure 6 shows the circuit breaker response time in seconds normalized to 1f as given by equation (3). the asymmetric charging and discharging of filter is a fair gauge of mosfet heating. t c sf d 3 1 253 60 2 4 (/ ) . (). = (3) following a circuit breaker trip, the device is latched-off and ? f ? a ? u ? l ? t is pulled low until the fault latch is cleared by pulling the on pin low (< 0.4v) for at least 100s. the filter pin is pulled low by an internal n-channel switch to discharge the capacitor quickly when the on pin volt- age falls below 0.4v and pulls down with 2.4a when the on pin voltage rises above 0.8v to initiate a new start-up cycle. the new timing cycle will not start until the filter pin voltage is below 0.2v. the electronic circuit breaker is disabled during the ? rst timing cycle upon start-up and any short-circuit faults will be ignored. figure 4. a continuous fault timing figure 5. multiple intermittent overcurrent condition v filter circuit breaker trips ab 1.253v normal mode fault mode 2.4? 60? 4216 f04 a1 i load v filter v gate circuit breaker trips 1.253v b1 cb fault cb fault cb fault a2 b2 a3 b3 25mv/r sense 60? 60? 60? 2.4? 2.4? 2.4? applicatio s i for atio wu u u
ltc4216 4216f 11 analog current limiting in addition to an electronic circuit breaker, the ltc4216 has included a novel analog current limit (acl) ampli? er that does not require an external compensation capacitor at the gate pin. the ampli? ers stability is compensated by the large gate input capacitance (c iss ) of the external mosfet used. these mosfets usually have c iss 1nf. however, if the mosfets gate input capacitance (c iss ) is too small for loop stability, then connect an external capacitor between the gate pin and ground to increase the total gate capacitance to 1nf. as given by equation (4), the mosfet current, i acl , is limited to the analog current limit voltage, v acl(th) , 40mv typical, across the sense resistor, r sense , connected between sensep and sensen pins. i v r acl acl th sense = ? () (4) the v acl(th) threshold is 1.6 times higher than the v cb(th) threshold (25mv typical) to provide dual level cur- rent sensing. when the acl ampli? er servos the mosfet current at v acl(th) across the sense resistor, it exceeds v cb(th) threshold causing the filter pin to charge c3 with 60a pull-up. if the condition persists long enough for c3 to reach the v filt(th) threshold (1.253v), gate is pulled low and ? f ? a ? u ? l ? t latched low. if the voltage across the sense resistor is greater than v acl(th) during an overload condition, the acl ampli? er will servo gate downwards in an attempt to control the mosfet current. since the gate pin voltage overdrives the mosfet in normal operation, the acl ampli? er needs time to discharge the gate to the threshold of the mosfet for gate regulation. for mild overload, the acl ampli? er can control the mosfet current, but in the event of a severe overload, the mosfet current may overshoot as the mosfet has large gate overdrive initially. the gate is quickly discharged to ground followed by the acl ampli- ? er taking control. for applications that require very fast analog current limit recovery from the gate undershoot as it discharges, connect a series resistor, r z , with an external capacitor, c z , at the gate pin as shown in figure 17. soft-start the ltc4216 features a soft-start function that controls the di/dt of the inrush current during power-up. as large output load capacitors are commonly used in low-voltage applications, the normal inrush can be large enough to glitch the load supply. with the soft-start function, the gate of the external mosfet is allowed to turn on very gradually to control the inrush current ? owing into the load capacitor without causing a supply glitch. with an external capacitor, c2, connected between the ss pin and ground, the gate is servoed by the acl ampli? er to track the rate of ss ramp-up during power-up. there are two slopes in the ss ramp-up pro? le: 10a current source pull-up for a normal ramp rate; and 1a current source pull-up for a slower ramp rate. both the ss ramp rates are given as follows: normal ss ramp rate: dv dt a c ss nom () = 10 2 (5) slower ss ramp rate: dv dt a c ss slow () = 1 2 (6) figure 6. circuit breaker filter response for intermittent overload applicatio s i for atio wu u u overload duty cycle, d (%) 0 20406080100 normalized response time (s/ f) 1 0.1 0.01 4216 f06 t/c3(s/ f) = 1.253/[(60 ?d) ?2.4]
ltc4216 4216f 12 for example if c nf dv dt v ms and dv dt vms ss nom ss slow ,, / ./ . () () 210 1 01 == = after the initial timing cycle, the ss capacitor is charged by a 10a current source pull-up and gate is held low by the acl ampli? er. as ss ramps up, the acl ampli? er releases the gate when it crosses its input offset volt- age. at this instant, ss switches the pull-up current from 10a to 1a for a slower ramp rate. gate continues to charge up with 20a pull-up before the mosfet reaches its turn-on threshold voltage. when the external mosfet is ? rst turned on, there is always a current step due to the high gain of the mosfet. the slower ss ramp rate allows the gate of the external mosfet to be turned on with a smaller inrush current step. when the external mosfet is turned on, load current starts to ? ow through the sense resistor, developing a voltage drop across it. this allows the acl ampli? er to servo the gate to the voltage across the sense resistor, thus controlling the rate of change of the inrush current. at this instant, ss switches back from 1a to 10a current source pull-up for a normal ramp rate. gate continues to ramp up as the acl ampli? er servos to track the ss ramp rate. at the end of ss ramp-up when ss reaches its ? nal value, gate is servoed to v acl(th) across the sense resistor. if the voltage across the sense resistor drops below v acl(th) due to a falling load current, the acl ampli? er shuts off and gate ramps further by a 20a pull-up. ss is pulled low under any of the following conditions: in v cc undervoltage lockout condition, during the ? rst timing cycle or when the circuit breaker fault times out. if the soft-start function is not used, leave the ss pin unconnected. inrush control with gate capacitor for applications not requiring soft-start to control the di/dt of the inrush current during power-up, an alternative way to limit the inrush is to control the gate pin voltage slew rate by connecting an external capacitor, c4, from the gate pin to ground, as shown in figure 7. the gate slew rate is given by: dv dt a cc gate gate = + 20 4 (7) where c gate is the associated parasitic gate capacitance due to the external mosfets gate input capacitance, c iss . the inrush current ? owing into the load capacitor, c load , is limited to: ic dv dt c cc a inrush load gate load gate == + 4 20 (8) for example, if c load = 4700f, c4 = 33nf and c gate = 5nf, i inrush = 2.5a. if c load is very large and i inrush exceeds the analog current limit, the gate is servoed to control the inrush current to v acl(th) /r sense . one limitation with this technique is that it slows down the system turn-on and turn-off time by adding a capaci- tor at the gate pin. should this technique be used, c4 50nf is recommended. however, having an external gate capacitor helps to eliminate voltage spikes coupled through the mosfets drain-to-gate capacitance to the gate pin when the supply power is ? rst applied. figure 7. inrush control with external gate capacitor sensep sensen gate fb c4 **additional details omitted for clarity ltc4216** r4 r3 r sense v in v out m1 + c load 4216 f07 applicatio s i for atio wu u u
ltc4216 4216f 13 normal power-up and power-down figure 8 illustrates the timing diagram for a normal power- up sequence in the case where a printed circuit board is inserted into a live backplane. at time point 1, the bias supply (v cc ) ramps up and en- ables the device when the supply voltage rises above the undervoltage lockout threshold (2.12v). at time point 2, sensep supply, together with the on pin, ramp up and start the ? rst timing cycle when the on pin voltage exceeds 0.8v. the timer capacitor is allowed to ramp up with 2a pull-up once all these conditions are met: gate < 0.2v, filter < 0.2v, timer < 0.2v, ss < 0.2v. at time point 3, timer reaches the v tmr(th) threshold and the ? rst timing cycle terminates. the electronic circuit breaker is enabled and timer capacitor is quickly discharged. at time point 4 checks are made for timer, gate, filter and ss < 0.2v, ?v sense below 25mv and ? f ? a ? u ? l ? t high before a gate ramp-up cycle begins. gate is held low by the analog cur- rent limit ampli? er as ss capacitor ramps up with a 10a current source. ss switches to 1a pull-up for a slower ramp rate when it crosses the input offset voltage of the acl ampli? er. at this time point, the acl ampli? er releases the gate and allows it to ramp up with a 20a pull-up. at time point 6, when the gate voltage reaches the turn-on threshold of the external mosfet, current begins ? owing into the load capacitor. the mosfet current level at this time point is controlled by the acl ampli? er and the gate ramp is slowed down. ss switches the pull-up current from 1a to 10a for a normal ramp rate. between time points 6 and 7, the acl ampli? er servos the gate voltage to track the ss ramp rate, limiting the slew rate of the load current. at time point 7, ss reaches its ? nal value and gate continue to ramp up with the 20a pull-up if the load current is not in analog current limit. at time point 8, the fb pin voltage exceeds 0.6v and the second timing cycle is started. when the conditions of timer < 0.2v, ?v sense < 25mv and ? f ? a ? u ? l ? t high are met, the timer capacitor is allowed to ramp up. when timer reaches the v tmr(th) threshold at time point 9, ? r ? e ? s ? e ? t goes high, indicating to the system controller that power is good. after this, the timer is held low. when the on pin voltage falls below (v on(th) C v on(hyst) ) threshold (0.72v), it initiates a power-down sequence. at time point 11, gate is discharged by both the acl ampli- ? er and a 100a current source pull-down, causing the output voltage to fall gradually. when the fb pin voltage falls below 0.6v at time point 12, ? r ? e ? s ? e ? t goes low after a glitch ? lter delay (see the section on fb glitch ? ltering), indicating that power is bad. when the on pin voltage falls below 0.4v, the device resets and gate is pulled low by a strong pull-down device. soft-start with analog current limiting when a very large output load capacitor is connected during soft-start, the gate voltage is servoed to regulate the inrush current to v acl(th) /r sense . this is illustrated in the timing diagram of figure 9. after the initial timing cycle, the gate is allowed to ramp up, tracking the ss ramp rate between time points 5 and 8. at time point 7, when the load current builds up as the gate pin voltage increases, the voltage across the sense resistor rises above v cb(th) (25mv typical). the filter capacitor starts to charge up by a 60a current source pull-up. at time point 8, ss reaches its ? nal value at the end of ss ramp cycle. this allows the gate to be regulated by the acl ampli? er at v acl(th) (40mv typical) across the sense resistor, r sense , limiting the inrush to: i mv r limit sense = 40 (9) the filter pin voltage continues to rise as the load ca- pacitor charges up with the limited load current. at time point 9, the fb pin voltage exceeds 0.6v, but the second timing cycle is not allowed to start as the voltage across the sense resistor exceeds 25mv. at time point 10, the load current falls as the load capacitor is near full charge and the voltage across the sense resistor drops below 40mv. the analog current limit loop shuts off and the gate ramps further till its ? nal value. the filter capacitor discharges by a 2.4a pull-down when the voltage across the sense resistor falls below 25mv at time point 11. the duration between time points 7 and 11 must be shorter than one circuit breaker delay, as given by equation (2), to avoid a fault time-out during gate ramp-up for very large load applicatio s i for atio wu u u
ltc4216 4216f 14 figure 8. normal power-up/power-down sequence capacitors. a second timing cycle starts at time point 11 when the fb pin voltage exceeds 0.6v and the voltage across the sense resistor drops below 25mv. ? r ? e ? s ? e ? t goes high at the end of the second timing cycle (time point 12) when timer reaches the v tmr(th) threshold. sensep on timer ss gate v out reset v cc power good v fb > 0.6v power bad v fb < 0.6v (v gate ?v out ) > v gs(th) v tmr(th) v tmr(th) tracks ss ramp 20? 2? 2? 0.72v 0.4v 0.8v 10? 10? 1? 12 3 4 5 6 7 8 9 check for gate, filter, timer, ss < 0.2v check for gate, filter, timer, ss < 0.2v and fault high 10 11 12 13 plug-in cycle first timing cycle power-good delay second timing cycle 4216 f08 start gate ramp electronic circuit breaker armed reset goes high in reset mode on goes low reset pulled low due to power bad start 2nd timing cycle (check timer < 0.2v and fault high) applicatio s i for atio wu u u
ltc4216 4216f 15 figure 9. normal power-up sequence (with analog current limiting) sensep on timer ss gate v out i load filter reset v cc power good v fb > 0.6v load current regulating at 40mv/r sense power bad v fb < 0.6v (v gate ?v out ) > v gs(th) (v sensep ?v sensen ) > 25mv filter ramps up when (v sensep ?v sensen ) > 25mv output in analog current limit, (v sensep ?v sensen ) = 40mv (v sensep ?v sensen ) < 25mv tracks ss ramp in regulation 20? 60? 2.4? v tmr(th) 2? v tmr(th) 2? 10? 10? 1? check for gate, filter, timer, ss < 0.2v check for gate, filter, timer, ss < 0.2v and fault high plug-in cycle first timing cycle power-good delay second timing cycle 4216 f09 12 3 4 5 6 7 8 9 1011 12 16 15 14 13 0.72v 0.4v 0.8v electronic circuit breaker armed reset goes high in reset mode (on < 0.4v) on goes low (on < 0.72v) output no longer in current limit reset pulled low due to power bad 2nd timing cycle cannot start with output in analog current limit v filt(th) applicatio s i for atio wu u u
ltc4216 4216f 16 power-up into an output-short figure 10 shows the timing diagram in the case when the output is a dead short during power-up. as gate ramps up at time point 6, the mosfet current increases due to the output short causing the voltage drop across the sense resistor to rise above 25mv. filter sources 60a, charg- ing the external capacitor. at time point 7, gate regulates to limit the output current to 40mv/r sense . if the output continues to be in analog current limit when the filter pin voltage reaches its threshold (1.253v) at time point 8, the circuit breaker trips and gate is pulled low. the device latches-off and ? f ? a ? u ? l ? t is pulled low, indicating a fault condition. the filter capacitor discharges through a 2.4a pull-down until the device resets. resetting the electronic circuit breaker when the ltc4216s electronic circuit breaker is tripped during a fault condition, ? f ? a ? u ? l ? t is asserted low and the ? r ? e ? s ? e ? t, ss and gate pins are all pulled to ground. this is shown in the timing diagram of figure 11. the ltc4216 remains latched-off until the external fault is cleared. to clear the internal fault latch and restart the device, pull the on pin low (< 0.4v) at time point 4 for at least 100s, after which the ? f ? a ? u ? l ? t will go high at time point 5. tog- gling the on pin from low to high (> 0.8v) initiates a new start-up cycle. sense resistor considerations the circuit breaker trip threshold of 25mv and the value of the sense resistor, r sense , connected between the sensep and sensen pins, determine the trip current level as given by equation (10). if the fault current level exceeds the analog current limit, the current is limited to a value given by equation (11). should the overload condition exist for more than one fault ? lter delay as given by equation (2), the circuit breaker trips and the device is latched-off. i v r mv r trip cb cb th sense sense () () = ? = 25 (10) i v r mv r acl acl th sense sense = ? = () 40 (11) for a new circuit design, the sense resistor value is ? rst calculated from the maximum operating load current under normal conditions and the minimum circuit breaker trip threshold. this is given by: r v i mv i sense cb th min load max load max = ? = (, ) () () . 21 5 (12) figure 10. power-up into an output-short and circuit breaker trips figure 11. mild overcurrent circuit breaker trips followed by device reset timer 2.4 a 2 a 40mv 25mv 10 a 10 a 1 a 12345678 4216 f10 0.8v tracks ss ramp fpd 60 a sensep-sensen filter ss gate v out on fault reset v filt(th) v tmr(th) v gate ?v out < v gs(th) fault filter delay gate regulating 2.4 a <40mv 25mv 4216 f11 fpd 60 a t rst(onlo) v filt(th) sensep-sensen filter fault reset ss gate v out 1 on 0.4v power bad v fb < 0.6v 23 4 5 mild overcurrent fault latch reset circuit breaker trips and latched-off reset pulled low due to power bad applicatio s i for atio wu u u
ltc4216 4216f 17 for example, if i load(max) = 5a, r sense = 4.3m . the nearest standard value is 4m . for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc4216s sensep and sensen pins are strongly recommended. figure 12 illustrates the correct way of making connections between the ltc4216 and the sense resistor. pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. the power rating of the sense resistor should accom- modate the fault current level during analog current limit so that the component is not damaged before the circuit breaker trips. circuit breaker trip current calculation for a selected r sense value, the typical load current that trips the circuit breaker is given by: i v r mv r trip typ cb th typ sense typ sense typ () (, ) () () = ? = 25 (13) the minimum load current that trips the circuit breaker is given by: i v r mv r trip min cb th min sense max sense max () (, ) () () . = ? = 21 5 (14) figure 12. making pcb connections to the sense resistor to sensep w to sensen track width w: 0.03? per ampere on 1oz copper current flow to load sense resistor current flow to load 4216 f12 where rr r sense max sense typ tol () () =+ ? ? ? ? ? ? 1 100 the maximum load current that trips the circuit breaker is given by: i v r mv r trip max cb th max sense min sense min () (, ) () () . = ? = 28 5 where (15) rr r sense min sense typ tol () () = ? ? ? ? ? ? 1 100 for example, if a sense resistor of 4m 1% r tol is used for current sensing, the typical trip current, i trip(typ ) = 6.25a. from equations (14) and (15), i trip(min) = 5.3a and i trip(max) = 7.2a respectively. for proper operation and to avoid tripping the circuit breaker unnecessarily, the minimum trip current, i trip(min) , must exceed the maximum operating load current of the circuit connected to the output of the mosfet. mosfet selection the external mosfet switch must have adequate safe operating area (soa) to handle short-circuit conditions before the circuit breaker trips. these considerations take precedence over continuous drain current ratings. a mosfet with adequate soa for a given application can always handle the required drain current, but the opposite may not be true. consult the manufacturers mosfet datasheet for safe operating area and effective transient thermal impedance curves. mosfet selection is a 3-step process by assuming the absence of a soft-start capacitor. first, r sense is chosen and then the time required to charge the load capacitance is determined. this timing, along with the maximum short- circuit current and maximum load supply voltage, de? nes an operating point that is checked against the mosfets soa curve. in addition, consider three other key parameters: applicatio s i for atio wu u u
ltc4216 4216f 18 1. maximum drain-to-source voltage, v ds(max) the v ds(max) rating must exceed the maximum load sup- ply voltage including spikes and ringing. 2. gate-to-source voltage, v gs , overdrive the absolute maximum rating for v gs is typically 8v for logic level and sub-logic level mosfets. 3. drain-to-source resistance, r ds(on) the r ds(on) should be low for low-voltage applications to allow its drain-to-source voltage, v ds(on) , to be a very small percentage of the supply voltage. to begin a design, ? rst specify the maximum operating load current and load capacitance. calculate the r sense value from equation (12). the minimum trip current, i trip(min) , given by equation (14) should be set to accommodate the maximum operating load current. during the start-up cycle, the ltc4216 may operate the mosfet in analog current limit, forcing v acl(th) between 32mv to 48mv across r sense . the minimum inrush current given by equation (16) is calculated using the minimum v acl(th) and maximum r sense value. i v r mv r inrush min acl th min sense max sense max () (, ) () () = ? = 32 (16) the maximum short-circuit current given by equation (17) is calculated using the maximum v acl(th) and minimum r sense value. i v r mv r short circuit max acl th max sense min sense min ? = ? = () (, ) () () 48 (17) select the filter capacitor, c3, based on the slowest expected charging rate; otherwise, filter might time-out before the load capacitor is fully charged. a value for c3 is calculated based on the maximum time it takes the load capacitor, c load , to charge to its maximum value of load supply (v in(max) ). that time is given by: t cv i charge load load in max inrush min () () () = (18) rearranging equation (2) for the circuit breaker response time, the filter capacitor, c3, is given by: c tsa v charge load 3 20 60 1 253 = ? () . () (19) returning to equation (2), the circuit breaker response time is calculated with a chosen c3 and used in conjunction with v in(max) and i short-circuit(max) to check the soa curves of a prospective mosfet. as a numerical design example for the typical application, consider v in(max) = 1.8v + 5%, maximum operating load current = 5a, c load = 1000f. equation (12) gives r sense = 4.3m . choose r sense = 4m 1% tolerance. from equations (14) and (16), i trip(min) = 5.3a (> i load(max) = 5a) and i inrush(min) = 7.9a respectively. equation (19) gives c3 = 10nf. to account for errors in c3, filter current (60a) and filter threshold (1.253v), the calculated value should be multiplied by 1.5, giving the nearest standard value of c3 = 18nf. if a short-circuit occurs, a current of up to i short- circuit(max) = 12.1a will ? ow through the mosfet for 400s as dictated by c3 = 18nf in equation (2). the mosfet must be selected based on this criterion and checked against the soa curve. v cc supply rc network the ltc4216 has two separate pins, v cc and sensep, for supply input and sensing: 1. v cc pin for powering the internal circuitry. 2. sensep pin, together with the sensen pin, for sens- ing the current ? owing from the load supply through the external sense resistor and n-channel mosfet to the output load. in most hot swap devices, v cc and sensep are one common pin, providing the devices supply and external mosfets current sensing. however, supply dips due to output-shorts can potentially trigger the device into an undervoltage lockout condition, causing the device to disable and its internal latches to reset. as bypass capacitors are not allowed on the powered supply side of the external mosfet switch residing on applicatio s i for atio wu u u
ltc4216 4216f 19 figure 13. connecting transient protection devices to the ltc4216s load supply rail the plug-in boards, the ltc4216 provides two separate pins for bias supply input and load supply sensing. with this con? guration, an rc network, r y and c y , shown in figure 13, can be used with the v cc pin to ride out supply glitches during output-shorts or adjacent board shorts. the rc network shown has a time constant of 7s and this is good enough for the supply to ride out most supply glitches, preventing the device from entering an under- voltage lockout condition unnecessarily or losing supply temporarily. when v cc and sensep pins are connected together, the r y value should be chosen such that v cc pin voltage is lower than sensep by 70mv; otherwise, part of v cc pin current will be diverted through sensep pin. this unique scheme of separating the devices supply input and sensing also provides the ? exibility of operating the load supply from ground to its supply rail with a minimum bias supply voltage of 2.3v. for proper operation, the load supply is required to be equal to or less than the bias sup- ply voltage (maximum 6v). supply transients protection there are two methods used in most applications to eliminate supply transients: 1. transient voltage suppressor to clip the transient to a safe level. 2. snubber (series rc) network. for applications with load supply voltages of 3.3v or higher, the ringing and overshoot during hot-swap- ping or output-shorts can easily exceed the absolute maximum rating of the ltc4216. to minimize the risk, a transient voltage suppressor and snubber network are highly recommended at the sensep pin. for ap- plications with load supply voltages of 2.5v or below, usually a snubber network is adequate to reduce the supply ringing. figure 13 shows the connections of the supply tran- sient protection devices, z1, r x and c x , around the ltc4216. the rc network, r y and c y , at the v cc pin also serve as a snubber circuit for the load supply (v in ) . on the pcb layout, these transient protection devices should be mounted very close to the ltc4216s load supply rail using short lead lengths to minimize lead inductance. sensep sensen gate v cc gnd gnd fb filter timer ltc4216** c y 0.33 f c x 0.1 f r4 r3 ss c1 z1 z1: smaj6.0a **additional details omitted for clarity c2 m1 c3 v out 5v c load r sense r y 22 ? r x 10 ? + 4216 f13 v in 5v applicatio s i for atio wu u u staggered pins connections the ltc4216 can be used on either the backplane side of the connector or a printed circuit board, and examples for both are shown in figure 14 and 15. printed circuit board edge connectors with staggered pins are recommended as the insertion and removal of circuit boards will sequence the pin connections. supplies (v cc and sensep) and ground connections on the printed circuit board should be wired to the long pins or blades of the edge connector. control signal (on) and status signals ( ? r ? e ? s ? e ? t and ? f ? a ? u ? l ? t) passing through the edge connector should be wired to short pins or blades. backplane and pcb connection sensing the ltc4216s on pin can be used in various ways to detect whether the printed circuit board is seated properly in the backplane connector before the ltc4216 begins a start-up cycle. an example is shown in figure 14, in which the ltc4216 is mounted on the pcb and the r1/r2 resistive divider is connected to the on pin. on the edge connector, r2 is wired to a short pin. before the connectors are mated, the on pin is held low by r1, keeping the ltc4216 in an off state. when the connectors are mated, the resistive divider is connected to the load supply (v in ) and the on pin voltage rises above 0.8v, turning the ltc4216 on.
ltc4216 4216f 20 an example with ltc4216 mounted on the backplane is shown in figure 15. in this case, the npn transistor, q1, and two resistors, r7 and r8, form the pcb connection sensing circuit with the on pin. with the pcb out of the backplane connector, q1 base is tied to load supply through r7, turning q1 on and pulling the ltc4216s on pin low. the base of q1 is also wired to the backplane connector pin. when the pcb is inserted into the backplane, q1 base is grounded through a short pin connection on the pcb. this turns off q1 and the ltc4216s on pin is allowed to pull high to the load supply through r8, turning it on. in the previous examples, the pcb connection sensing circuits are not wired with interrupt capability from the system controller. as shown in figure 16, adding logic- level discrete n-channel mosfets, m2 and m3, and a couple of resistors allow interrupt control to the sensing circuit. m2 is held on by its gate, pulling high through r8 to the load supply until the pcb is mated ? rmly to the backplane connector. a low logic-level for both the ? ? o ? n/rst and ? o ? n/off signals turns m2 and m3 off, allowing the on pin to be pulled high and turning ltc4216 on. a high logic-level for the ? o ? n/off signal turns off the device and pulls the gate low. the device is reset by pulling the ? o ? n/rst signal high. 5v hot swap application figure 17 shows a hot swap application circuit with v cc and sensep pins connected together to a 5v load supply (v in ). the resistive divider, r1/r2, sets the undervoltage threshold for the load supply and allows the system to start up only after the supply voltage rises above 4v. the resistive divider, r3/r4, monitors v out and signals the applicatio s i for atio wu u u figure 14. single channel 1.5v hot swap controller figure 15. hot swap controller on backplane with staggered pin connections sensep sensen gate timer fb fault reset ss filter ltc4216 c x 100nf c4 10nf r1 20k 1% r4 13k 1% r6 10k r3 10k 1% r2 3.3k 1% long backplane connector (female) pcb edge connector (male) gnd long short c1 10nf c2 10nf c3 68nf v out 1.5v 5a v cc 3.3v v in 1.5v gnd m1 si4864dy r5 10k + c load 4700 f fault reset p logic 4216 f14 long 11 10 9 8 7 12 1 4 2 536 v cc pcb connection sensing on c y 330nf r sense 0.004 ? r y 22 ? r x 10 ? sensep sensen gate timer fault reset fb ss filter ltc4216 c y 330nf r6 10k r9 100k c load 1000 f v out 3.3v 5a r3 10k 1% long backplane connector (female) pcb edge connector (male) gnd long short short short short c1 10nf c2 4.7nf c3 33nf m1 si4864dy r7 10k r5 10k fault reset 4216 f15 11 10 9 8 7 12 1 453 6 q1 2 v cc on r8 10k + r4 39.2k 1% c x 100nf pcb connection sensing v in 3.3v z1 z1: smaj6.0a q1: mmbt3904 r sense 0.004 ? r y 22 ? r x 10 ?
ltc4216 4216f 21 ? r ? e ? s ? e ? t high when v out rises above 4.5v. transient volt- age suppressor, z1, and snubber network, r x and c x , connected at sensep pin are highly recommended to protect the 5v supply system from ringing and voltage spikes during a fault condition. the rc network, r y and c y , connected at the v cc pin, allows the ltc4216 bias supply to ride out supply glitches during a fault condition or adjacent board shorts. auto-retry after a fault as shown in figure 18, the ltc4216 can be con? gured to automatically retry after a fault condition by connecting both the ? f ? a ? u ? l ? t and on pins together with an rc network. the network has a pull-up resistor, r auto , tied to the load supply (v in ) and an external capacitor, c auto , connected to ground. the auto-retry circuit will attempt to restart the ltc4216 after a circuit breaker trip, as shown in the timing diagram of figure 19. in addition to the cooling cycle provided by the timer period during auto-retry sequence, the rc time constant for the on pin voltage to reach 0.8v provides additional turn-off time to prevent the external mosfet from overheating. the auto-retry duty cycle is given by: duty cycle tt tt tt ss filter off timer ss filter + +++ ? 100 (20) where t timer = timer period as given by equation (1); t off = time taken to charge the capacitor, c auto , from ? f ? a ? u ? l ? t v ol to v on(th) threshold (0.8v). as there is an internal 5a current source pull-up at the ? f ? a ? u ? l ? t pin, it sensep sensen gate on timer fb fault reset ss 11 10 9 8 7 12 1 4 2 536 filter ltc4216 r1 5.62k 1% r5 39.2k 1% r7 10k r4 10k 1% r2 4.42k 1% r3 20k 1% r8 10k c y 330nf c x 100nf long backplane connector (female) pcb edge connector (male) gnd long short short short c1 10nf c2 4.7nf c3 33nf v out 3.3v 5a v in 3.3v on/rst on/off gnd m1 si4864dy r6 10k + c load 1000 f long v cc 5v fault reset p logic 4216 f16 v cc z1 m2 m3 z1: smaj6.0a m2, m3: 2n7002k pcb connection sensing r sense 0.004 ? r y 22 ? r x 10 ? figure 16. pcb connection sensing with on/off control applicatio s i for atio wu u u sensep sensen gate on fb fault reset ss 11 10 9 8 7 12 1 4 2 536 filter ltc4216 r4 64.9k 1% r6 10k r3 10k 1% r1 20k 1% c y 330nf c z 10nf c x 100nf r2 80.6k 1% long short long backplane connector (female) pcb edge connector (male) gnd c1 10nf c2 4.7nf c3 22nf v out 5v 5a v in 5v gnd m1 si4864dy r5 10k + c load 470 f fault reset p logic 4216 f17 v cc z1: smaj6.0a timer z1 r sense 0.004 ? r z 100 ? r y 22 ? r x 10 ? figure 17. 5v hot swap application
ltc4216 4216f 22 timer sensep?ensen sensep filter ss 2.4 a v tmr(th) v filt(th) 2 a v tmr(th) 2 a 40mv 25mv 10 a 10 a 1 a 1 2346789 0.4v 0.8v v ol 10 11 12 13 14 5 check for gate, filter, timer, ss < 0.2v check for gate, filter, timer, ss < 0.2v and fault high 4216 f19 on/fault 0.8v electronic circuit breaker armed output in analog current limit on/fault pulled low device reset 1st timing cycle restart filter ramps up when (v sensep ? sensen ) >25mv gate (v gate ?v out ) > v gs(th) tracks ss ramp gate regulating 60 a t filter t ss t off t timer t rst(onlo) t off t timer figure 19. auto-retry timing complicates the equation for t off . this is approximately given by: t rc v v vv r a off auto auto on th ol in on th auto ? + ( ) ( ) () () 5 (21) t filter = circuit breaker response time as given by equation (2); t ss = approximated time taken to charge the soft-start capacitor, c2, from 0v to its ? nal value (1.65v) by 10a current source only. for the component values shown, the external rc time constant is set at 0.2 second, t timer = 62ms, t off = 25ms at v in = 5v, t ss = 1.6ms, t filter = 480s and the auto-retry duty cycle is 2.3%. the auto-retry duty cycle can be further reduced by increasing both the t timer delay and the rc delay. as an example, increasing the timer capacitor, c1, value from 100nf to 330nf, and r auto value from 200k to 470k reduces the duty cycle to 0.8%. applicatio s i for atio wu u u figure 18. auto-retry application sensep sensen gate on fb ss 11 10 9 8 7 12 1 4 2 53 6 filter ltc4216 r3 10k 1% r4 64.9k 1% c y 330nf c x 100nf r auto 200k c auto 1 f r5 10k long short long backplane connector (female) pcb edge connector (male) gnd c1 100nf c2 4.7nf c3 22nf v in 5v v out 5v 5a gnd m1 si4864dy + c load 470 f v cc z1: smaj6.0a timer z1 fault reset reset 4216 f18 r sense 0.004 ? r y 22 ? r x 10 ?
ltc4216 4216f 23 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom view?xposed pad 1.70 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 0.25 0.05 3.30 0.10 (2 sides) 1 6 12 7 0.50 bsc pin 1 notch pin 1 top mark (note 6) 0.200 ref 0.00 ?0.05 (ue12/de12) dfn 0603 0.25 0.05 3.30 0.05 (2 sides) recommended solder pad pitch and dimensions 1.70 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695) package descriptio u
ltc4216 4216f 24 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/tp 0205 1k ? printed in usa part number description comments ltc1421 dual channels, hot swap controller operates from 3v to 12v, supports -12v, ssop-24 ltc1422 single channel, hot swap controller operates from 2.7v to 12v, so-8 ltc1642 single channel, hot swap controller operates from 3v to 16.5v, overvoltage protection up to 33v, ssop-16 ltc1645 dual channel, hot swap controller operates from 3v to 12v, power sequencing, so-8 or so-14 ltc1647-1/ltc1647-2/ dual channel, hot swap controller operates from 2.7v to 16.5v, so-8 or ssop-16 ltc1647-3 ltc4210 single channel, hot swap controller operates from 2.7v to 16.5v, active current limiting, sot23-6 ltc4211 single channel, hot swap controller operates from 2.5v to 16.5v, multifunction current control, msop-8 or msop-10 ltc4212 single channel, hot swap controller operates from 2.5v to 16.5v, power-up timeout, msop-10 ltc4214 negative voltage, hot swap controller operates from C 6v to C16v, msop-10 lt4220 positive and negative voltage, operates from 2.7v to 16.5v, ssop-16 dual channels, hot swap controller ltc4221 dual hot swap controller/sequencer operates from 1v to 13.5v, multifunction current control, ssop-16 ltc4230 triple channels, hot swap controller operates from 1.7v to 16.5v, multifunction current control, ssop-20 typical applicatio u related parts sensep sensen gate on fb filter ltc4216 r4 64.9k 1% r3 10k 1% c4 22nf c y 330nf c x 100nf r5 10k long short short long backplane connector (female) pcb edge connector (male) gnd c1 10nf c3 68nf v out 5v 2a v in 5v gnd m1 si9426dy + c load 470 f 4216 f20 v cc z1: smaj6.0a timer z1 reset reset r2 10k r sense 0.01 ? r y 22 ? r6 10 ? r x 10 ? figure 20. ltc4216cms with gate capacitor for slew rate control

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