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general description the MAX9526 is a low-power video decoder that con- verts ntsc or pal composite video signals to 8-bit or 10-bit ycbcr component video compliant with the itu- r bt.656 standard. the device powers up in fully oper- ational mode and automatically configures itself to decode the detected input standard. the MAX9526 typically consumes 200mw of power in normal opera- tion and typically less than 100? in shutdown mode. an internal 10-bit, 54mhz analog-to-digital converter (adc) samples the input with four times oversampling. the MAX9526 features a dc restoration circuit with off- set correction and automatic gain control to accurately optimize the full-scale range of the adc. an integrated analog anti-aliasing filter eliminates the need for external filtering. the MAX9526 includes a 2:1 input multiplexer with automatic signal selection based on activity at the inputs. an internal line-locked phase-locked loop (pll) gener- ates the sample clock and the line-locked clock (llc) output to provide an itu-compliant output. alternatively, the pll can be configured to provide a sample clock and output clock at 2x and 1x the frequency of the crystal oscillator, respectively. the MAX9526 provides a multiline adaptive comb filter to reduce cross-chrominance and cross-luminance artifacts. a single 1.8v supply is used for both the digital and analog supplies. the digital outputs operate from a separate +1.7v to +3.45v supply to allow direct con- nection to a wide range of digital processors. the MAX9526 operates over the -40? to +125? automo- tive temperature range and is available in both a 28-pin qsop and a 32-pin tqfn (5mm x 6mm). applications automotive entertainment systems collision avoidance systems security surveillance/cctv systems televisions features supports all ntsc and pal standards ntsc m, ntsc j, ntsc 4.43, pal b/g/h/i/d, pal m, pal n, pal 60 easy to configure and operate with only 16 user-programmable registers automatic configuration and standard select 10-bit 4x oversampling (54msps) adc with true 10-bit digital processing flexible output formatting 10-bit parallel itu-r bt.656 output with embedded trs 8-bit parallel itu-r bt.656 output with separate hs and vs +1.8v digital and analog supply voltage +1.7v to +3.45v digital i/o supply voltage full automotive temperature range (-40? to +125?) low-power modes shutdown (< 100 w typ) sleep mode with continuous activity detection (< 5mw typ) 2-to-1 video input mux with agc MAX9526 low-power, high-performance ntsc/pal video decoder ________________________________________________________________ maxim integrated products 1 19-4535; rev 0; 5/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. analog front-end digital decoder output processing sync processing, clock generation, and pll i 2 c interface and registers v in1 v in2 xtal/osc xtal2 sda scl devaddr irq d9?0 llc clock 10 10 10 nonstd video MAX9526 functional diagram ordering information part temp range pin-package MAX9526aei+ -40? to +125? 28 qsop MAX9526atj+ -40? to +125? 32 tqfn-ep* + denotes lead(pb)-free/rohs-compliant package. * ep = exposed pad.
MAX9526 low-power, high-performance ntsc/pal video decoder 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = v dvdd = +1.8v, v dvddio = +3.3v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to agnd .......................................................-0.3v to +2v dvdd to dgnd ........................................................-0.3v to +2v dvddio to dgnd .................................................-0.3v to +3.6v agnd to dgnd.....................................................-0.1v to +0.1v d9?0, llc to dgnd .........................-0.3v to (dvddio + 0.3v) v in1 , v in2 , v ref to agnd .......................-0.3v to (avdd + 0.3v) xtal/osc, xtal2 to agnd ....................................-0.3v to +2v irq , sda, scl, devadr to dgnd ......................-0.3v to +3.6v continuous current in/out all pins ...................................?0ma continuous power dissipation (t a = +70?) 28-pin qsop single-layer board (derate 10.8mw/? above +70?) .............................860mw 28-pin qsop multilayer board (derate 12.6mw? above +70?) ............................1009mw 32-pin tqfn multilayer board (derate 20.8mw/? above +70?) ...........................1663mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supplies analog supply voltage range avdd 1.7 1.8 1.9 v digital supply voltage range dvdd 1.7 1.8 1.9 v digital i/o supply voltage range dvddio 1.7 3.3 3.45 v normal operation 42 55 sleep mode 2.2 3 ma analog supply current (note 2) i avdd shutdown 0.5 100 ? normal operation 70 110 ma sleep mode 5 1000 digital supply current (note 2) i dvdd shutdown 5 1000 ? normal operation, v dvddio = 1.8v 3.5 normal operation, v dvddio = 3.3v 6.4 ma sleep mode, v dvddio = 3.3v 0.8 10 digital i/o supply current (note 2) i dvddio shutdown, v dvddio = 3.3v 0.8 10 ? video inputs, v ref , and clamp input voltage range guaranteed by full-scale conversion range 0.27 0.5 0.83 v p-p input resistance r in 2m input capacitance c in 8pf video input reference voltage (vref) v ref 850 mv sync-tip clamp level v clmp2 activity detect clamp 550 mv input clamping current activity detect clamp, v vin = v clmp2 + 150mv 2.0 ?
MAX9526 low-power, high-performance ntsc/pal video decoder _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units sync slice comparator level activity detect slicer, referenced to v clmp 50 mv slow 3 medium 6 medium-fast (default) 12 dc restore current dac full- scale range (source and sink) (note 3) fast 24 ? agcgain = 0x0, adagc = 1 0.51 d c restor e s ync- ti p level at v in1 /v in2 agcgain = 0xf, adagc = 1 0.72 v analog input filter and adc (note 4) c utoff fr eq uency ( 3d b) f 3db 13 mhz p assb and fl atness f < 5mhz, v vin = 0.65v p-p , reference level measured at 1mhz 0.25 db s top b and c utoff f s b 53 mhz s top b and attenuati on f > f sb , v vin = 0.65v p-p , reference level measured at 1mhz 36 db agc gain = 0x0 670 830 ful l - s cal e c onver si on rang e agc disabled, gain programmed using i 2 c (adagc = 1), referenced to v in1 /v in2 agc gain = 0xf 270 330 mv p-p agc gai n s tep si ze 0.167 v/v d i ffer enti al n onl i near i ty d n l agcgain = 0x0, adagc = 1 ?.5 lsb integ r al n onl i near i ty in l agcgain = 0x0, adagc = 1 1 lsb s i g nal - to- n oi se rati os n r incl ud es fi l ter + ad c + d i g i tal anti - al i asi ng fi l ter , i np ut i s - 1d bfs ; ad ag c = 1, agc gain [ 3:0] = 0x0, d efi ned as r ati o of rm s si g nal to rm s noi se i n d b 58.8 db 1.7v < v av d d < 1.9v , 1.7v < v d v d d < 1.9v -40 v av d d = 1.8v + 100m v p - p at 500kh z -67 v av d d = 1.8v + 100m v p - p at 3.58m h z -58 p ow er - s up p l y rej ecti on p s r ad agc = 1 agc gain [ 3:0] = 0x0 i np ut l evel = 1m h z si ne w ave at - 2d bfs v av d d = 1.8v + 100m v p - p at 4.43m h z -57 dbfs d i ffer enti al p hase dp 5-step modulated staircase, f = 3.58mhz or 4.43mhz 1.0 degrees electrical characteristics (continued) (v avdd = v dvdd = +1.8v, v dvddio = +3.3v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1)
MAX9526 low-power, high-performance ntsc/pal video decoder 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v dvdd = +1.8v, v dvddio = +3.3v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units d i ffer enti al gai ndg 5- step m od ul ated stai r case, f = 3.58m h z or 4.43m h z 1% 2t p ul se resp onse 2t = 200ns or 250ns 0.4 % 2t bar resp onse bar ti m e i s 18?, the beginning 2.5% and ending 2.5% of the bar time are ignored, 2t = 200ns or 250ns 0.2 % 2t p ul se to bar rati ng bar ti m e i s 18?, the beginning 2.5% and ending 2.5% of the bar time are ignored, 2t = 200ns or 250ns 0.2 % gr oup d el ay d i stor ti on 100kh z < f < 5m h z1ns d ec o d ed l u m in a n c e a n d c h r o m in a n c e c h a n n el s ( n o t e 5 ) c hr om a band w i d th bw c 1mhz lum a band w i d th bw l 5.5 mhz lum a n onl i near i ty 5- step stai r case 1 % lum a li ne ti m e d i stor ti on ( h - ti l t) ld m easur ed at the outp ut r eg ar d i ng acti ve vi d eo 0.5 % lum a fi el d ti m e d i stor ti on ( v - ti l t) fd m easur ed at the outp ut r eg ar d i ng acti ve vi d eo 0.1 % d ig it a l c o m po si t e d ec o d er lock ti m e 3 frames h or i zontal li ne ti m e s tati c v ar i ati on -5 +5 % m axi m um h or i zontal li ne ti m e ji tter ( async m od e) 5s m axi m um h or i zontal li ne ti m e ji tter ( llc m od e) 160 ns li ne- locked c l ock fr eq uency f llc v ar i es w i th i np ut l i ne r ate 27 mhz m i ni m um p eak s i g nal to rm s n oi se p r op er com p osi te d ecod er op er ati on 23 db pl l async m od e ji tter id eal i np ut cl ock 20 ps rms 000 180 001 250 010 375 011 ( d efaul t) 500 100 750 101 1000 110 1500 li ne- locked p ll loop band w i d th s et b y reg i ster 0x0e [ 2:0] 111 2000 hz
MAX9526 low-power, high-performance ntsc/pal video decoder _______________________________________________________________________________________ 5 electrical characteristics (continued) (v avdd = v dvdd = +1.8v, v dvddio = +3.3v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units crystal oscillator fr eq uency fund am ental m od e onl y 27.000 mhz x tal/os c , x tal2 inp ut c ap aci tance c x ta l , c x ta l2 4pf m axi m um load c ap aci tor c l1 , c l2 45 pf fr eq uency accur acy ?0 ppm x tal/os c log i c- low thr eshol d v il x tal osci l l ator d i sab l ed , cl ock i np ut m od e ( x tald is = 1) 0.3 x v dvdd v x tal/os c log i c- h i g h thr eshol d v ih x tal osci l l ator d i sab l ed , cl ock i np ut m od e ( x tald is = 1) 0.7 x v dvdd v x tal/os c inp ut leakag e c ur r ent i ih, i il x tal osci l l ator d i sab l ed , cl ock i np ut m od e ( x tald is = 1) -10 ?.01 +10 ? m axi m um inp ut c l ock ji tter 500 ps p-p i 2 c serial interface (note 6) serial-clock frequency f scl 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd , sta 0.6 ? scl pulse-width low t low 1.3 ? scl pulse-width high t high 0.6 ? setup time for a repeated start condition t su,sta 0.6 ? data hold time t hd , dat 0 900 ns data setup time t su , dat 100 ns sda and scl receiving rise time (note 7) t r 20 + 0.1c b 300 ns sda and scl receiving fall time (note 7) t f 20 + 0.1c b 300 ns v dvddio = 3.3v 20 + 0.1c b 250 sda transmitting fall time (note 7) t f v dvddio = 1.8v 150 ns setup time for stop condition t su , sto 0.6 ? bus capacitance c b 400 pf pulse width of suppressed spike t sp 050ns high-speed logic outputs (d9?0, llc) i ol = 5ma, v dvddio = 3.3v 0.4 output low voltage v ol i ol = 2ma, v dvddio = 1.7v 0.4 v
MAX9526 low-power, high-performance ntsc/pal video decoder 6 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v dvdd = +1.8v, v dvddio = +3.3v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units i oh = 5ma, v dvddio = 3.3v v dvddio x 0.8v output high voltage v oh i oh = 2ma, v dvddio = 1.7v v dvddio - 0.4v v data to llc rising edge hold time t hd 13.5 18.5 23.5 ns data to llc rising edge setup time t su 13.5 18.5 23.5 ns c l = 10pf, v dvddio = 1.8v 3 rise and fall time t r , t f c l = 25pf, v dvddio = 3.3v 3 ns output leakage i oh , i ol outputs in high-impedance mode -10 ?.01 +10 ? open-drain outputs (sda and irq ) i ol = 3ma, 1.7v < v dvddio < 2v 0.2 x v dvddio output low voltage v ol i ol = 3ma, 2v < v dvddio < 3.3v 0.4 v output high current i oh v out = 3.3v ?.01 10 ? logic inputs (sda, scl, devadr) logic-low threshold v il 0.3 x v dvddio v logic-high threshold v ih 0.7 x v dvddio v input leakage current i ih, i il -10 ?.01 +10 ? sda/scl off leakage current i ih avdd = dvdd = dvddio = 0v -10 ?.01 +10 ? note 1: all devices are 100% production tested at t a = +25?. specifications over temperature limits are guaranteed by design. note 2: ntsc 75% color bar signal applied to video input. c l = 10pf on d9?0 and llc. external xtal. note 3: internal test only. digital core controls sync level adjustment current to adjust offset in analog signal path. adjust level is based on value of sync level as converted by adc. digital core switches sourcing or sinking current into v in1 or v in2 nodes. speed of correction (value of current) is controlled through i 2 c. note 4: filter and adc performance measured using adc outputs prior to composite digital demodulation (decoding). note 5: decoded luminance and chrominance specifications measured using entire signal path from video input to digital compo- nent outputs. note 6: v dvddio = 1.8v and 3.3v. note 7: c b is in pf.
MAX9526 low-power, high-performance ntsc/pal video decoder _______________________________________________________________________________________ 7 full-scale conversion range MAX9526 toc01 gain code (reg0x0a[3:0]) (decimal) full-scale input range (mv p-p ) 5 10 400 600 800 200 015 analog input filter response MAX9526 toc02 frequency (mhz) amplitude (db) 10 1 -30 -20 -10 0 -40 0.1 100 adc effective number of bits vs. input frequency MAX9526 toc03 frequency (mhz) enob (lsb) 4 2 7.5 8.0 8.5 9.0 9.5 10.0 7.0 06 agcgain = 0000 digital anti-aliasing filter disabled adc snr vs. gain code MAX9526 toc04 agc gain code (reg0x0a[3:0]) (decimal) snr (db) 10 5 51 52 53 54 55 56 57 58 59 60 50 015 digital composite anti-aliasing filter MAX9526 toc05 frequency (mhz) amplitude (db) 20 10 -70 -60 -50 -40 -30 -20 -10 0 10 -80 030 digital y filter MAX9526 toc06 frequency (mhz) amplitude (db) 20 10 -70 -60 -50 -40 -30 -20 -10 0 10 -80 030 digital cb/cr filter MAX9526 toc07 frequency (mhz) amplitude (db) 68 24 -70 -60 -50 -40 -30 -20 -10 0 10 -80 010 pal ntsc digital notch filter MAX9526 toc08 frequency (mhz) amplitude (db) 68 24 -70 -60 -50 -40 -30 -20 -10 0 10 -80 0 pal ntsc decoded video output 100% color bars (y waveform) MAX9526 toc09 time ( s) amplitude (lsb) 40 20 200 400 600 800 1000 0 060 typical operating characteristics (v avdd = v dvdd = +1.8v, v dvddio = 3.3v, v agnd = v dgnd = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.)
MAX9526 low-power, high-performance ntsc/pal video decoder 8 _______________________________________________________________________________________ decoded video output 100% color bars (cb waveform) MAX9526 toc10 time ( s) amplitude (lsb) 40 20 200 400 600 800 1000 0 060 decoded video output 100% color bars (cr waveform) MAX9526 toc11 time ( s) amplitude (lsb) 40 20 200 400 600 800 1000 0 060 output clock jitter vs. pll bandwidth MAX9526 toc12 pll bandwidth (hz) output clock jitter (ns) 1500 1000 500 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0 2000 output clock jitter vs. video input level MAX9526 toc13 video input level (v) output clock jitter (ns) 0.6 0.5 0.3 0.4 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0.6 0.2 0.7 pllbw = 180hz output clock jitter vs. video input snr MAX9526 toc14 temperature ( c) output clock jitter (ns) 50 40 30 20 0.5 1.0 1.5 2.0 2.5 3.0 0 10 60 async mode llc mode pllbw = 180hz shutdown supply current vs. temperature MAX9526 toc15 temperature ( c) supply current ( a) 120 80 40 0 1 10 100 1000 0.1 -40 dvddio avdd dvdd power-supply rejection vs. frequency MAX9526 toc17 frequency (mhz) amplitude (dbfs) 1 0.1 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -90 0.01 10 avdd = 1.8v + 100mv p-p agcgain = 1111 agcgain = 0000 typical operating characteristics (continued) (v avdd = v dvdd = +1.8v, v dvddio = 3.3v, v agnd = v dgnd = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) video input and adc output 100% color bars MAX9526 toc16 time ( s) video input (v) adc output (lsb) 60 50 10 20 30 40 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0.5 200 400 600 800 1000 0 070
MAX9526 low-power, high-performance ntsc/pal video decoder _______________________________________________________________________________________ 9 pin description pin qsop tqfn-ep name function 130v in1 single-ended composite video input 1. ac-couple the input video signal with a 0.1? capacitor. 231v ref video reference bypass. bypass v ref to agnd with a 0.1? capacitor as close as possible to the device. 332v in2 single-ended composite video input 2. ac-couple the input video signal with a 0.1? capacitor. 4 1 agnd analog ground 5 2 avdd analog power-supply input. connect to a +1.8v supply. bypass avdd to agnd with a 0.1? capacitor. 6 3 xtal2 external crystal. connect xtal2 to one terminal of the crystal oscillator. ground xtal2 when applying an external clock to xtal/osc. 7 4 xtal/osc external crystal/oscillator. connect xtal/osc to one terminal of a crystal or an external clock source. connect xtal2 to the other terminal of the crystal oscillator. 8 5 i.c. internal connection. connect to dgnd. 9 6 devadr i 2 c device address select input. connect to dvdd, dgnd, or sda to select 1 of 3 available i 2 c slave addresses (see table 5). 10, 22 7, 21 dvdd digital power-supply input. connect to a +1.8v supply. bypass dvdd to dgnd with a 0.1? capacitor in parallel with a 10? capacitor. 11, 23 8, 22 dgnd digital ground. connect both dgnd terminals together. 12 10 sda i 2 c-compatible serial-data input/output. connect a 10k pullup resistor from sda to dvddio for full output swing. 13 11 scl i 2 c-compatible serial-clock input. connect a 10k pullup resistor from scl to dvddio for full output swing. 14 12 irq hardware interrupt open-drain output. if not masked, irq is pulled low when the bits in the status register change state. repeated faults have no effect on irq until irq is cleared by reading the corresponding status register. connect a 10k pullup resistor from irq to dvddio for full output swing. 15?0, 25?8 13?6, 18, 19, 24, 26, 27, 28 d0?9 digital video outputs bit 0?it 9, 10-bit component digital video outputs. the output format is 10-bit itu-r bt.656, 4:2:2 with embedded sync. d1 and d0 can be configured as horizontal and vertical sync outputs using the clock and output register 0x0d. d0 is lsb. 21 20 llc line-locked 27mhz clock output. with line-locked mode, the llc clock varies in response to horizontal line rate of the incoming video. in async mode, the llc clock is synchronous to the crystal (see table 1). 24 23 dvddio digital i/o power-supply input. accepts a +1.7v to +3.45v voltage input. bypass to dgnd with a 0.1? capacitor. 9, 17, 25, 29 n.c. no connection. not internally connected. ep exposed pad. ep is internally connected to gnd. connect ep to gnd.
MAX9526 detailed description the MAX9526 is a simple, low-power video decoder that converts all modes of ntsc and pal composite video signals to 10-bit ycbcr component video com- patible with the itu-r bt.656 standard. the device powers up in fully operational mode and automatically configures itself to standard ntsc or standard pal. an internal 10-bit, 54mhz adc samples at four times the sampling rate specified in itu-r bt.601. the ana- log front-end of the MAX9526 features a dc restoration circuit, automatic gain control, and automatic offset cor- rection. these blocks are controlled with digital pro- cessing to accurately optimize the full-scale range of the adc. an integrated analog anti-aliasing filter elimi- nates the need for off-chip filtering. the device includes a 2:1 input multiplexer that can be configured to auto- matically select the input based on activity. the system clock is generated with an external 27mhz crystal and an internal oscillator. optionally, a 27mhz or 54mhz external clock can be connected to the xtal/osc input. an internal line-locked digital pll is used to generate the 54mhz adc sample clock that is synchronous to the incoming video signal with up to ?% variation in horizontal line length. the digital out- put data and llc clock are line locked to the video input and provide a standard itu output. the pll can also be configured to asynchronously sample the input using the crystal oscillator or external clock. the MAX9526 provides a 5-line adaptive comb filter to separate the luminance (y) and chrominance (c) video components and reduce cross-chrominance and cross- luminance artifacts. the MAX9526 operates with any type of standard composite video signal source includ- ing dvd players, video cameras, navigation systems, and vcrs. the device powers up in fully operational video decoder mode. an i 2 c register interface monitors status and enables programming of many decoder functions including brightness, contrast, saturation, and hue. the 10-bit output can be reconfigured to provide 8-bit data with separate horizontal and vertical syncs. analog front-end (afe) the MAX9526 afe implements dc restoration, auto- matic gain control (agc), analog anti-aliasing filter (lpf), activity detection, channel selection, and analog- to-digital conversion. a block diagram of the afe is shown in figure 1. activity detect and automatic channel selection the MAX9526 continuously monitors activity at both video inputs, v in1 and v in2 . activity on the selected channel is detected using the adc output. on the unselected channel an analog sync-tip clamp and sync slicer are used to detect sync amplitudes greater than 50mv. in sleep mode, the analog sync-tip clamps and sync slicers are used to detect activity on both inputs, while the rest of the afe is in a shutdown state. the output of the activity detect circuit is reported through the status register 0x00. the user must manu- ally select which video input to process by setting insel in register 0x09 appropriately. the MAX9526 can optionally be configured to automati- cally select the video input that indicates the presence of activity by setting autosel = 1 in register 0x09. when activity is present on both v in1 and v in2 at power-up or when there is no activity on either input channel, v in1 is selected. when there is activity on v in2 and there is no activity on v in1 , then v in2 is selected. when v in2 is automatically selected with the presence of activity, the input only switches to v in1 when activity goes away on v in2 . low-power, high-performance ntsc/pal video decoder 10 ______________________________________________________________________________________ internal bias analog agc analog lpf dc restoration dac digital filtering digital control activity detect 10-bit adc to decoder 10 10 v in1 v in2 v ref figure 1. analog front-end
v ref generation a differential signal path is used to process the analog video signal to minimize the effect of noise coupling. a dc reference (v ref ) of 850mv is internally generated and decoupled externally with a 0.1? capacitor. identical signal paths and video buffers are used for both the selected video input and the video reference voltage. the signals are converted to a fully differential signal by the analog agc circuit. dc restoration dac the video inputs, v in1 and v in2 , are ac-coupled to the MAX9526 with 0.1? capacitors. the dc restoration cir- cuit sets the sync level at the output of the adc by sink- ing or sourcing current at the selected video input. a digital control at the adc output is used to monitor the average sync level. an error signal is generated in the digital control block that is used by a current dac to source or sink current to the ac-coupled input to restore the dc level. the dc restoration circuit also cor- rects the offset in the analog signal chain and sets the sync level at the adc output to code 32 (decimal). analog automatic gain control (analog agc) the MAX9526 includes an analog variable-gain amplifi- er with a digitally controlled gain for automatic gain control (agc). the agc uses the sync amplitude at the output of the adc to control the gain. for signals with- out copy protection, the agc adjusts the gain until the sync amplitude is 208 (decimal) codes at the adc out- put. for inputs with copy protection, the agc automati- cally compensates for the reduced sync amplitude on active lines. the analog agc loop can be disabled and the gain is set manually to 1 of 16 values using the gain control register 0x0a. the range of analog gain is 3.5db to 12db. analog lowpass filter (lpf) the MAX9526 includes a high-performance anti-aliasing analog lowpass filter with a 3db bandwidth of 13mhz (typ) and better than 0.25db (typ) passband flatness to 5mhz. this eliminates the need for external filtering on the video inputs. the filter typically provides 36db atten- uation at 53mhz (1mhz below adc sample rate). 54msps video adc a 10-bit, 54msps adc converts the filtered analog composite video signal for digital signal processing (composite video demodulation). digital filtering digital filtering at the adc output removes any out-of- band interference and improves the signal-to-noise ratio before decoding. the signal path includes a digi- tal anti-aliasing lowpass filter that has 1db of passband flatness to 5.5mhz and a minimum of 45db of stopband attenuation for frequencies greater than 9mhz. sync processing, clock generation, and pll the sync processing, clock generation, and pll extract the timing information from incoming video and gener- ate the clock for the rest of the chip. figure 2 shows the block diagram for this block. crystal oscillator/clock input the MAX9526 includes a low-jitter crystal oscillator cir- cuit optimized for use with an external 27mhz crystal. the device also accepts an external cmos logic-level clock at either 27mhz or 54mhz. to use an external clock (27mhz or 54mhz) instead of a crystal, set xtal_dis = 1 in register 0x0d. to use a 54mhz exter- nal clock instead of a 27mhz clock, sel_54mhz must also be set to 1 in register 0x0d. MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 11 oscillator xtal/osc xtal2 clock generator and pll sync processing 10 from afe mux clock nonstd video mux figure 2. sync processing, clock generation, and pll
MAX9526 sync processing the sync processing block extracts the sync information and automatically detects 525 line or 625 line inputs. clock generator and pll the pll operates in either line-locked clock (llc) mode or async mode. selection of the mode is con- trolled automatically by the MAX9526 or can optionally be overwritten with the llc_mode bits in pll control register 0x0e. in llc mode, a hybrid analog/digital pll generates a low-jitter line-locked clock. the 54mhz sample clock is synchronous to the input video. the llc clock output is also synchronous to the input video. the itu output has the correct number of samples per line and lines per field. the pll is designed to lock to signals with up to 160ns peak jitter. when the jitter exceeds the 160ns peak, the pll coasts until the jitter improves. if the jitter continuously exceeds the 160ns peak, the pll relocks and the hlock status bit in register 0x00 is set to 0. in llc mode, the bandwidth of the pll can be option- ally programmed to one of eight values between 180hz and 2000hz using the pllbw bits in pll control regis- ter 0x0e. the default value for the pll bandwidth is 500hz. in async mode, the sample clock frequency is generat- ed by multiplying the crystal frequency by a factor of two and the video signal is sampled asynchronously with the 2x crystal clock. to eliminate artifacts, the MAX9526 uses an adaptive poly-phase filter to correct timing and phase errors introduced by the asynchro- nous sampling. the llc output is generated by divid- ing the 54mhz sampling clock by two. the itu output in async mode has the correct number of lines per frame and the correct number of pixels per line except on the first line of each field. the timing correc- tion block uses this line to compensate for timing errors between the incoming video signal and the crystal. as a result, the first line of each field is longer or shorter for several pixels depending on the magnitude of the fre- quency difference between the incoming video signal and the local crystal. for example, a 100ppm frequency difference between the incoming video signal and the crystal results in approximately 23 extra or fewer pixels on the first line of each field. line length errors on line one are of no consequence for most applications since it is in the vertical blanking interval and does not contain active video or any other type of data. the types of inputs that cause the pll to automatically switch to async mode are video inputs with a nonstan- dard carrier frequency. for standard video, the carrier frequency is always a precise multiple of the horizontal frequency. a typical nonstandard input is video cassette recorders in which the carrier is not a precise multiple of the horizontal frequency. the nonstandard detect (nonstd) status from the decoder is used to automati- cally switch the pll to async mode when nonstandard carrier frequencies are detected. the nonstd status is monitored in the status register 0x00. clocking modes in addition to automatic configuration, the MAX9526 can also be manually configured to provide maximum flexibility in setting the clock inputs and outputs of the chip. table 1 summarizes the clocking modes that are supported. digital composite decoding figure 3 shows a block diagram of the digital compos- ite decoder. this block converts the digitized compos- ite video signal to digital component video. sync level correction and sync extraction the sync extraction function extracts the raw sync sig- nals from the video and the extracted sync information is sent to the sync processor. the sync level from the afe is code 32 (decimal) on a 10-bit scale and the blanking level is approximately 208 (decimal) codes above the sync level. the sync slicer default threshold is set to approximately the middle of the sync pulse at decimal code 128. the sync slice level can optionally be manually adjusted using the slice bits in register 0x0f. the sync level correction block features an optional digital clamp that can be enabled in register 0x09. enabling the digital clamp sets the sync level to code 0 (decimal) and gives higher frequency tracking of the input signals. when the digital clamp is enabled, the sync slice level in register 0x0f should be adjusted accordingly to provide equivalent noise rejection. sync processor and analog copy protection detection the sync processor extracts the horizontal sync and vertical sync signals. field pulses and burst gate puls- es are generated based on vsync and hsync, respectively. the sync processing block provides sync timing to measure the sync level and amplitude for the black level control and composite agc. the sync processor also detects incoming video signal stan- dards (525 line ntsc and 625 line pal). video stan- dard information is available in status register 0x01. the detected video standard is used to automatically configure the decoder. the MAX9526 detects ntsc-m (standard ntsc) and pal b/g/h/i/d (standard pal) low-power, high-performance ntsc/pal video decoder 12 ______________________________________________________________________________________
standards automatically. see the standard select, shutdown, and control register section for manual pro- gramming. the sync processor block also detects analog copy protection. extracted copy protection information is available in status register 0x01. composite automatic gain control (agc) in addition to the analog agc that optimizes the adc full-scale range, a digital agc is used to more accu- rately set the video amplitude. the composite agc uses the amplitude of the sync signal to set the gain. adaptive comb filter the MAX9526 uses a 5-line adaptive comb filter to sep- arate luminance and chrominance components from a single composite channel. the adaptation algorithm does not require configuration. the adaptive comb filter adjusts based on the relationship and content of video data between neighboring lines. the filter automatically adapts the comb filter structure between a 5-line filter and a notch filter. chrominance signal demodulator after luminance (y) and chrominance (c) components are separated, the y component passes through a delay line to compensate for the c component delay through the demodulator. the chrominance signal path contains an agc before the signal demodulator. the chrominance agc uses the color burst amplitude to set the gain. the chrominance is demodulated using a subcarrier signal locked to the burst. the demodulated chrominance signals, cb and cr, are lowpass filtered to eliminate unwanted products of demodulation. output formatting figure 4 shows the output formatting section of the MAX9526. image enhancement and color correction the MAX9526 provides contrast, brightness, hue, and saturation manual control in registers 0x05 to 0x08. time base correction the MAX9526 provides time base correction (tbc) to allow the decoder to properly process unstable and nonstandard video from sources such as a vcr. the time base correction minimizes the effect of sampling jitter to ensure that there are a correct number of pixels per active line. test pattern insertion the MAX9526 automatically outputs a black screen when there is no video at the inputs. the test pattern can also be configured to provide a blue screen, 75% color bars, or 100% color bars through register 0x0c. timing reference signal insertion and itu-r bt.656 encoding the MAX9526 multiplexes the y, cr, and cb signals with an embedded timing reference signal conforming to the itu-r bt.656 standard. sav and eav sequences are inserted into the data stream to indicate the active video time in itu-r bt.656 format. the output timing insertion is illustrated in figure 5. the sav and eav sequences are shown in table 2. output timing the output setup and hold diagram is shown in figure 6. MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 13 sync-level correction and sync extraction sync processor and analog copy protection detect composite agc adaptive comb filter line delays y-delay chrominance demodulator y/cb/cr filters lpf lpf chroma agc 10 from analog front-end y cb cr ntsc/pal timing info horz, vert, frame nonstd video nonstd video figure 3. digital composite decoding functional diagram
MAX9526 low-power, high-performance ntsc/pal video decoder 14 ______________________________________________________________________________________ sel _54mhz register 0x0d b4 xtal_dis register 0x0d b3 pllbyp register 0x0e b3 llc_mode register 0x0e b5-4 clock mode description 00000 input clock = 27mhz crystal. sample clock = line locked or async (autodetected). this is the default power-up mode for the MAX9526. 00010 input clock = 27mhz crystal. sample clock = line locked (forced on). 00011 input clock = 27mhz crystal. sample clock = 2x input clock. 0x1xx invalid modes. the pll can only be bypassed if the input clock is 54mhz. 01000 input clock = 27mhz external clock. sample clock = line locked or async (autodetected). 01010 input clock = 27mhz external clock. sample clock = line locked (forced on). 01011 input clock = 27mhz external clock. sample clock = 2x input clock. 1 0 x xx invalid mode. 54mhz crystal not supported. 11000 input clock = 54mhz external clock. sample clock = line locked or async (autodetected). 11010 input clock = 54mhz external clock. sample clock = line locked (forced on). 11011 input clock = 54mhz external clock. sample clock = input clock divided by 2, then multiplied by 2x through the pll. this mode uses the pll to filter high-frequency jitter on the input source. 111x0 invalid mode. the pll can only be bypassed when the output is not a line-locked clock. 11111 input clock = 54mhz external clock. sample clock = input clock. use this mode when a low-jitter, 54mhz input clock is used. table 1. MAX9526 clock mode summary
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 15 condition fvh value sav/eav code sequence field v time h time f v h first second third trs even blank eav 1 1 1 0xff 0x00 0x00 0xf1 even blank sav 1 1 0 0xff 0x00 0x00 0xec even active eav 1 0 1 0xff 0x00 0x00 0xda even active sav 1 0 0 0xff 0x00 0x00 0xc7 odd blank eav 0 1 1 0xff 0x00 0x00 0xb6 odd blank sav 0 1 0 0xff 0x00 0x00 0xab odd active eav 0 0 1 0xff 0x00 0x00 0x9d odd active sav 0 0 0 0xff 0x00 0x00 0x80 table 2. itu-r bt.656 sav and eav code sequence image enhancement and color correction timing reference signal insertion/ itu encoding time base correction test pattern insertion d9?0 llc horz, vert, frame y cb cr timing info 10 figure 4. digital output processing ffh clkp vd[7:0] hactive 00h 00h xy 80h 16h 80h 160h ffh 00h 00h xyh cb0 y0 cr0 y1 cb2 y2 cr2 y3 eav code sav code figure 5. timing diagram of itu-r bt.656 format d9?0 llc t hd t su figure 6. output setup and hold
MAX9526 low-power, high-performance ntsc/pal video decoder 16 ______________________________________________________________________________________ MAX9526 v in 0.1 f 37.5 37.5 i 2 c if xtal/osc llc dout itu-1 27mhz cvbs input 1 4-to-1 pixel level multiplexer and channel id inserter MAX9526 v in 0.1 f 37.5 37.5 i 2 c if xtal/osc llc dout itu-2 4-channel video mux 27mhz cvbs input 2 MAX9526 v in 0.1 f 37.5 37.5 i 2 c if xtal/osc llc dout itu-3 27mhz ctrl [1] 108mhz clock ctrl [0] cvbs input 3 MAX9526 v in 0.1 f 37.5 37.5 i 2 c if xtal/osc llc dout itu-4 27mhz cvbs input 4 sda scl i 2 c interface x4 q oscillator 27mhz figure 7. multiple video input processing
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 17 MAX9526 v in1 v ref i.c. agnd dgnd avdd dvdd fb dvddio llc clk 27mhz d9 d9 d8 d8 d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 irq d0 parallel output 10k 37.5 cvbs input 1 0.1 f 0.1 f 0.1 f 0.1 f10 f 0.1 f 10 f 10 f 0.1 f 1m * 27mhz irq addr +1.8v +3.3v or +1.8v gnd dvddio dvddio xtal/osc 47pf xtal2 47pf 37.5 v in2 devadr scl scl sda sda 37.5 10k cvbs input 2 10k 0.1 f 37.5 i 2 c interface *optional figure 8. MAX9526 typical application circuit with additional supply isolation
MAX9526 low-power, high-performance ntsc/pal video decoder 18 ______________________________________________________________________________________ parameter conditions min typ max units frequency fundamental mode only 27.000 mhz maximum crystal esr room temperature 30 line-locked mode ?0 accuracy async mode with multiple decoders ?0 ppm table 3. recommended crystal parameters smbus is a trademark of intel corp. applications information multiple decoder operation multiple asynchronous video input signals can be decoded synchronously using multiple MAX9526s in asynchronous (async) sampling mode. figure 7 shows an example of decoding four video input signals. the MAX9526 is configured for async sampling mode by writing the following registers: register 0x0d, b3 (xtal_dis) = 1 (disables the crystal oscillator) register 0x0e, b5-4 (llc_mode) = 11 (forces sampling to async mode) when the MAX9526 is in async sampling mode, the data outputs, d9?0, of all decoders are synchronous with the input clock (xtal/osc). the video content in the data outputs is not frame aligned because the video sources into each MAX9526 is asynchronous. a small fpga can be implemented to multiplex all four chan- nels into a single 8- or 10-bit bus. this fpga can also format the outputs to be compatible for input into a compression processor, which is commonly used in digital video recorders (dvrs). the crystal oscillator (external or internal) must have better than ?0ppm accuracy for acceptable decoding in this mode. an accuracy of ?0ppm is recommended for optimal performance. recommended crystal parameters recommended crystal parameters are shown in table 3. power-supply decoupling for systems where additional power-supply isolation is required, the circuit shown in figure 8 can be used. additional supply decoupling is added and analog power (avdd) isolation is increased with the use of a fer- rite bead (fb). the analog ground connection (agnd) should be connected to a separate ground plane that has a small bridge to the main ground plane of the sys- tem. the video input termination (v in1 /v in2 ), video refer- ence (v ref ) decoupling, and avdd supply decoupling should also be connected to the agnd ground plane. i 2 c serial interface the MAX9526 features an i 2 c/smbus ? -compatible, 2-wire serial interface consisting of a serial-data line (sda) and a serial-clock line (scl). sda and scl facili- tate communication between the MAX9526 and the master at clock rates up to 400khz. figure 9 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the MAX9526 by transmitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) con- dition and a stop (p) condition. each word transmitted to the MAX9526 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the MAX9526 transmits the proper slave address fol- lowed by a series of nine scl pulses. the MAX9526 transmits data on sda in sync with the master-generat- ed scl pulses. the master acknowledges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowl- edge, and a stop condition. sda operates as both an input and an open-drain output. a pullup resistor, typi- cally greater than 500 , is required on sda. scl oper- ates only as an input. a pullup resistor, typically greater than 500 , is required on scl if there are multiple mas- ters on the bus, or if the single master has an open- drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the MAX9526 from high-voltage spikes on the bus lines, as well as minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals (see the start and stop conditions section). start and stop conditions sda and scl idle high when the bus is not in use. a master initiates communication by issuing a start con- dition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 19 transition on sda while scl is high (figure 10). a start condition from the master signals the beginning of a transmission to the MAX9526. the master terminates transmission, and frees the bus, by issuing a stop con- dition. the bus remains active if a repeated start condition is generated instead of a stop condition. early stop conditions the MAX9526 recognizes a stop (p) condition at any point during data transmission except if the stop con- dition occurs in the same high pulse as a start (s) condition. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. slave address the slave address is defined as the seven most signifi- cant bits (msbs) followed by the read/write bit. for dev_addr connected to dgnd, setting the read/write bit to 1 (slave address = 0x43) configures the MAX9526 for read mode. setting the read/write bit to 0 (slave address = 0x42) configures the MAX9526 for write mode. the address is the first byte of information sent to the MAX9526 after the start condition. the MAX9526 slave address is configurable with dev_addr. table 5 shows the addresses of the MAX9526. acknowledge the acknowledge bit (ack) is a clocked 9th bit that the MAX9526 uses to handshake receipt each byte of data when in write mode (see figure 11). the MAX9526 pulls down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master retries communication. the master pulls down sda during the 9th clock cycle to acknowledge receipt of data when the MAX9526 is in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not acknowledge is sent when the master reads the final byte of data from the MAX9526, followed by a stop condition. write data format a write to the MAX9526 includes transmission of a start condition, the slave address with the r/ w bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a stop condition. figure 12 illustrates the proper frame format for writing one byte of data to the MAX9526. figure 13 illustrates the frame format for writing n bytes of data to the MAX9526. the slave address with the r/ w bit set to 0 indicates that the master intends to write data to the MAX9526. the MAX9526 acknowledges receipt of the address byte during the master-generated 9th scl pulse. the second byte transmitted from the master config- ures the MAX9526? internal register address pointer. the pointer tells the MAX9526 where to write the next byte of data. an acknowledge pulse is sent by the MAX9526 upon receipt of the address pointer data. the third byte sent to the MAX9526 contains the data that is written to the chosen register. an acknowledge pulse from the MAX9526 signals receipt of the data byte. the address pointer autoincrements to the next register address after each received data byte. this autoincrement feature allows a master to write to sequential registers within one continuous frame. figure 13 illustrates how to write to multiple registers with one frame. the master signals the end of transmission by issuing a stop (p) condition.
MAX9526 low-power, high-performance ntsc/pal video decoder 20 ______________________________________________________________________________________ read data format send the slave address with the r/ w bit set to 1 to initi- ate a read operation. the MAX9526 acknowledges receipt of its slave address by pulling sda low during the 9th scl clock pulse. a start (s) command fol- lowed by a read command resets the address pointer to register 0x00. the first byte transmitted from the MAX9526 is the con- tents of register 0x00. transmitted data is valid on the rising edge of scl. the address pointer autoincre- ments after each read data byte. this autoincrement feature allows all registers to be read sequentially within one continuous frame. a stop (p) condition can be issued after any number of read data bytes. if a stop condition is issued followed by another read operation, the first data byte to be read is from register 0x00. the address pointer can be preset to a specific register before a read command is issued. the master presets the address pointer by first sending the MAX9526? slave address with the r/ w bit set to 0 followed by the register address. a repeated start (sr) condition is then sent followed by the slave address with the r/ w bit set to 1. the MAX9526 then transmits the contents of the specified register. the address pointer autoincre- ments after transmitting the first byte. the master acknowledges receipt of each read byte during the acknowledge clock pulse. the master must acknowledge all correctly received bytes except the last byte. the final byte must be followed by a not acknowledge from the master and then a stop condi- tion. figure 14 illustrates the frame format for reading one byte from the MAX9526. figure 15 illustrates the frame format for reading multiple bytes from the MAX9526. scl sda start condition stop condition repeated start condition start condition t hd: sta t su: sta t hd: sta t sp t buf t su: sto t low t su: dat t hd: dat t high t r t f figure 9. i 2 c serial interface timing diagram 1 scl start condition sda 289 clock pulse for acknowledgment acknowledge not acknowledge figure 11. acknowledge scl sda ssrp figure 10. start, stop, and repeated start conditions
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 21 1 byte autoincrement internal register address pointer acknowledge from MAX9526 acknowledge from MAX9526 b1 b0 b3 b2 b5 b4 b7 b6 a a 0 acknowledge from MAX9526 r/w s a 1 byte acknowledge from MAX9526 b1 b0 b3 b2 b5 b4 b7 b6 p a slave address register address data byte 1 data byte n figure 13. writing n bytes of data to the MAX9526 a 0 slave address register address data byte acknowledge from MAX9526 r/w 1 byte autoincrement internal register address pointer acknowledge from MAX9526 acknowledge from MAX9526 b1 b0 b3 b2 b5 b4 b7 b6 s a a p figure 12. writing a byte of data to the MAX9526 acknowledge from MAX9526 1 byte autoincrement internal register address pointer acknowledge from MAX9526 not acknowledge from master a a p a 0 acknowledge from MAX9526 r/w sa r/w repeated start sr 1 slave address register address slave address data byte figure 14. reading one indexed byte of data from the MAX9526 acknowledge from MAX9526 1 byte autoincrement internal register address pointer acknowledge from MAX9526 a a a 0 acknowledge from MAX9526 r/w sa r/w repeated start sr 1 slave address register address slave address data byte figure 15. reading n bytes of indexed data from the MAX9526
MAX9526 low-power, high-performance ntsc/pal video decoder 22 ______________________________________________________________________________________ register b7 b6 b5 b4 b3 b2 b1 b0 reg addr power- on state status 0 vid1 vid2 0 cthr adcovr hlock nonstd lstlck 0x00 n/a status 1 0 l525 00000acp 0x01 n/a irq mask 0 ivid1 ivid2 0 icthr iadcovr ihlock inonstd ilstlck 0x02 0x00 irq mask 1 0 il525 00000iacp 0x03 0x00 standard select, shutdown, and control stdsel autod shdn reset sleep reset_s 0x04 0x10 contrast cont 0x05 0x80 brightness bright 0x06 0x00 hue hue 0x07 0x80 saturation satu 0x08 0x88 video input select and clamp autosel insel dcrestore_range 0 0 d_clmp_ dis 0 0x09 0x02 gain control cragc cmpagc 0 adagc adcgain 0x0a 0x00 color kill bw crkdis 1 0 cthrsh 0x0b 0x23 output test signal rawadc 0 tgenab tgtim tgsrc 0 cbar 0x0c 0x00 clock and output 0 clip llc_inv sel_54 mhz xtal_dis hsvs dataz llcz 0x0d 0x00 pll control 0 0 llc_mode pllbyp pllbw 0x0e 0x03 miscellaneous 0 0 disaaflt 1 sslice 0x0f 0x18 table 4. register map overview address connection (devadr) write address read address dvdd 0x40 0x41 dgnd 0x42 0x43 sda 0x44 0x45 table 5. i 2 c slave address programming the MAX9526 i 2 c register map table 4 shows an i 2 c register map. all static bits should not be programmed to any values other than the default value listed in table 4.
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 23 video input 1 active (v id1 ) 1 = active video detected at v in1 . 0 = no active video detected on v in1 . video input 2 active (v id2 ) 1 = active video detected at v in2 . 0 = no active video detected on v in2 . below color kill threshold (cthr) 1 = color carrier has fallen below color kill threshold since last register 0 read. 0 = color carrier has not fallen below color kill thresh- old since last register 0 read. cthr reports when the chroma carrier is below color kill threshold. see register 0x0b for color kill threshold and color kill enable settings. adc out-of-range (adcovr) 1 = adc has gone outside the full-scale range since last register 0 read. 0 = adc has not gone outside the full-scale range since last register 0 read. adcovr triggers when the adc input is above or below the adc input range. this bit is cleared after reading status register 0. adcovr is not triggered on lines during the vertical blanking interval, on lines at the start or end of the field that may have pulses from copy protection, or on lines that may have ancillary data. horizontal lock (hlock) 1 = line-locked pll is locked to horizontal line rate and has not lost lock since last status register 0 read. 0 = line-locked pll has lost lock since last status reg- ister 0 read. nonstandard video (nonstd) 1 = nonstandard video detected. 0 = standard video format detected. for standard video, the carrier frequency is always a precise multiple of the horizontal frequency. an exam- ple of nonstandard inputs are video cassette recorders in which the carrier is not a precise multiple of the hori- zontal frequency. demodulator lost lock (lstlck) 1 = demodulator has lost lock since last status register 0 read. 0 = demodulator has maintained lock since last status register 0 read. reg b7 b6 b5 b4 b3 b2 b1 b0 0x00 vid1 vid2 0 cthr adcovr hlock nonstd lstlck i 2 c bit descriptions reg b7 b6 b5 b4 b3 b2 b1 b0 0x01 0 l525 00000acp status register 1 status register 0 525 line mode (l525) 1 = 525 line video detected. 0 = 625 line video detected. this output is only valid when the decoder is locked and operating normally. analog copy protection (acp) 1 = analog copy protection detected. 0 = no analog copy protection detected.
MAX9526 low-power, high-performance ntsc/pal video decoder 24 ______________________________________________________________________________________ 525 line video interrupt enable (il525) 1 = change in l525 bit status triggers a hardware interrupt. 0 = no interrupt on l525 changes (default). this interrupt is masked by the hlock and lstlck status. changes in the l525 status triggers a hardware interrupt only when hlock = 1 and lstlck = 0. see register 0x01, b6. analog copy protection interrupt enable (iacp) 1 = any change in acp status bit (register 0x01, b0) triggers a hardware interrupt. 0 = no interrupt on analog copy protection changes (default). see register 0x01, b0. reg b7 b6 b5 b4 b3 b2 b1 b0 0x02 ivid1 ivid2 0 icthr iadcovr ihlock inonstd ilstlck interrupt mask register 0 reg b7 b6 b5 b4 b3 b2 b1 b0 0x03 0 il525 0 0 0 0 0 iacp interrupt mask register 1 active video 1 interrupt (ivid1) 1 = change in v id1 bit status triggers a hardware interrupt. 0 = no interrupt on v id1 changes (default). see register 0x00, b7. active video 2 interrupt (ivid2) 1 = change in v id2 bit status triggers a hardware interrupt. 0 = no interrupt on v id2 changes (default). see register 0x00, b6. color kill threshold interrupt (icthr) 1 = transition in ckill bit from 0 to 1 triggers a hard- ware interrupt. 0 = no interrupt on ckill changes (default). see register 0x00, b4. adc out-of-range interrupt enable (iadcovr) 1 = change in adcovr bit from 0 to 1 triggers a hardware interrupt. 0 = no interrupt on adcovr changes (default). see register 0x00, b3. horizontal lock interrupt enable (ihlock) 1 = change in hlock bit from 1 to 0 triggers a hardware interrupt. 0 = no interrupt on hlock changes (default). see register 0x00, b2. nonstandard video interrupt enable (inonstd) 1 = change in nonstd bit from 0 to 1 triggers a hardware interrupt. 0 = no interrupt on nonstd changes (default). see register 0x00, b1. demodulator lock interrupt enable (ilstlck) 1 = change in lstlock bit from 0 to 1 triggers a hardware interrupt. 0 = no interrupt on lstlock changes (default). see register 0x00, b0.
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 25 video standard select (stdsel) bit b7 (type) 1 = ntsc j, pal 60, ntsc 4.43. 0 = ntsc m (standard nstc), pal m, pal b/g/h/i/d (standard pal), pal combination n (default). bit b6 (525 line) 1 = 525 line video. 0 = 625 line video (or ntsc 4.43) (default). bit b6 sets the video line rate when autod = 0. when autod = 1 (default), b6 is ignored. bit b5 (unconventional video) 1 = pal combination n, pal m, ntsc 4.43, pal 60. 0 = pal b/g/h/i/d (standard pal), ntsc m (standard nstc), or ntsc j (default). the 3 bits in the stdsel register can be used to pro- gram the expected input video format. bit b6 (525 vs. 625 line video) can be automatically set by using the autodetect function (see autod bit description, regis- ter 0x04, b4). b[7:5] 000: pal b/g/h/i/d (standard pal) 001: pal combination n 010: ntsc m (standard nstc) 011: pal m 100: n/a 101: ntsc 4.43 110: ntsc j 111: pal60 standard autodetect (autod) 1 = automatically detects 525 vs. 625 line video (default). 0 = manually programs 525 vs. 625 line video. autodetect function can only be used to distinguish between standard pal and standard ntsc. the autodetect function requires register 0x04, b7 = b5 = 0. low-power shutdown (shdn) 1 = low-power shutdown mode. 0 = normal operation (default). in shutdown, all logic outputs are low (unless pro- grammed to high impedance using register 0x0d, b1). i 2 c register contents are retained during shutdown. system reset (reset) 1 = all registers and system state returned to power-on default conditions. 0 = normal operation (default). because all registers?contents are set to power-on default state, this bit clears itself after being written. sleep mode (sleep) 1 = low-power sleep mode. 0 = normal operation (default). in sleep mode, all logic outputs are low (unless pro- grammed to high impedance using register 0x0d, b1). i 2 c register contents are retained. video activity detect is still active. activity status is available in register 0x00. soft reset (reset_s) this bit resets everything on the device except the reg- ister values. this bit is self-clearing. 1 = soft reset. 0 = normal operation (default). reg b7 b6 b5 b4 b3 b2 b1 b0 0x04 stdsel autod shdn reset sleep reset_s standard select, shutdown, and control register
MAX9526 low-power, high-performance ntsc/pal video decoder 26 ______________________________________________________________________________________ brightness (bright) 0x00 = luma offset is 0 ire (default). 0x7f = luma offset is +75.66 ire. 0x80 = luma offset is -76.22 ire. reg b7 b6 b5 b4 b3 b2 b1 b0 0x05 cont contrast control register reg b7 b6 b5 b4 b3 b2 b1 b0 0x06 bright brightness control register hue (hue) 0x80 = chroma phase is 0 degrees with respect to color burst (default). 0xff = chroma phase is approximately +45 degrees with respect to color burst. 0x00 = chroma phase is -45 degrees with respect to color burst. reg b7 b6 b5 b4 b3 b2 b1 b0 0x07 hue hue control register saturation (satu) 0x00 = chroma gain is 0. 0x80 = chroma gain is 1. 0x88 = default. 0xff = chroma gain is 255/128, or approximately 2. when acp is detected (register 0x01, b0), 8 (decimal) is added to satu. reg b7 b6 b5 b4 b3 b2 b1 b0 0x08 satu saturation control register contrast (cont) 0x00 = luma gain is 0. 0x80 = luma gain is 1 (default). 0xff = luma gain is 255/128, or approximately 2. when acp is detected (register 0x01, b0), 15 (decimal) is subtracted from cont.
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 27 video auto-select (autosel) 1 = automatically selects video input with activity detect. when activity is present on both or neither v in1 and v in2 after a reset (por, register reset, sleep mode, shutdown), v in1 is selected. if there is activity on v in2 and no activity on v in1 , then v in2 is selected. when v in2 is automatically selected with the presence of activity, the input switches to v in1 only when activity goes away on v in2 . 0 = video input is selected manually (default). see insel (register 0x09, b6) for manual input selection. manual video input select (insel) 1 = select v in2 . 0 = select v in1 (default). video autoselect bit (autosel) must be 0 for this reg- ister to take effect. analog dc restoration current range (dcrestore_range) this bit sets the full-scale range of the dc restoration dac. increasing the full-scale current range increases the bandwidth and range of the dc restoration loop. 10 = slow (?? into video input coupling capacitor) 11 = medium (?? into video input coupling capacitor) 00 = medium-fast (?2? into video input coupling capacitor) (default) 01 = fast (?4? into video input coupling capacitor) digital clamp disable (d_clmp_dis) this bit disables the digital clamp. 1 = disables digital sync-tip clamp (default). 0 = enables digital sync-tip clamp. enabling the digital clamp sets the sync level to code 0 (decimal) and gives higher frequency tracking of input signals. if the digital clamp is enabled, the sync slice level in register 0x0f should be adjusted accordingly to provide equivalent noise rejection. typically, sslice[3:0] should be reduced by 2 lsbs when d_clmp_dis is set to 1. reg b7 b6 b5 b4 b3 b2 b1 b0 0x09 autosel insel dcrestore_range 0 0 d_clmp_dis 0 video input select and clamp control register reg b7 b6 b5 b4 b3 b2 b1 b0 0x0a cragc cmpagc 0 adagc agcgain gain-control register chrominance agc disable (cragc) 1 = chroma gain is frozen. 0 = automatic chroma gain is based on color burst level ( default). to freeze the chroma gain at the default value of 17 (hex), set cragc = 1 and apply a soft reset. composite agc disable (cmpagc) 1 = digital composite gain frozen at default value (80 (hex)). 0 = automatic digital composite gain based on sync level (default). disable analog automatic gain control (adagc) 1 = analog automatic gain control is disabled. 0 = analog automatic gain control is enabled (default). the analog automatic gain-control (agc) loop adjusts the agc gain to optimally use the available adc full- scale range.
MAX9526 low-power, high-performance ntsc/pal video decoder 28 ______________________________________________________________________________________ the color kill threshold is relative to the peak-to-peak amplitude of the color burst of the composite video sig- nal at the video inputs (v in1 /v in2 ). the threshold values assume the sync amplitude is the standard level. agc gain code typical full-scale conversion range (mv) agc gain code typical full-scale conversion range (mv) 0000 752 1000 417 0001 683 1001 394 0010 626 1010 375 0011 578 1011 357 0100 535 1100 341 0101 500 1101 326 0110 469 1110 313 0111 441 1111 300 table 7. analog agc code and gain values black and white (bw) 1 = chrominance demodulator is disabled and component video output is black and white only. 0 = chrominance demodulator is enabled (default). color kill disable (crkdis) 1 = color kill is disabled. 0 = automatic color kill is enabled (default). black and white (bw) control bit takes precedence over crkdis. reg b7 b6 b5 b4 b3 b2 b1 b0 0x0b bw crkdis 1 0 cthrsh color kill register cthrsh busrt amplitude (mv) cthrsh busrt amplitude (mv) 0000 off 1000 35 0001 off 1001 39 0010 19 1010 40 0011 (default) 25 1011 41 0100 27 1100 43 0101 29 1101 45 0110 30 1110 48 0111 31 1111 51 color kill threshold (cthrsh) analog agc gain (agcgain) this bit controls the gain of the analog agc preceding the adc. this bit only functions when adagc = 1. the gain steps are linear in magnitude. table 7 shows the agc? effect on the input full-scale conversion range.
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 29 adc-only mode (rawadc) 1 = d9?0 are the adc outputs directly without being processed by video demodulator. 0 = d9?0 are 10-bit ycbcr component video (default). with rawadc = 1, the d9?0 output data rate is 54msps and the llc clock output is 54mhz. figure 16 shows the typical setup and hold timings of the output signals with rawadc = 1. llc can optionally be inverted by setting llcinv = 1 in register 0x0d, b5. with rawadc = 1 the adc outputs are filtered with the digital lowpass filter before being routed to d9?0. the adc outputs can be directly connected to d9?0 with- out filtering by setting rawadc = 1 and disaaflt = 1 in register 0x0f, b5. reg b7 b6 b5 b4 b3 b2 b1 b0 0x0c rawadc 0 tgenab tgtim tgsrc 0 cbar color test signal register d9?0 llc (54mhz) ~8ns ~18.5ns ~8ns figure 16. typical setup and hold timings in rawadc mode
MAX9526 low-power, high-performance ntsc/pal video decoder 30 ______________________________________________________________________________________ output of decoder description stdsel register 0x04 b7-5 autod register 0x04 b4 tgenab register 0x0c b5 tgtim register 0x0c b4 tgsrc register 0x0c b3 no video input valid video input default mode, test pattern has last timing standard used at output 0x0 1 0 x x test pattern decoded input force test pattern with last timing standard used at output 0x0 1 1 x 1 test pattern test pattern force test pattern with 50hz timing xxx x 1 0 0 50hz test pattern 50hz test pattern force test pattern with 60hz timing xxx x 1 1 0 60hz test pattern 60hz test pattern force 50hz timing for decoding and test pattern x0x 0 0 x x 50hz test pattern decoded input with 50hz timing force 60hz timing for decoding and test pattern x1x 0 0 x x 60hz test pattern decoded input with 60hz timing table 8. output test signal setup test pattern generation in default mode, the MAX9526 outputs a test pattern when video is removed. the timing standard for the test pattern is the last timing standard that is at the output of the decoder. if the MAX9526 is reset and has no video inputs, the default output timing standard is 525 lines (60hz). see register 0x04 for manually configuring the video standard decoding. table 8 gives some common examples of setting up video standards and test pat- tern generation. test pattern enable (tgenab) 1 = force a test pattern at video output. 0 = output a test pattern if no video is present at the video inputs (default). test signal output timing standard (tgtim) 1 = 525 line, 60hz frame rate. 0 = 625 line, 50hz frame rate (default). this bit is ignored if tgsrc = 1. test signal timing source (tgsrc) 1 = test generator uses timing from incoming video signal (if signal is valid). 0 = test generator uses internally generated timing (default). color bar select (cbar) 00 = black screen (default) 01 = blue screen 10 = 75% color bars 11 = 100% color bars
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 31 itu-r bt.656 standard clipping level (clip) 1 = clip itu output to y range is between 64?40 and cbcr range is between 64?60. 0 = clip itu output to y range and cbcr range is between 5?019 (default). inverted line-locked clock (llc_inv) this signal inverts the polarity of the line-locked clock that is output from the MAX9526. this can be used to solve board level timing problems for other devices. 1 = invert llc clock. 0 = do not invert llc clock (default). input clock frequency select (sel_54mhz) 1 = 54mhz clock at xtal/osc input. 0 = 27mhz clock at xtal/osc input (default). this bit is only applicable when the crystal oscillator is disabled (xtal_dis = 1). crystal oscillator disable (xtal_dis) 1 = xtal/osc is either a 27mhz or a 54mhz cmos clock input. 0 = enables the 27mhz crystal oscillator (default). horizontal/vertical sync output (hsvs) 1 = d1 and d0 output horizontal and vertical sync pulses, respectively. 0 = d1 and d0 are lsbs of digital component video output (default). the rising edge of horizontal sync (hs) coincides with the end of active video (rises after 3ffh 000h of eav code). the falling edge coincides with the start of active video (sav) code (falls after completing 3ffh 000h of sav code). figure 17 shows the horizontal and vertical sync timing. the vertical sync pulse (vs) line transitions are detailed in table 9. note that the vs line transitions on pin d0 are shifted by 1 to 2 lines relative to the v flag transi- tions embedded in the itu data stream. the v flag tran- sitions embedded in the itu data stream follow the itu-r bt.656-4 standard. data output disable (dataz) 1 = logic data outputs (d9?0) are disabled and placed in high-impedance state. 0 = logic data outputs (d9?0) are enabled (default). the dataz bit forces data outputs high impedance regardless of whether the device is in shutdown. clock output disable (llcz) 1 = logic clock output (llc) are disabled and placed in a high-impedance state. 0 = logic clock output (llc) is enabled (default). the llcz bit forces llc high impedance regardless of whether the device is in shutdown. reg b7 b6 b5 b4 b3 b2 b1 b0 0x0d 0 clip llc_inv sel_54mhz xtal_dis hsvs dataz llcz clock and output control register vertical sync pulses (vs on pin d0) 625 525 start (vs = 1) line 623 line 2 field 1 finish (vs = 0) line 21 line 21 start (vs = 1) line 309 line 265 field 2 finish (vs = 0) line 335 line 284 table 9. vs (pin d0) line transitions
MAX9526 low-power, high-performance ntsc/pal video decoder 32 ______________________________________________________________________________________ disable digital anti-aliasing filter (disaafilt) disable the digital anti-aliasing filter following the adc. 1 = disables filter. 0 = enables filter (default). sync slicing level (sslice) sets the sync slicing level. 1111 = slice at 240 (decimal), near the blanking level. 1000 = slice at 128 (decimal), near the center of the sync (default). 0100 = slice at 64 (decimal), about 25% of the sync. 0000 = slice at 0 (decimal), near the bottom of the sync. all values between 0000 and 1111 are valid. reg b7 b6 b5 b4 b3 b2 b1 b0 0x0e 0 0 llc_mode pllbyp pllbw pll control register reg b7 b6 b5 b4 b3 b2 b1 b0 0x0f 0 0 disaafilt 1 sslice miscellaneous register line-locked clock mode (llc_mode) 0x = async mode or line-locked mode is set automati- cally (default). 10 = pll is forced to line-locked mode. 11 = pll is forced to async mode. pll bypass mode (pllbyp) when pllbyp = 1, the adc and the decoder use the input crystal or clock (xtal/osc, xtal2) directly. 1 = bypass the pll. 0 = pll is enabled (default). line-locked pll tracking speed (pllbw) pllbw controls a digital loop filter that sets the band- width of the line-locked pll. 000 = 180hz 001 = 250hz 010 = 375hz 011 = 500hz (default) 100 = 750hz 101 = 1khz 110 = 1.5khz 111 = 2khz cb359 sav(ff) sav(00) sav(00) sav(xy) cb0 y0 cr0 y718 cr359 y719 eav(ff) eav(00) eav(00) eav(xy) blank blank blank blank blank blank llc d9?2 hs 2 clk 1 clk vs = 1 vs = 0 2 clk figure 17. horizontal sync timing
MAX9526 MAX9526 tqfn top view 29 30 28 27 12 11 13 avdd xtal/osc i.c. devadr dvdd 14 agnd dvddio dvdd llc d6 d5 d4 12 d9 4567 23 24 22 20 19 18 n.c. v in1 d1 d0 irq scl xtal2 dgnd 3 21 31 10 v ref sda 32 9 v in2 n.c. d8 26 15 d2 d7 25 16 d3 dgnd n.c. 8 17 n.c. *ep *ep = exposed pad + pin configurations 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 v in1 d9 d8 d7 d6 dvddio dgnd dvdd llc top view MAX9526 qsop + v ref v in2 xtal2 agnd avdd xtal/osc i.c. 20 19 9 10 d5 d4 devadr dvdd 18 17 11 12 d3 d2 dgnd sda 16 15 13 14 d1 d0 scl irq process information process: cmos low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 33
MAX9526 low-power, high-performance ntsc/pal video decoder 34 ______________________________________________________________________________________ MAX9526 v in1 v ref i.c. agnd dgnd avdd dvdd dvddio llc clk 27mhz d9 d9 d8 d8 d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 irq d0 parallel output 10k 37.5 cvbs input 1 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 27mhz irq addr +1.8v +3.3v or +1.8v gnd dvddio dvddio xtal/osc 47pf xtal2 47pf 37.5 v in2 devadr scl scl sda sda 37.5 10k cvbs input 2 10k 0.1 f 37.5 i 2 c interface typical operating circuit
MAX9526 low-power, high-performance ntsc/pal video decoder ______________________________________________________________________________________ 35 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . qfn thin.eps package type package code document no. 28 qsop e28-1 21-0055 32 tqfn-ep t3256-1 21-0140
MAX9526 low-power, high-performance ntsc/pal video decoder 36 ______________________________________________________________________________________ package information (continued) for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
MAX9526 low-power, high-performance ntsc/pal video decoder maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 37 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package information (continued) for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . qsop.eps

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