for:char printed on:mon, feb 6, 1995 09:32:08 from book:dl121ch4 (5) view document:mc74f283 (5) view last saved on:fri, feb 3, 1995 16:03:54
4-146 fast and ls ttl data 4-bit binary full adder (with fast carry) the mc54/74f283 high-speed 4-bit binary full adder with internal carry lookahead, accepts two 4-bit binary words (a 0 a 3 , b 0 b 3 ) and a carry input (c 0 ). it generates the binary sum outputs (s 0 s 3 ) and the carry output (c 4 ) from the most significant bit. the f283 will operate with either active-high or active-low operands (positive or negative logic). functional description the f283 adds two 4-bit binary words (a plus b) plus the incoming carry c 0 . the binary sum appears on the sum (s 0 s 3 ) and outgoing carry (c 4 ) outputs. the binary weight of the various inputs and outputs is indicated by the sub- script numbers, representing powers of two. 2 0 (a 0 + b 0 + c 0 ) + 2 1 (a 1 + b 1 ) + 2 2 (a 2 + b 2 ) + 2 3 (a 3 + b 3 ) = s 0 + 2s 1 + 4s 2 + 8s 3 + 16c 4 where (+) = plus interchanging inputs of equal weight does not af fect the operation.thus c 0 , a 0 , b 0 can be arbitrarily assigned to pins 5, 6 and 7. due to the symmetry of the binary add function, the f283 can be used either with all inputs and outputs active high (positive logic) or with all inputs and outputs active low (nega - tive logic). see figure a. note that if c 0 is not used it must be tied low for active-high logic or tied high for active-low logic. due to pin limitations, the intermediate carries of the f283 are not brought out for use as inputs or outputs. however , other means can be used to effec- tively insert a carry into, or bring a carry out from, an intermediate stage. fig - ure b shows how to make a 3-bit adder . t ying the operand inputs of the fourth adder (a 3 , b 3 ) low makes s 3 dependent only on, and equal to, the carry from the third adder . using somewhat the same principle, figure c shows a way of dividing the f283 into a 2-bit and a 1-bit adder . the third stage adder (a 2 , b 2 , s 2 ) is used merely as a means of getting a carry (c 10 ) signal into the fourth stage (via a 2 and b 2 ) and bringing out the carry from the second stage on s 2 . note that as long as a 2 and b 2 are the same, whether high or low , they do not influence s 2 . similarly , when a 2 and b 2 are the same the carry into the third stage does not influence the carry out of the third stage. figure d shows a method of implementing a 5-input encoder , where the inputs are equally weighted. the outputs s 0 , s 1 and s 2 present a binary number equal to the number of inputs i 1 i 5 that are true. figure e shows one method of implement - ing a 5-input majority gate. when three or more of the inputs i 1 i 5 are true, the output m 5 is true. connection diagram 14 13 12 11 10 9 1 2 3 4 5 6 7 16 15 8 v cc s 1 b 2 a 2 s 2 a 3 s 3 b 3 c 4 b 1 a 1 s 0 a 0 b 0 c 0 gnd mc54/74f283 4-bit binary full adder (with fast carry) fast ? schottky ttl j suffix ceramic case 620-09 n suffix plastic case 648-08 16 1 16 1 ordering information mc54fxxxj ceramic mc74fxxxn plastic mc74fxxxd soic 16 1 d suffix soic case 751b-03 logic symbol v cc = pin 16 gnd = pin 8 7 5 6 3 2 14 15 12 11 9 10 13 1 4 s 0 s 1 s 2 s 3 c 4 a 0 a 1 b 1 a 2 b 2 a 3 b 3 b 0 c 0
4-147 fast and ls ttl data mc54/74f283 logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. c 0 a 0 b 0 a 1 b 1 a 2 b 2 a 3 b 3 s 0 s 1 s 2 s 3 c 4 guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 54, 74 4.5 5.0 5.5 v t a operating ambient temperature range 54 55 25 125 c t a operating ambient temperature range 74 0 25 70 c i oh output current e high 54, 74 e e 1.0 ma i ol output current e low 54, 74 e e 20 ma figure a. active-high versus active-low interpretation c 0 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 s 0 s 1 s 2 s 3 c 4 logic levels l l h l h h l l h h h l l h active high 0 0 1 0 1 1 0 0 1 1 1 0 0 1 active low 1 1 0 1 0 0 1 1 0 0 0 1 1 0 active high: 0 + 10 + 9 = 3 + 16 active low: 1 + 5 + 6 = 12 + 0
4-148 fast and ls ttl data mc54/74f283 figure b. 3-bit adder a 0 l c 3 c 4 c 0 s 0 s 1 s 2 s 3 b 0 a 1 b 1 a 2 b 2 a 3 b 3 figure c. 2-bit and 1-bit adders c 0 a 0 b 0 a 1 b 1 c 10 a 10 b 10 s 0 s 1 c 2 s 10 c 11 a 0 c 0 s 0 s 1 s 2 s 3 c 4 b 0 a 1 b 1 a 2 b 2 a 3 b 3 figure d. 5-input encoder i 1 i 2 l i 3 i 4 i 5 2 0 2 1 2 2 a 0 c 4 c 0 s 0 s 1 s 2 s 3 b 0 a 1 b 1 a 2 b 2 a 3 b 3 figure e. 5-input majority gate m 5 i 1 i 2 i 3 i 4 i 5 a 0 c 4 c 0 s 0 s 1 s 2 s 3 b 0 a 1 b 1 a 2 b 2 a 3 b 3 dc characteristics over operating temperature range (unless otherwise specified) symbol parameter limits unit test conditions symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage v il input low voltage 0.8 v guaranteed input low voltage v ik input clamp diode voltage 1.2 v i in = 18 ma v cc = min v oh output high voltage 54, 74 2.5 3.4 v i oh = 1.0 ma v cc = 4.5 v v oh output high voltage 74 2.7 3.4 v i oh = 1.0 ma v cc = 4.75 v v ol output low voltage 0.35 0.5 v i ol = 20 ma v cc = min i ih input high current 20 m a v in = 2.7 v v cc = max i ih input high current 100 m a v in = 7.0 v v cc = max i il input low current c 0 input 0.6 ma vin = 0.5 v vcc = max i il input low current c 0 input 0.6 ma vin = 0.5 v vcc = max i il a and b inputs 1.2 ma vin = 0.5 v vcc = max i os output short circuit current (note 2) 60 150 ma v out = 0 v v cc = max i cc power supply current 36 55 ma inputs = 4.5 v v cc = max notes: 1. for conditions such as min or max, use the appropriate value specified under guaranteed operating ranges. 2. not more than one output should be shorted at a time, nor for more than 1 second.
4-149 fast and ls ttl data mc54/74f283 ac characteristics symbol parameter 54/74f 54f 74f unit symbol parameter t a = +25 c t a = 55 to +125 c t a = 0 to +70 c unit symbol parameter v cc = +5.0 v v cc = 5.0 v 10% v cc = 5.0 v 10% unit symbol parameter c l = 50 pf c l = 50 pf c l = 50 pf unit symbol parameter min typ max min max min max unit t plh propagation delay 3.5 7.0 9.5 3.5 14 3.5 10.5 ns t phl c 0 to s n 4.0 7.0 9.5 4.0 14 4.0 10.5 ns t plh propagation delay 3.0 7.0 9.5 3.0 14 3.0 10.5 ns t phl a n or b n to s n 3.5 7.0 9.5 3.5 14 3.5 10.5 ns t plh propagation delay 3.5 5.7 7.5 3.5 10.5 3.5 8.5 ns t phl c 0 to c 4 3.0 5.4 7.0 3.0 10 3.0 8.0 ns t plh propagation 3.0 5.7 7.5 3.0 10.5 3.0 8.5 ns t phl a n or b n to c 4 3.0 5.3 7.0 3.0 10 3.0 8.0 ns
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