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MC13111afb MC13111afta MC13111bfb MC13111bfta

universal narrowband fm receiver integrated circuit fb suffix plastic package case 848b (qfp52) 52 order this document by MC13110a/d 1 device tested operating temperature range package ordering information MC13110afb t a = 40 to +85 c qfp52 fta suffix plastic package case 932 (lqfp48) 48 1 MC13110afta lqfp48 MC13110bfb qfp52 MC13110bfta lqfp48 qfp52 lqfp48 qfp52 lqfp48 1 motorola analog ic device data
the MC13110a/b and MC13111a/b integrates several of the functions required for a cordless telephone into a single integrated circuit. this significantly reduces component count, board space requirements, external adjustments, and lowers overall costs. it is designed for use in both the handset and the base. ? MC13110a and MC13111a: fully programmable in all power modes ? MC13110b and MC13111b: mpu clk out and second local oscillator are aalways ono. there is no inactive mode ? dual conversion fm receiver complete dual conversion receiver antenna input to audio out 80 mhz maximum carrier frequency rssi output carrier detect output with programmable threshold comparator for data recovery operates with either a quad coil or ceramic discriminator ? compander expander includes mute, digital volume control, speaker driver, programmable low pass filter, and gain block compressor includes mute, programmable low pass filter, limiter, and gain block ? MC13110a/b only: frequency inversion scrambler function controlled via mpu interface programmable carrier modulation frequency ? dual universal programmable pll supports new 25 channel u.s. standard with no external switches universal design for domestic and foreign cordless telephone standards digitally controlled via a serial interface port receive side includes 1st lo vco, phase detector, and 14bit programmable counter and 2nd lo with 12bit counter transmit section contains phase detector and 14bit counter mpu clock outputs eliminates need for mpu crystal ? low battery detect provides two levels of monitoring with separate outputs separate, adjustable trip points ? 2.7 to 5.5 v operation (15 m a current consumption in inactive mode) ? an1575: refer to this application note for a list of the aworldwide cordless telephone frequencies r x phase detector t x phase detector low battery detect simplified block diagram this device contains 8262 active transistors. expander 1st mixer data out r x in 2nd mixer t x pd out t x out limiting if amplifier detector r x out t x in low battery indicator r x pd in r x pd out 1st lo 2nd lo carrier detect out spi rssi rssi m p serial interface compressor scrambler scrambler = MC13110a/b only note: mpu clock out 2nd lo this document contains information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 1997 rev 0
MC13110a/b MC13111a/b 2 motorola analog ic device data 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 13 12 11 10 9 8 7 6 5 4 3 2 1 27 28 29 30 31 32 33 34 35 36 37 38 39 bd1 out da out bd2 out t c cap c in amp out t da in v r det out rssi x out x in cc audio x audio in lo lo v gnd audio sa out sa in e out e e in scr out ref ref vb 1 2 cap cap ctrl 1 out 1 in q coil lim out v lim c2 lim c1 lim in sgnd rf mix gnd rf cc rf 2 in mix 2 out mix 1 out mix 1 in mix 1 in 1 2 out vag pd ref gnd pll t data en clk clk out cd out x pd t x vco pll v r x lo 2 in lo 2 1st mix 2nd mix 2nd lo 1st lo 1st lo vco if amp/ limiter detector rssi lpf aalpf 2 2nd lo sc filter clock mic amp t x gain adjust lpf alc c cap compressor limiter t x mute ref 2 ref 1 low battery detect data amp carrier detect r x gain adjust r x mute speaker amp speaker mute expander vol control 1st lo vb 25 4 1 12 b prog ref ctr 2nd lo 14 b prog r x ctr v ref reg 2.5 v 14 b prog t x ctr m p serial interface prog clk ctr t x phase detect r x phase detect 2nd lo 10.240 pin connections qfp52 12 11 10 9 8 7 6 5 4 3 2 1 vag pd ref gnd pll t data en clk clk out x pd t x vco pll v r x out lo 2 13 14 15 16 17 18 19 20 21 22 23 24 da out bd out t c cap c in amp out t da in v r det out q coil x out x in cc audio x audio in 25 26 27 28 29 30 31 32 33 34 35 36 lim out v lim c2 lim c1 lim in rssi mix gnd rf cc rf 2 in mix 2 out mix 1 out mix 1 in mix 1 in 1 2 48 47 46 45 44 43 42 41 40 39 38 37 lo lo v gnd audio sa out sa in e out e e in scr out lo 2 vb cap cap ctrl 1 out 1 in 1st mix 2nd mix 2nd lo lpf aalpf carrier detect data amp v cc audio m p serial interface prog clk ctr t x phase detect r x phase detect reg 2.5 v 14 b prog t x ctr mic amp speaker amp speaker mute expander vol control 25 4 1 12 b prog ref ctr vb 1st lo programmable low battery detect in cd out lqfp48 6 b prog sc clk ctr 1st lo detector rssi if amp/ limiter 2nd lo 1st lo vco 14 b prog r x ctr v ref 2nd lo 10.240 lpf lpf 4.129 khz bypass bypass 4.129 khz 40 scrambler modulating clock = MC13110a/b only scrambler note: r x gain adjust r x mute 2 sc filter clock t x gain adjust lpf alc c cap compressor limiter t x mute 6 b prog sc clk ctr lpf lpf 4.129 khz bypass bypass 4.129 khz 40 scrambler modulating clock scrambler 2nd lo
MC13110a/b MC13111a/b 3 motorola analog ic device data maximum ratings characteristic symbol value unit power supply voltage v cc 0.5 to +6.0 vdc junction temperature t j 65 to +150 c maximum power dissipation, t a = 25 c p d 70 mw notes: 1. devices should not be operated at these limits. the arecommended operating conditionso provide for actual device operation. 2. esd data available upon request. recommended operating conditions characteristic symbol min typ max unit supply voltage v cc 2.7 3.6 5.5 vdc operating ambient temperature t a 40 85 c input voltage low (data, clk, en) v il 0.3 v input voltage high (data, clk, en) v ih pll v ref 0.3 v bandgap reference voltage v b 1.5 v note : 3. all limits are not necessarily functional concurrently. dc electrical characteristics (v cc = 3.6 v, t a = 25 c, unless otherwise specified, ip3 = 0; test circuit figure 1.) characteristic symbol figure min typ max unit static current 1 active mode act i cc 5.5 8.5 10.5 ma receive mode r x i cc 3.1 4.1 5.3 ma standby mode std i cc 465 560 m a inactive mode [note 4] inact i cc 15 30 m a current increase when ip3 = 1 (active and receive modes) i ip3 1 1.4 1.8 ma note: 4. MC13110b/MC13111b versions have no inactive mode.
MC13110a/b MC13111a/b 4 motorola analog ic device data electrical characteristics (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or r x mode, unless otherwise specified; test circuit figure 1.) characteristic figure input pin measure pin symbol min typ max unit fm receiver (f rf = 46.77 mhz [usa ch 21], f dev = 3.0 khz, f mod = 1.0 khz, v cap ctrl = 1.2 v) input sensitivity (for 12 db sinad at det out using cmessage weighting filter) 50 w termination, generator referred 68, 69 mix 1 in 1 /in 2 det out v sin 2.2 100 m vrms dbm singleended, matched input, generator referred 0.4 115 differential, matched input, generator referred 0.4 115 first and second mixer voltage gain total (v in = 1.0 mvrms, with cf 1 and cf 2 load) 1 mix 1 in 1 or in 2 mix 2 out mx gaint 24 29 db isolation of first mixer output and second mixer input (v in = 1.0 mvrms, with cfi removed) mix 1 in 1 or in 2 mix 2 in mixiso 60 db total harmonic distortion (v in = 3.16 mvrms) 1 mix 1 in 1 or in 2 det out thd 1.4 2.0 % recovered audio (v in = 3.16 mvrms) 1 mix 1 in 1 or in 2 det out afo 80 112 150 mvrms am rejection ratio (v in = 3.16 mvrms, 30% am, @ 1.0 khz) 1 mix 1 in 1 or in 2 det out amr 30 48 db signal to noise ratio (v in = 3.16 mvrms, no modulation) mix 1 in 1 or in 2 det out snr 48 db first mixer (no modulation, f in = usa ch21, 46.77 mhz, 50 w termination at inputs) input impedance singleended 16 mix 1 in 1 or in 2 r ps1 c ps1 1.6 3.7 k w pf differential 16 mix 1 in 1 /in 2 r pd1 c pd1 1.6 1.8 output impedance 14 mix 1 out r p1 out c p1 out 300 3.7 w pf voltage conversion gain (v in = 1.0 mvrms, with cf 1 filter as load) 17, 18 mix 1 in 1 or in 2 mix 1 out mx gain1 12 db 1.0 db voltage compression level (input referred) ip3 bit set to 0 19, 21 mix 1 in 1 or in 2 mix 1 out v o mix 1 1 db 20 21 mvrms dbm ip3 bit set to 1 20, 21 56 12 third order intercept (input referred) [note 5] ip3 bit set to 0 19, 21 mix 1 in 1 or in 2 mix 1 out toi mix1 64 11 mvrms dbm ip3 bit set to 1 20, 21 178 2.0 3.0 db if bandwidth 22 mix 1 in 1 or in 2 mix 1 out mix 1 bw 13 mhz note: 5. third order intercept calculated for input levels 10 db below 1.0 db compression point.
MC13110a/b MC13111a/b 5 motorola analog ic device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or r x mode, unless otherwise specified; test circuit figure 1.) characteristic unit max typ min symbol measure pin input pin figure second mixer (no modulation, f in = 10.7 mhz, 50 w termination at inputs) input impedance 24 mix 2 in mix 2 in r p2 in c p2 in 2.8 3.6 k w pf output impedance 24 mix 2 out r p2 out c p2 out 1.5 6.1 k w pf voltage conversion gain (v in = 1.0 mvrms, with cf 2 filter as load) 26, 27 mix 2 in mix 2 out mx gain2 20 db 1.0 db voltage compression level (input referred) ip3 bit set 0 28, 30 mix 2 in mix 2 out v o mix 2 1 db 32 17 mvrms dbm ip3 bit set 1 29, 30 45 14 third order intercept (input referred) [note 6] ip3 bit set 0 28, 30 mix 2 in mix 2 out toi mix2 136 4.3 mvrms dbm ip3 bit set 1 29, 30 158 3.0 3.0 db if bandwidth 31 mix 2 in mix 2 out mix 2 bw 2.5 mhz limiter/demodulator (f in = 455 khz, f dev = 3.0 khz, f mod = 1.0 khz) input impedance 49 lim in lim in r plim c plim 1.5 16 k w pf detector output impedance det out r o 1.1 k w if 3.0 db limiting sensitivity 1 lim in det out if sens 71 100 m vrms demodulator bandwidth lim in det out bw 20 khz rssi/carrier detect (no modulation) rssi output dynamic range 56 mix 1 in rssi rssi 80 db dc voltage range 56 mix 1 in rssi dc rssi 0.2 to 1.5 vdc carrier detect threshold cd threshold adjust = (10100) (threshold relative to mix 1 in level) 57 mix 1 in cd out v t 15 m vrms hysteresis, cd = (10100) (threshold relative to mix 1 in level) 57 mix1 in cd out hys 2.0 db output high voltage cd = (00000), rssi = 0.2 v 1 rssi cd out v oh v cc 0.1 3.6 v output low voltage cd = (11111), rssi = 0.9 v 1 rssi cd out v ol 0.02 0.4 v carrier detect threshold adjustment range (programmable through mpu interface) 126 v t range 20 to 11 db carrier detect threshold number of programmable levels 126 v tn 32 note: 6. third order intercept calculated for input levels 10 db below 1.0 db compression point.
MC13110a/b MC13111a/b 6 motorola analog ic device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or r x mode, unless otherwise specified; test circuit figure 1.) characteristic unit max typ min symbol measure pin input pin figure r x audio path (f in = 1.0 khz, active mode, scrambler bypassed) absolute gain (v in = 20 dbv) 1, 72 r x audio in sa out g 4.0 0 4.0 db gain tracking (referenced to e out for v in = 20 dbv) 1, 76 e in e out g t db v in = 30 dbv 21 20 19 v in = 40 dbv 42 40 38 total harmonic distortion (v in = 20 dbv) 1, 76 r x audio in sa out thd 0.7 1.0 % maximum input voltage (v cc = 2.7 v) 76 r x audio in 11.5 dbv maximum output voltage (increase input voltage until output voltage thd = 5.0%, then measure output voltage) 1 e in e out v omax 2.0 0 dbv input impedance r x audio in ei z in 600 75 k w pp x e in in 7.5 attack time e cap = 0.5 m f, r filt = 40 k (see appendix b) e in e out t a 3.0 ms release time e cap = 0.5 m f, r filt = 40 k (see appendix b) e in e out t r 13.5 ms compressor to expander crosstalk v in = 10 dbv, v (e in) = ac gnd 1 c in e out c t 90 70 db r x muting ( d gain) v in = 20 dbv, r x gain adj = (01111) 1 r x audio in e out m e 84 60 db r x high frequency corner r x path, v r x audio in = 20 dbv 1 r x audio in scr out r x f ch 3.779 3.879 3.979 khz low pass filter passband ripple (v in = 20 dbv) 1, 73 r x audio in scr out ripple 0.4 0.6 db r x gain adjust range (programmable through mpu interface) 125 r x audio in scr out r x range 9.0 to 10 db r x gain adjust steps number of programmable levels 125 r x audio in scr out r x n 20 db audio path noise, cmessage weighting (input acgrounded) 70 r x audio in scr out e out sa out en 85 <95 <95 dbv volume control adjust range 123 e in e out v cn range 14 to 16 db volume control number of programmable levels 123 e in e out v cn 16 speaker amp/sp mute (active mode) maximum output swing r l = no load, v in = 3.4 vpp r l = 130 w , v in = 2.8 vpp r l = 620 w , v in = 4.0 vpp 1, 79 sa in sa out v omax 2.8 2.0 3.2 2.6 3.4 vpp speaker amp muting v in = 20 dbv, r l = 130 w 1 sa in sa out m sp 92 60 db
MC13110a/b MC13111a/b 7 motorola analog ic device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or r x mode, unless otherwise specified; test circuit figure 1.) characteristic unit max typ min symbol measure pin input pin figure data amp comparator hysteresis 1 da in da out hys 30 42 50 mv threshold voltage da in da out v t v cc 0.7 v input impedance 1 da in z i 200 250 280 k w output impedance da out z o 100 k w output high voltage v in = v cc 1.0 v, i oh = 0 ma 1 da in da out v oh v cc 0.1 3.6 v output low voltage v in = v cc 0.4 v, i ol = 0 ma 1 da in da out v ol 0.1 0.4 v maximum frequency da in da out f max 10 khz mic amp (f in = 1.0 khz, external resistors set to gain of 1, active mode) open loop gain t x in amp out avol 100,000 v/v gain bandwidth t x in amp out gbw 100 khz maximum output swing (r l = 10 k w) t x in amp out v omax 3.2 vpp t x audio path (f in = 1.0 khz, t x gain adj = (01111); alc, limiter, and mutes disabled; active mode, scrambler bypassed) absolute gain (v in = 10 dbv) 1, 83 t x in t x out g 4.0 0 4.0 db gain tracking (referenced to t x out for v in = 10 dbv) v in = 30 dbv v in = 40 dbv 1, 87 t x in t x out g t 11 17 10 15 9.0 13 db total harmonic distortion (v in = 10 dbv) 1, 87 t x in t x out thd 0.8 1.8 % maximum output voltage (increase input voltage until output voltage thd = 5.0%, then measure output voltage. t x gain adjust = 8 db) 1 t x in t x out v omax 2.0 0 dbv input impedance c in z in 10 k w attack time (c cap = 0.5 m f, r filt = 40 k (see appendix b)) c in t x out t a 3.0 ms release time (c cap = 0.5 m f, r filt = 40 k (see appendix b)) c in t x out t r 13.5 ms expander to compressor crosstalk (v in = 20 dbv, speaker amp no load, v (c in) = ac gnd) 1 e in t x out c t 60 40 db t x muting (v in 10 dbv) 1 t x in t x out m c 88 60 db alc output level (alc enabled) v in = 10 dbv v in = 2.5 dbv 1, 87, 90 t x in t x out alc out 15 13 13 11 8.0 6.0 dbv alc slope (alc enabled) 1 t x in t x out slope 0.1 0.25 0.4 db/db v in = 10 dbv x p v in = 2.5 dbv alc input dynamic range c in t x out dr 16 to 2.5 dbv limiter output level (v in = 2.5 dbv, limiter enabled) 1 t x in t x out v lim 10 8.0 dbv t x high frequency corner [note 7] (vt x in = 10 dbv, mic amp = unity gain) 1 t x in t x out t x f c 3.6 3.7 3.8 khz note: 7. the filter specification is based on a 10.24 mhz 2nd lo, and a switchedcapacitor (sc) filter counter divider ratio of 31. if other 2nd lo frequencies and/or sc filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting sc filter clock frequency.
MC13110a/b MC13111a/b 8 motorola analog ic device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or r x mode, unless otherwise specified; test circuit figure 1.) characteristic unit max typ min symbol measure pin input pin figure t x audio path (f in = 1.0 khz, t x gain adj = (01111); alc, limiter, and mutes disabled; active mode, scrambler bypassed) low pass filter passband ripple (v in = 10 dbv) 1, 84 t x in t x out ripple 0.7 1.2 db maximum compressor gain (v in = 70 dbv) c in t x out av max 23 db t x gain adjust range (programmable through mpu interface) 125 c in t x out t x range 9.0 to 10 db t x gain adjust steps number of programmable levels 125 c in t x out t x n 20 r x and t x scrambler (2nd lo = 10.24 mhz, t x gain adj = (01111), r x gain adj = (01111), volume control = (0 db default levels), scf clock divider = 31. total is divide by 62 for scf clock frequency of 165.16 khz) r x high frequency corner (note 8) r x path, f = 479 hz, v r x audio in = 20 dbv r x audio in scr out r x f ch 3.55 3.65 3.75 khz t x high frequency corner (note 8) t x path, f = 300 hz, v t x in = 10 dbv, mic amp = unity gain t x in t x out t x f ch 3.829 3.879 3.929 khz absolute gain r x : v in = 20 dbv t x : v in = 10 dbv, limiter disabled r x audio in t x in e out t x out av 4.0 4.0 0.4 1.0 4.0 4.0 db pass band ripple r x + t x path 1.0 m f from t x out to r x audio in, f in = low corner frequency to high corner frequency c in e out ripple 1.9 2.5 db scrambler modulation frequency r x : 100 mv (20 dbv) t x : 316 mv (10 dbv) r x audio in c in e out t x out f mod 4.119 4.129 4.139 khz group delay r x + t x path 1.0 m f from t x out to r x audio in, f in = 1.0 khz c in e out gd 1.0 ms x , in f in = low corner frequency to high corner frequency c in e out gd 4.0 carrier breakthrough r x + t x path 1.0 m f from t x out to r x audio in c in e out cbt 60 db baseband breakthrough r x + t x path 1.0 m f from t x out to r x audio in, f in = 1.0 khz, f meas = 3.192 khz c in e out bbt 50 db low battery detect average threshold voltage before electronic adjustment (v ref _adj = (0111)) 1, 131 ref 1 ref 2 bd 1 out bd 2 out vt i 1.38 1.48 1.58 v average threshold voltage after electronic adjustment (v ref _adj = (adjusted value)) 1 ref 1 ref 2 bd 1 out bd 2 out vt f 1.475 1.5 1.525 v hysteresis ref 1 ref 2 bd 1 out bd 2 out hys 4.0 mv input current (v in = 1.0 and 2.0 v) 1 ref 1 ref 2 i in 50 50 na output high voltage (v in = 2.0 v) 1 ref 1 ref 2 bd 1 out bd 2 out v oh v cc 0.1 3.6 v note: 8. the filter specification is based on a 10.24 mhz 2nd lo, and a switchcapacitor (sc) filter counter divider ratio of 31. if other 2nd lo frequencies and/or sc filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting sc filter clock frequency.
MC13110a/b MC13111a/b 9 motorola analog ic device data electrical characteristics (continued) (v cc = 3.6 v, v b = 1.5 v, t a = 25 c, active or r x mode, unless otherwise specified; test circuit figure 1.) characteristic unit max typ min symbol measure pin input pin figure low battery detect output low voltage (v in = 1.0 v) 1 ref 1 ref 2 bd 1 out bd 2 out v ol 0.2 0.4 v battery detect internal threshold after electronic adjustment of v b voltage 1, 128 v cc audio bd 2 out v bd select = (111) cc ibs 7 3.381 3.455 3.529 bd select = (110) ibs 6 3.298 3.370 3.442 bd select = (101) ibs 5 3.217 3.287 3.357 bd select = (100) ibs 4 3.134 3.202 3.270 bd select = (011) ibs 3 2.970 3.034 3.098 bd select = (010) ibs 2 2.886 2.948 3.010 bd select = (001) ibs 1 2.802 2.862 2.922 pll phase detector output source current (v pd = gnd + 0.5 v to pll v ref 0.5 v) r x pd t x pd i oh 1.0 ma output sink current (v pd = gnd + 0.5 v to pll v ref 0.5 v) r x pd t x pd i ol 1.0 ma pll loop characteristics maximum 2nd lo frequency (no crystal) lo 2 in f 2ext 12 mhz maximum 2nd lo frequency (with crystal) lo 2 in lo 2 out f 2ext 12 mhz maximum t x vco (input frequency), v in = 200 mvpp t x vco f txmax 80 mhz pll voltage regulator regulated output level (i l = 0 ma, after v ref adjustment) 1 pll v ref v o 2.4 2.5 2.6 v line regulation (i l = 0 ma, v cc = 3.0 to 5.5 v) 1 v cc audio pll v ref v reg line 11.8 40 mv load regulation (i l = 1.0 ma) 1 v cc audio pll v ref v reg load 20 1.4 mv microprocessor serial interface input current low (v in = 0.3 v, standby mode) 1 data, clk, en i il 5.0 0.4 m a input current high (v in = 3.3 v, standby mode) 1 data, clk, en i ih 1.6 5.0 m a hysteresis voltage data, clk, en v hys 1.0 v maximum clock frequency data, en, clk 2.0 mhz input capacitance data, clk, en c in 8.0 pf en to clk setup time 106 en, clk t suec 200 ns data to clk setup time 105 data, clk t sudc 100 ns hold time 105 data, clk t h 90 ns recovery time 106 en, clk t rec 90 ns input pulse width en, clk t w 100 ns mpu interface powerup delay (90% of pll v ref to data,clk, en) 108 t pumpu 100 m s
MC13110a/b MC13111a/b 10 motorola analog ic device data figure 1. production test circuit (52 pin qfp) 4700 32.4 k 0.1 3.01 k 0.047 1.5 k 22.1 k 10.240 mhz 5.0 50 8.2 0.1 1.0 f m 0.1 10 f m 0.1 t x vco 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 13 12 11 10 9 8 7 5 4 3 2 16 v cca 0.1 0.1 7.5 k 49.9 k 33 rf in 0.01 49.9 0.01 cf 1 10.7 mhz cf 2 455 khz 332 v cc 0.1 0.1 0.1 10 l 2 22.1 k mpu clock output 0.01 r x loop filter 10 f m 0.1 0.1 l3 1.0 k 1.0 k v ref2 v ref1 110 10 f m 1.0 f m 49.9 k note: this schematic is only a partial representation of the actual production test circuit. 100 k 100 k v cc t x out data out bd 1 out bd 2 out v cc carrier detect out v cca da in 0.1 0.1 49.9 k 0.1 10 f m 0.1 v cc audio 0.01 1000 0.1 49.9 k 15 k 100 k 0.1 7.5 k 1.0 m f to v cc r mix det out t x in scr out e in e out sa in sa out rssi det out r v da in t amp out c in c cap t bd da out bd lo lo v cap ctrl gnd audio sa out sa in e out e cap e in scr out ref ref v 1 in 1 out 2 1 b x audio in cc audio x in x out 2 out 1 out t sgnd rf lim in lim out lo lo v t gnd pll data en clk clk out cd 2 in 2 out gnd rf q ag out pll v mix mix mix mix lim c coil x pd ref x pd x vco 1 1 in 2 1 out 2 out 2 in lim c v 1 2 cc rf in 1 r x audio in mic amp out legend: if 1, then capacitor value = pf if <1, then capacitor value = f m MC13111a/b ic 0.1 c in MC13110a/b
MC13110a/b MC13111a/b 11 motorola analog ic device data pin function description pin s y mbol/ e i l i l ci i (52 pi qfp) dii lqfp48 qfp52 symbol/ type equivalent internal circuit (52 pin qfp) description 48 1 1 2 lo 2 in lo 2 out lo 2 out 2 lo 2 in 1 pll v ref pll v ref 100 100 pll v ref these pins form the pll reference oscillator when connected to an external parallelresonant crystal (10.24 mhz typical). the reference oscillator is also the second local oscillator (lo 2 ) for the rf receiver. alo 2 ino may also serve as an input for an externally generated reference signal which is typically accoupled. when the ic is set to the inactive mode, lo 2 in is internally pulled low to disable the oscillator. the input capacitance to ground at each pin (lo 2 in/ lo 2 out) is 3.0 pf. 2 3 v ag v ag 3 pll v ref v cc audio 30 k v ag is the internal reference voltage for the switched capacitor filter section. this pin must be decoupled with a 0.1 m f capacitor. 3 4 r x pd (output) 46 pll v ref pll v ref 15 this pin is a tristate voltage output of the r x and t x phase detector. it is either ahigho, alowo, or ahigh impedance,o depending on the phase difference of the phase detector input signals. during lock, very narrow p ulses with a fre q uenc y e q ual to the 5 6 t x pd (output) r x pd, t x pd 4, 6 15 narrow pulses with a frequency equal to the reference frequency are present. this pin drives the external r x and t x pll loop filters. r x and t x pd outputs can sink or source 1.0 ma. 4 5 pll v ref pll v ref 5 132 k v cc audio pll v ref is a pll voltage regulator output pin. an internal voltage regulator provides a stable power supply voltage for the r x and t x pll's and can also be used as a regulated supply voltage for other ic's. it can source up to 1.0 ma externally. proper supply filtering is a must on this pin. pll v ref is pulled up to v cc audio for the standby and inactive modes (note 1). 6 7 gnd pll ground pin for digital pll section of ic. 7 8 t x vco (input) t x vco 8 pll v ref 1.0 k pll v ref t x vco is the transmit divide counter input which is driven by an accoupled external transmit loop vco. the minimum signal level is 200 mvpp @ 60.0 mhz. this pin also functions as the test mode input for the counter tests.
MC13110a/b MC13111a/b 12 motorola analog ic device data pin function description (continued) description equivalent internal circuit (52 pin qfp) symbol/ type pin description equivalent internal circuit (52 pin qfp) symbol/ type qfp52 lqfp48 8 9 10 9 10 11 data en clk (input) data, en, clk 9, 10, 11 v cc audio 240 pll v ref 1.0 m a microprocessor serial interface input pins are for programming various counters and control functions. the switching thresholds are referenced to pll v ref and gnd pll. the inputs operate up to v cc . these pins have 1.0 m a internal pulldown currents. 11 12 clk out (output) clk out 12 v cc audio v cc audio 1.0 k the microprocessor clock output is derived from the 2nd lo crystal oscillator and a programmable divider with divide ratios of 2 to 312.5. it can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. the driver has an internal resistor in series with the output which can be combined with an external capacitor to form a low pass filter to reduce radiated noise on the pcb. this output also functions as the output for the counter test modes. 1) for the MC13110a/b and MC13111a/b the clk out can be disabled via the mpu interface. 2) for the MC13110b and MC13111b this output is always active (on) (note 2). 12 13 cd out (i/o) cd comparator cd out 13 v cc audio 240 pll v ref hardware interrupt dual function pin; 1) carrier detect output (open collector with external 100 k w pullup resistor. 2) hardware interrupt input which can be used to awakeupo from the inactive mode. 14 bd 1 out 14 16 v cc audio low battery detect output #1 is an open collector with external pullup resistor. 14 16 bd 2 out (output) bd 1 out bd 2 out 14 , 16 low battery detect output #2 is an open collector with external pullup resistor. 13 15 da out (output) da out 15 v cc audio v cc audio 100 k data amplifier output (open collector with internal 100 k w pullup resistor). 15 17 t x out (output) t x out 17 v cc audio v b t x out is the t x path audio output. internally this pin has a lowpass filter circuitry with 3 db bandwidth of 4.0 khz. t x gain and mute are programmable through the mpu interface. this pin is sensitive to load capacitance.
MC13110a/b MC13111a/b 13 motorola analog ic device data pin function description (continued) description equivalent internal circuit (52 pin qfp) symbol/ type pin description equivalent internal circuit (52 pin qfp) symbol/ type qfp52 lqfp48 16 18 c cap c cap 18 v cc audio v cc audio 40 k c cap is the compressor rectifier filter capacitor pin. it is recommended that an external filter capacitor to v cc audio be used. a practical capacitor range is 0.1 to 1.0 m f. 0.47 m f is the recommended value. 17 19 c in (input) c in 19 v cc audio 12.5 k v b c in is the compressor input. this pin is internally biased and has an input impedance of 12.5 k. c in must be accoupled. 18 20 amp out (output) v cc audio 21 v cc audio microphone amplifier output. the gain is set with external resistors. the feedback resistor should be less than 200 k w . 19 21 t x in (input) amp out 20 v b t x in 21 t x in is the t x path input to the microphone amplifier (mic amp). an external resistor is connected to this pin to set the mic amp gain and input impedance. t x in must be accoupled, too. 20 22 da in (input) da in 22 v cc audio 250 k 250 k v cc audio the data amplifier input (da in) resistance is 250 k w and must be accoupled. hysteresis is internally provided. 21 23 v cc audio v cc audio is the supply for the audio section. it is necessary to adequately filter this pin. 22 24 r x audio in (input) r x audio in 24 v cc audio 600 k v b the r x audio input resistance is 600 k w and must be accoupled. 23 25 det out (output) det out 25 v cc audio v cc rf 240 30 m a det out is the audio output from the fm detector. this pin is dccoupled from the fm detector and has an output impedance of 1100 w .
MC13110a/b MC13111a/b 14 motorola analog ic device data pin function description (continued) description equivalent internal circuit (52 pin qfp) symbol/ type pin description equivalent internal circuit (52 pin qfp) symbol/ type qfp52 lqfp48 30 26 rssi v cc audio 186 k 26 v cc rf v cc rf rssi rssi is the receive signal strength indicator. this pin must be filtered through a capacitor to ground. the capacitance value range should be 0.01 to 0.1 m f. this is also the input to the carrier detect comparator. an external r to ground shifts the rssi voltage. 24 27 q coil q coil 27 v cc rf v cc rf a quad coil or ceramic discriminator connects this pin as part of the fm demodulator circuit. dccouple this pin to v cc rf through the quad coil or the external resistor. 26 29 v cc rf v cc supply for rf receiver section (1st lo, mixer, limiter, demodulator). proper supply filtering is needed on this pin too. 25 28 lim out lim c 1 31 v cc rf 28 v cc rf v cc rf v cc rf 53.5 k a quad coil or ceramic discriminator are connected to these pins as part of the fm demodulator circuit. a coupling capacitor connects this pin to the quad coil or ceramic discriminator as part of the fm demodulator circuit. this pin can drive coupling capacitors up to 47 pf with no deterioration in performance. 27 28 30 31 lim c 2 lim c 1 1 lim out lim in 32 lim c 2 30 52 k 1.5 k if amplifier/limiter capacitor pins. these decoupling capacitors should be 0.1 m f. they determine the if limiter gain and low frequency bandwidth. 29 32 lim in (input) lim c 2 52 k signal input for if amplifier/limiter. signals should be accoupled to this pin. the input impedance is 1.5 k w at 455 khz. 33 sgnd rf this pin is not connected internally but should be grounded to reduce potential coupling between pins. 31 34 mix 2 in (input) mix 2 in 34 v cc rf v cc rf 3.0 k mix 2 in is the second mixer input. signals are to be accoupled to this pin, which is biased internally to v cc rf. the input impedance is 2.8 k w at 455 khz. the input impedance can be reduced by connecting an external resistor to v cc rf.
MC13110a/b MC13111a/b 15 motorola analog ic device data pin function description (continued) description equivalent internal circuit (52 pin qfp) symbol/ type pin description equivalent internal circuit (52 pin qfp) symbol/ type qfp52 lqfp48 32 35 mix 2 out (output) mix 2 out 35 v cc rf v cc rf 1.2 k mix 2 out is the second mixer output. the second mixer has a 3 db bandwidth of 2.5 mhz and an output impedance of 1.5 k w . the output current drive is 50 m a. 33 36 gnd rf ground pin for rf section of the ic. 34 37 mix 1 out (output) mix 1 out 37 v cc rf v cc rf 200 the first mixer has a 3 db if bandwidth of 13 mhz and an output impedance of 300 w . the output current drive is 300 m a and can be programmed for 1.0 ma. 35 38 mix 1 in 2 (input) v cc rf v cc rf 950 950 v ref 20 k signals should be accoupled to this pin, which is biased internally to v cc 1.6 v. the singleended and differential input impedance are about 1.6 and 1.8 k w at 46 mhz, respectively. 36 39 mix 1 in 1 (input) mix 1 in 2 , mix 1 in 1 38, 39 950 950 37 38 40 41 lo 1 in lo 1 out lo 1 out 41 lo 1 in 40 tank elements, an internal varactor and capacitor matrix for 1st lo multivibrator oscillator are connected to these pins. the oscillator is useable up to 80 mhz. 39 42 v cap ctrl v cap ctrl 42 v cc rf 55 k v cap ctrl is the 1st lo varactor control pin. the voltage at this pin is referenced to gnd audio and varies the capacitance between lo 1 in and lo 2 out. an increase in voltage will decrease capacitance. 40 43 gnd audio ground for audio section of the ic. 41 44 sa out (output) 44 v cc audio sa i 45 v cc audio the speaker amplifier gain is set with an external feedback resistor. it should be less than 200 k w . the speaker amplifier can be muted through the mpu interface. 42 45 sa in (input) sa out v b sa in an external resistor is connected to the speaker amplifier input (sa in). this will set the gain and input impedance and must be accoupled.
MC13110a/b MC13111a/b 16 motorola analog ic device data pin function description (continued) description equivalent internal circuit (52 pin qfp) symbol/ type pin description equivalent internal circuit (52 pin qfp) symbol/ type qfp52 lqfp48 43 46 e out (output) e out 46 v cc audio v b the output level of the expander output is determined by the volume control. volume control is programmable through the mpu interface. 44 47 e cap e cap 47 v cc audio v cc audio 40 k e cap is the expander rectifier filter capacitor pin. connect an external filter capacitor between v cc audio and e cap. the recommended capacitance range is 0.1 to 1.0 m f. 0.47 m f is the suggested value. 45 48 e in (input) e in 48 v cc audio v b 30 k the expander input pin is internally biased and has input impedance of 30 k w . 46 49 scr out (output) scr out 49 v cc audio v b scr out is the r x audio output. an internal low pass filter has a 3 db bandwidth of 4.0 khz. 50 ref 2 50, 51 v cc audio reference voltage input for low battery detect #2. 51 ref 1 ref 2 , ref 1 reference voltage input for low battery detect #1. 47 52 v b v b 52 v cc audio v cc audio 240 v b is the internal half supply analog ground reference. this pin must be filtered with a capacitor to ground. a typical capacitor range of 0.5 to 10 m f is desired to reduce crosstalk and noise. it is important to keep this capacitor value equal to the pll v ref capacitor due to logic timing (note 9). note: 9. a capacitor range of 0.5 to 10 m f is recommended. the capacitor value should be the same used on the v b pin (pin 52). an additional high quality parallel capacitor of 0.01 m f is essential to filter out spikes originating from the pll logic circuitry.
MC13110a/b MC13111a/b 17 motorola analog ic device data device description and application information the following text, graphics, tables and schematics are provided to the user as a source of valuable technical information about the universal cordless telephone ic. this information originates from thorough evaluation of the device performance for the us and french applications. this data was obtained by using units from typical wafer lots. it is important to note that the forgoing data and information was from a limited number of units. by no means is the user to assume that the data following is a guaranteed parametric. only the minimum and maximum limits identified in the electrical characteristics tables found earlier in this spec are guaranteed. general circuit description the MC13110a/b and MC13111a/b are a low power dual conversion narrowband fm receiver designed for applications up to 80 mhz carrier frequency. this device is primarily designated to be used for the 49 mhz cordless phone (ct0), but has other applications such as low data rate narrowband data links and as a backend device for 900 mhz systems where baseband analog processing is required. this device contains a first and second mixer, limiter, demodulator, extended range receive signal strength (rssi), receive and transmit baseband processing, dual programmable pll, low battery detect, and serial interface for microprocessor control. the fm receiver can also be used with either a quadrature coil or ceramic resonator. refer to the pin function description table for the simplified internal circuit schematic and description of this device. dc current and battery detect figures 3 through 6 are the current consumption for inactive, standby, receive, and active modes versus supply voltages. figures 7 and 8 show the typical behavior of current consumption in relation to temperature. the relationship of additional current draw due to ip3 bit set to <1> and supply voltage are shown in figures 9 and 10. for the low battery detect, the user has the option to operate the ic in the programmable or nonprogrammable modes. note that the 48 pin package can only be used in the programmable mode. figure 128 describes this operation (refer to the serial interface section under clock divider register). in the programmable mode several different internal threshold levels are available (figure 2). the bits are set through the scf clock divider register as shown in figures 108 and 126. the reference for the internal divider network is v cc audio. the voltages on the internal divider network are compared to the internal reference voltage, vb, generated by an internal source. since the internal comparator used is noninverting, a high at v cc audio will yield a high at the battery detect output, and vice versa for v cc audio set to a low level. for the 52 pin package option, the ref 1 and ref 2 pins need to be tied to v cc when used in the programmable mode. it is essential to keep the external reference pins above gnd to prevent any possible poweron reset to be activated. when considering the nonprogrammable mode (bits set to <000>) for the 52 pin package, the ref 1 and ref 2 pins become the comparators reference. an internal switch is activated when the nonprogrammable mode is chosen connecting ref 1 and ref 2. here, two external precision resistor dividers are used to set independent thresholds for two battery detect hysteresis comparators. the voltages on ref 1 and ref 2 are again compared to the internally generated 1.5 v reference voltage (vb). the low battery detect threshold tolerance can be improved by adjusting a trimpot in the external resistor divider (user designed). the initial tolerance of the internal reference voltage (vb) is 6.0%. alternately, the tolerance of the internal reference voltage can be improved to 1.5% through mpu serial interface programming (refer to the serial interface section, figure 131). the internal reference can be measured directly at the avbo pin. during final test of the telephone, the vb internal reference voltage is measured. then, the internal reference voltage value is adjusted electronically through the mpu serial interface to achieve the desired accuracy level. the voltage reference register value should be stored in rom during final test so that it can be reloaded each time the combo ic is powered up. the low battery detect outputs are open collector. the battery detect levels will depend on the accuracy of the vb voltage. figure 12 indicates that the vb voltage is fairly flat over temperature. figure 2. internal low battery detect levels (with vb = 1.5 v) battery detect select ramping up (v) ramping down (v) average (v) hysteresis (mv) 0 1 2.867 2.861 2.864 4.0 2 2.953 2.947 2.950 6.0 3 3.039 3.031 3.035 8.0 4 3.207 3.199 3.204 8.0 5 3.291 3.285 3.288 6.0 6 3.375 3.367 3.371 8.0 7 3.461 3.453 3.457 8.0 note: 10. battery detect select 0 is the nonprogrammable operating mode.
MC13110a/b MC13111a/b 18 motorola analog ic device data figure 3. current versus supply voltage inactive mode 0 5.0 10 15 20 25 30 35 40 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v cc , supply voltage (v) figure 4. current versus supply voltage standby mode, mcu clock output on at 2.048 mhz 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 mcu clock out off mcu clock out on i inact ic, supply current ( m a) std i cc , supply current (ma) 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v cc , supply voltage (v) dc current figure 5. current versus supply voltage receive mode 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 mcu clock out off mcu clock out on v cc , supply voltage (v) r cc , supply current (ma) x i 7.7 figure 6. current versus supply voltage active mode 7.0 7.1 7.2 7.3 7.4 7.5 7.6 7.8 7.9 8.0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 mcu clock out off mcu clock out on act i , supply current (ma) cc v cc , supply voltage (v) figure 7. current versus temperature normalized to 25 c 10 5.0 0 5.0 10 15 40 30 20 10 0 10 20 30 40 50 60 70 80 90 t a , temperature ( c) inactive standby delta current drain (% from 25 c) 12 10 8.0 6.0 4.0 2.0 0 2.0 4.0 6.0 0 figure 8. current versus temperature normalized to 25 c 40 30 20 10 10 20 30 40 50 60 70 80 90 t a , temperature ( c) active receive delta current drain (% from 25 c)
MC13110a/b MC13111a/b 19 motorola analog ic device data dc current 1.40 1.42 1.50 1.30 1.32 1.34 1.36 1.38 1.44 1.46 1.48 figure 9. additional supply current consumption versus supply voltage, ip3 = <1> 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 v cc , supply voltages (v) delta current drain (ma) figure 10. additional ip3 supply current consumption versus temperature normalized to 25 c 20 15 10 5 0 5 10 40 30 20 10 0 10 20 30 40 50 60 70 80 90 t a , temperature ( c) delta current drain (% from 25 c) receive/active receive/active 650 500 figure 11. current standby mode versus mcu clock output 300 350 400 450 550 600 700 750 800 1.0 10 100 1000 mcu clk out divide value no load mcu clock off 10 pf load std i , supply current (ma) cc figure 12. vb voltage versus temperature normalized to 1.5 v at 25 c 1.4925 1.4950 1.4975 1.5000 1.5025 1.5050 1.5075 2010 0 1020 3040 506070 8090 t a , temperature ( c) v , normalized vb voltage (v) s
MC13110a/b MC13111a/b 20 motorola analog ic device data first and second mixer mixer description the 1st and 2nd mixers are similar in design. both are double balanced to suppress the lo and the input frequencies to give only the sum and difference frequencies at the mixer output. typically the lo is suppressed better than 50 db for the first mixer and better than 40 db for the second mixer. the gain of the 1st mixer has a 3.0 db corner at approximately 13 mhz and is used at a 10.7 mhz if. it has an output impedance of 300 w and matches to a typical 10.7 mhz ceramic filter with a source and load impedance of 330 w . a series resistor may be used to raise the impedance for use with crystal filters. they typically have an input impedance much greater than 330 w . first mixer figures 17 through 20 show the first mixer transfer curves for the voltage conversion gain, output level, and intermodulation. notice that there is approximately 10 db linearity improvement when the aip3 increaseo bit is set to <1>. the aip3 increaseo bit is a programmable bit as shown in the serial programmable interface section under the r x counter latch register. the ip3 = <1> option will increase the supply current demand by 1.3 ma. figure 13. first mixer input and output impedance schematic 1st mixer mix 1 in mix 1 out r pi c pi r po c po figure 14. first mixer output impedance unit output impedance b ip3 = <0> (set low) 304 w // 3.7 pf b ip3 = <1> (set high) 300 w // 4.0 pf figures 13, 14, and 16 represent the input and output impedance for the first mixer. notice that the input singleended and differential impedances are basically the same. the output impedance as described in figure 14 will be used to match to a ceramic or crystal filter's input impedance. a typical ceramic filter input impedance is 330 w while crystal filter input impedance is usually 1500 w . exact impedance matching to ceramic filters are not critical, however, more attention needs to be given to the filter characteristics of a crystal filter. crystal filters are much narrower. it is important to accurately match to these filters to guaranty a reasonable response. to find the if bandwidth response of the first mixer refer to figure 22. the 3.0 db bandwidth point is approximately 13 mhz. figure 15 is a summary of the first mixer feedthrough parameters. figure 15. first mixer feedthrough parameters parameter (dbm) 1st lo feedthrough @ mix 1 in 1 70.0 1st lo feedthrough @ mix 1 out 55.5 rf feedthrough @ mix 1 out with 30 dbm 61.0 figure 16. first mixer input impedance over input frequency ui us center channels france center channels unit 49 mhz 46 mhz 41 mhz 26 mhz singleended 1550 w // 3.7 pf 1560 w // 3.7 pf 1570 w // 3.8 pf 1650 w // 3.7 pf differential 1600 w // 1.8 pf 1610 w // 1.8 pf 1670 w // 1.8 pf 1710 w // 1.8 pf note: 11. singleended data is from measured results. differential data is from simulated results.
MC13110a/b MC13111a/b 21 motorola analog ic device data mix 1 out, mixer output (dbm) 1.0 15 40 0 40 14 2.7 10 40 0 40 14 f, if frequency (mhz) mix 1 in, mixer input level (dbm) mix 1 in, mixer input level (dbm) v o 1.0 db mix v cc audio, audio supply voltage (v) mix 1 out, mixer output (dbm) mix 1 in, mixer input level (dbm) mx gain1 , voltage figure 17. first mixer voltage conversion gain, ip3_bit = 0 mix 1 in, mixer input level (dbm) figure 18. first mixer voltage conversion gain, ip3_bit = 1 figure 19. first mixer output level and intermodulation, ip3_bit = 0 figure 20. first mixer output level and intermodulation, ip3_bit = 1 figure 21. first mixer compression versus supply voltage figure 22. first if bandwidth fundamental level 3rd order intermodulation fundamental level 3rd order intermodulation conversion gain (db) 12 20 10 20 12 40 8.0 40 10 60 60 8.0 4.0 80 80 2.0 100 100 10 12 5.0 14 0 16 5.0 18 10 20 15 22 35 35 30 30 25 25 20 20 15 15 10 10 10 35 3.3 35 30 30 25 25 20 4.2 20 15 4.8 15 10 5.4 10 100 3.6 3.9 4.5 3.0 5.1 ip3_bit = 1 1 , 1.0 db voltage compression (dbm) 6.0 6.0 ip3_bit = 0 mx gain1 , voltage conversion gain (db) mx gain1 , voltage conversion gain (db) v cc = 3.6 v if = 10.695 mhz, 330 w v cc = 3.6 v if = 10.695 mhz, 330 w v cc = 3.6 v if = 10.695 mhz, 330 w v cc = 3.6 v if = 10.695 mhz, 330 w first mixer if = 10.695 mhz, 330 w v cc = 3.6 v r l = 330 w lo = 36.075 mhz
MC13110a/b MC13111a/b 22 motorola analog ic device data second mixer figures 26 through 29 represents the second mixer transfer characteristics for the voltage conversion gain, output level, and intermodulation. there is a slight improvement in gain when the aip3 bito is set to <1> for the second mixer. (note: this is the same programmable bit discussed earlier in the section.) figure 23. second mixer input and output impedance schematic 2nd mixer mix 2 in mix 2 out r pi c pi r po c po figure 24. second mixer input and output impedances unit input impedance r pi // c pi output impedance r po // c po ip3 = <0> (set low) 2817 w // 3.6 pf 1493 w // 6.1 pf ip3 = <1> (set high) 2817 w // 3.6 pf 1435 w // 6.2 pf the 2nd mixer input impedance is typically 2.8 k w . it requires an external 360 w parallel resistor for use with a standard 330 w , 10.7 mhz ceramic filter. the second mixer output impedance is 1.5 k w making it suitable to match standard 455 khz ceramic filters. the if bandwidth response of the second mixer is shown in figure 31. the 3.0 db corner is 2.5 mhz. the feedthrough parameters are summarized in figure 25. figure 25. second mixer feedthrough parameters parameter (dbm) 2nd lo feedthrough @ mix 2 out 42.9 if feedthrough @ mix 2 out with 30 dbm 61.7
MC13110a/b MC13111a/b 23 motorola analog ic device data 0.1 2.7 mix 2 out, mixer output (dbm) v o 1.0 db mix 2 , 1.0 db mx gain2 , voltage conversion gain (db) 25 10 10 40 10 22 f, if frequency (mhz) mix 2 in, mixer input level (dbm) mix 2 in, mixer input level (dbm) v cc audio, audio supply voltage (v) mix 2 in, mixer input level (dbm) figure 26. second mixer conversion gain, ip3_bit = 0 mix 2 in, mixer input level (dbm) figure 27. second mixer conversion gain, ip3_bit = 1 figure 28. second mixer output level and intermodulation, ip3_bit = 0 figure 29. second mixer output level and intermodulation, ip3_bit = 1 figure 30. second mixer compression versus supply voltage figure 31. second if bandwidth mix 2 out, mixer output (dbm) voltage compression (dbm) fundamental level 3rd order intermodulation ip3_bit = 1 ip3_bit = 0 fundamental level 3rd order intermodulation 10 20 30 18 50 16 70 90 12 14 16 18 20 22 12 14 22 20 10 18 30 16 50 14 70 90 20 15 10 5.0 0 40 40 40 35 35 30 30 25 25 20 20 15 15 10 10 1.0 35 3.3 35 30 30 25 25 20 4.2 20 15 4.8 15 10 5.4 10 10 3.6 3.9 4.5 3.0 5.1 mx gain2 , voltage conversion gain (db) mx gain2 , voltage conversion gain (db) v cc = 3.6 v if = 455 khz r l = 1500 w second mixer v cc = 3.6 v if = 455 khz r l = 1500 w v cc = 3.6 v if = 455 khz r l = 1500 w v cc = 3.6 v if = 455 khz r l = 1500 w if = 455 khz r l = 1500 w v cc = 3.6 v r l = 1500 w
MC13110a/b MC13111a/b 24 motorola analog ic device data first local oscillator the 1st lo is a multivibrator oscillator. the tank circuit is composed of a parallel external capacitance and inductance, internal programmable capacitor matrix, and internal varactor. the local oscillator requires a voltage controlled input to the internal varactor and an external loop filter driven by onboard phaselock control loop (pll). the 1st lo internal component values have a tolerance of 15%. a typical dc bias level on the lo input and lo output is 0.45 vdc. the temperature coefficient of the varactor is +0.08%/ c. the curve in figure 33 is the varactor control voltage range as it relates to varactor capacitance. it represents the expected internal capacitance for a given control voltage (v cap ctrl) of the MC13110a/b and MC13111a/b. figure 32 shows a representative schematic of the first lo function. lo 1 in lo 1 out v cap ctrl programmable internal capacitor 1st lo varactor varactor c ext l ext figure 32. first local oscillator schematic to select the proper l ext and c ext we can do the following analysis. from figure 34 it is observed that an inductor will have a significant affect on first lo performance, especially over frequency. the overall minimum q required for first lo to function as it relates to the lo frequency is also given in figure 34. choose an inductor value, say 470 nh. from figure 34, the minimum operating q is approximately 25. from the following equation: q coil = r p /x coil where: r p = parallel equivalent impedance (figure 35). c ext can be determined as follows: f lo 1 2 l ext c ext where: l ext = external inductance , c ext = external capacitance. figure 34 clearly indicates that for lower coil values, higher quality factors (q) are required for the first lo to function properly. also, lower lo frequencies need higher q's. in figure 35 the internal programmable capacitor selection relative to the first lo frequency and the parallel impedance is shown. this information will help the user to decide what inductor (l ext ) to choose for best performance in terms of q. refer to the auxiliary register in the serial interface section for further discussion on lo programmability.
MC13110a/b MC13111a/b 25 motorola analog ic device data 100 120 0 100 overall minimum q value lo inductor value (nh) r p , representative parallel w c 1 c 15 , capacitance select figure 33. first lo varicap capacitance versus control voltage figure 34. first lo minimum required overall q value versus inductor value figure 35. representative parallel impedance versus capacitor select figure 36. varicap value at v cv = 1.0 v over temperature figure 37. control voltage versus channel number, u.s. handset application figure 38. control voltage versus channel number, u.s. baseset application 30 mhz 40 mhz 50 mhz 30 mhz 40 mhz 50 mhz impedance (k ) 100 80 60 40 20 0 10 1000 1 6 4 3 8 9 10 11 12 13 14 15 257 first local oscillator 0 15 , capacitance (pf) v capctrl , control voltage (v) 14 12 13 11 10 9.0 8.0 7.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cap 10.2 v cap , capacitance (pf) t a , ambient temperature ( c) 9.8 9.4 9.8 20 0 25 70 85 55 10.6 11 1 1.7 ch1ch25, u.s. handset channel application cap 11 cap 10 cap 9 cap 6 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 3 5 7 9 11 13 15 17 19 21 23 25 1.8 ctrl, control voltage (v) 1.7 ch1ch25, u.s. baseset channel application cap 8 cap 3 cap 4 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1 3 5 7 9 11 13 15 17 19 21 23 25 v cap 1.8 ctrl, control voltage (v) v cap
MC13110a/b MC13111a/b 26 motorola analog ic device data second local oscillator the 2nd lo is a cmos oscillator. it is used as the pll reference oscillator and local oscillator for the second frequency conversion in the rf receiver. it is designed to utilize an external parallel resonant crystal. see schematic in figure 39. figure 39. second local oscillator schematic 2nd lo r pi c pi r po c po gm lo 2 in lo 2 out xtal c 2 c 1 figure 40. second local oscillator input and output impedance input impedance (r pi // c pi ) 11.6 k w // 2.9 pf output impedance (r po // c po ) 9.6 k w // 2.7 pf figure 41 shows a typical gain/phase response of the second local oscillator. load capacitance (c l ), equivalent series resistance (esr), and even supply voltage will have and affect on the 2nd lo response as shown in figures 45 and 46. except for the standby mode open loop gain is fairly constant as supply voltage increases from 2.5 v. this is due to the regulated voltage of 2.5 v on pll v ref . from the graphs it can seen that optimum performance is achieved when c1 equals c2 (c1/c2 = 1). figure 46 represents the esr versus crystal load capacitance for the 2nd lo. this relationship was defined by using a 6.0 db minimum loop gain margin at 3.6 v. this is considered the minimum gain margin to guarantee oscillator startup. oscillator startup is also significantly affected by the crystal load capacitance selection. in figures 42 and 43 the relationship between crystal load capacitance, supply voltage, and external load capacitance ratio (c2/c1), can be seen. the lower the load capacitance the better the performance. given the desired crystal load capacitance, c1 and c2 can be determined from figure 47. it is also interesting to point out that current consumption increases when c1 c2, as shown in figure 44. be careful not to overdrive the crystal. this could cause a noise problem. an external series resistor on the crystal output can be added to reduce the drive level, if necessary. v gain2 , lo voltage gain (db) 0 6.0 10.235 15 startup time (ms) capacitor ratio (c2:c1) figure 41. second lo gain/phase @ 10 dbm f, frequency (mhz) figure 42. startup time versus capacitor ratio, inactive to r x mode gain 10.24 mhz crystal c l = 10 pf r s = 20 w v cc = 5.0 v v cc = 3.6 v v cc = 2.3 v v cc = 2.7 v 10 5.0 0 5.0 10 15 20 25 5.0 4.0 3.0 2.0 1.0 0 10.24 10.245 phase 90 67.5 45 22.5 0 22.5 45 67.5 90 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10.24 mhz crystal c l = 10 pf r s = 20 w c1 = c2 = 15 pf second local oscillator
MC13110a/b MC13111a/b 27 motorola analog ic device data 0 30 0 800 0 20 capacitor ratio (c2:c1) i std , standby current ( a) m capacitor ratio (c2:c1) capacitor ratio (c2:c1) avol, open loop gain (db) v cc = 2.3 v v cc = 2.7, 3.6, 5.0 v 10.24 mhz crystal c l = 10 pf r s = 20 w r x mode 10.24 mhz crystal c l = 10 pf r s = 20 w 10.24 mhz crystal c l = 24 pf r s = 16 w standby current with clk_out running at 2.048 mhz standby current with clk_out off oscillator level v cc = 5.0 v v cc = 3.6 v v cc = 2.7 v v cc = 2.3 v lo 2 , second oscillator level (dbm) startup time (ms) 16 12 8.0 4.0 0 25 20 15 10 5.0 0 700 600 500 400 300 200 100 0 0.5 0.5 0.5 1.0 1.0 1.0 1.5 1.5 1.5 2.0 2.0 2.0 2.5 2.5 2.5 3.0 3.0 3.0 3.5 3.5 3.5 4.0 4.0 4.0 13 12 11 10 9.0 second local oscillator figure 43. startup time versus capacitor ratio, inactive to r x mode figure 44. second lo current consumption versus capacitor ratio figure 45. maximum open loop gain versus capacitor ratio 10 1000 w esr, equivalent resistance ( ) crystal load capacitance (pf) figure 46. maximum allowable equivalent series resistance (esr) versus crystal load capacitance 10 100 12 14 16 18 20 22 24 26 28 30 32 curve valid for f osc in the range of 10 mhz to 12 mhz 0 70 optimum c1 and c2 value (pf) required parallel crystal load capacitance (pf) figure 47. optimum value for c1 and c2 versus equivalent required parallel capacitance of the crystal 50 60 40 30 20 10 0 5.0 10 15 20 30 35 25 c1 = c2
MC13110a/b MC13111a/b 28 motorola analog ic device data if limiter and demodulator the limiting if amplifier typically has about 110 db of gain; the frequency response starts rolling off at 1.0 mhz. decoupling capacitors should be placed close to pins 31 and 32 to ensure low noise and stable operation. the if input impedance is 1.5 k w . this is a suitable match to 455 khz ceramic filters. figure 48. if limiter schematic lim out lim in limiter stage r pi c pi figure 49. limiter input impedance unit input impedance (r pi ) input impedance (c pi ) lim in 1538 w 15.7 pf figure 50. quadrature detector demodulator schematic q coil lim out 1 c 28 10 p r ext 22.1 k toko q coil 7mcs8128z the quadrature detector is coupled to the if with an external capacitor between pins 27 and 28. thus, the recovered signal level output is increased for a given bandwidth by increasing the capacitor. the external quadrature component may be either a lcr resonant circuit, which may be adjustable, or a ceramic resonator which is usually fixed tuned. (more on ceramic resonators later.) the bandwidth performance of the detector is controlled by the loaded q of the lc tank circuit (figure 50). the following equation defines the components which set the detector circuit's bandwidth: (1) r t = q x l , where r t is the equivalent shunt resistance across the lc tank. x l is the reactance of the quadrature inductor at the if frequency (x l = 2 p f l). the 455 khz if center frequency is calculated by: (2) f c = [2 p (l cp) 1/2 ] 1 where l is the parallel tank inductor. cp is the equivalent parallel capacitance of the parallel resonant tank circuit. the following is a design example for a detector at 455 khz and a specific loaded q: the loaded q of the quadrature detector is chosen somewhat less than the q of the if bandpass for margin. for an if frequency of 455 khz and an if bandpass of 20 khz, the if bandpass q is approximately 23; the loaded q of the quadrature tank is chosen slightly lower at 15. example: let the total external c = 180 pf. (note: the capacitance is the typical capacitance for the quad coil.) since the external capacitance is much greater than the internal device and pcb parasitic capacitance, the parasitic capacitance may be neglected. rewrite equation (2) and solve for l: l = (0.159) 2 /(c f c 2 ) l = 678 m h ; thus, a standard value is chosen: l = 680 m h (surface mount inductor) the value of the total damping resistor to obtain the required loaded q of 15 can be calculated from equation (1): r t = q(2 p f l) r t = 15(2 p )(0.455)(680) = 29.5 k w the internal resistance, r int at the quadrature tank pin 27 is approximately 100 k w and is considered in determining the external resistance, r ext which is calculated from: r ext = ((r t )(r int ))/(r int r t ) r ext = 41.8 k w ;thus, choose a standard value: r ext = 39 k w in figure 50, the r ext is chosen to be 22.1 k w . an adjustable quadrature coil is selected. this tank circuit represents one popular network used to match to the 455 khz carrier frequency. the output of the detector is represented as a ascurveo as shown in figure 52. the goal is to tune the inductor in the area that is most linear on the ascurveo (minimum distortion) to optimize the performance in terms of dc output level. the slope of the curve can also be adjusted by choosing higher or lower values of r ext . this will have an affect on the audio output level and bandwidth. as r ext is increased the detector output slope will decrease. the maximum audio output swing and distortion will be reduced and the bandwidth increased. of course, just the opposite is true for smaller r ext . a ceramic discriminator is recommended for the quadrature circuit in applications where fixed tuning is desired. the ceramic discriminator and a 5.6 k w resistor are placed from pin 27 to v cc . a 22 pf capacitor is placed from pin 28 to 27 to properly drive the discriminator. murata erie has designed a resonator for this part (cdbm455c48 for usa & a/p regions and cdbm450c48 for europe). this resonator has been designed specifically for the MC13110/111 family. figure 51 shows the schematic used to generate the ascurveo and waveform shown in figure 54 and 55.
MC13110a/b MC13111a/b 29 motorola analog ic device data figure 51. ceramic resonator demodulator schematic with murata cdbm450c48 c 28 390 p r ext 2.7 k ceramic resonator murata cdbm450c34 lim out 1 q coil (cdbm455c48 us; cdbm450c48 france) the ascurveo for the ceramic discriminator shown in figure 54 is centered around 450 khz. it is for the french application. the same resonator is also used for the us application and is centered around 455 khz. clearly, the ascurveso for the resonator and quad coil have very similar limiter outputs. as discussed previously, the slope of the ascurveo centered around the center frequency can be controlled by the parallel resistor, r ext . distortion, bandwidth, and audio output level will be affected. figure 52. scurve of limiter discriminator with quadrature coil 0.2 0.6 1.0 1.4 2.2 425 435 445 485 lim in, input frequency (khz) 1.8 455 465 475 det out, dc voltage (v) toko 7mcs8128z figure 53. typical limiter output waveform with quadrature coil if limiter and demodulation figure 54. scurve of limiter discriminator with ceramic resonator 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.7 440 442 444 446 448 460 lim in, input frequency (khz) 1.4 1.5 450 452 454 456 458 det out, dc voltage (v) murata cdbm450c48 1.6 figure 55. typical limiter output waveform with ceramic resonator ac voltage level (v) f = 455 khz vpp typ = 344 mv 0 1.0 t, time (ms) 600 400 200 800 ac voltage level (v) f = 450 khz vpp typ = 370 mv 0 1.0 t, time (ms) 600 400 200 800
MC13110a/b MC13111a/b 30 motorola analog ic device data rssi and carrier detect the received signal strength indicator (rssi) indicates the strength of the if level. the output is proportional to the logarithm of the if input signal magnitude. rssi dynamic range is typically 80 db. a 187 k w resistor to ground is provided internally to the ic. this internal resistor converts the rssi current to a voltage level at the arssio pin. to improve the rssi accuracy over temperature an internal compensated reference is used. figure 56 shows the rssi versus rf input. the slope of the curve is 16.5 mv/db. the carrier detect output (cd out) is an opencollector transistor output. an external pullup resistor of 100 k w will be required to bias this device. to form a carrier detect filter a capacitor needs to be connected from the rssi pin to ground. the carrier detect threshold is programmable through the mpu interface (see acarrier detect threshold programmingo in the serial interface section). the range can be scaled by connecting additional external resistance from the rssi pin to ground in parallel with the capacitor. from figure 57, the affect of an external resistor at rssi on the carrier detect level can be noticed. since there is hysteresis in the carrier detect comparator, one trip level can be found when the input signal is increased while the another one can be found when the signal is decreased. figure 58 represents the rssi ripple in relation to the rf input for different filtering capacitors at rssi. clearly, the higher the capacitor, the less the ripple. however, at low carrier detect thresholds, the ripple might supersede the hysteresis of the carrier detect. the carrier detect output may appear to be unstable. using a large capacitor will help to stabilize the rssi level, but rssi charge time will be affected. figure 59 shows this relationship. the user must decide on a compromise between the rssi ripple and rssi startup time. choose a 0.01 m f capacitor as a starting point. for low carrier detect threshold settings, a 0.047 m f capacitor is recommended. 60 rssi and carrier detect 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 120 100 80 60 40 20 0 mix 1 in, rf input (dbm) figure 56. typical rssi voltage level versus rf input rssi output (vdc) 90 80 70 50 40 30 20 0 100 1000 r rssi , load resistance (k w ) figure 57. carrier detect threshold versus external rssi resistor 10 decreasing signal limiter input mixer 1 input increasing signal decreasing signal increasing signal mix 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 11 120 110 100 90 80 70 60 mix 1 in, rf input (dbm) figure 58. rssi ripple versus rf input level for different rssi capacitors 0 5.0 10 15 20 25 35 0.01 0.10 c rssi , load capacitance ( m f) figure 59. rssi charge time versus capacitor value 30 rssi charge time (ms) 8.0 9.0 10 10 nf 22 nf 33 nf 47 nf 100 nf 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 rssi ripple (mvrms) 1 in, rf input (dbm)
MC13110a/b MC13111a/b 31 motorola analog ic device data rf system performance the sensitivity of the ic is typically 0.4 m vrms matched (single ended or differential) with no preamp. to achieve suitable system performance, a preamp and passive duplexer may be used. in production final test, each section of the ic is separately tested to guarantee its system performance in the specific application. the preamp and duplexer (differential, matched input) yields typically 115 dbm @ 12 db sinad sensitivity performance under full duplex operation. see figure 45 and 48. the duplexer is important to achieve full duplex operation without significant adesensingo of the receiver by the transmitter. the combination of the duplexer and preamp circuit should attenuate the transmitter power to the receiver by over 60 db. this will improve the receiver system noise figure without giving up too much imd performance. the duplexer may be a two piece unit offered by shimida, sansui, or toko products (designed for 25 channel ct0 cordless phone). the duplexer frequency response at the receiver port has a notch at the transmitter frequency band of about 35 to 40 db with a 2.0 to 3.0 db insertion loss at the receiver frequency band. the preamp circuit utilizes a tuned transformer at the output side of the amplifier. this transformer is designed to bandpass filter at the receiver input frequency while rejecting the transmitter frequency. the tuned preamp also improves the noise performance by reducing the bandwidth of the pass band and by reducing the second stage contribution of the 1st mixer. the preamp is biased such that it yields suitable noise figure and gain. the following matching networks have been used to obtain 12 db sinad sensitivity numbers: 1:5 15 1:5 15 figure 60. matching input networks differential match singleended match singleended 50 w mix 1 in 1 mix 1 in 2 mix 1 in 1 mix 1 in 2 mix 1 in 1 mix 1 in 2 rf in 1 rf in 1 rf in 1 360 680 39 39 49.9 w 0.01 0.01 the exact impedance looking into the rf in1 pin is displayed in the following table along with the sensitivity levels. figure 61. 12 db sinad sensitivity levels, us handset application channel 21 sensitivity (dbm) input impedance (dbm) differential matched 115.3 50.2 0.1j singleended match 114.8 50.2 0.1j singleended 50 w 100.1 50.2 0.1j the graphs in figures 64 to 69 are performance results based on evaluation board schematic (figure 138). this evaluation board did not use a duplexer or preamp stage. figure 62 is a summary of the rf performance and figure 63 contains the french rf performance summary. figure 62. rf performance summary for us applications MC13110a/MC13111a (fdev = 3.0 khz, fmod = 1.0 khz, 50 w ) parameter handset baseset unit sensitivity at 12 db sinad 100.1 100.1 dbm recovered audio 132 132 mvrms sinad @ 30 dbm 41.8 41.4 db thd @ 30 dbm 0.8 0.8 % s/n @ 30 dbm 78.2 78.5 db amrr @ 30 dbm 73.4 72.2 db rssi range >80 >80 db figure 63. rf performance summary for us french applications MC13110a/MC13111a (fdev = 1.5 khz, fmod = 1.0 khz, 50 w ) parameter handset baseset unit sensitivity at 12 db sinad 91 90.8 dbm recovered audio 89.8 90 mvrms sinad @ 30 dbm 42.1 44.3 db thd @ 30 dbm 0.8 0.8 % s/n @ 30 dbm 75.7 75.1 db amrr @ 30 dbm 56 84.7 db rssi range >80 >80 db
MC13110a/b MC13111a/b 32 motorola analog ic device data 110 90 70 50 30 10 120 100 80 60 40 20 0 s+n+d n+d amr n sa out, speaker amplifier output (dbv) mix 1 in 1 , first mixer input (dbm) 102 101 100 99 98 97 96 15913172125 12 db sinad (dbm) us channel numbers 0 10 20 30 40 50 60 70 80 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 120 100 80 60 40 20 0 sinad s/n rssi mix 1 in, rf input (dbm) figure 64. typical receiver performance parameters u.s. handset application channel 21 rssi output (v) sinad, s/n (db) 35 40 45 50 55 60 65 70 85 128 129 130 131 132 133 134 135 138 1357 911 25 sinad s/n amrr u.s. handset channel number figure 65. typical performance parameters over u.s. handset channel frequencies sa out, speaker amplifier output (mvrms) sinad, s/n, amrr (db) 80 75 13 15 17 19 21 23 136 137 sa out level 35 40 45 50 55 60 65 70 85 128 129 130 131 132 133 134 135 138 1357 911 25 sinad s/n amrr u.s. baseset channel number figure 66. typical performance parameters over u.s. baseset channel frequencies sa out, speaker amplifier output (mvrms) sinad, s/n, amrr (db) 80 75 13 15 17 19 21 23 136 137 sa out level rf system performance figure 67. typical receiver performance for us handset application channel 21 figure 68. 12 db sinad sensitivity over us handset application channels figure 69. 12 db sinad sensitivity over us baseset application channels 102 101 100 99 98 97 96 1 5 9 1317 2125 12 db sinad (dbm) us channel numbers
MC13110a/b MC13111a/b 33 motorola analog ic device data receive audio path the r x audio signal path begins at arx audio ino and goes through the ic to ae outo. the ar x audio ino, ascr outo, and ae ino pins are all accoupled. this signal path consists of filters; programmable r x gain adjust, r x mute, and volume control, and finally the expander. the typical maximum output voltage at ae outo should be approximately 0 dbv @ thd = 5.0% . figures 71 to 73 represent the receive audio path filter response. the filter response attenuation is very sharp above 3900 hz, which is the cutoff frequency. inband (audio), outofband, and ripple characteristics are also shown in these graphs. the group delay (figure 75) has a peak around 6.5 khz. this spike is formed by rapid change in the phase at the frequency. in practice this does not cause a problem since the signal is attenuated by at least 50 db. the output capability at ascr outo and ae outo are shown in figures 76, 77, and 78. the results were obtained by increasing the input level for 2.0% distortion at the outputs. in figure 70, noise data for the r x audio path is shown. at scr out, the noise level clearly rises when the scrambler is enabled. however, assuming a nominal output level of 20 dbv (100 mvrms) at the 0 db gain setting, the noise floor is more than 56 db below the audio signal. however, the noise data at e out and sa out is much more improved. speaker amp the speaker amp is an inverting railtorail operational amplifier. the noninverting input is connected to the internal vb reference. external resistors and capacitors are used to set the gain and frequency response. the asa ino input pin must be accoupled. the typical output voltage at asa outo is 2.6 v pp with a 130 w load. the speaker amp response is shown in figures 79 and 80. data amp comparator the data amp comparator is an inverting hysteresis comparator. its open collector output has an internal 100 k w pullup resistor. a band pass filter is connected between the adet outo pin and the ada ino pin with component values as shown in the application circuit schematic. the ada ino input signal needs to be accoupled, too. figure 70. r x path noise data receive scrambler receive gain (db) volume (db) scr_out (dbv) e_out (dbv) sa_out (dbv) off/on muted muted < 95 < 95 < 95 off 9.0 14 92 < 95 < 95 off 0 0 85 < 95 < 95 off 1.0 16 76 < 95 < 95 on (MC13110a/b) 9.0 14 85 < 95 < 95 on (MC13110a/b) 0 0 77 < 95 < 95 on (MC13110a/b) 10 16 66 < 95 < 95
MC13110a/b MC13111a/b 34 motorola analog ic device data e out , output voltage level (dbv) phase ( ) 40 5.0 100 180 100 5.0 100 10 100 0.5 100 10 e in , input voltage level (dbv) f, frequency (hz) f, frequency (hz) f, frequency (hz) voltage gain (db) figure 71. r x audio wideband frequency response f, frequency (hz) figure 72. r x audio inband frequency response figure 73. r x audio ripple response figure 74. r x audio inband phase response figure 75. r x audio inband group delay figure 76. r x audio expander response 135 5.0 90 15 0.3 45 0 25 0.1 45 90 0.1 0.3 135 180 55 0.5 110 5.0 1.0 15 25 45 0.1 55 65 0 1000 1000 10000 100000 10000 1000000 20 1000 1000 1000 10000 10000 10000 0 group delay (ms) 35 expander transfer distortion 10 30 50 90 70 45 f, frequency (hz) 35 35 30 25 15 10 5.0 distortion (%) 28 24 20 16 8.0 4.0 0 12 r x audio in to scr out v in = 20 dbv r x audio in to scr out v in = 20 dbv r x audio in to scr out v in = 20 dbv r x audio in to scr out v in = 20 dbv v , gain voltage gain (db) v , gain r x audio in to scr out v in = 20 dbv voltage gain (db) v , gain r x audio
MC13110a/b MC13111a/b 35 motorola analog ic device data scr out, output voltage level (dbv) 9.0 r x programmable volume level setting r x programmable gain control setting figure 77. r x audio maximum output voltage versus gain control setting figure 78. r x audio maximum output voltage versus volume setting 4.0 8.0 10 12 16 20 7.0 5.0 3.0 1.0 1.0 3.0 5.0 7.0 9.0 1.4 1.2 1.0 0.8 0.6 0.4 0 14 10 6.0 2.0 2.0 6.0 10 14 v cc = 3.6 v thd = 2% e out , output voltage level (dbv) 6.0 14 18 0.2 v cc = 3.6 v thd = 2% sa out, output voltage level(dbv) sa out, output voltage level (dbv) 1.8 sa in, input voltage level (dbv) figure 79. r x audio speaker amplifier drive sa in, input voltage level (dbv) figure 80. r x audio speaker amplifier distortion no load 130 w 1.4 0 25 15 5.0 0 0 0 0.8 0.8 1.6 2.4 2.8 1.6 2.4 3.2 3.2 620 w no load 620 w 1.6 1.2 1.0 0.8 0.6 0.4 0.2 20 10 0.4 1.2 2.0 2.8 0.4 1.2 2.0 130 w r x audio
MC13110a/b MC13111a/b 36 motorola analog ic device data transmit audio path this portion of the audio path goes from ac ino to at x outo. the ac ino pin will be accoupled. the audio transmit signal path includes automatic level control (alc) (also referred to as the compressor), t x mute, limiter, filters, and t x gain adjust. the alc provides asofto limiting to the output signal swing as the input voltage slowly increases. with this technique the gain is slightly lowered to help reduce distortion of the audio signal. the limiter section provides hard limiting due to rapidly changing signal levels, or transients. this is accomplished by clipping the signal peaks. the alc, t x mute, and limiter functions can be enabled or disabled via the mpu serial interface. the t x gain adjust can also be remotely controlled to set different desired signal levels. the typical maximum output voltage at at x outo should be approximately 0 dbv @ thd = 5.0%. figures 82 to 86 represent the transmit audio path filter response. the filter response attenuation, again, is very definite above 3800 hz. this is the filter cutoff frequency. inband (audio), wideband, and ripple characteristics are also shown in these graphs. the compressor transfer characteristics, shown in figure 87, has three different slopes. a typical compressor slope can be found between 55 and 15 dbv. here the slope is 2.0. at an input level above 15 dbv the automatic level control (alc) function is activated and prevents hard clipping of the output. the slope below 55 dbv input level is one. this is where the compressor curve ends. above 5.0 dbv the output actually begins to decrease and distort. this is due to supply voltage limitations. in figure 88 the alc function is off. here the compressor curve continues to increase above 15 dbv up to 4.0 dbv. the limiter begins to clip the output signal at this level and distortion is rapidly rising. similarly, figure 68 (alc and limiter off) shows to compressor transfer curve extending all the way up to the maximum output. finally, figure 90 through 93 show the t x out signal versus several combinations of alc and limiter selected. figure 81 is the noise data measured for the MC13110a/13111a. this data is for 0 db gain setting and 20 dbv (100 mvrms) audio levels. figure 81. t x path noise data transmit scrambler transmit gain (db) amp_out (dbv) t x _out (dbv) off/on muted muted < 95 off 9.0 < 95 83 off 0 < 95 74 off 10 < 95 64 on (MC13110a) 9.0 < 95 82 on (MC13110a) 0 < 95 73 on (MC13110a) 10 < 95 63 mic amp like the speaker amp the mic amp is also an inverting railtorail operational amplifier. the noninverting input terminal is connected to the internal vb reference. external resistors and capacitors are used to set the gain and frequency response. the at x ino input is accoupled.
MC13110a/b MC13111a/b 37 motorola analog ic device data 100 100 180 5.0 0.3 100 10 f, frequency (hz) f, frequency (hz) f, frequency (hz) f, frequency (hz) figure 82. t x audio wideband frequency response figure 83. t x audio inband frequency response figure 84. t x audio ripple response figure 85. t x audio inband phase response 10 30 50 70 100 0.1 0.1 0.3 0.6 0.7 5.0 15 25 35 55 135 45 45 135 180 100 1000 1000 10000 1000 1000 100000 10000 10000 1000000 10000 c in to t x out v in = 10 dbv c in to t x out v in = 10 dbv c in to t x out v in = 10 dbv 90 45 0.2 0 0.2 0.4 0.5 c in to t x out v in = 10 dbv phase ( ) 90 0 90 voltage gain (db) v , gain voltage gain (db) v , gain voltage gain (db) v , gain 0 20 40 60 80 t x audio out, output voltage level (dbv) 60 0 100 10 c in, input voltage level (dbv) group delay (ms) figure 86. t x audio inband group delay f, frequency (hz) figure 87. t x audio compressor response compressor 10 1.0 20 0 25 35 40 10 1000 10000 c in to t x out v in = 10 dbv t x 0.1 distortion alc on, limiter on or off 5.0 15 30 50 40 30 20 10 0 distortion ( % ) 4.0 2.0 0 3.0 1.0
MC13110a/b MC13111a/b 38 motorola analog ic device data 9.0 output level (mv) t, time ( m s) t, time ( m s) t, time ( m s) t x programmable gain control setting a 4.0 12 16 20 out, output voltage level (dbv) t x b c 8.0 7.0 5.0 3.0 1.0 1.0 3.0 5.0 7.0 9.0 a: alc off, limiter off b: alc off, limiter on c: alc on, limiter on or off v cc = 3.6 v output level (mv) output level (mv) limiter and alc off limiter on and alc off limiter on and alc on 0 200 mv/div 500 m s/div 200 mv/div 500 m s/div 200 mv/div 500 m s/div out, output voltage level (dbv) t x out, output voltage level (dbv) t x distortion (%) 4.0 2.0 0 3.0 1.0 distortion (%) 4.0 2.0 0 3.0 1.0 0 60 0 c in, input voltage level (dbv) c in, input voltage level (dbv) 5.0 40 10 15 20 30 40 50 50 40 30 20 10 0 10 40 30 10 0 20 alc off, limiter on distortion alc off, limiter off 10 60 25 35 5.0 10 15 20 25 30 35 compressor transfer compressor transfer distortion figure 88. t x audio compressor response figure 89. t x audio compressor response figure 90. t x audio maximum output voltage versus gain control setting figure 91. t x output audio response figure 92. t x output audio response figure 93. t x audio output response t x audio
MC13110a/b MC13111a/b 39 motorola analog ic device data pll synthesizer section pll frequency synthesizer general description figure 95 shows a simplified block diagram of the programmable universal dual phase locked loop (pll) designed into the MC13110a/b and MC13111a/b ic. this dual pll is fully programmable through the mcu serial interface and supports most country channel frequencies including usa (25 ch), spain, australia, korea, new zealand, u.k., netherlands, france, and china (see channel frequency tables in an1575, aworldwide cordless telephone frequencieso). the 2nd local oscillator and reference divider provide the reference frequency signal for the r x and t x pll loops. the programmed divider value for the reference divider is selected based on the crystal frequency and the desired r x and t x reference frequency values. for the u.k., additional divide by 25 and divide by 4 blocks are provided to allow for generation of the 1.0 khz and 6.2 khz reference frequencies. the 14bit r x counter is programmed for the desired first local oscillator frequency. the 14bit t x counter is programmed for the desired transmit channel frequency. all counters powerup to a set default state for usa channel #21 using a 10.24 mhz reference frequency crystal (see powerup default latch register state in the serial programmable interface section). to extend the sensitivity of the 1st lo for u.s. 25 channel operation, internal fixed capacitors can be connected to the tank circuit through microprocessor programmable control. when designing the external pll loop filters, it is recommended that the t x and r x phase detectors be considered as current drive type outputs. the loop filter control voltage must be 0.5 v away from either the positive or negative supply rail. pll i/o pin configurations the 2nd lo, r x and t x pll's, and mpu serial interface are powered by the internal voltage regulator at the apll v ref o pin. the apll v ref o pin is the output of a voltage regulator which is powered from the av cc audioo power supply pin. it is regulated by an internal bandgap voltage reference. therefore, the maximum input and output levels for most of the pll i/o pins (lo2 in, lo2 out, r x pd, t x pd, t x vco) is the regulated voltage at the apll v ref o pin. the esd protection diodes on these pins are also connected to apll v ref o. internal level shift buffers are provided for the pins (data, clk, en, clk out) which connect directly to the microprocessor. the maximum input and output levels for these pins is v cc . figure 94 shows a simplified schematic of the i/o pins. figure 94. pll i/o pin simplified schematics pll v ref (2.5 v) in i/o v cc audio (2.7 to 5.5 v) pll v ref (2.5 v) v cc audio (2.7 to 5.5 v) clk out pin data, clk and en pins lo 2 in, lo 2 out, r x pd, t x pd and t x vco pins out 2.0 m a pll loop control voltage range the control voltage for the t x and r x loop filters is set by the phase detector outputs which drive the external loop filters. the phase detectors are best considered to have a current mode type output. the output can have three states; ground, high impedance, and positive supply, which in this case is the voltage at apll v ref o. when the loop is locked the phase detector outputs are at high impedance. an exception of this state is for narrow current pulses, referenced to either the positive or negative supply rails. if the loop voltages get within 0.5 v of either rail the linear current output starts to degrade. the phase detector current source was not designed to operate at the supply rails. vco tuning range will also be limited by this voltage range the maximum loop control voltage is the apll v ref o voltage which is 2.5 v. if a higher loop control voltage range is desired, the apll v ref o pin can be pulled to a higher voltage. it can be tied directly to the v cc voltage (with suitable filter capacitors connected close to each pin). when this is done, the internal voltage regulator is automatically disabled. this is commonly used in the telephone base set where an external 5.0 v regulated voltage is available. it is important to remember, that if apll v ref o is tied to v cc and v cc is not a regulated voltage, the pll loop parameters and lockup time will vary with supply voltage variation. the phase detector gain constant, k pd , will not be affected if the apll v ref o is tied to v cc. figure 95. dual pll simplified block diagram 14b programmable r x counter 14b programmable t x counter 12b programmable reference counter 25 1 4 lo 2 in lo 2 out 1 2 t x pd 8 6 t x vco r x pd 4 lo 1 in 40 lo 1 out 41 t x phase detector (current output) r x phase detector (current output) lp loop filter t x ref r x ref u.k. base u.k. handset u.k. handset u.k. base v cap ctrl 42 1st lo lp loop filter t x vco programmable internal capacitor
MC13110a/b MC13111a/b 40 motorola analog ic device data loop filter characteristics lets consider the following discussion on loop filters. the fundamental loop characteristics, such as capture range, loop bandwidth, lockup time, and transient response are controlled externally by loop filtering. figure 96 is the general model for a phase lock loop (pll). phase detector (k pd ) filter (k f ) vco (k o ) fo divider (k n ) fi figure 96. pll model where: k pd = phase detector gain constant k f = loop filter transfer function k o = vco gain constant k n = divide ratio (1/n) fi = input frequency fo = output frequency fo/n = feedback frequency divided by n from control theory the loop transfer function can be represented as follows: a = k pd k f k o k n open loop gain k pd can be either expressed as being 2.5 v/4.0 p or 1.0 ma/2.0 p for the ct0 circuits. more details about performance of different type pll loops, refer to motorola application note an535. the loop filter can take the form of a simple low pass filter. a current output, type 2 filter will be used in this discussion since it has the advantage of improved step response, velocity, and acceleration. the type 2 low pass filter discussed here is represented as follows: from phase detector to vco r2 c2 c1 figure 97. loop filter with additional integrating element from figure 97, c apacitor c1 forms an additional integrator, providing the type 2 response, and filters the discrete current steps from the phase detector output. the function of the additional components r2 and c2 is to create a pole and a zero (together with c1) around the 0 db point of the open loop gain. this will create sufficient phase margin for stable loop operation. in figure 98, the open loop gain and the phase is displayed in the form of a bode plot. since there are two integrating functions in the loop, originating from the loopfilter and the vco gain, the open loop gain response follows a second order slope (40 db/dec) creating a phase of 180 degrees at the lower and higher frequencies. the filter characteristic needs to be determined such that it is adding a pole and a zero around the 0 db point to guarantee sufficient phase margin in this design (qp in figure 98). phase figure 98. bode plot of gain and phase in open loop condition a, open loop gain w p open loop gain q p 180 90 0 0 the open loop gain including the filter response can be expressed as: a openloop k pd k o (1 jw(r2c2) ) jwk n jw 1 jw r2c1c2 c1 c2 (1) the two time constants creating the pole and the zero in the bode plot can now be defined as: t1 r2c1c2 c1 c2 t2 r2c2 (2) by substituting equation (2) into (1), it follows: a openloop k pd k o t1 w 2 c1k n t2 1 jwt2 1 jwt1 (3) the phase margin (phase + 180) is thus determined by: q p arctan ( wt2 ) arctan ( wt1 ) (4) at w=w p , the derivative of the phase margin may be set to zero in order to assure maximum phase margin occurs at w p (see also figure 98). this provides an expression for w p : dq p dw 0 t2 1 ( wt2 ) 2 t1 1 ( wt1 ) 2 (5) w w p 1 t2t1 (6) or rewritten: t1 1 w p 2 t2 (7)
MC13110a/b MC13111a/b 41 motorola analog ic device data by substituting into equation (4), solve for t2: t2 tan q p 2 4 w p (8) by choosing a value for w p and q p , t1 and t2 can be calculated. the choice of q p determines the stability of the loop. in general, choosing a phase margin of 45 degrees is a good choice to start calculations. choosing lower phase margins will provide somewhat faster locktimes, but also generate higher overshoots on the control line to the vco. this will present a less stable system. larger values of phase margin provide a more stable system, but also increase locktimes. the practical range for phase margin is 30 degrees up to 70 degrees. the selection of w p is strongly related to the desired locktime. since it is quite complicated to accurately calculate lock time, a good first order approach is: t_lock 3 w p (9) equation (9) only provides an order of magnitude for lock time. it does not clearly define what the exact frequency difference is from the desired frequency and it does not show the effect of phase margin. it assumes, however, that the phase detector steps up to the desired control voltage without hesitation. in practice, such step response approach is not really valid. the two input frequencies are not locked. their phase maybe momentarily zero and force the phase detector into a high impedance mode. hence, the lock times may be found to be somewhat higher. in general, w p should be chosen far below the reference frequency in order for the filter to provide sufficient attenuation at that frequency. in some applications, the reference frequency might represent the spacing between channels. any feedthrough to the vco that shows up as a spur might affect adjacent channel rejection. in theory, with the loop in lock, there is no signal coming from the phase detector. but in practice leakage currents will be supplied to both the vco and the phase detector. the external capacitors may show some leakage, too. hence, the lower w p , the better the reference frequency is filtered, but the longer it takes for the loop to lock. as shown in figure 98, the open loop gain at w p is 1 (or 0 db), and thus the absolute value of the complex open loop gain as shown in equation (3) solves c1: c1 k pd k o t1 w 2 k n t2 1 w p t2 2 1 w p t1 2 (10) with c1 known, and equation (2) solve c2 and r2 : c2 c1 t2 t1 1 (11) r2 t2 c2 (12) the vco gain is dependent on the selection of the external inductor and the frequency required. the free running frequency of the vco is determined by: f 1 2 lc t (13) in which l represents the external inductor value and c t represents the total capacitance (including internal capacitance) in parallel with the inductor. the vco gain can be easily calculated via the internal varicap transfer curve shown below. figure 99. varicap capacitance versus control voltage 0 15 , capacitance (pf) 14 12 13 11 10 9.0 8.0 7.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cap as can be derived from figure 99, the varicap capacitance changes 1.3 pf over the voltage range from 1.0 v to 2.0 v: cvar 1.3 pf v (14) combining (13) with (14) the vco gain can be determined by: k o 1 jw 1 2 l c t cvar 2 1 2 l c t cvar 2
(15) although the basic loopfilter previously described provides adequate performance for most applications, an extra pole may be added for additional reference frequency filtering. given that the channel spacing in a ct0 telephone set is based on the reference frequency, and any feedthrough to
MC13110a/b MC13111a/b 42 motorola analog ic device data the first lo may effect parameters like adjacent channel rejection and intermodulation. figure 100 shows a loopfilter architecture incorporating an additional pole. from phase detector to vco r2 c2 c1 figure 100. loop filter with additional integrating element c3 r3 for the additional pole formed by r3 and c3 to be efficient, the cutoff frequency must be much lower than the reference frequency. however, it must also be higher than w p in order not to compromise phase margin too much. the following equations were derived in a similar manner as for the basic filter previously described. similarly, it can be shown: a openloop k pd k o k n w 2 ( c1 c2 c3 ) w 2 c1c2c3r2r3 1 jwt2 1 jwt1 (16) in which: t1 ( c1 c2 ) t2 ( c1c2 ) t3 c1 c2 c3 w 2 c1t2t3 (17) t2 r2c2 t3 r3c3 (19) (18) from t1 it can be derived that: c2 ( t1 t2 ) c3 c1 t2 t3 t1 w 2 t1t2t3 t3 t1 (20) in analogy with (10), by forcing the loopgain to 1 (0 db) at w p , we obtain: c1 ( t1 t2 ) c2t3 c3t2 k pd k o k n w p 2 1 w p t2 2 1 w p t1 2 (21) solving for c1: c1 ( t2 t1 ) t3c3 ( t3 t1 ) t2c3 ( t3 t1 ) k pd k o t1 w p 2 k n 1 w p t2 2 1 w p t1 2 ( t3 t1 ) t2 ( t3 t1 ) t3 t2 t3 t1 w p 2 t1t2t3 t3 (22) by selecting w p via (9), the additional time constant expressed as t3, can be set to: t3 1 kw p (23)
MC13110a/b MC13111a/b 43 motorola analog ic device data the kfactor shown determines how far the additional pole frequency will be separated from w p . selecting too small of a kfactor, the equations may provide negative capacitance or resistor values. too large of a kfactor may not provide the maximum attenuation. by selecting r3 to be 100 k w , c3 becomes known and c1 and c2 can be solved from the equations. by using equations (8) and (7), time constants t2 and t1 can be derived by selecting a phase margin. finally, r2 follows from t2 and c2. the following pages, the loopfilter components are determined for both handset and baseset the us application based on the equations described. choose k to be approximately five times w p (5.0w p ). in an application, w p is chosen to be 20 times less than the reference frequency of 5.0 khz and the phase margin has been set to 45 degrees. this provides a lock time according to (9) of about 2.0 ms (order of magnitude). with the adjacent channels spaced at least 15 khz away, reference feedthrough at w p will not be directly disastrous but still, the additional pole may be added in the loopfilter design for added safety. in an application, w p is chosen to be 20 times less than the reference frequency of 5.0 khz and the phase margin has been set to 45 degrees. this provides a lock time according to (9) of about 2.0 ms (order of magnitude). with the adjacent channels spaced at least 15 khz away, reference feedthrough at w p will not be directly disastrous but still, the additional pole may be added in the loopfilter design for added safety. open loop gain (db) figure 101. open loop response handset us with selected values f, frequency (hz) phase margin 100 1000 10000 100000 1000000 80 40 0 40 80 0 20 40 60 80 phase margin (degrees) loop gain from phase detector to vco 22 k .068 6800 1000 100 k figure 102. open loop response baseset us with selected values from phase detector to vco 18 k .082 8200 1000 100 k open loop gain (db) f, frequency (hz) phase margin 100 1000 10000 100000 1000000 80 40 0 40 80 0 20 40 60 80 phase margin (degrees) loop gain figure 103. handset us conditions l = 470 uh f ref = 5.0 khz rf = 46.77 mhz q p = 45 degrees vco center = 36.075 mhz w p = w ref / 20 radians results equations select k pd = 159.2 ua/rad k vco = 3.56 mrad/v (14), (15) t2 = 1540 m s (8) t1 = 264 m s (7) t3 = 91 m s with k = 7 c1 = 7.6 nf (21) c1 = 6.8 nf c2 = 70.9 nf (20) c2 = 68 nf r2 = 21.7 k w (18) r2 = 22 k w r3 = 100 k w choose: r3 = 100 k w c3 = 909.5 pf (19) c3 = 1 nf figure 104. baseset us conditions l = 470 uh f ref = 5.0 khz rf = 49.83 mhz q p = 45 degrees vco center = 39.135 mhz w p = w ref / 20 radians results equations select k pd = 159.2 ua/rad k vco = 4.54 mrad/v (14), (15) t2 = 1540 m s (8) t1 = 264 m s (7) t3 = 91 m s with k = 7 c1 = 9.1 nf (21) c1 = 8.2 nf c2 = 83.5 nf (20) c2 = 82 nf r2 = 18.4 k w (18) r2 = 18 k w r3 = 100 k w choose: r3 = 100 k w c3 = 909.5 pf (19) c3 = 1 nf
MC13110a/b MC13111a/b 44 motorola analog ic device data serial programmable interface microprocessor serial interface the data, clock, and enable (adatao, aclko, and aeno respectively) pins provide a mpu serial interface for programming the reference counters, the transmit and receive channel divide counters, the switched capacitor filter clock counter, and various other control functions. the adatao and aclko pins are used to load data into the MC13111a/b shift register (figure 109). figure 105 shows the timing required on the adatao and aclko pins. data is clocked into the shift register on positive clock transitions. figure 105. data and clock timing requirement data, clk, en data clk t sudc t r t f 50% 50% t h 10% 90% after data is loaded into the shift register, the data is latched into the appropriate latch register using the aeno pin. this is done in two steps. first, an 8bit address is loaded into the shift register and latched into the 8bit address latch register. then, up to 16bits of data is loaded into the shift register and latched into the data latch register. it is specified by the address that was previously loaded. figure 106 shows the timing required on the en pin. latching occurs on the negative en transition. figure 106. enable timing requirement clk en t suec 50% 50% 50% t rec previous data latched last clock first clock 50% the state of the aeno pin when clocking data into the shift register determines whether the data is latched into the address register or a data register. figure 107 shows the address and data programming diagrams. in the data programming mode, there must not be any clock transitions when aeno is high. the clock can be in a high state (default high) or a low state (default low) but must not have any transitions during the aeno high state. the convention in these figures is that latch bits to the left are loaded into the shift register first. a minimum of four aclko rising edge transition must occur before a negative aeno transition will latch data or an address into a register. figure 107. microprocessor interface programming mode diagrams data latch 8bit address en data en address register programming mode 16bit data data register programming mode latch latch msb msb lsb lsb the mpu serial interface is fully operational within 100 m s after the power supply has reached its minimum level during powerup (see figure 108). the mpu interface shift registers and data latches are operational in all four power saving modes; inactive, standby, r x , and active modes. data can be loaded into the shift registers and latched into the latch registers in any of the operating modes. figure 108. microprocessor serial interface powerup delay v cc t pumpu 2.7 v data, clk, en
MC13110a/b MC13111a/b 45 motorola analog ic device data data registers figure 109 shows the data latch registers and addresses which are used to select each of each registers. latch bits to the left (msb) are loaded into the shift register first. the lsb bit must always be the last bit loaded into the shift register. bits proceeding the register must be a0'so as shown. powerup defaults for data registers when the ic is first powered up, all latch registers are initialized to a defined state. the device is initially placed in the r x mode with all mutes active. the reference counter is set to generate a 5.0 khz reference frequency from a 10.24 mhz crystal. the switched capacitor filter clock counter is set properly for operation with a 10.24 mhz crystal. the t x and r x counter registers are set for usa handset channel frequency, number 21 (channel 6 for previous fcc 10 channel band). figure 110 shows the initial powerup states for all latch registers. 6. (00000110) scf clock dividers latch (MC13111a/b only) 0 6b switched capacitor filter clock counter latch 4b voltage reference adjust msb lsb msb lsb 3b low battery detect threshold select 00 figure 109. microprocessor interface data latch registers 14b t x counter msb lsb 1. (00000001) 2. (00000010) 3. (00000011) 4. (00000100) 5. (00000101) 6. (00000110) latch address t x counter latch r x counter latch reference counter latch mode control latch gain control latch scf clock dividers latch (MC13110a/b only) 12b reference counter msb lsb u.k. bs select stdby mode 4b vol control r x mode t x mute r x mute sp mute 5b t x gain control 5b r x gain control 5b cd threshold control u.k. hs select 0 alc disable mpu clk 2 limiter disable clk disable 0 0 0 0 0 6b switched capacitor filter clock counter latch 4b voltage reference adjust msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb 0 mpu clk 1 mpu clk 0 3b low battery detect threshold select 14b r x counter msb lsb 0 ip3 increase t x sbl bypass 7. (00000111) auxillary latch 0 0 0 0 0 0 0 0 0 3b test mode 4b 1st lo capacitor selection r x sbl bypass
MC13110a/b MC13111a/b 46 motorola analog ic device data figure 110. latch register powerup defaults ri c msb lsb register count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t x 9966 1 0 0 1 1 0 1 1 1 0 1 1 1 0 r x 7215 0 1 1 1 0 0 0 0 1 0 1 1 1 1 ref 2048 0 0 1 0 0 0 0 0 0 0 0 0 0 0 mode n/a 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 gain n/a 0 1 1 1 1 0 1 1 1 1 1 0 1 0 0 scf (MC13110a/b) 31 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 scf (MC13111a/b) 31 0 0 0 0 1 1 1 0 1 1 1 1 1 aux n/a 0 0 0 0 0 0 0 note: 12. bits 6 and 7 in the scf latch register are odon't careso for the MC13111a/b since this part does not have a scrambler. t x and r x counter registers the 14 bit t x and r x counter registers are used to select the transmit and receive channel frequencies. in the r x counter there is an aip3 increaseo bit that allows the ability to trade off increased receiver mixer performance versus reduced power consumption. with aip3 increaseo = <1>, there is about a 10 db improvement in 1 db compression and 3rd order intercept for both the 1st and 2nd mixers. however, there is also an increase in power supply current of 1.3 ma. the powerup default for the MC13111a/b is aip3 increaseo = <0>. the register bits are shown in figure 111. reference counter register reference counter figure 113 shows how the reference frequencies for the r x and t x loops are generated. all countries except the u.k. require that the t x and r x reference frequencies be identical. in this case, set au.k. base selecto and au.k. handset selecto bits to a0o. then the fixed divider is set to a1o and the t x and r x reference frequencies will be equal to the crystal oscillator frequency divided by the programmable reference counter value. the u.k. is a special case which requires a different reference frequency value for t x and r x . for u.k. base operation, set au.k. base selecto to a1o. for u.k. handset operation, set au.k. handset selecto to a1o. the netherlands is also a special case. a 2.5 khz reference frequency is used for both the t x and r x reference and the total divider value required is 4096. this is larger than the maximum divide value available from the 12bit reference divider (4095). in this case, set au.k. base selecto to a1o and set au.k. handset selecto to a1o. this will give a fixed divide by 4 for both the t x and r x reference. then set the reference divider to 1024 to get a total divider of 4096. figure 111. r x and t x counter register latch bits 14b t x counter msb lsb 14b r x counter msb lsb t x counter latch 0 0 ip3 increase 0 r x counter latch figure 112. reference counter register 12b ref counter msb lsb u.k. handset select u.k. base select 0 0
MC13110a/b MC13111a/b 47 motorola analog ic device data figure 113. reference counter register programming mode 0 0 1 1 0 1 0 1 1 25 4 4 1 4 25 4 lo 2 out t x reference frequency 12b programmable reference counter 25 1.0 4.0 lo 2 in r x reference frequency u.k. base u.k. handset u.k. handset u.k. base u.k. handset select u.k. base select lo 2 t x divider value r x divider value application all but u.k. and netherlands u.k. base set u.k. hand set netherlands base and hand set figure 114. reference frequency and divider values MC13110a/b MC13111a/b reference u.k. base/ sc filter sc filter scrambler scrambler crystal divider handset reference clock clock modulation modulation frequency value divider frequency divider frequency divider frequency 10.24 mhz 2048 1 5.0 khz 31 165.16 khz 40 4.129 khz 10.24 mhz 1024 4 5.0 khz 31 165.16 khz 40 4.129 khz 11.15 mhz 2230 1 5.0 khz 34 163.97 khz 40 4.099 khz 12.00 mhz 2400 1 5.0 khz 36 166.67 khz 40 4.167 khz 11.15 mhz 1784 1 6.25 khz 34 163.97 khz 40 4.099 khz 11.15 mhz 446 4 6.25 khz 34 163.97 khz 40 4.099 khz 11.15 mhz 446 25 1.0 khz 34 163.97 khz 40 4.099 khz figure 115. mode control register stdby mode 4b volume control r x mode t x mute r x mute sp mute alc disable limiter disable clk disable 0 mpu clk 1 mpu clk 0 mpu clk 2 reference frequency selection the alo 2 ino and alo 2 outo pins form a reference oscillator when connected to an external parallelresonant crystal. the reference oscillator is also the second local oscillator for the rf receiver. figure 114 shows the relationship between different crystal frequencies and reference frequencies for cordless phone applications in various countries. alo 2 ino may also serve as an input for an externally generated reference signal which is accoupled. the switched capacitor filter 6bit programmable counter must be programmed for the crystal frequency that is selected since this clock is derived from the crystal frequency and must be held constant regardless of the crystal that is selected. the actual switched capacitor clock divider ratio is twice the programmed divider ratio due to the a fixed divide by 2.0 after the programmable counter. the scrambler mixer modulation frequency is the switched capacitor clock divided by 40 for the MC13110a/b. mode control register the power saving modes; mutes, disables, volume control, and microprocessor clock output frequency are all set by the mode control register. operation of the control register is explained in figures 115 through 119. figure 116. mute and disable control bit descriptions alc disable 1 0 automatic level control disabled normal operation t x limiter disable 1 0 t x limiter disabled normal operation clock disable (MC13110a/111a) 1 0 mpu clock output disabled normal operation clock disable (MC13110b/111b) 1 0 don't care normal operation t x mute 1 0 transmit channel muted normal operation r x mute 1 0 receive channel muted normal operation sp mute 1 0 speaker amp muted normal operation
MC13110a/b MC13111a/b 48 motorola analog ic device data power saving operating modes when the MC13110a/b or MC13111a/b are used in a handset, it is important to conserve power in order to prolong battery life. there are five modes of operation for the MC13110a/MC13111a; active, r x , standby, interrupt, and inactive. the MC13110b/MC13111b has three modes of operation. they are active, r x , and standby. in the active mode, all circuit blocks are powered. in the r x mode, all circuitry is powered down except for those circuit sections needed to receive a transmission from the base. in the standby and interrupt modes, all circuitry is powered down except for the circuitry needed to provide the clock output for the microprocessor. in the inactive mode, all circuitry is powered down except the mpu serial interface. latch memory is maintained in all modes. all mode functions are the same for the MC13110b/MC13111b, except that there is no inactive mode. with the bo version the mpu clock is always running so that there can never be a register reset if the memory is disturbed. figure 118 shows the control register bit values for selection of each power saving mode and figure 118 shows the circuit blocks which are powered in each of these operating modes. figure 117. power saving mode selection stdby mode bit r x mode bit acd out/ hardware interrupto pin power saving mode MC13110a/MC13111a 0 0 x active 0 1 x r x 1 0 x standby 1 1 1 or high impedance inactive 1 1 0 interrupt MC13110b/MC13111b [note 14] 0 0 x active 0 1 x r x 1 x x standby 1 1 0 interrupt notes : 13. axo is a don't care 14. mpu clock out is oalways ono figure 118. circuit blocks powered during power saving modes ci i bl k MC13110a/MC13111a ci i bl k MC13110b/MC13111b circuit blocks active r x standby inactive apll v ref o regulated voltage x x x 1 x 1, 2 mpu serial interface x x x x 2 2nd lo oscillator x x x mpu clock output x x x rf receiver and 1st lo vco x x r x pll x x carrier detect x x data amp x x low battery detect x x t x pll x r x and t x audio paths x notes: 15. in standby and inactive modes, apll v ref o remains powered but is not regulated. it will fluctuate with v cc . 16. there is no inactive mode for MC13110b/MC13111b. power saving application option 1 (MC13110b and MC13111b only) when the handset is in standby, power can be reduced by entering a alow powero mode and periodically switching to asniffo mode to check for incoming calls. figure 119. shows an application where the aclk outo pin provides the clock for the mpu. in this application, the 2nd lo and mpu clock run continuously. the mpu maintains control at all times and sets the timing for transitions into the asniffo mode. power is saved in the low power mode by putting the MC13110b/MC13111b into its astandbyo mode. only the 2nd lo and mpu clock divider are active. by programming the mpu clock divider to a large divide value of 20, 80, or 312.5 this will reduce the mpu clock frequency and save power in the mpu.
MC13110a/b MC13111a/b 49 motorola analog ic device data power saving application option 2 (MC13110a and MC13111a only) in some handset applications it may be desirable to power down all circuitry including the microprocessor (mpu). first put the MC13110a/MC13111a into the inactive mode. this turns off the mpu clock output (see figure 120) and disables the microprocessor. once a command is given to switch the ic into an ainactiveo mode, the mpu clock output will remain active for a minimum of one reference counter cycle (about 200 m s) and up to a maximum of two reference counter cycles (about 400 m s). this is performed in order to give the mpu adequate time to power down. an external timing circuit should be used to initiate the turnon sequence. the acd outo pin has a dual function. in the active and r x modes it performs the carrier detect function. in the standby and inactive modes the carrier detect circuit is disabled and the acd outo pin is in a ahigho state, because of an external pullup resistor. in the inactive mode, the acd outo pin is the input for the hardware interrupt function. when the acd outo pin is pulled alowo, by the external timing circuit, the ic switches from the inactive to the interrupt mode. thereby turning on the mpu clock output. the mpu can then resume control of the ic. the acd outo pin must remain low until the mpu changes the operating mode from interrupt to standby, active, or r x modes. figure 119. power saving application option 1 timer mpu clk divider clk in spi port clk out spi port lo 2 out lo 2 in MC13110b MC13111b microprocessor mode mpu timer mpu clock out alow powero asniffo standby mode r x mode 32.8, 128 or 512 khz 4.0 mhz
MC13110a/b MC13111a/b 50 motorola analog ic device data figure 120. power saving application option 2 (MC13110a/MC13111a only) mpu clk divider clk in spi port clk out spi port lo 2 out lo 2 in MC13110a/ MC13111a microprocessor cd out/ hw interrupt interrupt external timer v cc mode en cd out/hardware interrupt mpu clock out cd out low delay after mpu selects inactive mode to when cd turns off. cd turns off external timer pulls pin low mpu initiates mode change timer output disabled mpu initiates inactive mode ampu clock outo remains active for a minimum of one count of reference counter after acd out/hardware interrupto pin goes high active/r x inactive interrupt standby/r x /active mpu aclk outo divider programming the aclk outo signal is derived from the second local oscillator. it can be used to drive a microprocessor (mpu) clock input. this will eliminate the need for a separate crystal to drive the mpu, thus reducing system cost. figure 121 shows the relationship between the second lo crystal frequency and the clock output for each divide value. figure 122 shows the aclk outo register bit values. with a 10.24 mhz crystal, the divide by 312.5 gives the same clock frequency as a clock crystal and allows the mpu to display the time on a lcd display without additional external components. figure 121. clock output values cr y stal clock output divider crystal frequency 2 2.5 3 4 5 20 80 312.5 10.24 mhz 5.120 mhz 4.096 mhz 3.413 mhz 2.560 mhz 2.048 mhz 512 khz 128 khz 32.768 khz 11.15 mhz 5.575 mhz 4.460 mhz 3.717 mhz 2.788 mhz 2.230 mhz 557 khz 139 khz 35.680 khz 12.00 mhz 6.000 mhz 4.800 mhz 4.000 mhz 3.000 mhz 2.400 mhz 600 khz 150 khz 38.400 khz
MC13110a/b MC13111a/b 51 motorola analog ic device data figure 122. clock output divider mpu clk bit #2 mpu clk bit #1 mpu clk bit #0 clk out divider value 0 0 0 2 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 2.5 1 0 1 20 1 1 0 80 1 1 1 312.5 mpu aclk outo powerup default divider value the powerup default divider value is adivide by 5o. this provides a mpu clock of about 2.0 mhz after initial powerup. the reason for choosing a relatively low clock frequency at initial powerup is because some microprocessors operate using a 3.0 v power supply and have a maximum clock frequency of 2.0 mhz. after initial powerup, the mpu can change the clock divider value and set the clock to the desired operating frequency. special care was taken in the design of the clock divider to insure that the transition between one clock divider value and another is asmootho (i.e. there will be no narrow clock pulses to disturb the mpu). mpu aclk outo radiated noise on circuit board the clock line running between the MC13110a/b or MC13111a/b and the microprocessor has the potential to radiate noise. problems in the system can occur, especially if the clock is a square wave digital signal with large high frequency harmonics. in order to minimize the radiated noise, a 1000 w resistor is included onchip in series with the aclk outo output driver. a small capacitor or inductor with a capacitor can be connected to the aclk outo line on the pcb to form a one or two pole low pass filter. this filter should significantly reduce noise radiated by attenuating the high frequency harmonics on the signal line. the filter can also be used to attenuate the signal level so that it is only as large as required by the mpu clock input. to further reduce radiated noise, the pcb signal trace length should be kept to a minimum. volume control programming the volume control adjustable gain block can be programmed in 2 db gain steps from 14 db to +16 db. the powerup default value for the MC13110a/b and MC13111a/b is 0 db. (see figure 123) figure 123. volume control volume control bit #3 volume control bit #2 volume control bit #1 volume control bit #0 volume control # gain/attenuation amount 0 0 0 0 0 14 db 0 0 0 1 1 12 db 0 0 1 0 2 10 db 0 0 1 1 3 8 db 0 1 0 0 4 6 db 0 1 0 1 5 4 db 0 1 1 0 6 2 db 0 1 1 1 7 0 db 1 0 0 0 8 2 db 1 0 0 1 9 4 db 1 0 1 0 10 6 db 1 0 1 1 11 8 db 1 1 0 0 12 10 db 1 1 0 1 13 12 db 1 1 1 0 14 14 db 1 1 1 1 15 16 db
MC13110a/b MC13111a/b 52 motorola analog ic device data gain control register the gain control register contains bits which control the t x voltage gain, r x voltage gain, and carrier detect threshold. operation of these latch bits are explained in figures 124, 125 and 126. t x and r x gain programming the t x and r x audio signal paths each have a programmable gain block. if a t x or r x voltage gain, other than the nominal powerup default, is desired, it can be programmed through the mpu interface. alternately, these programmable gain blocks can be used during final test of the telephone to electronically adjust for gain tolerances in the telephone system (see figure 125). in this case, the t x and r x gain register values should be stored in rom during final test so that they can be reloaded each time the ic is powered up. figure 124. gain control latch bits 5b t x gain control 5b r x gain control 5b cd threshold control 0 figure 125. t x and r x gain control gain control bit #4 gain control bit #3 gain control bit #2 gain control bit #1 gain control bit #0 gain control # gain/attenuation amount <6 9 db 0 0 1 1 0 6 9 db 0 0 1 1 1 7 8 db 0 1 0 0 0 8 7 db 0 1 0 0 1 9 6 db 0 1 0 1 0 10 5 db 0 1 0 1 1 11 4 db 0 1 1 0 0 12 3 db 0 1 1 0 1 13 2 db 0 1 1 1 0 14 1 db 0 1 1 1 1 15 0 db 1 0 0 0 0 16 1 db 1 0 0 0 1 17 2 db 1 0 0 1 0 18 3 db 1 0 0 1 1 19 4 db 1 0 1 0 0 20 5 db 1 0 1 0 1 21 6 db 1 0 1 1 0 22 7 db 1 0 1 1 1 23 8 db 1 1 0 0 0 24 9 db 1 1 0 0 1 25 10 db >25 10 db
MC13110a/b MC13111a/b 53 motorola analog ic device data carrier detect threshold programming the acd outo pin gives an indication to the microprocessor if a carrier signal is present on the selected channel. the nominal value and tolerance of the carrier detect threshold is given in the carrier detect specification section of this document. if a different carrier detect threshold value is desired, it can be programmed through the mpu interface as shown in figure 126 below. alternately, the carrier detect threshold can be electronically adjusted during final test of the telephone to reduce the tolerance of the carrier detect threshold. this is done by measuring the threshold and then by adjusting the threshold through the mpu interface. in this case, it is necessary to store the carrier detect register value in rom so that the cd register can be reloaded each time the combo ic is powered up. if a preamp is used before the first mixer it may be desirable to scale the carrier detect range by connecting an external resistor from the arssio pin to ground. the internal resistor is 187 k w . figure 126. carrier detect threshold control cd bit #4 cd bit #3 cd bit #2 cd bit #1 cd bit #0 cd control # carrier detect threshold 0 0 0 0 0 0 20 db 0 0 0 0 1 1 19 db 0 0 0 1 0 2 18 db 0 0 0 1 1 3 17 db 0 0 1 0 0 4 16 db 0 0 1 0 1 5 15 db 0 0 1 1 0 6 14 db 0 0 1 1 1 7 13 db 0 1 0 0 0 8 12 db 0 1 0 0 1 9 11 db 0 1 0 1 0 10 10 db 0 1 0 1 1 11 9 db 0 1 1 0 0 12 8 db 0 1 1 0 1 13 7 db 0 1 1 1 0 14 6 db 0 1 1 1 1 15 5 db 1 0 0 0 0 16 4 db 1 0 0 0 1 17 3 db 1 0 0 1 0 18 2 db 1 0 0 1 1 19 1 db 1 0 1 0 0 20 0 db 1 0 1 0 1 21 1 db 1 0 1 1 0 22 2 db 1 0 1 1 1 23 3 db 1 1 0 0 0 24 4 db 1 1 0 0 1 25 5 db 1 1 0 1 0 26 6 db 1 1 0 1 1 27 7 db 1 1 1 0 0 28 8 db 1 1 1 0 1 29 9 db 1 1 1 1 0 30 10 db 1 1 1 1 1 31 11 db
MC13110a/b MC13111a/b 54 motorola analog ic device data clock divider/voltage adjust register this register controls the divider value for the programmable switched capacitor filter clock divider, the low battery detect threshold select, the voltage reference adjust, and the scrambler bypass mode (MC13110a/b only). operation is explained in figures 127 through 134. the t x and r x audio bits are don't cares for either the MC13111a or the MC13111b device. however, for the MC13110a/b, these bits are defined. figure 129 describes the operation. note the powerup default bit is set to <0>, which is the scrambler bypass mode. low battery detect the low battery detect circuit can be operated in programmable and nonprogrammable threshold modes. the nonprogrammable threshold mode is only available in the 52 qfp package. in this mode, there are two low battery detect comparators and the threshold values are set by external resistor dividers which are connected to the ref1 and ref2 pins. in the programmable threshold mode, several different threshold levels may be selected through the alow battery detect threshold registero as shown in figure 128. the poweron default value for this register is <0,0,0> and is the nonprogrammable mode. figure 130 shows equivalent schematics for the programmable and nonprogrammable operating modes. figure 127. clock divider/voltage adjust latch bits 00 6b switched capacitor filter clock counter latch 4b voltage reference adjust 3b low battery detect threshold select 0 msb msb lsb lsb (MC13111a/b) t x sbl bypass r x sbl bypass 6b switched capacitor filter clock counter latch 4b voltage reference adjust 3b low battery detect threshold select 0 msb msb lsb lsb (MC13110a/b) figure 128. low battery detect threshold selection low battery detect threshold select bit #2 low battery detect threshold select bit #1 low battery detect threshold select bit #0 select # operating mode nominal low battery detect threshold value (v) 0 0 0 0 nonprogrammable n/a 0 0 1 1 programmable 2.850 0 1 0 2 programmable 2.938 0 1 1 3 programmable 3.025 1 0 0 4 programmable 3.200 1 0 1 5 programmable 3.288 1 1 0 6 programmable 3.375 1 1 1 7 programmable 3.463 note: 17. nominal threshold value is before electronic adjustment. figure 129. MC13110a/b bypass mode bit description (MC13110a/b only) t x scrambler bypass 1 0 t x scrambler postmixer lpf and mixer bypassed normal operation with t x scrambler r x scrambler bypass 1 0 r x scrambler postmixer lpf and mixer bypassed normal operation r x scrambler
MC13110a/b MC13111a/b 55 motorola analog ic device data figure 130. low battery detect equivalent schematics ref2 ref 1 vb 50 51 52 bd2 out bd1 out 16 14 v ref nonprogrammable threshold mode: 52qfp package vb 47 v cc audio bd out 21 14 v ref programmable threshold mode: 48lqfp package vb 52 v cc audio bd2 out 23 16 v ref programmable threshold mode: 52qfp package
MC13110a/b MC13111a/b 56 motorola analog ic device data voltage reference adjustment an internal 1.5 v bandgap voltage reference provides the voltage reference for the abd 1 outo and abd 2 outo low battery detect circuits, the apll v ref o voltage regulator, the av b o reference, and all internal analog ground references. the initial tolerance of the bandgap voltage reference is 6%. the tolerance of the internal reference voltage can be improved to 1.5% through mpu serial interface programming. during final test of the telephone, the battery detect threshold is measured. then, the internal reference voltage value is adjusted electronically through the mpu serial interface to achieve the desired accuracy level. the voltage reference register value should be stored in rom during final test so that it can be reloaded each time the MC13110a/b or MC13111a/b is powered up (see figure 131). figure 131. bandgap voltage reference adjustment v ref adj. bit #3 v ref adj. bit #2 v ref adj. bit #1 v ref adj. bit #0 v ref adj. # v ref adj. amount 0 0 0 0 0 9.0% 0 0 0 1 1 7.8% 0 0 1 0 2 6.6% 0 0 1 1 3 5.4% 0 1 0 0 4 4.2% 0 1 0 1 5 3.0% 0 1 1 0 6 1.8% 0 1 1 1 7 0.6% 1 0 0 0 8 +0.6 % 1 0 0 1 9 +1.8 % 1 0 1 0 10 +3.0 % 1 0 1 1 11 +4.2 % 1 1 0 0 12 +5.4 % 1 1 0 1 13 +6.6 % 1 1 1 0 14 +7.8 % 1 1 1 1 15 +9.0 % switched capacitor filter clock programming a block diagram of the switched capacitor filter clock divider is show in figure 132. there is a fixed divide by 2 after the programmable divider. the switched capacitor filter clock value is given by the following equation; (scf clock) = f(2nd lo) / (scf divider value * 2). the scrambler modulation clock frequency (smcf) is proportional to the scf clock. the following equation defines its value: smcf = (scf clock)/40 the scf divider should be set to a value which brings the scf clock as close to 165.16 khz as possible. this is based on the 2nd lo frequency which is chosen in figure 114. figure 132. scf clock divider circuit lo 2 out 6b programmable scf clock counter lo 2 in 2nd lo crystal scf clock divide by 2.0 scrambler modulation clock divide by 40 MC13110a/b only corner frequency programming for MC13110a/b and MC13111a/b four different corner frequencies may be selected by programming the scf clock divider as shown in figures 133 and 134. it is important to note, that all filter corner frequencies will change proportionately with the scf clock frequency and scrambler modulation frequency. the powerup default scf clock divider value is 31. figure 133. corner frequency programming for 10.240 mhz 2nd lo MC13110a/b MC13111a/b scf clock divider total divide value scf clock freq. (khz) r x upper corner frequency (khz) t x upper corner frequency (khz) scrambler modulation frequency (clk/40) (khz) scrambler lower corner frequency (hz) scrambler upper corner frequency (khz) 29 58 176.55 4.147 3.955 4.414 267.2 3.902 29 30 58 60 176 . 55 170.67 4 . 147 4.008 3 . 955 3.823 4 . 414 4.267 267 . 2 258.3 3 . 902 3.772 31 32 62 64 165.16 160 00 3.879 3 758 3.700 3 584 4.129 4 000 250.0 242 2 3.650 3 536 32 64 160.00 3.758 3.584 4.000 242.2 3.536 note: 18. all filter corner frequencies have a tolerance of 3%. 19. r x and t x upper corner frequencies are the same corner frequencies for the MC13110a/b in scrambler bypass
MC13110a/b MC13111a/b 57 motorola analog ic device data figure 134. corner frequency programming for 11.15 mhz 2nd lo MC13110a/b MC13111a/b scf clock divider total divide value scf clock freq. (khz) r x upper corner frequency (khz) t x upper corner frequency (khz) scrambler modulation frequency (clk/40) (khz) scrambler lower corner frequency (hz) scrambler upper corner frequency (khz) 32 64 174.22 4.092 3.903 4.355 263.7 3.850 32 33 64 66 174 . 22 168.94 4 . 092 3.968 3 . 903 3.785 4 . 355 4.223 263 . 7 255.7 3 . 850 3.733 34 35 68 70 163.97 159 29 3.851 3 741 3.673 3 568 4.099 3 982 248.2 241 1 3.624 3 520 35 70 159.29 3.741 3.568 3.982 241.1 3.520 notes: 20. all filter corner frequencies have a tolerance of 3%. 21. r x and t x upper corner frequencies are the same corner frequencies for the MC13110a/b in scrambler bypass figure 135. auxiliary register latch bits 4b 1st lo capacitor selection 3b test mode msb lsb msb lsb 0 0 0 0 0 0 0 0 0 figure 136. digital test mode description tm # tm 2 tm 1 tm 0 counter under test or test mode option at x v co o input signal aclk outo output expected 0 0 0 0 normal operation >200 mvpp 1 0 0 1 r x counter 0 to 2.5 v input frequency/r x counter value 2 0 1 0 t x counter 0 to 2.5 v input frequency/t x counter value 3 0 1 1 reference counter + divide by 4/25 0 to 2.5 v input frequency/reference counter value * 100 4 1 0 0 sc counter 0 to 2.5 v input frequency/sc counter value * 2 5 1 0 1 alc gain = 10 option n/a n/a 6 1 1 0 alc gain = 25 option n/a n/a auxiliary register the auxiliary register contains a 4bit first lo capacitor selection latch and a 3bit test mode latch. operation of these latch bits are explained in figures 135, 136 and 137. test modes test modes are be selected through the 3bit test mode register. in test mode, the at x vcoo input pin is multiplexed to the input of the counter under test. the output of the counter under test is multiplexed to the aclk outo output pin so that each counter can be individually tested. make sure test mode bits are set to a0'so for normal operation. test mode operation is described in figure 136. during normal operation, the at x vcoo input can be a minimum of 200 mvpp at 80 mhz and s hould be ac coupled. input signals should be standard logic levels of 0 to 2.5 v and a maximum frequency of 16 mhz. first local oscillator programmable capacitor selection there is a very large frequency difference between the minimum and maximum channel frequencies in the 25 channel u.s. standard. the internal varactor adjustment range is not large enough to accommodate this large frequency span. an internal capacitor with 15 programmable capacitor values can be used to cover the 25 channel frequency span without the need to add external capacitors and switches. the programmable internal capacitor can also be used to eliminate the need to use an external variable capacitor to adjust the 1st lo center frequency during telephone assembly. figure 32 shows the schematic of the 1st lo tank circuit. figure 137 shows the register control bit values. the internal programmable capacitor is composed of a matrix bank of capacitors that are switched in as desired. programmable capacitor values between about 0 and 16 pf can be selected in steps of approximately 1.1 pf. the internal parallel resistance values in the table can be used to calculate the quality factor (q) of the oscillator if the q of the external inductor is known. the temperature coefficient of the varactor is 0.08%/ c. the temperature coefficient of the internal programmable capacitor is negligible. tolerance on the varactor and programmable capacitor values is 15%.
MC13110a/b MC13111a/b 58 motorola analog ic device data figure 137. first local oscillator internal capacitor selection 1st lo cap. bit 3 1st lo cap. bit 2 1st lo cap. bit 1 1st lo cap. bit 0 1st lo cap. select internal programmable capacitor value (pf) varactor value over 0.3 to 2.5 v (pf) equivalent internal parallel resistance at 40 mhz (k w ) equivalent internal parallel resistance at 51 mhz (k w ) 0 0 0 0 0 0.0 9.7 to 5.8 1200 736 0 0 0 1 1 0.6 9.7 to 5.8 79.3 48.8 0 0 1 0 2 1.7 9.7 to 5.8 131 80.8 0 0 1 1 3 2.8 9.7 to 5.8 31.4 19.3 0 1 0 0 4 3.9 9.7 to 5.8 33.8 20.8 0 1 0 1 5 4.9 9.7 to 5.8 66.6 41 0 1 1 0 6 6.0 9.7 to 5.8 49.9 30.7 0 1 1 1 7 7.1 9.7 to 5.8 40.7 25.1 1 0 0 0 8 8.2 9.7 to 5.8 27.1 16.7 1 0 0 1 9 9.4 9.7 to 5.8 21.6 13.3 1 0 1 0 10 10.5 9.7 to 5.8 20.5 12.6 1 0 1 1 11 11.6 9.7 to 5.8 18.6 11.5 1 1 0 0 12 12.7 9.7 to 5.8 17.2 10.6 1 1 0 1 13 13.8 9.7 to 5.8 15.8 9.7 1 1 1 0 14 14.9 9.7 to 5.8 15.3 9.4 1 1 1 1 15 16.0 9.7 to 5.8 14.2 8.7
MC13110a/b MC13111a/b 59 motorola analog ic device data other applications information pcb board layout considerations the ideal printed circuit board (pcb) lay out would be doublesided with a full ground plane on one side. the ground plane would be divided into separate sections to prevent any audio signal from feeding into the first local oscillator via the ground plane. leaded components, can likewise, be inserted on the ground plane side to improve shielding and isolation from the circuit side of the pcb. the opposite side of the pcb is typically the circuit side. it has the interconnect traces and surface mount components. in cases where cost allows, it may be beneficial to use multilayer boards to further improve isolation of components and sensitive sections (i.e. rf and audio). for the ct0 band, it is also permissible to use singlesided pc layouts, but with continuous full ground fill in and around the components. the proper placement of certain components specified in the application circuit may be very critical. in a layout design, these components should be placed before the other less critical components are inserted. it is also imperative that all rf paths be kept as short as possible. finally, the MC13110a/b and MC13111a/b ground pins should be tied to ground at the pins and v cc pins should have adequate decoupling to ground as close to the ic as possible. in mixed mode systems where digital and rf/analog circuitry are present, the v cc and v ee buses need to be acdecoupled and isolated from each other. the design must also take great caution to avoid interference with low level analog circuits. the receiver can be particularly susceptible to interference as they respond to signals of only a few microvolts. again, be sure to keep the dc supply lines for the digital and analog portions separate. avoid ground paths carrying common digital and analog currents, as well. component selection the evaluation circuit schematics specify particular components that were used to achieve the results shown in the typical curves and tables, but alternate components should give similar results. the MC13110a/b and MC13111a /b ic are capable of matching the sensitivity, imd, adjacent channel rejection, and other performance criteria of a multichip analog cordless telephone system. for the most part, the same external components are used as in the multichip solution. vb and pll v ref vb is an internally generated bandgap voltage. it functions as an ac reference point for the operational amplifiers in the audio section as well as for the battery detect circuitry. this pin needs to be sufficiently filtered to reduce noise and prevent crosstalk between r x audio to t x audio signal paths. a practical capacitor range to choose that will minimize crosstalk and noise relative to start up time is 0.5 m f to 10 m f. the start time for a 0.5 m f capacitor is approximately 5.0 ms, while a 10 m f capacitor is about 10 ms. the apll v ref o pin is the internal supply voltage for the r x and t x pll's. it is regulated to a nominal 2.5 v. the av cc audioo pin is the supply voltage for the internal voltage regulator. two capacitors with 10 m f and 0.01 m f values must be connected to the apll v ref o pin to filter and stabilize this regulated voltage. the apll v ref o pin may be used to power other ic's as long as the total external load current does not exceed 1.0 ma. the tolerance of the regulated voltage is initially 8.0%, but is improved to 4.0% after the internal bandgap voltage reference is adjusted electronically through the mpu serial interface. the voltage regulator is turned off in the standby and inactive modes to reduce current drain. in these modes, the apll v re fo pin is internally connected to the av cc audioo pin (i.e., the power supply voltage is maintained but is now unregulated). it is important to note that the momentary drop in voltage below 2.5 v during this transition may affect initial pll lock times and also may trigger the reset. to prevent this, the pll v ref capacitor described above should be kept the same or larger than the vb capacitor, say 10 m f as shown in the evaluation and application diagrams. dc coupling choosing the right coupling capacitors for the compander is also critical. the coupling capacitors will have an affect on the audio distortion, especially at lower audio frequencies. a useful capacitor range for the compander timing capacitors is 0.1 m f to 1.0 m f. it is advised to keep the compander capacitors the same value in both the handset and baseset applications. all other dc coupling capacitors in the audio section will form high pass filters. the designer should choose the overall cut off frequency (3.0 db) to be around 200 hz. designing for lower cut off frequencies may add unnecessary cost and capacitor size to the design, while selecting too high of a cut off frequency may affect audio quality. it is not necessary or advised to design each audio coupling capacitors for the same cut off frequency. design for the overall system cut off frequency. (note: do not expect the application, evaluation, nor production test schematics to necessarily be the correct capacitor selections.) the goals of these boards may be different than the systems approach a designer must consider. for the supply pins (v cc audio and v cc rf) choose a 10 m f in parallel with a high quality 0.01 m f capacitor. separation of the these two supply planes is essential, too. this is to prevent interference between the rf and audio sections. it is always a good design practice to add additional coupling on each supply plane to ground as well. the if limiter capacitors are recommended to be 0.1 m f. smaller values lower the gain of the limiter stage. the 3.0 db limiting sensitivity and sinad may be adversely affected.
MC13110a/b MC13111a/b 60 motorola analog ic device data appendix a figure 138. 12 mix out lim in 2 bnc bnc 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 20 19 18 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 28 27 c38 0.01 c37 0.01 r34 txt c35 0.01 MC13111a r37 txt c28 txt f1 txt f2 txt c31 0.1 c30 0.1 r28 txt l1 txt c53 1000 c54 0.01 c55 10 m r53 47 v cc gnd rssi bnc det out da in t x in amp out t x out bd 2 out da out bd 1 out r x pd pll v ref t x pd t x vco clk out cd out connector controllor rf in 1 rf in 2 lo 2 in v cap ctrl sa out e out scr out bnc bnc bnc c39 0.01 r39 49.9 r40 49.9 t2l2 txt c40 txt r44 150 c44 47 m c45 220 p r45 47 k r46 47 k c46 0.1 c47 0.47 c48 0.47 v cc v cc v cc r51a 82 k r50a 110 k r51b 100 k r50b 100 k c52 10 m r42a txt r4a txt c42a txt r42b txt r4b txt c1 txt c2 txt c3 0.1 xc txt c42b txt c4 txt c5a 0.01 r9 10 k r10 10 k r11 10 k r13 100 k v cc r14 100 k r16 100 k v cc v cc v cc c18 0.47 c19 0.1 r20 47 k c20 220 p r21 47 k c21 0.1 c23a 0.01 c24 0.01 c23b 10 m c26 0.047 mix 1 in 1 mix 1 in 2 mix 1 out gnd rf mix 2 out mix 2 in sgnd rf lim in lim c1 lim c2 v cc rf lim out q coil lo 1 in lo 1 out v cap ctrl gnd audio sa out sa in e out e cap e in scr out ref 2 ref 1 v b rssi det out r x audio in v cc audio da in t x in amp out c in c cap t x out bd 2 out da out bd 1 out lo 2 in v ag pll v t x pd gnd pll data en clk clk out cd out lo 2 out r x pd ref t x vco mix out mix in t1 txt txt: see text c5b 10 m figure 138. evaluation board schematic MC13110a
MC13110a/b MC13111a/b 61 motorola analog ic device data appendix a figure 139. evaluation board bill of materials for u.s. and french application cnb usa application handset french application base cnb rf (50 w ) rf m h d rf crystal (50 w ) rf ceramic (50 w ) rf m h d comp. number (50 w ) rf matched y (50 w ) (50 w ) rf matched input matching t1 n.m. toko 1:5 n.m. n.m. toko 1:5 292gns765a0 292gns765a0 c38 0.01 n.m. 0.01 0.01 n.m. c39 0.01 n.m. 0.01 0.01 n.m. 10.7 mhz filter f1 ceramic ceramic crystal ceramic ceramic r37 0 0 1.2 k 0 0 r34 360 360 3.01 k 360 360 450 khz filter f2 4 element 4 element 4 element 4 element 4 element murata e murata e murata g murata g murata g demodulator l1 q coil toko q coil toko ceramic murata ceramic murata ceramic murata 7mcs8128z 7mcs8128z cdbm 450c34 cdbm 450c34 cdbm 450c34 r28 22.1 k 22.1 k 2.7 k 2.7 k 2.7 k c28 10 p 10 p 390 p 390 p 390 p oscillator xtal 10.24 10.24 11.15 11.15 11.15 c1 = 10 p c1 = 10 p c1 = 18 p c1 = 18 p c1 = 18 p c2 18 p 18 p 33 p 33 p 33 p c1 525 p 525 p 15 p + 525 p 15 p + 525 p 15 p + 525 p first lo l2 0.47 toko t1370 0.47 toko t1370 0.22 toko t1368 0.22 toko t1368 0.22 toko t1368 c40 hs/bs hs: 27 pf hs: 27 pf bs: 100 p bs: 100 p bs: 100 p bs: 22 pf bs: 22 pf hs: 68 pf hs: 68 pf hs: 68 pf loop filter handset/baseset r4a hs: 0 hs: 0 hs: 0 hs: 0 hs: 0 bs: 0 bs: 0 bs: 0 bs: 0 bs: 0 r4b hs: 0 hs: 0 hs: 0 hs: 0 hs: 0 bs: 0 bs: 0 bs: 0 bs: 0 bs: 0 c4 hs: 6800 hs: 6800 hs: 8600 hs: 8600 hs: 8600 bs: 8200 bs: 8200 bs: 6800 bs: 6800 bs: 6800 r42a hs: 100 k hs: 100 k hs: 100 k hs: 100 k hs: 100 k bs: 100 k bs: 100 k bs: 100 k bs: 100 k bs: 100 k r42b hs: 22 k hs: 22 k hs: 18 k hs: 18 k hs: 18 k bs: 18 k bs: 18 k bs: 22 k bs: 22 k bs: 22 k c42a hs: 1000 hs: 1000 hs: 1000 hs: 1000 hs: 1000 bs: 1000 bs: 1000 bs: 1000 bs: 1000 bs: 1000 c42b hs: 0.068 hs: 0.068 hs: 0.082 hs: 0.082 hs: 0.082 bs: 0.082 bs: 0.082 bs: 0.068 bs: 0.068 bs: 0.068
MC13110a/b MC13111a/b 62 motorola analog ic device data appendix b applications circuit rf input t rfin gnd duplexer 12 3456 c2 0.1 r1 33 k r4 220 c4 0.01 q1 mpsh10 gnd 0.033 c3 gnd t1 r3 220 r2 100 k 8519n p1 p2 p3 s1 s2 c6 47 m f sp1 150300 w + 22 0.47 m h l3 r8 47 k r7 47 k 0.1 c10 c9 220 0.47 c12 v cc a 0.47 c13 r10 110 k r12 82 k 0.1 c16 0.1 c15 r13 100 k r11 100 k v b 10 m f c14 gnd c18 5.025 x1 10.24 c17 18 c19 0.1 100 k 1000 gnd gnd c22 0.01 10 m f c23 c27 10 r16 30 3.3 m f c24 22 m f c25 r17 1.0 k r18 680 r19 18 k t vt 4.7 m f c26 gnd t vco r20 10 k r21 10 k r22 10 k fl1 r36 330 fl2 23 1 23 1 c74 0.10 c73 0.10 c70 10 r34 22 k gnd gnd v cc rf p35 47 0.01 c72 c71 10 m f t2 8128z rssi 0.01 c86 c89 0.047 r32 8.2 k r33 47 k c87 1000 c88 0.15 0.01 c35 c34 33 0.1 c29 c28 0.47 v cc a t audio v cc a r25 100 k r24 100 k r23 100 k v cc cardetect batt dead r data low batt clk out clk en data c7 10 gnd gnd c33 3300 r28 27 k r30 680 k r29 27 k 0.047 c31 6800 c30 gnd gnd c84 0.01 r31 47 v cc a v cc 3.9 k 1.0 k 10 m f c32 gnd mic1 mic electret figure 140. basic cordless telephone transceiver application circuit 12345678910111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 l o 2 i n l o 2 o u t v a g r x p d l l v r e f p t x p d n d p l l g t x c o v d a t a e n c l k cd out u t o c l k v b ref 1 ref 2 scr out e in e cap e out sa in sa out gnd audio v cap ctrl lo 1 out lo 1 in mix 1 in 1m i x 1 i n 2 m i x 1 o u t g n d r f m i x 2 o u t m i x 2 i n s g n d r f l i m i n l i m c 1 l i m c 2 v c c r f l i m o u t q coil rssi det out r x audio in v cc audio da in t x in amp out c in c cap t x out bd 2 out da out bd 1 out ic1 r x t x n t a r26 r27 c5 n d g n d g n d g v cc rf x x x x x MC13110a/b speaker figure 140. + + + + + + 1000 10 0.068 18 k 8200 m f legend: if 1, then capacitor value = pf if <1, then capacitor value = f m MC13111a/b
MC13110a/b MC13111a/b 63 motorola analog ic device data appendix b batt1 v+ v c54 10 f m c53 0.01 gnd v cc v cc rf v cc a l6 56 h m c55 0.22 gnd c58 10 f m gnd gnd c56 0.1 c57 2.2 f m t x audio r54 100 k r53 68 k r51 110 k r37 22 k r39 110 k t x data r41 27 k r42 91 k c40 10 c38 8.0 c37 6800 u5 c49 2.0 c48 120 l4 0.22 h m c59 180 t vt 2109 vr2 1 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c46 36 c47 36 t vco r50 1.5 k c45 10 gnd r49 100 c44 4700 13630 t3 cx 7.5 p1 p2 p3 s1 s2 c41 51 t rfin 51 l5 0.22 h m c43 51 r47 75 k r46 220 k r45 110 r44 110 r43 110 0.022 c50 0.022 c51 0.022 c52 c60 0.1 f m x v cc vr x x x ic2 mc2833d variable rf osc decoupling rf osc modulator rf mic amp tr 2 mic amp tr 2 gnd tr 2 tr 1 v tr 1 tr 1 reactance output input output input emitter base output base emitter collector cc collector + + + w figure 140. basic cordless telephone transceiver application circuit (continued)
MC13110a/b MC13111a/b 64 motorola analog ic device data appendix c measurement of compander attack/decay time this measurement definition is based on eia/ccitt recommendations. compressor attack time for a 12 db step up at the input, attack time is defined as the time for the output to settle to 1.5x of the final steady state value. compressor decay time for a 12 db step down at the input, decay time is defined as the time for the input to settle to 0.75x of the final steady state value. decay time 0.75x final value 1.5x final value attack time 0 mv 0 mv input output 12 db expander attack for a 6.0 db step up at the input, attack time is defined as the time for the output to settle to 0.57x of the final steady state value. expander decay for a 6.0 db step down at the input, decay time is defined as the time for the output to settle to 1.5x of the final steady state value. decay time 1.5x final value 0.57x final value attack time 0 mv input output 6.0 db 0 mv
MC13110a/b MC13111a/b 65 motorola analog ic device data fb suffix plastic package case 848b04 (qfp52) issue c outline dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane c. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. detail a l 39 40 26 27 1 52 14 13 l a b v s ab m 0.20 (0.008) d s h ab 0.05 (0.002) s ab m 0.20 (0.008) d s c d b v b s ab m 0.20 (0.008) d s h ab 0.05 (0.002) s ab m 0.20 (0.008) d s c h 0.10 (0.004) c seating plane datum plane m g h e c m detail c u q x w k t r detail c dim min max min max inches millimeters a 9.90 10.10 0.390 0.398 b 9.90 10.10 0.390 0.398 c 2.10 2.45 0.083 0.096 d 0.22 0.38 0.009 0.015 e 2.00 2.10 0.079 0.083 f 0.22 0.33 0.009 0.013 g 0.65 bsc 0.026 bsc h 0.25 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 7.80 ref 0.307 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 12.95 13.45 0.510 0.530 t 0.13 0.005 u 0 0 v 12.95 13.45 0.510 0.530 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref b b detail a a, b, d jn d f base metal section bb s ab m 0.02 (0.008) d s c
MC13110a/b MC13111a/b 66 motorola analog ic device data fta suffix plastic package case 93202 (lqfp48) issue d ???? ???? ???? a a1 t z 0.200 (0.008) ab tu u 4x z 0.200 (0.008) ac tu 4x b b1 1 12 13 24 25 36 37 48 z s1 s v v1 p ae ae t, u, z detail y detail y base metal n j f d s tu m 0.080 (0.003) z s ac section aeae ab ac ad g 0.080 (0.003) ac m top & bottom q w k x e c h 0.250 (0.010) gauge plane r 9 detail ad dim a min max min max inches 7.000 bsc 0.276 bsc millimeters a1 3.500 bsc 0.138 bsc b 7.000 bsc 0.276 bsc b1 3.500 bsc 0.138 bsc c 1.400 1.600 0.055 0.063 d 0.170 0.270 0.007 0.011 e 1.350 1.450 0.053 0.057 f 0.170 0.230 0.007 0.009 g 0.500 basic 0.020 basic h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.250 basic 0.010 basic q 1 5 1 5 r 0.150 0.250 0.006 0.010 s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref notes: 1 dimensioning and tolerancing per ansi y14.5m, 1982. 2 controlling dimension: millimeter. 3 datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4 datums t, u, and z to be determined at datum plane ab. 5 dimensions s and v to be determined at seating plane ac. 6 dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7 dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350 (0.014). 8 minimum solder plate thickness shall be 0.0076 (0.0003). 9 exact shape of each corner is optional. outline dimensions
MC13110a/b MC13111a/b 67 motorola analog ic device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.
MC13110a/b MC13111a/b 68 motorola analog ic device data mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 4321, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 nishigotanda, shinagawaku, tokyo 141, japan. 81354878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ MC13110a/d ?

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