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quad power low side driver with 2 x 5a and 2 x 3a output current capability low r dson typically 200m w and 300m w @ tj = 25c internal output clamping struc- tures with v fb = 50v for fast induc- tive load current recirculation limited output voltage slew rate for low emi protected m p compatible enable and input wide operating supply voltage range 4.5v to 32v real time diagnostic functions: - output shorted to gnd - output shorted to vss - open load measured in on and off condition - load bypass detection - overtemperature device protection functions: - overload disable - reverse supply voltage protected vs up to -2v - selective thermal shutdown description the l9346 is a monolithic integrated quad low side driver realized in an advanced multipow- may 2000 ? out1 out 4 vs channel 1 channel 4 output control overtemp r qs delay timer overload openload gnd d4 in4 en d1 in1 r io diagnostic control out 2 channel 2 d2 in2 out 3 channel 3 d3 in3 52v block diagram ordering numbers: l9346pd (power so20) L9346DIE (chip) l9346 quad intelligent power low side switch power so20 chip 1/13
erbcd mixed technology. the device is intended to drive valves in automotive environment. the inputs are m p compatible. particular care has been taken to protect the device against failures, to avoid electromagnetic interferences and to of- fer extensive real time diagnostic. absolute maximum ratings symbol parameter conditions value unit v s dc supply voltage -2 to 32 v v sp supply voltage pulse (duration <200ms) -2 to 45 v ? ? ? dv s dt ? ? ? supply voltage slope 10 v/ m s v in, en input voltage ? i ? 10ma -2 to 16 v v d diagnostic dc output voltage ? i ? 50ma -0.3 to 16 v v odc dc output voltage -0.3 to 45 v i o1, 2 dc output current out 1, 2 5 a i o3, 4 dc output current out 3, 4 3 a i or1, 2 reverse output current -5 a i or3, 4 reverse output current -3 a e o1, 2 switch-off energy for inductive loads t eo = 250 m s, 1) 50 mj e o3, 4 t = 5ms 30 mj d v gnd gnd potential difference t j = -40 to 150c 0.3 v t jeo juntion temperature during switch-off ? t 30 min 175 c ? t 15 min 190 c t j juntion temperature -40 to t jdis c t stg storage temperature -55 to 150 c t jdis thermal disable junction temp. threshold 180 to 210 c the device is esd protected, tested according to mil883c with 2kv. note 1) : t eo is the clamping time (see fig.1) pgnd out1 d1 in 4 en gnd in 3 d2 out2 pgnd pgnd pgnd out4 d4 in 1 vs nc in 2 d3 out3 heat sink connected to pins 1, 10, 11, 20 pin connection description (continued) l9346 2/13
thermal data symbol parameter value unit r th j-c thermal resistance junction to case 3 k/w pin functions n. name function 1 gnd power grounded 2 out 1 output 1 (5a) 3 d1 diagnostic 1 4 in 4 input 4 5 vs supply voltage 6 nc not connected 7 in 3 input 3 8 d2 diagnostic 2 9 out 2 output 2 (5a) 10 gnd power ground 11 gnd power ground 12 out 3 output 3 (3a) 13 d3 diagnostic 3 14 in 2 input 2 15 gnd signal ground 16 en common enable 17 in 1 input 1 18 d4 diagnostic 4 19 out 4 output 4 (3a) 20 gnd power ground t eo v s t t v o1 - 4 v ocl figure 1: t eo clamping time l9346 3/13
esd figure 2: pad position (chipsize 4.95 x 3.88) l9346 4/13
pad coordinates (reference point x = 0, y = 0: center of die) pat opening center position pad nr. pad name size in ( m m) description coordinates in ( m m) xy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 pg3 pg3 pg2 pg2 out2 out2 d2 in3 vs in4 d1 out1 out1 pg1 pg1 pg4 pg4 out4 out4 d4 in1 en gnd in2 d3 out3 out3 178 x 280 178 x 280 178 x 280 178 x 280 280 x 178 280 x 178 178 x 178 178 x 178 178 x 178 178 x 178 178 x 178 280 x 178 280 x 178 178 x 178 178 x 178 178 x 178 178 x 178 280 x 178 280 x 178 178 x 178 178 x 178 178 x 178 178 x 178 178 x 178 178 x 178 280 x 178 280 x 178 power ground 3 power ground 3 power ground 2 power ground 2 output 2 5a output 2 5a diagnostic 2 input 3 supply voltage input 4 diagnostic 1 output 1 5a output 1 5a power ground 1 power ground 1 power ground 4 power ground 4 output 4 3a output 4 3a diagnostic 4 input 1 common enable signal ground input 2 diagnostic 3 output 3 3a output 3 3a 2286.5 2286.5 2286.5 2286.5 1472.5 1722.5 1036 648 -260 -648 -1036 -1722.5 -1472.5 -2286 -2286 -2286 -2286 -1448 -1656 -970 -582 -194 194 582 970 1656.5 1448.5 1175 506 98 -842 -844 -1644 -1644 -1644 -1644 -1644 -1644 -1644 -844 -842 98 506 1175 865 1644 1644 1644 1644 1644 1644 1644 1644 865 test pad size x y gate 2 vterm2 iolred esd vterm1 gate1 gate4 vterm4 vterm3 gate3 d = 102 d = 102 d = 102 178 x 178 d = 102 d = 102 d = 102 d = 102 d = 102 d = 102 1447 1260 449.5 260 -1260 -1447 -1381 -1194.5 1194.5 1381 -1612 -1600 -1455.5 -1644 -1600 -1612 1600 1600 1600 1600 l9346 5/13
electrical characteristics (operating range) the electrical characteristics are valid within the below defined operating range, unless otherwise specified.) symbol parameter test condition min. typ. max. unit v s board supply voltage 4.5 12 32 v t j1 junction temperature -40 150 c t j2 junction temperature s t 15min 2) over life time 150 t jdis c note: 2) parameters guaranteed by correlation electrical characteristics (v s = 4.5 to 32v; -40c t j1 150c < t j2 t jdis , unless other- wise specified.) symbol parameter test condition value t j1 value t j2 unit min. typ. max. min. max. supply i vs off dc supply current off en = 1.0v 5 10 ma i vs on dc supply current on v s 14v; v in , v en = 2v 8 ma diagnostic outputs d 1 - d 4 v dl diagnostic output low voltage i d 3ma 0.65 1.0 1.5 v i dle diagnostic output leakage current v d = 14v 3) 0.1 2 20 m a outputs out 1 - out 4 v ouv 1-4 open load voltage threshold v in = 1v 0.525 x v s 0.55 x v s 0.575 x v s 0.5 x v s 0.65 x v s v v ouv hys 1-4 hysteresis 0.003 x v s v d v ouv 1-4, 2-3, 4-1, 3-2 open load difference voltage threshold v in1,4/2,3 = 1v, 4.5v vo c 16v, 4.5v v s 16v, vo c = output voltage of other channel vo c - 1.0v vo c - 1.25v vo c - 1.5v vo c - 0.8v vo c - 1.7v v v ouv hys 1-4, 2-3, 4-1, 3-2 open load hysteresis 40 mv i ouc 1, 2, 3, 4 open load current threshold v en = v in = 2v; v s = 6.5 to 16v 160 320 480 580 ma i ooc 1, 2 over load current threshold v s > 6.5v; v out = 32v 510 4 a i ooc 3, 4 36 2.4 a v ocl output voltage during clamping i ocl 3 200ma 45 52 60 v s on,off output (fall, rise) slew rate 4) i ouc i o i ooc 400 1500 2850 200 3500 v/ms r io internal output pull down resistor v en = 1v 10 20 40 50 k w r dson 1, 2 output on resistance t j = 25c t j = 150c v s > 9.5v, i o1,2 = 2a 200 300 500 m w r dson 3, 4 t j = 25c t j = 150c; i o3,4 = 1.3a 300 450 750 m w note: 2) parameters guaranteed by correlation 3) the diagnostic output is short circuit protected up to v d = 16v 4) v s = 9 to 16v l9346 6/13
electrical characteristics (continued) symbol parameter test condition value t j1 value t j2 unit min. typ. max. min. max. inputs in1-4, en v in,en l logic input/enable low voltage -0.3 1 0.8 v v in,en h logic input/enable high voltage in, en 2.0 16 v v en,in hys logic input hysteresis 0.2 0.4 0.8 v i in input sink current v in = 2 to 12v 5) 10 30 60 240 m a i en enable sink current 10 20 40 240 m a timing t d on output delay on time 6) fig. 7 4 25 m s t d off output delay off time 6) fig. 7 5 15 30 m s t dh-l, diag diag. delay output off time 6) fig. 6 8 65 90 m s t d iou diagnostic open load delay time v s = 9 to 16v, fig 8 i o i ouc 850 m s t dol diagnostic overload delay switch-off time v s = 9 to 16v, fig 8 i o > i ooc 50 160 300 m s t d en on enable on time 6) fig. 7 4 25 m s t d en off enable off time 6) fig. 7 4 25 m s note: 5) open pins (en, in) are detected as low 6) v s = 9 to 16v i ouc i o i ooc diagnostic table conditions en in out diag. normal function l x off l hloffl hhon 7) h gnd short v otyp < 0.55v s lxoffh load bypass d v o1-4/2-3 3 1.25v h l off h open load i o1,2,3,4typ < 320ma h h on 7) l t jtyp 3 190c overtemperature 8) xxoffl over load i omin 1,3 > 5a i omin 2,4 > 3a hhoffl reset and overtemperature latch x dc dont care dc dont care note: 7) for v s = 4.5 to 6.5v, i o 2a, the diag. table is valid 8) if one diag. status shows the overtemperature, recognition, in parallel this output will be switched off internally. the corresponding channel should be switched off additionally by its input signal, otherwise the overload latch will be set after t dol is passed. this behaviour is related to the overdrop sensing which is used as over load recognition. the overtemperature is latched (diag = l) until the level of the in signal changes to low. l9346 7/13
circuit description the l9346 is a quad low side driver for inductive loads like valves in automotive environment. the internal pull down current sources at the en- able and input pins assure in case of open in- put conditions that the device is switched off. an output voltage slope limitation for du/dt is imple- mented to reduce the emi. an integrated active flyback voltage limitation clamps the output volt- age during the flyback phase to 50 v. each driver is protected against short circuit at v out < 32v and thermal overload. in short circuit condition the output will be disabled after a short delay time t dol . the thermal disable for tj > 180c of the output will be reseted if the junction temperature decreases about 20c below the dis- able threshold temperature. the overtemperature information is stored until in = l. for the real time error diagnosis the voltage and the current of the outputs are compared with in- ternal fixed values v ouv for off and i ouc for on conditions to recognize open load (r l 3 20 k w , r l > 38 w ) in off and on conditions. also the output voltages v o1 - 4 are compared to each other output in off condition with a fixed offset of d v ouv to recognize load bypasses. to suppress the d v ouv diagnoses during the flyback phases of the compared output, the d vouv diag- nostic includes a latch function. reaching the flyback clamping voltage v ocl the diagnostic signal is reseted by a latch. to activate again this kind of diagnostic a low signal at the correspondent input or the enable pin must be applied (see also fig.3). the outputs 1 and 4 are compared for d v ouv and also outputs 2 and 3 are compared. the diagnostic output level in connection with dif- ferent enable and input conditions allows to recognize different fail states, like overtemp, short to v ss , short to gnd, bypass to gnd and dis- connected load (see diagnostic table). the diagnostic output is protected against short circuit. exceeding the over load current threshold i ooc , the output current will be limited internally during the diagnostic overload delay switch-off time t dol . the device complies the iso pulses imposed to the supply voltage of the valves without any fail- ures of the functionality. 5v t t 5v t 5a 3a in v i o i ool i ouc d v t dol figure 3. diagnostic overload delay time l9346 8/13
e n , in v on 0.85 x v out 0.15 x v out , don t t denon , doff t t denoff figure 5. timing (t denon , t don , t denoff , t doff ) 5v t d on t t t 0.85 vs 0.15 vs vs v in v out v v (en)h (en)l s on v t v diag 0.5 v d d v ouv s off 0.85vs t denon t denoff t d h-l diag d off figure 4. output slope (resistive load for testing) l9346 9/13
& & latch latch l1 (l2) l4 (l3) out1 out4 v batt. + - + - 55% vs & & r s q r s enable q r io r io in 1 vo uv1 (out2) (out3) in 4 vo uv4 figure 7. block diagram - open load voltage detection in open load current diou t dol t v d ouc i i ooc v on figure 6. timing (t dol , t diou ) l9346 10/13
vo u io o v en v in io u v d open load current open load voltage open load voltage open load c urrent open load current on normal operation latched over. load diagnostic la tc h res et on norma l operation normal operation off figure 8. logic diagram z valve z valve controller +5v p z valve z valve i/o i/o kl 15 kl 30 +45v vcc i/o i/o i/o i/o i/o i/o i/o gnd +5v +5v +5v v batt out1 out4 vs channel 1 channel 4 output control overtemp r qs delay timer overload openload gnd d4 in4 en d1 in1 r io diagnostic control out2 channel 2 d2 in2 out3 channel 3 d3 in3 52v figure 9. application circuit diagram l9346 11/13
jedec mo-166 powerso20 e a2 a e a1 pso20mec detail a t d 1 11 20 e1 e2 h x 45 detail a lead slug a3 s gage plane 0.35 l detail b r detail b (coplanarity) gc - c - seating plane e3 b c n n h bottom view e3 d1 dim. mm inch min. typ. max. min. typ. max. a 3.6 0.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 d (1) 15.8 16 0.622 0.630 d1 9.4 9.8 0.370 0.386 e 13.9 14.5 0.547 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 g 0 0.1 0.000 0.004 h 15.5 15.9 0.610 0.626 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 10? (max.) s t10 0.394 (1) "d and f" do not include mold flash or protrusions. - mold flash or protrusions shall not exceed 0.15 mm (0.006"). - critical dimensions: "e", "g" and "a3" outline and mechanical data 8? (max.) 10 l9346 12/13
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com l9346 13/13

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