june 1996 ndt454p p-channel enhancement mode field effect transistor general description features ____________________________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise noted symbol parameter ndt454p units v dss drain-source voltage -30 v v gss gate-source voltage 20 v i d drain current - continuous (note 1a) 5.9 a - pulsed 15 p d maximum power dissipation (note 1a) 3 w (note 1b) 1.3 (note 1c) 1.1 t j ,t stg operating and storage temperature range -65 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 42 c/w r q jc thermal resistance, junction-to-case (note 1) 12 c/w * order option j23z for cropped center drain lead. ndt454p rev. d2 power sot p-c hannel enhancement mode power field effect transistors are produced using fairchild's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance and provide superior switching performance . these devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -5.9 a, -30v. r ds(on ) = 0.05 w @ v gs = -10v r ds(on ) = 0.07 w @ v gs = -6v r ds(on ) = 0.09 w @ v gs = -4.5v . high density cell design for extremely low r ds(on). high power and current handling capability in a widely used surface mount package. d d s g d s g ? 1997 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = -250 a -30 v i dss zero gate voltage drain current v ds = -24 v, v gs = 0 v -1 a v ds = -15 v, v gs = 0 v t j = 70 c -5 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2) v gs (th) gate threshold voltage v ds = v gs , i d = -250 a -1 -2.7 v r ds(on) static drain-source on-resistance v gs = -10 v, i d = -5.9 a 0.038 0.05 w v gs = -6 v, i d = -5.2 a 0.046 0.07 v gs = -4.5 v, i d = -4.6 a 0.064 0.09 i d (on) on-state drain current v gs = -10 v, v ds = -5 v -15 a v gs = -4.5, v ds = -5v -5 g fs forward transconductance v ds = 15 v, i d = 5.9 a 10 s dynamic characteristics c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 950 pf c oss output capacitance 610 pf c rss reverse transfer capacitance 220 pf switching ch aracteristics (note 2 ) t d(on ) turn - on delay time v dd = -15 v, i d = -1 a, v gen = -10 v, r gen = 6 w 10 30 ns t r turn - on rise time 18 60 ns t d(off) turn - off delay time 80 120 ns t f turn - off fall time 45 100 ns q g total gate charge v ds = -15 v, i d = -5.9 a, v gs = -10 v 29 40 nc q gs gate-source charge 3 q gd gate-drain charge 11 ndt454p rev. d2
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -1.9 a v sd drain-source diode forward voltage v gs = 0 v, i s = -5.9 a (note 2 ) -0.85 -1.3 v t rr reverse recovery time v gs = 0v, i f = -5.9 a, di f /dt = 100 a/s 100 ns notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) t j typical r q ja using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 42 o c/w when mounted on a 1 in 2 pad of 2oz copper. b. 95 o c/w when mounted on a 0.066 in 2 pad of 2oz copper. c. 110 o c/w when mounted on a 0.0123 in 2 pad of 2oz copper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. ndt454p rev. d2 1a 1b 1c
ndt454p rev. d2 -5 -4 -3 -2 -1 0 -30 -25 -20 -15 -10 -5 0 v , drain-source voltage (v) i , drain-source current (a) -6.0 -4.0 v =-10v gs ds d -3.0 -4.5 -3.5 -5.0 -20 -16 -12 -8 -4 0 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance v = -3.5v gs d r , normalized ds(on) -6.0v -10v -6.0v -5.0v -4.0v -4.5v figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. typical electrical characteristics -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = -10v gs i = -5.9a d r , n o r m a l i z e d d s ( o n ) -20 -15 -10 -5 0 0.5 1 1.5 2 i , drain current (a) drain-source on-resistance d r , normalized ds(on) 25c -55c v = -10v gs t = 125c j figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with drain current and temperature. -5 -4 -3 -2 -1 -20 -16 -12 -8 -4 0 -v , gate to source voltage (v) -i , drain current (a) 25 125 v = -10v ds gs d t = -55c j -50 -25 0 25 50 75 100 125 150 0.6 0.7 0.8 0.9 1 1.1 1.2 t , junction temperature (c) gate-source threshold voltage i = -250a d v = v ds gs j v , normalized th figure 5. transfer characteristics. figure 6. gate threshold variation with temperature.
ndt454p rev. d2 -50 -25 0 25 50 75 100 125 150 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1 t , junction temperature (c) drain-source breakdown voltage i = -250a d bv , normalized dss j 0 0.3 0.6 0.9 1.2 1.5 0.001 0.01 0.1 1 5 10 20 -v , body diode forward voltage (v) -i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s figure 7. breakdown voltage variation with temperature. figure 8. body diode forward voltage variation with source current and temperature. typical electrical characteristics (continued) 0 10 20 30 40 0 2 4 6 8 10 q , gate charge (nc) -v , gate-source voltage (v) g gs i = -5.9a d v = -10v ds -15v -20v 0.1 0.3 1 3 10 30 100 200 300 500 1000 2000 3000 -v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss d s -v dd r l v out v gs dut v in r gen g figure 9. capacitance characteristics. figure 10. gate charge characteristics. figure 11. switching test circuit. figure 12. switching waveforms. 10% 50% 90% 10% 90% 90% 50% v in v out on off d(off) f r d(on) t t t t t t inverted 10% pulse width
ndt454p rev. d2 -20 -15 -10 -5 0 0 4 8 12 16 20 i , drain current (a) g , t r a n s c o n d u c t a n c e ( s i e m e n s ) t = -55c j 25c d fs v = -15v ds 125c figure 13. transconductance variation with drain current and temperature. figure 16. maximum safe operating area. typical electrical and thermalcharacteristics (continued) 0 0.2 0.4 0.6 0.8 1 2 3 4 5 6 7 2oz copper mounting pad area (in ) i , steady-state drain current (a) d 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air v = -10v a o gs 0 0.2 0.4 0.6 0.8 1 0.5 1 1.5 2 2.5 3 3.5 2oz copper mounting pad area (in ) steady-state power dissipation (w) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air a o 0.1 0.2 0.5 1 2 5 10 30 50 0.01 0.03 0.1 0.3 1 3 10 30 - v , drain-source voltage (v) -i , drain current (a) ds d 1s 100ms 10s dc 10ms rds(on) limit 1ms v = -10v single pulse r = see note 1c t = 25c gs a q ja 100us figure 15 . maximum steady-state drain current versus copper mounting pad area. figure 14 . sot-223 maximum steady-state power dissipation versus copper mounting pad area. figure 15 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design. 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1 c q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2
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