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any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft?s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. cmos ic ordering number : enn5427b 91099th (ot)/22897ha (ot)/63196ha (ot) no. 5427-1/23 lc72133m, 72133v sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan pll frequency synthesizer for electronic tuning overview the lc72133m and lc72133v are a phase-locked loop frequency synthesizer lsi circuits for use in radio tuners. it supports low-voltage (2.7 to 3.6 v) operation and can implement high-performance am/fm tuners easily. functions ? high speed programmable dividers ? fmin: 10 to 120 mhz ..........pulse swallower (built-in divide-by-two prescaler), v dd 2.7 v 10 to 130 mhz ..........pulse swallower (built-in divide-by-two prescaler), v dd 3.0 v ? amin: 2 to 40 mhz ..............pulse swallower 0.5 to 10 mhz ...........direct division ? if counter ? ifin: 0.4 to 12 mhz ...........am/fm if counter ? reference frequencies ? twelve selectable frequencies (4.5 or 7.2 mhz crystal) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50 and 100 khz ? phase comparator ? dead zone control ? unlock detection circuit ? deadlock clear circuit ? built-in mos transistor for forming an active low-pass filter ? i/o ports ? dedicated output ports: 4 ? input or output ports: 2 ? support clock time base output ? serial data i/o ? support ccb format communication with the system controller. (compatible with lc72131) ? operating ranges ? supply voltage........................2.7 to 3.6 v ? operating temperature............?20 to +70c ? package mfp20 ssop20 ? ccb is a trademark of sanyo electric co., ltd. ? ccb is sanyo?s original bus format and all the bus addresses are controlled by sanyo.
lc72133m, 72133v package dimensions unit: mm 3036b-mfp20 unit: mm 3179a-ssop20 1 20 10 11 12.6 0.15 1.27 0.35 0.59 1.8 max 1.5 0.1 5.4 0.625 6.35 7.6 sanyo: mfp20 [lc72133m] 110 11 6.4 6.7 0.5 4.4 0.1 1.6max 1.0 20 0.65 0.22 0.43 0.15 sanyo: ssop20 [lc72133v] no. 5427-2/23 specifications absolute maximum ratings at ta = 25c, v ss = 0 v parameter symbol pins ratings unit supply voltage v dd max v dd ?0.3 to +5.5 v v in 1 max ce, cl, di, ain ?0.3 to +5.5 v maximum input voltage v in 2 max xin, fmin, amin, ifin ?0.3 to v dd +0.3 v v in 3 max io1, io2 ?0.3 to +15 v v o 1 max do ?0.3 to +5.5 v maximum output voltage v o 2 max xout, pd ?0.3 to v dd + 0.3 v v o 3 max bo1 to bo4, io1, io2, aout ?0.3 to +15 v i o 1 max bo1 0 to 3.0 ma maximum output current i o 2 max aout, do 0 to 6.0 ma i o 3 max bo2 to bo4, io1, io2 0 to 6.0 ma allowable power dissipation pd max ta 70c: lc72133m 180 mw ta 70c: lc72133v 160 mw operating temperature topr ?20 to +70 c storage temperature tstg ?40 to +125 c
no. 5427-3/23 lc72133m, 72133v allowable operating ranges at ta = ?20 to +70c, v ss = 0 v note: * recommended crystal oscillator ci values: ci 120 (for a 4.5 mhz crystal) ci 70 (for a 7.2 mhz crystal) crystal oscillator: hc-49/u (manufactured by kinseki, ltd.), cl = 12 pf c1 = c2 = 15 pf the circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and oth er items. therefore we recommend consulting with the manufacturer of the crystal for evaluation and reliability. parameter symbol pins conditions min typ max unit supply voltage v dd v dd 2.7 3.6 v input high-level voltage v ih 1 ce, cl, di 0.7 v dd 5.5 v v ih 2 io1, io2 0.7 v dd 13 v input low-level voltage v il ce, cl, di, io1, io2 0 0.3 v dd v v o 1do 0 5.5 v output voltage v o 2 bo1 to bo4, io1, io2, 013v aout f in 1xin v in 118mhz f in 2-1 fmin v in 2-1 10 90 mhz f in 2-2 fmin v in 2-2 10 120 mhz input frequency f in 2-3 fmin v in 2-1, v dd 3.0 v 10 130 mhz f in 3 amin v in 3, sns = 1 2 40 mhz f in 4 amin v in 4, sns = 0 0.5 10 mhz f in 5 ifin v in 5 0.4 12 mhz v in 1xin f in 1 400 900 mvrms v in 2-1 fmin f in 2-1, f in 2-3 70 900 mvrms v in 2-2 fmin f in 2-2 100 900 mvrms input amplitude v in 3 amin f in 3, sns = 1 70 900 mvrms v in 4 amin f in 4, sns = 0 70 900 mvrms v in 5-1 ifin f in 5, ifs = 1 70 900 mvrms v in 5-2 ifin f in 6, ifs = 0 100 900 mvrms supported crystals xtal xin, xout * 4.0 8.0 mhz c 2 c 1 xout xin lc72133m lc72133v a11904
no. 5427-4/23 lc72133m, 72133v electrical characteristics for the allowable operating ranges at ta = ?20 to +70c, v ss = 0 v parameter symbol pins conditions min typ max unit rf1 xin 1.0 m built-in feedback resistance rf2 fmin 500 k rf3 amin 500 k rf4 ifin 250 k built-in pull-down resistor rpd1 fmin 200 k rpd2 amin 200 k hysteresis v his ce, cl, di, io1, io2 0.1 v dd v output high level voltage v oh 1pd i o = ?1 ma v dd ? 1.0 v v ol 1pd i o = 1 ma 1.0 v v ol 2bo1 i o = 0.5 ma 0.6 v i o = 1 ma 1.2 v output low level voltage v ol 3do i o = 1 ma 0.25 v i o = 3 ma 0.75 v v ol 4 bo2 to bo4, io1, io2 i o = 1 ma 0.25 v i o = 5 ma 1.25 v v ol 5aout i o = 1 ma, ain = 1.3 v 0.5 v i ih 1 ce, cl, di v i = 5.5 v 5.0 a i ih 2 io1, io2 v i = 13 v 5.0 a input high level current i ih 3xin v i = v dd 1.3 8 a i ih 4 fmin, amin v i = v dd 2.7 15 a i ih 5 ifin v i = v dd 5.4 30 a i ih 6ain v i = 5.5 v 200 na i il 1 ce, cl, di v i = 0 v 5.0 a i il 2 io1, io2 v i = 0 v 5.0 a input low level current i il 3xin v i = 0 v 1.3 8 a i il 4 fmin, amin v i = 0 v 2.7 15 a i il 5 ifin v i = 0 v 5.4 30 a i il 6ain v i = 0 v 200 na i off 1 bo1 to bo4, aout, v o = 13 v 5.0 a output off leakage current io1, io2 i off 2do v o = 5.5 v 5.0 a high level three-state i offh pd v o = v dd 0.01 200 na off leakage current low level three-state i offl pd v o = 0 v 0.01 200 na off leakage current input capacitance c in fmin 6pf xtal = 7.2 mhz, i dd 1v dd f in 2 = 130 mhz, 2 5 ma v in 2 = 70 mvrms pll block stopped current drain i dd 2v dd (pll inhibit), 0.3 ma xtal oscillator operating (xtal = 7.2 mhz) i dd 3v dd pll block stopped 30 a xtal oscillator stopped
pin assignment block diagram no. 5427-5/23 lc72133m, 72133v 1 xin 20 xout 2 ce 19 v ss 3 di 18 aout 4 cl 17 ain 5 do 16 pd 6 15 v dd 7 bo1 14 fmin 8 bo2 13 amin 9 bo3 12 10 io1 11 ifin s s s s s bo4 io2 a11902 top view xin xout fmin amin ce di cl do v dd v ss power on reset ccb i/f data shift register latch bo1 bo2 bo3 bo4 io1 io2 12bits programmable divider swallow counter 1/16, 1/17 4bits 1/2 phase detector charge pump unlock detector universal counter pd ain aout ifin a11903 reference divider 1 20 14 13 2 3 4 5 15 19 6 7 8 9 10 12 11 18 17 16
pin functions no. 5427-6/23 lc72133m, 72133v symbol pin no. type functions circuit configuration xin xout fmin amin ce cl di do v dd 1 20 14 13 2 4 3 5 15 xtal osc local oscillator signal input local oscillator signal input chip enable clock data input data output power supply ? crystal resonator connection (4.5/7.2 mhz) ? fmin is selected when the serial data input dvs bit is set to 1. ? the input frequency range is from 10 to 130 mhz. ? the input signal passes through the internal divide-by- two prescaler and is input to the swallow counter. ? the divisor can be in the range 272 to 65535. however, since the signal has passed through the divide-by-two prescaler, the actual divisor is twice the set value. ? amin is selected when the serial data input dvs bit is set to 0. ? when the serial data input sns bit is set to 1: ? the input frequency range is 2 to 40 mhz. ? the signal is directly input to the swallow counter. ? the divisor can be in the range 272 to 65535, and the divisor used will be the value set. ? when the serial data input sns bit is set to 0: ? the input frequency range is 0.5 to 10 mhz. ? the signal is directly input to a 12-bit programmable divider. ? the divisor can be in the range 4 to 4095, and the divisor used will be the value set. set this pin high when inputting (di) or outputting (do) serial data. ? used as the synchronization clock when inputting (di) or outputting (do) serial data. ? inputs serial data transferred from the controller to the lc72133. ? outputs serial data transferred from the lc72133 to the controller. the content of the output data is determined by the serial data doc0 to doc2. ? the lc72133 power supply pin (v dd = 2.7 to 3.6 v) ? the power on reset circuit operates when power is first applied. continued on next page. operating fmin input frequency conditions 10 to 90 mhz 10 to 120 mhz 10 to 130 mhz operating power- 2.7 to 3.6 v 2.7 to 3.6 v 3.0 to 3.6 v supply voltage operating input 70 to 900 100 to 900 70 to 900 levels mvrms mvrms mvrms a11905 a11906 a11907 a11908 s a11910 s a11910 s a11911
continued from preceding page. no. 5427-7/23 lc72133m, 72133v symbol pin no. type functions circuit configuration v ss bo1 bo2 bo3 bo4 io1 io2 pd ain aout ifin 19 6 7 8 9 10 12 16 17 18 11 ground output port i/o port charge pump output lpf amplifier transistor if counter ? the lc72133 ground ? ? dedicated output pins ? the output states are determined by bo1 to bo4 bits in the serial data. data: 0 = open, 1 = low ? a time base signal (8 hz) can be output from the bo1 pin. (when the serial data tbc bit is set to 1.) ? care is required when using the bo1 pin, since it has a higher on impedance than the other output ports (pins bo2 to bo4). ? the data = 0 (open) state is selected after the power-on reset. ? i/o dual-use pins ? the direction (input or output) is determined by bits ioc1 and ioc2 in the serial data. data: 0 = input port, 1 = output port ? when specified for use as input ports: the state of the input pin is transmitted to the controller over the do pin. input state: low = 0 data value high = 1 data value ? when specified for use as output ports: the output states are determined by the io1 and io2 bits in the serial data. data: 0 = open, 1 = low ? these pins function as input pins following a power on reset. ? pll charge pump output when the frequency generated by dividing the local oscillator frequency by n is higher than the reference frequency, a high level is output from the pd pin. similarly, when that frequency is lower, a low level is output. the pd pin goes to the high impedance state when the frequencies match. ? the n-channel mos transistor used for the pll active low-pass filter. ? accepts an input in the frequency range 0.4 to 12 mhz. ? the input signal is directly transmitted to the if counter. ? the result is output starting the msb of the if counter using the do pin. ? four measurement periods are supported: 4, 8, 32, and 64 ms. a11912 a11913 s a11914 a11915 a11916
serial data i/o methods the lc72133 inputs and outputs data using the sanyo ccb (computer control bus) audio lsi serial bus format. this lsi adopts an 8-bit address format ccb. no. 5427-8/23 lc72133m, 72133v i/o mode address function b0 b1 b2 b3 a0 a1 a2 a3 1 2 3 in1 (82) in2 (92) out (a2) 0 001 0 100 1 001 0 100 0 101 0 100 ? control data input mode (serial data input) ? 24 data bits are input. ? see the ?di control data (serial data input) structure? item for details on the meaning of the input data. ? control data input mode (serial data input) ? 24 data bits are input. ? see the ?di control data (serial data input) structure? item for details on the meaning of the input data. data output mode (serial data output) ? the number of bits output is equal to the number of clock cycles. ? see the ?do output data (serial data output) structure? item for details on the meaning of the output data. first data in1/2 first data out first data out i/o mode determined b0 b1 b2 b3 a0 a1 a2 a3 ce cl di do ? ? ? ? ? cl: normal high ? cl: normal low a11917
1. di control data (serial data input) structure ? in1 mode ? in2 mode no. 5427-9/23 lc72133m, 72133v di 00010100 p0 p1 p2 p3 p4 p5 p6 p7 p8 (1) p-ctr (3) if-ctr (2) r-ctr p9 p10 p11 p12 p13 p14 p15 sns dvs cte xs r0 r1 r2 r3 address a11918 first data in1 di 10010100 ioc1 ioc2 io1 io2 bo1 bo2 bo3 bo4 dnc (10) pd-c (11) ifs (12) test doc0 doc1 doc2 ul0 ul1 dz0 dz1 gt0 gt1 tbc dlc ifs test0 test1 test2 (9) time (13) don't care (5) o-port (4) io-c (3) if-ctr (8) dz-c (7) unlock (6) do-c address a11919 first data in2
2. di control data functions no. 5427-10/23 lc72133m, 72133v no. control block/data functions related data programmable divider data ? data that sets the programmable divider. p0 to p15 a binary value in which p15 is the msb. the lsb changes depending on dvs and sns. ( * : don?t care) note: p0 to p3 are ignored when p4 is the lsb. dvs, sns ? selects the signal input pin (amin or fmin) for the programmable divider, switches the input frequency range. ( * : don?t care) note: see the ?programmable divider? item for more information. reference divider data ? reference frequency (fref) selection data. r0 to r3 note: pll inhibit the programmable divider block and the if counter block are stopped, the fmin, amin, and ifin pins are set to the pull-down state (ground), and the charge pump goes to the high impedance state. xs ? crystal resonator selection xs = 0: 4.5 mhz xs = 1: 7.2 mhz the 7.2 mhz frequency is selected after the power-on reset. if counter control data ? if counter measurement start data cte cte = 1: counter start cte = 0: counter reset gt0, gt1 ? determines the if counter measurement period. ifs note: see the ?if counter? item for more information. i/o port specification data ? specifies the i/o direction for the bidirectional pins io1 and io2. ioc1, ioc2 data: 0 = input mode, 1 = output mode output port data ? data that determines the output from the bo1 to bo4, io1 and io2 output ports bo1 to bo4, io1, io2 data: 0 = open, 1 = low ? the data = 0 (open) state is selected after the power-on reset. (1) (2) (3) (4) (5) ioc1 ioc2 dvs sns lsb divisor setting (n) actual divisor 1 * p0 272 to 65535 twice the value of the setting 0 1 p0 272 to 65535 the value of the setting 0 0 p4 4 to 4095 the value of the setting dvs sns input pin input frequency range 1 * fmin 10 to 130 mhz 0 1 amin 2 to 40 mhz 0 0 amin 0.5 to 10 mhz gt1 gt0 measurement time (ms) wait time (ms) 0 0 4 3 to 4 0 1 8 3 to 4 1 0 32 7 to 8 1 1 64 7 to 8 r3 r2 r1 r0 reference frequency (khz) 0000 100 0001 50 0010 25 0011 25 0 1 0 0 12.5 0 1 0 1 6.25 0 1 1 0 3.125 0 1 1 1 3.125 1000 10 1001 9 1010 5 1011 1 1100 3 1101 15 1 1 1 0 pll inhibit + xtal osc stop 1 1 1 1 pll inhibit continued on next page.
continued from preceding page. no. 5427-11/23 lc72133m, 72133v no. control block/data functions related data do pin control data ? data that determines the do pin output doc0, doc1, doc2 the open state is selected after the power-on reset. note: 1. end-uc: check for if counter measurement completion ? when end-uc is set and the if counter is started (i.e., when cte is changed from zero to one), the do pin automatically goes to the open state. ? when the if counter measurement completes, the do pin goes low to indicate the measurement completion state. ? depending on serial data i/o (ce: high) the do pin goes to the open state. 2. goes to the open state if the i/o pin is specified to be an output port. caution: the state of the do pin during a data input period (an in1 or in2 mode period with ce high) will be open, regardless of the state of the do control data (doc0 to doc2). also, the do pin during a data output period (an out mode period with ce high) will output the contents of the internal do serial data in synchronization with the cl pin signal, regardless of the state of the do control data (doc0 to doc2). unlock detection data ? selects the phase error (?e) detection width for checking pll lock. ul0, ul1 a phase error in excess of the specified detection width is seen as an unlocked state. note: in the unlocked state the do pin goes low and the ul bit in the serial data becomes zero. phase comparator ? controls the phase comparator dead zone. control data dz0, dz1 dead zone widths: dza < dzb < dzc < dzd clock time base setting tbc to one causes an 8 hz, 40% duty clock time base signal to be output tbc from the bo1 pin. (bo1 data is invalid in this mode.) charge pump control data ? forcibly controls the charge pump output. dlc note: if deadlock occurs due to the vco control voltage (vtune) going to zero and the vco oscillator stopping, deadlock can be cleared by forcing the charge pump output to low and setting vtune to v cc . (this is the deadlock clearing circuit.) (6) (7) (8) (9) (10) ul0, ul1, cte, ioc1, ioc2 doc0, doc1, doc2 bo1 doc2 doc1 doc0 do pin state 0 0 0 open 0 0 1 low when the unlock state is detected 0 1 0 end-uc * 1 0 1 1 open 1 0 0 open 1 0 1 the io1 pin state * 2 1 1 0 the io2 pin state * 2 1 1 1 open ul1 ul0 ?e detection width detector output 0 0 stopped open 0 1 0 ?e is output directly 1 0 0.55 s ?e is extended by 1 to 2 ms 1 1 1.11 ?e is extended by 1 to 2 ms dz1 dz0 dead zone mode 00dza 01dzb 10dzc 11dzd dlc charge pump output 0 normal operation 1 forced low continued on next page. do pin ? counter start ? counter complete ? ce: high a11920
continued from preceding page. 3. do output data (serial data output) ? out mode 4. do output data no. 5427-12/23 lc72133m, 72133v no. control block/data functions related data if counter control data ? note that if this value is set to zero the system enters input sensitivity degradation mode, (11) ifs and the sensitivity is reduced to 10 to 30 mv rms. * see the ?if counter operation? item for details. lsi test data ? lsi test data test 0 to test 2 test0 (12) test1 these values must all be set to 0. test2 these test data are set to 0 automatically after the power-on reset. (13) dnc don?t care. this data must be set to 0. no. control block/data functions related data i/o port data ? latched from the pin states of the io1 and io2 i/o ports. i2, i1 ? these values follow the pin states regardless of the input or output setting. ? data is latched at the point where the circuit enters data output mode (out mode). i1 io1 pin state high: 1 i2 io2 pin state low: 0 pll unlock data ? latched from the state of the unlock detection circuit. ul ul 0: unlocked ul 1: locked or detection stopped mode if counter binary data ? latched from the value of the if counter (20-bit binary counter). c19 to c0 c19 msb of the binary counter c0 lsb of the binary counter (1) (2) (3) ioc1, ioc2 ul0, ul1 cte, gt0, gt1 di 01010100 do i2 (1) in-port (2) unlock (3) if-ctr i1 ? ul c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 address a11921 ? : "0" data first data out
5. serial data input (in1/in2) t su , t hd , t el , t es , t eh 0.75 s, t lc < 0.75 s 6. serial data output (out) t su , t hd , t el , t es , t eh 0.75 s, t dc , t dh < 0.35 s note: since the do pin is an n-channel open-drain circuit, the time for the data to change (t dc and t dh ) will differ depending on the value of the pull-up resistor and printed circuit, board capacitance. no. 5427-13/23 lc72133m, 72133v t su t hd b0 b1 b2 b3 a0 a1 a2 a3 p0 p1 p2 p3 r0 r1 r2 r3 ce cl di t el t es t eh t lc a11922 t su t hd b0 b1 b2 b3 a0 a1 a2 a3 p0 p1 p2 p3 r0 r1 r2 r3 ce cl di t el t es t eh t lc a11923 t su t hd b0 b1 b2 b3 a0 a1 a2 a3 i2 i1 ul c3 c2 c1 c0 ce cl di do t el t es t eh t dh t dc t dc a11924 t su t hd b0 b1 b2 b3 a0 a1 a2 a3 i2 i1 ul c3 c2 c1 c0 ce cl di do t el t es t eh t dh t dc t dc a11925 internal data internal data ? cl: normal high ? cl: normal low ? cl: normal high ? cl: normal low
7. serial data timing no. 5427-14/23 lc72133m, 72133v parameter symbol pins conditions min typ max unit data setup time t su di, cl 0.75 s data hold time t hd di, cl 0.75 s clock low-level time t cl cl 0.75 s clock high-level time t ch cl 0.75 s ce wait time t el ce, cl 0.75 s ce setup time t es ce, cl 0.75 s ce hold time t eh ce, cl 0.75 s data latch change time t lc 0.75 s t dc do, cl differs depending on the 0.35 s data output time value of the pull-up resistor and the printed circuit board t dh do, ce capacitances. t dc t dc t dh t lc t eh t es t el t cl t ch t hd t su v ih v ih v ih v ih v il v ih v il v ih v il v il v il v il ce cl di do a11926 t dc t dh t lc t eh t es t el t ch t cl t hd t su v ih v ih v ih v ih v il v ih v il v ih v il v il v il ce cl di do a11927 internal data latch internal data latch when stopped with cl high when stopped with cl low old old new new
programmable divider structure note: * don?t care. 1. programmable divider calculation examples ? fm, 50 khz steps (dvs = 1, sns = *, fmin selected) fm rf = 80.0 mhz (if = ?10.7 mhz) fm vco = 69.3 mhz pll fref = 25 khz (r0 to r1 = 1, r2 to r3 = 0) 69.3 mhz (fm vco) 25 khz (fref) 2 (fmin: divide-by-two prescaler) = 1386 056a (hex) ? sw, 5 khz steps (dvs = 0, sns = 1, amin high speed side selected) sw rf = 21.75 mhz (if = +450 khz) sw vco = 22.20 mhz pll fref = 5 khz (r0 = r2 = 0, r1 = r3 = 1) 22.2 mhz (sw vco) 5 khz (fref) = 4440 1158 (hex) ? mw, 10 khz steps (dvs = 0, sns = 0, amin low-speed side selected) mw rf = 1000 khz (if = +450 khz) mw vco = 1450 khz pll fref = 10 khz (r0 to r2 = 0, r3 = 1) 1450 khz (mw vco) 10 khz (fref) = 145 091 (hex) no. 5427-15/23 lc72133m, 72133v dvs sns input pin set divisor actual divisor: n input frequency range (mhz) a1 * fmin 272 to 65535 twice the set value 10 to 130 b 0 1 amin 272 to 65535 the set value 2 to 40 c 0 0 amin 4 to 4095 the set value 0.5 to 10 fvco/n fref pd ?e fvco = fref n programmable divider (c) (b) (a) swallow counter 4bits 12bits 1/2 dvs sns amin fmin a11928 a11929 a650 0101011010100000 * 11100 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 sns dvs cte xs r0 r1 r2 r3 a11930 8511 000110101000100010 0101 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 sns dvs cte xs r0 r1 r2 r3 a11931 190 **** 10001001000000 0001 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 sns dvs cte xs r0 r1 r2 r3
if counter structure the lc72133 if counter is a 20-bit binary counter. the result, i.e., the counter?s msb, can be read serially from the do pin. the if frequency (fc) is measured by determining how many pulses were input to an if counter in a specified measurement period, gt. fc = (c = fc gt) c: count value (number of pulses) 1. if counter frequency calculation examples ? when the measurement period (gt) is 32 ms, the count (c) is 53980 hexadecimal (342400 decimal): if frequency (fc) = 342400 32 ms = 10.7 mhz ? when the measurement period (gt) is 8 ms, the count (c) is e10 hexadecimal (3600 decimal): if frequency (fc) = 3600 8 ms = 450 khz c gt no. 5427-16/23 lc72133m, 72133v gt1 gt0 measurement time measurement period (gt) (ms) wait time (twu) (ms) 0 0 4 3 to 4 0 1 8 3 to 4 1 0 32 7 to 8 1 1 64 7 to 8 l s b m s b 0 to 3 4 to 7 8 to 11 12 to 15 16 to 19 cte do pin (c) a11932 c = fc gt (fc) (gt) gt0 gt1 4/8/32/64 ms ifin a11933 5398 0 01010011100110000000 i2 i1 ul c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 a11934 00e1 0 00000000111000010000 i2 i1 ul c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 if counter (20-bit binary counter)
2. if counter operation before starting the if count, the if counter must be reset in advance by setting cte in the serial data to 0. the if count is started by changing the cte bit in the serial data from 0 to 1. the serial data is latched by the lc72133 when the ce pin is dropped from high to low. the if signal must be supplied to the ifin pin in the period between the point the ce pin goes low and the end of the wait time at the latest. next, the value of the if counter at the end of the measurement period must be read out during the period that cte is 1. this is because the if counter is reset when cte is set to 0. note: when operating the if counter, the control microprocessor must first check the state of the if-ic sd (station detect) signal and only after determining that the sd signal is present turn on if buffer output and execute an if count operation. autosearch techniques that use only the if counter are not recommended, since it is possible for if buffer leakage output to cause incorrect stops at points where there is no station. ifin minimum input sensitivity standard f (mhz) note: values in parentheses are actual performance values presented as reference data. no. 5427-17/23 lc72133m, 72133v ifs 0.4 f < 0.5 0.5 f < 8 8 f 12 1: normal mode 70 mvrms 70 mvrms 70 mvrms (0.5 to 5 mvrms) (2 to 10 mvrms) 0: degradation mode 100 mvrms 100 mvrms 100 mvrms (10 to 15 mvrms) (30 to 50 mvrms) ce ifin gt a11935 frequency measurement period data with cte = 1 wait time measurement period count start count end (end-uc)
unlock detection timing 1. unlock detection determination timing unlocked state detection is performed in the reference frequency (fref) period (interval). therefore, in principle, unlock determination requires a time longer than the period of the reference frequency. however, immediately after changing the divisor n (frequency) unlock detection must be performed after waiting at least two periods of the reference frequency. figure 1 unlocked state detection timing for example, if fref is 1 khz, i.e., the period is 1 ms, after changing the divisor n, the system must wait at least 2 ms before checking for the unlocked state. figure 2 circuit structure no. 5427-18/23 lc72133m, 72133v a11936 ce data latch vco/n n- counter fref r n data latch vco preset fref vco/n unlock l. p. f a11937 ?error (unlock) old data new data old divisor n new divisor n' the divisor n is not updated in the first period. note: after changing the divisor, ?error is output after two fref periods. unlock detection circuit phase comparator ?error
2. unlock detection software figure 3 3. unlocked state data output using serial data output in the lc72133, once an unlocked state occurs, the unlocked state serial data (ul) will not be reset until a data input (or output) operation is performed. at the data output point in figure 3, although the vco frequency has stabilized (locked), since no data output has been performed since the divisor n was changed the unlocked state data remains in the unlocked state. as a result, even though the frequency has stabilized (locked), the system remains (from the standpoint of the data) in the unlocked state. therefore, the unlocked state data acquired at data output , which occurs immediately after the divisor n was changed, should be treated as a dummy data output and ignored. the second data output (data output ? ) and following outputs are valid data. locked state determination flowchart 4. directly outputting unlocked state data from the do pin (set by the do pin control data) since the locking state (high = locked, low = unlocked) is output directly from the do pin, the dummy data processing described in section 3 above is not required. after changing the divisor n, the locking state can be checked after waiting at least two reference frequency periods. no. 5427-19/23 lc72133m, 72133v a11938 ce * yes no n vco frequency ?error unlock (ul) serial data input unlock detection pin output data input data output ? data output ? old data new data locked locked unlocked divisor n modification (data input) dummy data output valid data output locked? ............... ............... wait for at least two reference frequency periods. valid data can be output at intervals of one reference frequency period or longer note: locking state determination is more reliable if it is based on reading valid output data several times.
clock time base usage notes the pull-up resistor used on the clock time base output pin (bo1) should be at least 100 k . also, to prevent chattering we recommend using a schmitt input at the controller (microprocessor) that receives this signal. this is to prevent degrading the vco c/n characteristics when a loop filter is formed using the built-in low-pass filter transistor. since the clock time base output pin and the low-pass filter have a common ground internal to the ic, it is necessary to minimize the time base output pin current fluctuations and to suppress their influence on the low-pass filter. other items 1. notes on the phase comparator dead zone since correction pulses are output from the charge pump even if the pll is locked when the charge pump is in the on/on state, the loop can easily become unstable. this point requires special care when designing application circuits. the following problems may occur in the on/on state. ? side band generation due to reference frequency leakage ? side band generation due to both the correction pulse envelope and low frequency leakage schemes in which a dead zone is present (off/off) have good loop stability, but have the problem that acquiring a high c/n ratio can be difficult. on the other hand, although it is easy to acquire a high c/n ratio with schemes in which there is no dead zone, it is difficult to achieve high loop stability. therefore, it can be effective to select dza or dzb, which have no dead zone, in applications which require an fm s/n ratio in excess of 90 to 100 db, or in which an increased am stereo pilot margin is desired. on the other hand, we recommend selecting dzc or dzd, which provide a dead zone, for applications which do not require such a high fm signal-to-noise ratio and in which either am stereo is not used or an adequate am stereo pilot margin can be achieved. no. 5427-20/23 lc72133m, 72133v dz1 dz0 dead zone mode charge pump dead zone 0 0 dza on/on ? ?0 s 0 1 dzb on/on ?0 s 1 0 dzc off/off +0 s 1 1 dzd off/off + +0 s s rt 100 k v dd v cc vco vt aout ain pd lc72133m lc72133v a11939 bo1 microprocessor schmitt input time base output loop filter
dead zone the phase comparator compares fp to a reference frequency (fr) as shown in figure 4. although the characteristics of this circuit (see figure 5) are such that the output voltage is proportional to the phase difference ? (line a), a region (the dead zone) in which it is not possible to compare small phase differences occurs in actual ics due to internal circuit delays and other factors (line b). a dead zone as small as possible is desirable for products that must provide a high s/n ratio. however, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularly- priced products. this is because it is possible for rf signals to leak from the mixer to the vco and modulate the vco in popularly-priced products in the presence of strong rf inputs. when the dead zone is narrow, the circuit outputs correction pulses and this output can further modulate the vco and generate beat frequencies with the rf signal. figure 4 figure 5 2. notes on the fmin, amin, and ifin pins coupling capacitors must be placed as close as possible to their respective pin. a capacitance of about 100 pf is desirable. in particular, if a capacitance of 1000 pf or over is used for the if pin, the time to reach the bias level will increase and incorrect counting may occur due to the relationship with the wait time. 3. notes on if counting sd must be used in conjunction with the if counting time when using if counting, always implement if counting by having the microprocessor determine the presence of the if-ic sd (station detect) signal and turn on the if counter buffer only if the sd signal is present. schemes in which auto-searches are performed with only if counting are not recommended, since they can stop at points where there is no signal due to leakage output from the if counter buffer. 4. do pin usage techniques in addition to data output mode times, the do pin can also be used to check for if counter count completion and for unlock detection output. also, an input pin state can be output unchanged through the do pin and input to the controller. 5. power supply pins a capacitor of at least 2000 pf must be inserted between the power supply v dd and v ss pins for noise exclusion. this capacitor must be placed as close as possible to the v dd and v ss pins. 6. vco setup applications must be designed so that the vco (local oscillator) does not stop, even if the control voltage (vtune) goes to 0v. if it is possible for the oscillator to stop, the application must use the control data (dlc) to temporarily force vtune to v cc to prevent the deadlock from occuring. (deadlock clear circuit) 7. front end connection example since this product is designed with the relatively high resistance of 200 k for the pull-down (on) resistors built in to the fmin and amin pins, a common am/fm local oscillator buffer can be used as shown in the following circuit. no. 5427-21/23 lc72133m, 72133v reference divider fr programmable divider fp phase detector lpf vco mix rf a11940 a11941 (a) (b) ? (ns) dead zone v
no. 5427-22/23 lc72133m, 72133v fmin pll fe amin fm osc am osc osc buffer out a10186 on resistance: 200 k on resistance: 200 k a11943 xin ce di cl do bo1 bo2 bo3 bo4 xout v ss aout ain pd v dd fmin amin io2 io1 ifin open open open open open input port input port lc72133m lc72133v
ps no.5427-23/23 lc72133m, 72133v this catalog provides information as of september, 1999. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer?s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer?s products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are contr olled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?delivery specification? for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. application system example 1 xin 20 xout 2 ce 19 v ss 3 di 18 aout 4 cl 17 ain 5 do ce di cl do 16 pd 6 bo1 15 v dd 7 bo2 14 fmin 8 bo3 13 amin 9 bo4 12 io2 10 io1 11 ifin s s s s s lc72133m lc72133v -com unlock sd end-uc ifcount st-indie amvco fmvco fm/am-if tuner-system sd if-request fm/am mono/st st-indicate v cc a11944 this section is susceptible to noise due to its high impedance. therefore, the pattern lines should be kept as short as possible and this area should be coverd with a ground pattern.

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