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esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 1/12 psram 8-mbit (512k x 16) pseudo static ram features ? advanced low-power architecture ? high speed: 55 ns, 70 ns ? wide voltage range: 2.7v to 3.6 v ? typical active current: 2 ma @ f = 1 mhz ? typical active current: 11 ma @ f = f max ? low standby power ? automatic power-down when deselected functional description the M24L816512DA is a high-performance cmos pseudo static ram (psram) organized as 512k words by 16 bits that supports an asynchronous memory interface. this device features advanced circuit design to provide ultra-low active current. this is ideal for portable applications such as cellular telephones. the device can be put into standby mode reducing power consumption dr amatically when deselected ( 1 ce low, ce2 high or both bhe and ble are high). the input/output pins(i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected ( 1 ce high, ce2 low), oe is deasserted high, or during a write operation (chip enabled and write enable we low). reading from the device is accomplished by asserting the chip enables ( 1 ce low and ce2 high) and output enable ( oe ) low while forcing the write enable ( we ) high. if byte low enable ( ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable ( bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table for a complete description of read and write modes. logic block diagram
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 2/12 pin configuration[2, 3, 4] 48-ball vfbga top view product portfolio product power dissipation operating i cc (ma) v cc range (v) f = 1mhz f = f max standby, i sb2 (a) product min. typ. max. speed(ns) typ.[5] max. typ.[5] max. typ. [5] max. 55 22 M24L816512DA 2.7 3.0 3.6 70 2 5 11 17 55 100 110(for v cc >3.3v ) notes: 2.dnu pins are to be left floating or tied to vss. 3.ball g2, h6 are the address expansion pins for the 16-mbit and 32-mbit densities respectively. 4.nc ?no connect??not connect ed internally to the die. 5.typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc (typ) and t a = 25c.
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 3/12 maximum ratings (above which the useful life may be impaired. for user guide-lines, not tested.) storage temperature .............. ................ ...?65c to +150c ambient temperature with power applied ..............................................?40c to +85c supply voltage to gr ound potential ................ ? 0.4v to 4.6v dc voltage applied to outputs in high-z state[6, 7, 8] ....................................... ? 0.4v to 3.7v dc input voltage[6, 7, 8] .............. ............ .......... ? 0.4v to 3.7v output current into outputs (low) ............................20 ma static discharge voltage ........ ................ ............... .. > 2001v (per mil-std-883, method 3015) latch-up current ...... .............. ................ ............... .> 200 ma operating range range ambient temperature (t a ) v cc extended ? 25c to +85c 2.7v to 3.6v industrial ? 40c to +85c 2.7v to 3.6v dc electrical characteristics (over the operating range) [5, 6, 7, 8] -55 -70 parameter description test conditions min. typ .[5] max. min. typ. [5] max. unit v cc supply voltage 2.7 3.0 3.6 2.7 3.6 v v oh output high voltage i oh = ? 0.1 ma v cc - 0.4 v cc - 0.4 v v ol output low voltage i ol = 0.1 ma 0.4 0.4 v v ih input high voltage 0.8* v cc v cc + 0.4v 0.8* v cc v cc +0 .4v v v il input low voltage f = 0 -0.4 0.4 -0.4 0.4 v i ix input leakage current gnd v in < v cc -1 +1 -1 +1 a i oz output leakage current gnd v out v cc , output disabled -1 +1 -1 +1 a f = f max = 1/t rc 11 22 11 17 i cc v cc operating supply current f = 1 mhz v cc = 3.6v i out = 0ma cmos level 2 5 2 5 ma i sb1 automatic ce power-down current ?cmos inputs ce v cc ? 0.2v, v in v cc ? 0.2v, v in 0.2v, f = f max (address and data only), f = 0 ( oe , we , bhe and ble ) 100 400 100 400 a v cc = 3.3v 100 100 i sb2 automatic ce power-down current ?cmos inputs ce v cc ? 0.2v, v in v cc ? 0.2v or v in 0.2v, f = 0 v cc = 3.6v 55 110 55 110 a capacitance[9] parameter description test conditions max. unit c in input capacitance 8 pf c out output capacitance t a = 25c, f = 1 mhz v cc = v cc(typ) 8 pf thermal resistance[9] parameter description test conditions bga unit ja thermal resistance(junction to ambient) 55 c/w jc thermal resistance (junction to case) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/ jesd51. 17 c/w notes: 6.v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 7.v il(min) = ?0.5v for pulse durations less than 20 ns. 8.overshoot and undershoot s pecifications are characteri zed and are not 100% tested. 9.tested initially and after design or process changes that may affect these parameters.
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 4/12 ac test loads and waveforms parameters 3.0v v cc unit r1 22000 ? r2 22000 ? r th 11000 ? v th 1.50 v switching characteristics over the operating range[10, 11, 12, 13, 14] -55 -70 parameter description min. max. min. max. unit read cycle t rc read cycle time 55[14] 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 5 5 ns t ace 1 ce low and ce2 high to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z[11, 12] 5 5 ns t hzoe oe high to high z[11, 12] 25 25 ns t lzce 1 ce low and ce2 high to low z[11, 12] 5 5 ns t hzce 1 ce high and ce2 low to high z[11, 12] 25 25 ns t dbe ble / bhe low to data valid 55 70 ns t lzbe ble / bhe low to low z[11, 12] 5 5 ns t hzbe ble / bhe high to high z[11, 12] 10 25 ns t sk [14] address skew 0 10 ns notes: 10. test conditions assume signal transition time of 1v/ns or higher, timing reference levels of v cc(typ) /2, input pulse levels of 0v to v cc(typ) , and output loading of the specified i ol /i oh and 30-pf load capacitance 11. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the out puts enter a high-impedance state. 12. high-z and low-z parameters are characterized and are not 100% tested. 13. the internal write time of the memory is defined by the overlap of we , 1 ce = v il , ce2 = v ih , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. to achieve 55-ns performance, the read access should be ce controlled. in this case t ace is the critical parameter and t sk is satisfied when the addresses are stable prior to chip enab le going active. for the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 5/12 switching characteristics (over the operat ing range) (continued)[10, 11, 12, 13, 14] -55 -70 parameter description min. max. min. max. unit write cycle[13] t wc write cycle time 55 70 ns t sce 1 ce low and ce2 high to write end 45 55 ns t aw address set-up to write end 45 55 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 55 ns t bw ble / bhe low to write end 50 55 ns t sd data set-up to write end 42 42 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z[11, 12] 25 25 ns t lzwe we high to low-z[11, 12] 5 5 ns switching waveforms read cycle 1 (address transition controlled)[14, 15, 16] read cycle 2 ( oe controlled)[14, 15] notes: 15. we is high for read cycle. 16. device is continuously selected. oe , ce = v il
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 6/12 switching waveforms (continued) write cycle 1 ( we controlled) [12, 13, 17, 18, 19] write cycle 2 ( 1 ce or ce2 controlled) [12, 13, 17, 18, 19] notes: 17.data i/o is high impedance if oe v ih . 18.if chip enable goes in active simultaneously with we = high, the output remains in a high-impedance state. 19.during the don?t care period in the data i/o waveform, the i/os are in out put state and input signals should not be applied.
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 7/12 switching waveforms (continued) write cycle 3 ( we controlled, oe low)[18, 19] write cycle 4 ( bhe / ble controlled, o e low)[18, 19]
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 8/12 avoid timing esmt pseudo sram has a timing which is not s upported at read operation, if your system has multiple invalid address signal shorter than trc during over 15 s at read operation shown as in abnormal timing, it requires a normal read timing at leat during 15 s shown as in avoidable timing 1 or toggle 1 ce to high ( R t rc ) one time at least shown as in avoidable timing 2. abnormal timing avoidable timing 1 avoidable timing 2 ce1 15 s R we address t rc ce1 15 s R we address t R rc ce1 15 s R we address t rc t R rc
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 9/12 truth table[20] 1 ce ce2 we oe bhe ble inputs/outputs mode power h x x x x x high z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read (upper byte and lower byte) active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); (i/o 8 ?i/o 15 ) in high z read (lower byte only) active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); (i/o 0 ?i/o 7 ) in high z read (upper byte only) active (i cc ) l h h h l l high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l h high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write (upper byte and lower byte) active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); (i/o 8 ?i/o 15 ) in high z write (lower byte only) active (i cc ) l h l x l h data out (i/o 8 ?i/o 15 ); (i/o 0 ?i/o 7 ) in high z write (upper byte only) active (i cc ) ordering information speed (ns) ordering code package type operating range 55 M24L816512DA- 55beg 48-ball very fine pitch bga (6.0 x 8.0 x 1.2 mm) (pb-free) extended 70 M24L816512DA - 70beg 48-ball very fine pitch bga (6.0 x 8.0 x 1.2 mm) (pb-free) extended 55 M24L816512DA-55big 48-ball very fine pitch bg a (6.0 x 8.0 x 1.2 mm) (pb-free) industrial 70 M24L816512DA-70big 48-ball very fine pitch bg a (6.0 x 8.0 x 1.2 mm) (pb-free) industrial note: 20.h = logic high, l = logic low, x = don?t care.
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 10/12 package diagrams 48-ball (6 mm x 8mm x 1.2 mm) fbga
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 11/12 revision history revision date description 1.0 2007.07.04 original 1.1 2008.07.04 1. move revision history to the last 2. modify voltage range 2.7v~3.3v to 2.7v~3.6v 3. add industrial grade 4. add avoid timing
esmt M24L816512DA elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.1 12/12 important notice all rights reserved. no part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the produ cts or specification in this document without notice. the information contained h erein is presented only as a guide or examples for the application of our products. no res ponsibility is assumed by esmt for any infringement of patents, co pyrights, or other intellect ual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patent s, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inher ently a certain rate of failure. to minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer w hen making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support device s or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.

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