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? 1 ? e00782e2z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA3314ER 24 pin vqfn (plastic) description the CXA3314ER is a general-purpose pll ic which directly frequency divides rf up to 6ghz in combination with an external vco and loop. features ? low current consumption: 9ma (typ. at v cc = 3v) low voltage operation: 2.7 to 3.3v small package: 24-pin vqfn (plastic) supports sleep mode: 10a (max. at v cc = 3v) data setting by a 3-wire interface reference frequency divider reference counter: 15 bits (3 to 32767) comparison frequency divider fixed frequency division: 4 swallow counter: 5 bits (0 to 31) main counter: 13 bits (3 to 8191) comparison frequency division value: 4 (992 to 262143) built-in charge pump circuit with high-speed pull-in and normal modes lock signal output function applications this ic is ideal for the synthesizers of microwave communications equipment up to 6ghz and general-purpose pll synthesizers such as in high- speed, high frequency measurement equipment. etc (its) related vco modules wireless lan communications high-speed, high frequency measurement equipment structure bipolar silicon monolithic ic absolute maximum ratings (ta = 25c) supply voltage v cc 3.6 v operating temperature topr ?30 to +85 c storage temperature tstg ?65 to +150 c allowable power dissipation p d 900 mw operating condition supply voltage v cc 2.7 to 3.3 v note on esd strength this product has a low esd strength to ensure the high frequency characteristics. sony semiconductor devices are classified into esd strength ranks from a to e based on esd test results according to sony original criteria. these esd ranks are set for each test, and indicate the esd risk for each breakdown model. 6ghz pll
? 2 ? CXA3314ER block diagram and pin configuration 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 10 11 12 24 23 22 21 20 19 v ss lkdet cex data clk le testdis cpout cpv cc sub rfinn rfinp gnd v ss refin rext dmpsw i/2i cpgnd v dd v dd nc nc nc v cc high-speed pull-in control intermittent operation control circuit lock detector 3-wire control reference counter (15 bits) fixed frequency division (4) prescaler cp (fast/slow) test circuit buffer pfd swallow counter (5 bits) main counter (13 bits) dual modulus (32, 33) prescaler
? 3 ? CXA3314ER pin description pin no. symbol v cc 1 sub 21 gnd 24 power supply. substrate. connect to gnd normally. ground. standard dc voltage [v] equivalent circuit description 2, 3, 4 nc no connected. v dd 5, 6 13, 14 v ss power supply for output stage. ground. 15 refin reference frequency signal input. 16 rext internal reference current setting. connect to gnd via a external resistor (1.8k ? ). icp = i 6.7 i i rext icp: charge pump current i: internal reference current i rext : external resistor current internal charge pump current switching. analog circuit block v cc gnd sub 1 21 24 digtal circuit block v dd sub v ss 5 6 21 13 14 v dd v ss sub 15 21 6 13 100 200 100k v dd v ss sub 6 13 16 21 8.5k i 3 ? 3 0 0 0 1/2v cc 0.15
? 4 ? CXA3314ER cpgnd 18 cpout 19 cpv cc 20 ground for the charge pump output. charge pump output. power supply for the charge pump output. rfinn 22 vco signal input. rfinp 23 cpv cc cpgnd sub 18 21 20 19 v cc gnd 24 22 1 23 2000 2000 3 0 ? vcc ? 0.9 vcc ? 0.9 pin no. symbol standard dc voltage [v] equivalent circuit description 17 dmpsw connect to the loop filter via a resistor. v dd v ss sub 13 6 17 21 666 333 ?
? 5 ? CXA3314ER pin description pin no. symbol i/o description 7 8 9 10 11 testdis le clk data cex i i i i i high: active test mode switch pin. low: test mode latch input. clock input. data input. high: power save power save function pins. low: active lock detection signal output. active mode high: lock low: unlock test mode refer to ? 2. test mode setting ? on page 12. 12 lkdet o v dd in v ss 5 6 13 14 v dd out v ss 5 6 12 13 14 equivalent circuit
? 6 ? CXA3314ER electrical characteristics (v cc = 3v, ta = 25 c) symbol conditions unit item max. ty p. min. icc icc (ps) f-rf v-rf f-ref v-ref current flowing to pins 1, 6 and 20 during operation (pin 11 (cex): 0) current flowing to pins 1, 6 and 20 in sleep mode (pin 11 (cex): high) v-rf = ? 10dbm f-rf = 5.845ghz v-ref = 0.2vp-p f-ref = 10mhz ma ? ghz dbm mhz vp-p current consumption current consumption (in sleep mode) operating frequency input level reference input operating frequency reference input level 14 10 6 +10 30 2.0 9 2 ? 12 10 0.2 design reference values symbol conditions unit item max. ty p. min. v ih i ih v il i il r iref r irf on ? ? ? ? dc resistance value dc resistance value dc resistance value v ? v ? k ? ? ? cex data clk le refin input resistance rfinn input resistance pin 17 input resistance v cc +1 gnd + 0.2 +1 100 2000 3000 v cc ? 0.2 ? 1 0 ? 1 high input voltage high input current low input voltage low input current
? 7 ? CXA3314ER electrical characteristics measurement circuit and application circuit 3v 3v 0.1 51 51 100p 100p 0.1 0.1 3v 51 1000p 1.8k sma plane gnd power line terminal 50 ? strip 0.3mm line 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 10 11 12 24 23 22 21 20 19 v ss lkdet cex data clk le testdis cpout cpv cc sub rfinn rfinp gnd v ss refin rext dmpsw cpgnd v dd v dd nc nc nc v cc application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 8 ? CXA3314ER 1. counter frequency division value and pull-in mode setting method the CXA3314ER sets data using the three dt, ck and le signals. at this time, serial data is input as described below. 21-bit serial data is loaded via dt in order from the msb at the rising edge of ck. after 21 bits have been input, the data is actually set at the rising edge of le. dt e = msb c 1 = lsb c 2 msb' (f, ven) ck le or tch tcs tcwl tes tew teh tcwh however, as mentioned above, if the counter overlaps with the preset timing of the frequency division value, there is the risk that an incorrect preset value may be preset in the counter. therefore, the frequency division value should be set in sync with the counter output so as to avoid the preset timing. that is to say, the counter frequency division value is set after waiting for up to one cycle of the previous comparison cycle. therefore, ck input is prohibited for the previous comparison cycle (tcmp) after le. the ac characteristics are as follows. tcmp: previous comparison cycle description of operation the CXA3314ER can make the following operation settings using the three dt, ck and le signals. counter frequency division value and pull-in mode settings reference counter (r counter) frequency division value setting swallow counter and main counter (n counter) frequency division value settings pull-in mode setting initialization test mode test mode setting standby mode setting 1 1-1 1-2 1-3 1-4 1-5 2 3 item item number symbol t cs t ch t cwh t cwl t ew t es t eh data to clock setup time data to clock hold time clock pulse width high clock pulse width low load enable pulse width clock to load enable setup time clock load enable hold time 50 10 50 50 50 50 tcmp ns ns ns ns ns ns ns item min. unit
? 9 ? CXA3314ER 1-1. reference counter (r counter) frequency division value setting when the control bits [c 1 , c 2 ] = [0, 0], the 15 bits (r 15 to r 1 ) of the serially input 21 bits are set as the reference counter frequency division value r. the value input as the frequency division value must satisfy the condition 3 r 32767. in addition, (s, i, e) of the upper 4 bits are set simultaneously with the r value as the pull-in mode. the serial input format is as follows. 15-bit reference counter frequency division value r (3 r 32767) c 1 c 2 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 r 15 s ? ie reference counter frequency division value control bits = [0, 0] pull-in mode selection pull-in mode end judgment ? always set to "0". lsb msb r 3 4 : 32767 r 15 0 0 : 1 r 14 0 0 : 1 r 13 0 0 : 1 r 12 0 0 : 1 r 11 0 0 : 1 r 10 0 0 : 1 r 9 0 0 : 1 r 8 0 0 : 1 r 7 0 0 : 1 r 6 0 0 : 1 r 5 0 0 : 1 r 4 0 0 : 1 r 3 0 1 : 1 r 2 1 0 : 1 r 1 1 0 : 1 the final two bits of the serial input are the control bits (c 1 , c 2 ), and the setting item is selected according to these values. the setting items corresponding to the control bit values are as follows. c 1 0 1 1 0 r counter frequency division value setting, pull-in mode setting n counter frequency division value setting, pull-in start/end initialization test mode setting setting item c 2 0 0 1 1
? 10 ? CXA3314ER 1-2. swallow counter and main counter (n counter) frequency division value setting the n counter is comprised of a 5-bit swallow counter and a 13-bit main counter. when the control bits [c 1 , c 2 ] = [1, 0], the 18 bits (n 18 to n 1 ) of the serially input 21 bits are set as the n counter frequency division value n = 32 m + s. the values input as the frequency division values must satisfy the conditions 0 s 31 and s m 8191. adding the condition that the n value be a continuous value, the optional setting range is 992 n 262143. note that in the CXA3314ER, the input to the n counter is the fixed 1/4 frequency division of the vco output. therefore, care must be taken as vco frequency/comparison frequency (vck) = 4 n. in addition, the uppermost bit (f) is set simultaneously with the n value as the pull-in start/end bit. the serial input format is as follows. 5-bit swallow counter frequency division value s (0 s 31, s m) 13-bit main counter frequency division value m (3 m 8191) c 1 c 2 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 11 n 12 n 13 n 14 n 15 n 16 n 17 n 18 f swallow/main counter frequency division value control bits = [1, 0] pull-in mode start/end lsb msb s 0 1 : 31 n 5 0 0 : 1 n 4 0 0 : 1 n 3 0 0 : 1 n 2 0 0 : 1 n 1 0 1 : 1 m 3 4 : 8191 n 18 0 0 : 1 n 17 0 0 : 1 n 16 0 0 : 1 n 15 0 0 : 1 n 14 0 0 : 1 n 13 0 0 : 1 n 12 0 0 : 1 n 11 0 0 : 1 n 10 0 0 : 1 n 9 0 0 : 1 n 8 0 1 : 1 n 7 1 0 : 1 n 6 1 0 : 1
? 11 ? CXA3314ER 1-4. initialization when the control bits [c 1 , c 2 ] = [1, 1], the counter frequency division value and pull-in mode setting bits are initialized and set to r = 40, n = 5795, f = 1, si = 11, and e = 1. the serial input format is as follows. c 1 c 2 control bits = [1, 1] lsb msb 1-3. pull-in mode setting the uppermost bit (f) set simultaneously with the n value and (s, i, e) of the upper 4 bits set simultaneously with the r value are used for various settings in pull-in mode. the meaning of each bit is as follows. c 1 c 2 f control bits = [1, 0] n counter setting lsb msb pull-in mode setting (f) c 1 c 2 e i s control bits = [0, 0] r counter setting lsb msb pull-in mode setting (e, i, s) ? always set to "0". ? f: pull-in mode start/end flag pull-in mode is activated and the lock detector is cleared when the f flag is set to "1". pull-in mode ends when the f flag is set to "0". e: pull-in mode end judgment flag pull-in mode automatically ends when the e flag is "1" and lock is detected. when the e flag is "0", pull-in mode continues until the f flag is set to "0". is: pull-in mode flags these flags select the high-speed pull-in method used in pull-in mode. the various methods are active at the following timings. loop filter saturation reset cp current doubled damping resistance value halved when the s flag is "1". when the i flag is "1". when either of the s or i flags is "1".
? 12 ? CXA3314ER 2. test mode setting switching between normal operation mode and test mode is controlled by the testdis pin. normal operation mode results when testdis is ? 1 ? , and test mode when ? 0 ? . in test mode, the mode settings can also be controlled by 3-wire interface input. the input format is the same as that described above. note that the settings are valid only while testdis is ? 0 ? . when testdis is ? 1 ? , t 0 , t 1 , t 2 and t 3 are all initialized to ? 0 ? . the test mode operations set by the setting bits are shown in the table below. 3. standby mode setting standby operation is controlled by the cex pin. normal operation mode results when cex is ? 0 ? , and standby mode when ? 1 ? . in standby mode, the r counter, n counter, pfd and lock detector are all cleared, and the cp output is maintained at high impedance. in addition, the counter frequency division value setting and pull-in mode setting are saved. t 0 x x 0 1 0 1 t 1 x x 0 0 1 1 t 2 x x x x x x t 3 0 1 0 0 0 0 frequency division error detection flag function off frequency division error detection flag function on; output to lkdet pin rck signal output to lkdet pin vck signal output to lkdet pin mod signal output to lkdet pin pull-in on/off signal output to lkdet pin x: don ? t care 1-5. test mode when the control bits [c 1 , c 2 ] = [0, 1], the test command is set. the serial input format is as follows. test mode operation is described in detail in the following section. c 1 c 2 t 0 t 1 t 2 t 3 control bits = [0, 1] test mode selection lsb msb
? 13 ? CXA3314ER loop filter constant settings the loop filter constant calculation method is shown below. parameter definitions n: counter frequency division value ? 1 k vco : vco sensitivity (rad/s/v) ? 2 n: natural angular frequency (rad/s) fn: natural frequency (hz) k pd : charge pump gain (a/rad) ? 3 : damping factor ? 4 lut: lock-up time (s) k pd k vco n c n = = 2 fn 2 n c r = ? 1 frequency division value n = (vco oscillation frequency) (comparison frequency) ? 2 the k vco unit is normally expressed as mhz/v, but here it is multiplied by 2 to adjust the dimensions and expressed as rad/s/v. ? 3 the charge pump is a current output type. here, the current capacitance is divided by 2 to adjust the dimensions and expressed as a/rad. note that the charge pump current capacitance of this ic is approximately 300? in normal mode and approximately 600? in cp current doubled mode (rext = 1.8k ? ). ? 4 = 0.5 0.7 (typ.) set c1 and r1 to the c and r values obtained by the formula above. c2 is generally set to 1/10 the value of c1. set r2 so that the composite resistance of r1//r2 is the r value obtained by the formula above when the charge pump current value is doubled. (see ? 3 .) 17 19 dmpsw cpout c1 c2 gnd loop filter r1 r2 n 2 1 lut 2.5 5 n fn = ( lut = ) =
? 14 ? CXA3314ER example of representative characteristics 5 0 refin input sensitivity characteristics ? 5 ? 10 ? 15 ? 20 ? 25 ? 30 ? 35 0 20406080 ref input frequency [mhz] ref input level [dbm] 100 120 140 v cc = 3.0v, ta = 26?c 20 10 rfin input sensitivity characteristics ? ?0 ?0 ?0 ?0 ?0 ?0 01 23 456 7 rf input frequency [ghz] rf input level [dbm] 8 91011 v cc = 3.0v, ta = 26?c 16 14 current consumption 12 10 8 6 4 2 2.5 3.0 3.5 4.0 supply voltage [v] current consumption [ma] 4.5 5.0 v cc = 3.0v, ta = 26?c
?15 CXA3314ER ? example of 3-wire serial data settings r = 3 r = 32764 n = 992 n = 50000 n = 262143 reset initialize r = 100, n = 250 r = 100, n = 2500 r = 100, e = 1, i = 1, n = 2500 r = 100, e = 1, s = 1, n = 2500 r = 100, i, s = 1, n = 2500, f = 1 0 000 000 001 111 100 000 01 0 001 100 001 101 010 000 01 0 111 111 111 111 111 111 01 0 000 000 000 011 111 010 01 0 000 000 100 111 000 100 01 1 000 000 100 111 000 100 01 0 000 000 000 000 000 011 00 0 000 111 111 111 111 100 00 0 000 000 000 001 100 100 00 0 000 000 000 001 100 100 00 1 100 000 000 001 100 100 00 1 001 000 000 001 100 100 00 0 101 000 000 001 100 100 00 110 0 000 000 000 000 000 01 0 000 000 001 010 010 000 11 r value n value msb lsb msb lsb
?16 CXA3314ER package outline unit: mm c sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating copper alloy package structure 4.0 3.6 a b 0.05 m s a-b c s (0.39) (0.15) vqfn-24p-03 24pin vqfn(plastic) 0.04g 0.1 s a-b c x 4 0.1 s a-b c x 4 0.4 0.05 s 0.7 c 0.6 1.0 4.78 terminal section 0.2 0.01 0.225 0.03 solder plating 0.14 0.13 0.025 + 0.09 0.03 (stand off) 0.03 0.03 ( ? 1) 0.6 0.1 45 ? 0.9 0.1 pin 1 index 1 7 12 13 18 19 24 6 sony corporation lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec. c sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating copper alloy package structure 4.0 3.6 a b 0.05 m s a-b c s (0.39) (0.15) vqfn-24p-03 24pin vqfn(plastic) 0.04g 0.1 s a-b c x 4 0.1 s a-b c x 4 0.4 0.05 s 0.7 c 0.6 1.0 4.78 terminal section 0.2 0.01 0.225 0.03 solder plating 0.14 0.13 0.025 + 0.09 0.03 (stand off) 0.03 0.03 ( ? 1) 0.6 0.1 45 ? 0.9 0.1 pin 1 index 1 7 12 13 18 19 24 6

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