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512kx72 pipelined n t ram tm - 1 - rev 0.1 december 2001 K7N327245M preliminary document title 512kx72-bit pipelined n t ram tm the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. revision history rev. no. 0.0 0.1 remark preliminary preliminary history 1. initial document. 1. speed bin merge. from k7n327249m to K7N327245M 2. ac parameter change. toh(min)/tlzc(min) from 0.8 to 1.5 at -25 toh(min)/tlzc(min) from 1.0 to 1.5 at -22 toh(min)/tlzc(min) from 1.0 to 1.5 at -20 draft date may. 10. 2001 dec. 31. 2001
512kx72 pipelined n t ram tm - 2 - rev 0.1 december 2001 K7N327245M preliminary 32mb ntram(flow through / pipelined) , double late write ram x72 ordering informa tion org. part number mode vdd speed ft ; access time(ns) pipelined ; cycle time(mhz) pkg temp 2mx18 k7m321825m-q(h/f)c65/75/85 flowthrough 3.3 6.5/7.5/8.5ns q:100tqfp h:119bga f:165fbga c (commercial temperature range) k7n321801m-q(h/f)c25/22/20/16/15/13 pipelined 3.3 250/225/200/167/150/133mhz k7n321845m-q(h/f)c25/22/20/16/15/13 pipelined 2.5 250/225/200/167/150/133mhz 1mx36 k7m323625m-q(h/f)c65/75/85 flowthrough 3.3 6.5/7.5/8.5ns k7n323601m-q(h/f)c25/22/20/16/15/13 pipelined 3.3 250/225/200/167/150/133mhz k7n323645m-q(h/f)c25/22/20/16/15/13 pipelined 2.5 250/225/200/167/150/133mhz 512kx72 K7N327245M-hc25/22/20/16/15/13 pipelined (normal type) 2.5 250/225/200/167/150/133mhz h : 209bga k7z327285m-hc27/25 pipelined (sigma type) 1.8 275/250mhz
512kx72 pipelined n t ram tm - 3 - rev 0.1 december 2001 K7N327245M preliminary 512kx72-bit pipelined n t ram tm the K7N327245M is 37,748,736-bits synchronous static srams. the n t ram tm , or no turnaround random access memory uti- lizes all the bandwidth in any combination of operating cycles. address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. burst order control must be tied "high or low". asynchronous inputs include the sleep mode enable(zz). output enable controls the outputs at any given time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. for read cycles, pipelined sram output data is temporarily stored by an edge triggered output register and then released to the out- put buffers at the next rising edge of clock. the K7N327245M are implemented with samsung s high per- formance cmos technology and is available in 209bga pack- ages. multiple power and ground pins minimize ground bounce. general description features ? 2.5v 5% power supply. ? byte writable function. ? enable clock and suspend operation. ? single read/write control pin. ? self-timed write cycle. ? three chip enable for simple depth expansion with no data contention . ? a interleaved burst or a linear burst mode. ? asynchronous output enable control. ? power down mode. ? ttl-level three-state outputs. ? 209bga(11x19 ball grid array package). n t ram tm and no turnaround random access memory are trademarks of samsung. logic block diagram we bw x clk cke cs 1 cs 2 cs 2 adv oe zz dqa 0 ~ dqh 7 address address register c o n t r o l l o g i c a 0 ~a 1 72 dqpa ~ dqph output buffer register data-in register data-in register k k k register burst address counter write address register write control logic c o n t r o l r e g i s t e r k a [0:18] lbo a 2 ~a 18 a 0 ~a 1 (x=a ~ h) 512k x 72 memory array fast access times parameter symbol -25 -22 -20 -16 -15 -13 unit cycle time tcyc 4.0 4.4 5.0 6.0 6.7 7.5 ns clock access time tcd 2.6 2.8 3.2 3.5 3.8 4.2 ns output enable access time toe 2.6 2.8 3.2 3.5 3.8 4.2 ns
512kx72 pipelined n t ram tm - 4 - rev 0.1 december 2001 K7N327245M preliminary 209bga package pin configurations (top view) pin name symbol pin name symbol pin name a a 0 ,a 1 adv we clk cke cs 1 cs 2 cs 2 bw x (x=a~h) oe zz lbo tck tms tdi tdo address inputs burst address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control jtag test clock jtag test mode select jtag test data input jtag test data output v dd v ss n.c. dqa dqb dqc dqd dqe dqf dqg dqh dqpa~ph v ddq power supply ground no connect data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs data inputs/outputs output power supply K7N327245M(512k x 72) notes : 1. ** a 0 and a 1 are the two least significant bits(lsb) of the address field and set the internal burst counter if burst is desired . 1 2 3 4 5 6 7 8 9 10 11 a dqg dqg a cs 2 a adv a cs 2 a dqb dqb b dqg dqg bw c bw g nc we a bw b bw f dqb dqb c dqg dqg bw h bw d nc cs 1 nc bw e bw a dqb dqb d dqg dqg v ss nc nc oe nc nc v ss dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb f dqc dqc v ss v ss v ss nc v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd nc v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss nc v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd nc v dd v ddq v ddq dqf dqf k nc nc clk nc v ss cke v ss nc nc nc nc l dqh dqh v ddq v ddq v dd nc v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss nc v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd nc v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss zz v ss v ss v ss dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd v ss nc nc lbo nc nc v ss dqe dqe u dqd dqd nc a nc(64m) a a a nc dqe dqe v dqd dqd a a a a 1** a a a dqe dqe w dqd dqd tms tdi a a 0** a tdo tck dqe dqe
512kx72 pipelined n t ram tm - 5 - rev 0.1 december 2001 K7N327245M preliminary function description burst sequence table (interleaved burst, lbo =high) lbo pin high case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 bq table (linear burst, lbo =low) note : 1. lbo pin must be tied to high or low, and floating state must not be allowed . lbo pin low case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 the K7N327245M is n t ram tm designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, or vice versa. all inputs (with the exception of oe , lbo and zz) are synchronized to rising clock edges. all read, write and deselect cycles are initiated by the adv input. subsequent burst addresses can be internally generated by th e burst advance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for next operation. clock enable( cke ) pin allows the operation of the chip to be suspended as long as necessary. when cke is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. n t ram tm latches external address and initiates a cycle, when cke , adv are driven to low and all three chip enables( cs 1 , cs 2 , cs 2 ) are active . output enable( oe ) can be used to disable the output at any given time. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, cke is driven low, all three chip enables( cs 1 , cs 2 , cs 2 ) are active, the write enable input signals we are driven high, and adv driven low.the internal array is read between the first rising edge and the second rising edge of the clock and th e data is latched in the output register. at the second clock edge the data is driven out of the sram. also during read operation oe must be driven low for the device to drive out the requested data. write operation occurs when we is driven low at the rising edge of the clock. bw [h:a] can be used for byte write operation. the pipe- lined n t ram tm uses a late-late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are registered, and the data associated with that address is required two cycle later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst seguence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the state of the lbo pin. when this pin is low, linear burst sequence is selected. and when this pin is high, interleaved burst sequence is selected. during normal operation, zz must be driven low. when zz is driven high, the sram will enter a power sleep mode after 2 cycles. a t this time, internal state of the sram is preserved. when zz returns to low, the sram normally operates after 2 cycles of wake up time.
512kx72 pipelined n t ram tm - 6 - rev 0.1 december 2001 K7N327245M preliminary state diagram for n t ram tm begin write burst write begin read write d s r e a d burst read d s w r i t e d s read d s r e a d d s w r i t e b u r s t deselect b u r s t r e a d b u r s t w r i t e read write burst burst notes : 1. an ignore clock edge cycle is not shown is the above diagram. this is because cke high only blocks the clock(clk) input and does not change the state of the device. 2. states change on the rising edge of the clock(clk) command action ds deselect read begin read write begin write burst begin read begin write continue deselect
512kx72 pipelined n t ram tm - 7 - rev 0.1 december 2001 K7N327245M preliminary synchronous truth table notes : 1. x means "don t care". 2. the rising edge of clock is symbolized by ( - ). 3. a continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table. 5. operation finally depends on status of asynchronous input pins(zz and oe ). cs 1 cs 2 cs 2 adv we bw x oe cke clk address accessed operation h x x l x x x l - n/a not selected x l x l x x x l - n/a not selected x x h l x x x l - n/a not selected x x x h x x x l - n/a not selected continue l h l l h x l l - external address begin burst read cycle x x x h x x l l - next address continue burst read cycle l h l l h x h l - external address nop/dummy read x x x h x x h l - next address dummy read l h l l l l x l - external address begin burst write cycle x x x h x l x l - next address continue burst write cycle l h l l l h x l - n/a nop/write abort x x x h x h x l - next address write abort x x x x x x x h - current address ignore clock truth tables write truth table (x72) notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( - ). we bw a bw b bw c bw d bw e bw f bw g bw h operation h x x x x x x x x read l l h h h h h h h write byte a l h l h h h h h h write byte b l h h l h h h h h write byte c l h h h l h h h h write byte d l h h h h l h h h write byte e l h h h h h l h h write byte f l h h h h h h l h write byte g l h h h h h h h l write byte h l l l l l l l l l write all bytes l h h h h h h h h write abort/nop
512kx72 pipelined n t ram tm - 8 - rev 0.1 december 2001 K7N327245M preliminary asynchronous truth table operation zz oe i/o status sleep mode h x high-z read l l dq l h high-z write l x din, high-z deselected l x high-z notes 1. x means "don t care". 2. sleep mode means power sleep mode of which stand-by current does not depend on cycle time. 3. deselected means power sleep mode of which stand-by current depends on cycle time. absolute maximum ratings* *note : stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.3 to 3.6 v voltage on any other pin relative to v ss v in -0.3 to v dd +0.3 v power dissipation p d 1.6 w storage temperature t stg -65 to 150 c operating temperature t opr 0 to 70 c storage temperature range under bias t bias -10 to 85 c operating conditions (0 c t a 70 c) *note : v dd and v ddq must be supplied with identical vlotage levels . parameter symbol min typ. max unit supply voltage v dd 2.375 2.5 2.625 v v ddq 2.375 2.5 2.625 v ground v ss 0 0 0 v capacitance* (t a =25 c, f=1mhz) *note : sampled not 100% tested. parameter symbol test condition min max unit input capacitance c in v in =0v - 5 pf output capacitance c out v out =0v - 7 pf
512kx72 pipelined n t ram tm - 9 - rev 0.1 december 2001 K7N327245M preliminary (t a =0 to 70 c, v dd =2.5v 5%, unless otherwise specified) test conditions parameter value input pulse level 0 to 2.5v input rise and fall time(measured at 20% to 80%) 1.0v/ns input and output timing reference levels v ddq /2 output load see fig. 1 v ss v ih v ss- 0.8v 20% t cyc (min) dc electrical characteristics (v dd =2.5v 5%, t a =0 c to +70 c) notes : 1. reference ac operating conditions and characteristics for input and timing. 2. data states are all zero. 3. in case of i/o pins, the max. v ih =v ddq +0.3v parameter symbol test conditions min max unit notes input leakage current(except zz) i il v dd =max ; v in =v ss to v dd -2 +2 m a output leakage current i ol output disabled, -2 +2 m a operating current i cc v dd =max i out =0ma cycle time 3 t cyc min -25 - tbd ma 1,2 -22 - tbd -20 - tbd -16 - tbd -15 - tbd -13 - tbd standby current i sb device deselected, i out =0ma, zz v il , f=max, all inputs 0.2v or 3 v dd -0.2v -25 - tbd ma -22 - tbd -20 - tbd -16 - tbd -15 - tbd -13 - tbd i sb1 device deselected, i out =0ma, zz 0.2v, f=0, all inputs=fixed (v dd -0.2v or 0.2v) - tbd ma i sb2 device deselected, i out =0ma, zz 3 v dd -0.2v, f=max, all inputs v il or 3 v ih - tbd ma output low voltage v ol i ol =1.0ma - 0.4 v output high voltage v oh i oh =-1.0ma 2.0 - v input low voltage v il -0.3* 0.7 v input high voltage v ih 1.7 v dd +0.3** v 3
512kx72 pipelined n t ram tm - 10 - rev 0.1 december 2001 K7N327245M preliminary (v dd =2.5v 5% , t a =0 to 70 c) output load(b), (for t lzc , t lzoe , t hzoe & t hzc ) dout 1538 w 5pf* +2.5v 1667 w fig. 1 * including scope and jig capacitance output load(a) dout zo=50 w rl=50 w vl=v ddq /2 30pf* ac timing characteristics notes : 1. all address inputs must meet the specified setup and hold times for all rising clock(clk) edges when adv is sampled low an d cs is sampled low. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. chip selects must be valid at each rising edge of clk(when adv is low) to remain enabled. 3. a write cycle is defined by we low having been registered into the device at adv low, a read cycle is defined by we high with adv low, both cases must meet setup and hold times. 4. to avoid bus contention, at a given voltage and temperature t lzc is more than t hzc. the specs as shown do not imply bus contention because t lzc is a min. parameter that is worst case at totally different test conditions (0 c,2.625v) than t hzc , which is a max. parameter(worst case at 70 c,2.375v) it is not possible for two srams on the same board to be at such different voltage and temperature. parameter symbol -25 -22 -20 -16 -15 -13 unit min max min max min max min max min max min max cycle time t cyc 4.0 - 4.4 - 5.0 - 6.0 - 6.7 - 7.5 - ns clock access time t cd - 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns output enable to data valid t oe - 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns clock high to output low-z t lzc 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns output hold from clock high t oh 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns output enable low to output low-z t lzoe 0 - 0 - 0 - 0 - 0 - 0 - ns output enable high to output high-z t hzoe - 2.6 - 2.8 - 3.0 - 3.0 - 3.0 - 3.5 ns clock high to output high-z t hzc - 2.6 - 2.8 - 3.0 - 3.0 - 3.0 - 3.5 ns clock high pulse width t ch 1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 - ns clock low pulse width t cl 1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 - ns address setup to clock high t as 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns cke setup to clock high t ces 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns data setup to clock high t ds 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns write setup to clock high ( we , bw x ) t ws 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns address advance setup to clock high t advs 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns chip select setup to clock high t css 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns address hold from clock high t ah 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns cke hold from clock high t ceh 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns data hold from clock high t dh 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns write hold from clock high ( we , bw x ) t wh 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns address advance hold from clock high t advh 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns chip select hold from clock high t csh 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns zz high to power down t pds 2 - 2 - 2 - 2 - 2 - 2 - cycle zz low to power up t pus 2 - 2 - 2 - 2 - 2 - 2 - cycle
512kx72 pipelined n t ram tm - 11 - rev 0.1 december 2001 K7N327245M preliminary sleep mode sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb2 . the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an asynchronous, active high input that causes the device to enter sleep mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. any operation pending when entering sleep mode is not guaranteed to successful complete. therefore, sleep mode (read or write) must not be initiated until valid pend- ing operations are completed. similarly, when exiting sleep mode during t pus , only a deselect or read cycle should be given while the sram is transitioning out of sleep mode. sleep mode electrical characteristics description conditions symbol min max units current during sleep mode zz 3 v ih i sb2 10 ma zz active to input ignored t pds 2 cycle zz inactive to input sampled t pus 2 cycle zz active to sleep current t zzi 2 cycle zz inactive to exit sleep current t rzzi 0 k t pds zz setup cycle t rzzi zz isupply all inputs (except zz) outputs (q) t zzi t pus zz recovery cycle deselect or read only high-z don t care i sb2 sleep mode waveform normal operation cycle deselect or read only
512kx72 pipelined n t ram tm - 12 - rev 0.1 december 2001 K7N327245M preliminary ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible test access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg- ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controll er without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo tdi tms tck test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. this instruction is not ieee 1149.1 compliant. 2. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 3. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 4. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 5. sample instruction dose not places dqs in hi-z. 6. this instruction is reserved for future use. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 3 0 1 0 sample-z boundary scan register 2 0 1 1 bypass bypass register 4 1 0 0 sample boundary scan register 5 1 0 1 reserved do not use 6 1 1 0 bypass bypass register 4 1 1 1 bypass bypass register 4
512kx72 pipelined n t ram tm - 13 - rev 0.1 december 2001 K7N327245M preliminary note : 1. nc and vss pins included in the scan exit order are read as "x" ( i.e. don t care). bit pin id 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 boundary scan exit order id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit(0) 512kx72 0000 00111 00101 xxxxxx 00001001110 1 scan register definition part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bits 32 bits 123 bits bit pin id 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 bit pin id 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 t b d
512kx72 pipelined n t ram tm - 14 - rev 0.1 december 2001 K7N327245M preliminary jtag dc operating conditions note : the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd 2.4 2.5 2.6 v input high level v ih 1.7 - v dd +0.3 v input low level v il -0.3 - 0.7 v output high voltage v oh 2.0 - - v output low voltage v ol - - 0.4 v jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5 - ns tms input hold time t chmx 5 - ns tdi input setup time t dvch 5 - ns tdi input hold time t chdx 5 - ns sram input setup time t svch 5 - ns sram input hold time t chsx 5 - ns clock low to output valid t clqv 0 10 ns jtag ac test conditions parameter symbol min unit note input high/low level v ih /v il 2.5/0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level v ddq /2 v tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
512kx72 pipelined n t ram tm - 15 - rev 0.1 december 2001 K7N327245M preliminary c l o c k c k e a d d r e s s w r i t e c s a d v o e d a t a o u t t i m i n g w a v e f o r m o f r e a d c y c l e n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l t c h t c l t c e s t c e h t a s t a h a 1 a 2 a 3 t w s t w h t c s s t c s h t o e t h z o e t l z o e t c d t o h t h z c q 3 - 4 q 3 - 3 q 3 - 2 q 3 - 1 q 2 - 4 q 2 - 3 q 2 - 2 q 2 - 1 q 1 - 1 d o n t c a r e u n d e f i n e d t c y c t a d v s t a d v h
512kx72 pipelined n t ram tm - 16 - rev 0.1 december 2001 K7N327245M preliminary t i m i n g w a v e f o r m o f w r t e c y c l e c l o c k a d d r e s s w r i t e c s a d v d a t a i n t c h t c l a 2 a 3 d 2 - 1 d 1 - 1 d 2 - 2 d 2 - 3 d 2 - 4 d 3 - 1 d 3 - 2 d 3 - 3 o e d a t a o u t t d s t d h d o n t c a r e u n d e f i n e d t c y c c k e a 1 d 3 - 4 t c e s t c e h n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l q 0 - 4 t h z o e q 0 - 3
512kx72 pipelined n t ram tm - 17 - rev 0.1 december 2001 K7N327245M preliminary t i m i n g w a v e f o r m o f s i n g l e r e a d / w r i t e c l o c k a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l t d s t d h d a t a o u t a 2 a 4 a 5 d 2 t o e t l z o e q 1 d o n t c a r e u n d e f i n e d t c y c c k e t c e s t c e h a 1 a 3 a 7 a 6 q 3 q 4 q 7 q 6 d 5 n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l a 9 a 8
512kx72 pipelined n t ram tm - 18 - rev 0.1 december 2001 K7N327245M preliminary t i m i n g w a v e f o r m o f c k e o p e r a t i o n c l o c k a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l d a t a o u t a 1 a 2 a 3 a 4 a 5 t c e s t c e h d o n t c a r e u n d e f i n e d t c y c c k e t d s t d h d 2 q 4 q 1 n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l t c d t l z c t h z c q 3 a 6
512kx72 pipelined n t ram tm - 19 - rev 0.1 december 2001 K7N327245M preliminary t i m i n g w a v e f o r m o f c s o p e r a t i o n c l o c k a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l d a t a o u t a 1 a 2 a 3 a 4 a 5 d o n t c a r e u n d e f i n e d t c y c c k e d 5 q 4 t c e s t c e h q 1 q 2 t o e t l z o e d 3 t c d t l z c n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l t h z c t d h t d s
512kx72 pipelined n t ram tm - 20 - rev 0.1 december 2001 K7N327245M preliminary 209 bump bga package dimensions 14mm x 22mm body, 1.0mm bump pitch, 11x19 bump array 209- ? 0.06 0.10 1.00(bsc) 12.50 0 . 5 0 0 . 0 5 0 . 9 0 c1.00 c0.70 14.00 2 2 . 0 0 2 0 . 5 0 0 . 0 5 note : 1. all dimensions are in millimeters. 2. solder ball to pcb offset: 0.10 max. 3. pcb to cavity offset: 0.10 max. indicator of ball(1a) location 1.00x10=10.00(bsc) 1 . 0 0 ( b s c ) 1 . 0 0 x 1 8 = 1 8 . 0 0 ( b s c ) 1 . 5 0 2 . 2 0 m a x

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