1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg64129s-d3 june 2004 rev. 0 preliminary* 1g- 128mx64 ddr sdram unbuffered description the w3eg64129s is a 124mx64 double data rate sdram memory module based on 512mb ddr sdram component. the module consists of sixteen 128mx4 ddr sdrams in 66 pin tsop package mounted on a 184 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * this product is under development, is not quali? ed or characterized and is subject to change without notice. features clock speeds of 100mhz and 133mhz double-data-rate architecture bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2,5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh serial presence detect power supply: 2.5v 0.20v jedec standard 184 pin dimm package operating frequencies ddr266 @cl=2 ddr266 @cl=2.5 ddr200 @cl=2 clock speed 133mhz 133mhz 100mhz cl-t rcd -t rp 2-2-2 2.5-3-3 2-2-2
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg64129s-d3 june 2004 rev. 0 preliminary pin symbol pin symbol pin symbol pin symbol 1v ref 47 nc 93 v ss 139 v ss 2 dq0 48 a0 94 dq4 140 nc 3v ss 49 nc 95 dq5 141 a10 4 dq1 50 v ss 96 v ccq 142 nc 5 dqs0 51 nc 97 dqs9 143 v ccq 6 dq2 52 ba1 98 dq6 144 nc 7v cc 53 dq32 99 dq7 145 v ss 8dq354v ccq 100 v ss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 nc 56 dqs4 102 nc 148 v cc 11 v ss 57 dq34 103 nc 149 dqs13 12 dq8 56 v ss 104 v ccq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 v ss 15 v ccq 61 dq40 107 dqs10 153 dq44 16 ck1 62 v ccq 108 v cc 154 ras# 17 ck1# 63 we# 109 dq14 155 dq45 18 v ss 64 dq41 110 dq15 156 v ccq 19 dq10 65 cas# 111 cke1 157 cs0# 20 dq11 66 v ss 112 v ccq 158 cs1# 21 cke0 67 dqs5 113 nc 159 dqs14 22 v ccq 68 dq42 114 dq20 160 v ss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 v cc 116 v ss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 v ss 72 dq48 118 a11 164 v ccq 27 a9 73 dq49 119 dqs11 165 dq52 28 dq18 74 v ss 120 v cc 166 dq53 29 a7 75 ck2# 121 dq22 167 nc 30 v ccq 76 ck2 122 a8 168 v cc 31 dq19 77 v ccq 123 dq23 169 dqs15 32 a5 78 dqs6 124 v ss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 v ss 80 dq51 126 dq28 172 v ccq 35 dq25 81 v ss 127 dq29 173 nc 36 dqs3 82 v ccid 128 v ccq 174 dq60 37 a4 83 dq56 129 dqs12 175 dq61 38 v cc 84 dq57 130 a3 176 v ss 39 dq26 85 v cc 131 dq30 177 dqs16 40 dq27 86 dqs7 132 v ss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 v ss 88 dq59 134 nc 180 v ccq 43 a1 89 v ss 135 nc 181 sa0 44 nc 90 wp 136 v ccq 182 sa1 45 nc 91 sda 137 ck0 183 sa2 46 v cc 92 scl 138 ck0# 184 v ccspd pin configuration a0-a12 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output dqs0-dqs16 data strobe input/output ck0, ck1, ck2 clock input ck0#. ck1#, ck2# clock input cke0, cke1 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# write enable v cc power supply (2.5v) v ccq power supply for dqs (2.5v) v ss ground v ref power supply for reference v ccspd serial eeprom power supply (2.3v to 3.6v) sda serial data i/o scl serial clock sa0-sa2 address in eeprom v ccid v cc indenti? cation flag nc no connect pin names
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg64129s-d3 june 2004 rev. 0 preliminary functional block diagram dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs8 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs10 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs11 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs12 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs13 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs15 cs 0# dqs4 dqs1 dqs5 dqs2 dqs3 dqs14 dqs6 dqs7 dq15 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs resistors: 22 ohms. dq0-d15 a0-a12 d0-d15 ras# d0-d7 cas# dq8-d15 cke0 d0-d15 cke1 d0-d15 we# d0-d15 cs1# dqs9 a0 serial p d a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d17 d0 d17 v cc /v ccq d0 - d17 d0 - - d17 v ref v ccspd spd ba0 - ba1 clock input 5 sdrams ck0/ck0# ck1/ck1# ck2/ck2# 4 sdrams 6 sdrams 6 sdrams dqs0 i/o3 i/o2 i/o1 i/o0 d0 cs0# dqs8 i/o3 i/o2 i/o1 i/o0 d0 cs1# dqs9 i/o3 i/o2 i/o1 i/o0 d0 cs1# dqs10 i/o3 i/o2 i/o1 i/o0 d0 cs1# dqs11 i/o3 i/o2 i/o1 i/o0 d0 cs1# dqs12 i/o3 i/o2 i/o1 i/o0 d0 cs1# dqs13 i/o3 i/o2 i/o1 i/o0 d0 cs1# dqs14 i/o3 i/o2 i/o1 i/o0 d0 cs1# dqs15 i/o3 i/o2 i/o1 i/o0 d0 cs1# dqs1 i/o3 i/o2 i/o1 i/o0 d1 cs0# dqs2 i/o3 i/o2 i/o1 i/o0 d2 cs0# dqs3 i/o3 i/o2 i/o1 i/o0 d3 cs0# dqs4 i/o3 i/o2 i/o1 i/o0 d4 cs0# dqs5 i/o3 i/o2 i/o1 i/o0 d5 cs0# dqs6 i/o3 i/o2 i/o1 i/o0 d6 cs0# dqs7 i/o3 i/o2 i/o1 i/o0 d7 cs0#
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg64129s-d3 june 2004 rev. 0 preliminary absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 to 3.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 to 3.6 v storage temperature t stg -55 to +150 c power dissipation p d 16 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability dc characteristics 0c t a 70c, v cc = 2.5v 0.2v parameter symbol min max unit supply voltage v cc 2.3 2.7 v supply voltage v ccq 2.3 2.7 v reference voltage v ref 1.15 1.35 v termination voltage v tt 1.15 1.35 v input high voltage v ih v ref + 0.15 v ccq + 0.3 v input low voltage v il -0.3 v ref -0.15 v output high voltage v oh v tt + 0.76 v output low voltage v ol v tt -0.76 v capacitance t a = 25c. f = 1mhz, v cc = 2.5v, v ref = 1.4v 200mv parameter symbol max unit input capacitance (a0-a11) c in1 53 pf input capacitance (ras#,cas#,we#) c in2 53 pf input capacitance (cke0, cke1) c in3 29 pf input capacitance (ck0-2,ck0-2#) c in4 18 pf input capacitance (cs0#, cs1#) c in5 29 pf input capacitance (dqm0-dqm8) c in6 8pf input capacitance (ba0-ba1) c in7 53 pf data input/output capacitance (dq0-dq63)(dqs) c out 8pf
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg64129s-d3 june 2004 rev. 0 preliminary i dd specifications and test conditions recommended operating conditions, 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v includes ddr sdram component only parameter symbol conditions ddr266@cl=2 max ddr266@cl=2.5 max ddr200@cl=2 max units operating current i dd0 one device bank; active - precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. 2840 2840 2840 ma operating current i dd1 one device bank; active-read- precharge burst = 2; t rc =t rc (min); t ck =t ck (min); l out = 0ma; address and control inputs changing once per clock cycle. 3040 3040 3040 ma precharge power- down standby current i dd2p all device banks idle; power-down mode; t ck =t ck (min); cke=(low) 95 95 95 rna idle standby current i dd2f cs# = high; all device banks idle; t ck =t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs and dm. 800 800 800 ma active power-down standby current i dd3p one device bank active; power- down mode; t ck (min); cke=(low) 800 800 800 ma active standby current i dd3n cs# = high; cke = high; one device bank; active-precharge; t rc =t ras (max); t ck =t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. 1520 1520 1520 ma operating current i dd4r burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); l out = 0ma. 3520 3520 3520 ma operating current i dd4w burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle. 4000 4000 4000 rna auto refresh current i dd5 t rc = t rc (min) 4960 4960 4960 ma self refresh current i dd6 cke 0.2v 80 80 80 ma operating current i dd7a four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands. 7680 7680 7680 ma
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg64129s-d3 june 2004 rev. 0 preliminary i dd1 : operating current : one bank 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. only one bank is accessed with t rc (min), burst mode, address and control inputs on nop edge are changing once per clock cycle. i out = 0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck= 10ns, cl2, bl=4, t rcd= 2*t ck , t ras= 5*t ck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck= 7.5ns, cl=2.5, bl=4, t rcd= 3*t ck , t rc= 9*t ck , t ras= 5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl=2, bl=4, t rcd =3*t ck , t rc =9*t ck , t ras =5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst i dd7a : operating current : four banks 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. four banks are being interleaved with t rc (min), burst mode, address and control inputs on nop edge are not changing. iout=0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck =10ns, cl2, bl=4, t rrd =2*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck =7.5ns, cl=2.5, bl=4, t rrd =3*t ck , t rcd =3*t ck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl2=2, bl=4, t rrd =2*t ck , t rcd =2*t ck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst detailed test conditions for ddr sdram i dd1 & i dd7a legend: a = activate, r = read, w = write, p = precharge, n = nop a (0-3) = activate bank 0-3 r (0-3) = read bank 0-3
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg64129s-d3 june 2004 rev. 0 preliminary 133.48 (5.255" max.) 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.78 (0.070) 49.53 (1.950) 3.00 (0.118) (4x) 30.48 (1.20) max 2.31 (0.091) (2x) 1.27 (0.050 typ.) 6.35 (0.250) 128.95 (5.077") 131.34 (5.171") 3.81 (0.150 max) 3.99 (0.157) (min) 1.27 0.10 (0.050 0.004) package dimensions for d3 * all dimensions are in millimeters and (inches) ordering information for d3 part number speed cas latency t rcd t rp height* W3EG64129S262D3 133mhz/266mb/s 2 2 2 30.48 (1.20") w3eg64129s265d3 133mhz/266mb/s 2.5 3 3 30.48 (1.20") w3eg64129s202d3 100mhz/200mb/s 2 2 2 30.48 (1.20")
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg64129s-d3 june 2004 rev. 0 preliminary document title 1gb - 128mx64, ddr sdram unbuffered revision history rev # history release date status rev a created datasheet 9-23-02 advanced rev 0 0.1 updated cap and i dd specs. 0.2 removed "ed" from part marking 0.3 moved from advanced to preliminary 6-04 primary
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