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advance information copyright ? intel corporation, 1997 february 1997 order number: 272917-003 8 x 930a x universal serial bus microcontroller the 8 x 930a x usb microcontroller is based on an 8 x c251s x microcontroller core. it consists of standard 8 x c251sx peripherals plus an added usb function. the 8 x 930a x uses the standard instruction set of the mcs 251 architecture, which is binary code compatible with the mcs 51 architecture. the usb function integrates the usb transceiver, serial bus interface engine (sie), function interface unit (fiu) and transmit/receive fifos. the usb function also supports full-speed/low-speed data rates, suspend/resume modes, isochronous/non-isochronous transfers, and is fully compliant with the usb rev 1.0 specification. n complete universal serial bus specification 1.0 compatibility supports isochronous and non-isochronous data bidirectional half-duplex link n on-chip usb transceiver n serial bus interface engine (sie) packet decoding/generation crc generation and checking nrzi encoding/decoding and bit-stuffing n usb reset interrupt n four transmit fifos three 16-byte fifos one configurable fifo (up to 1 kbyte) n four receive fifos three 16-byte fifos one configurable fifo (up to 1 kbyte) n automatic transmit/receive fifo management n suspend/resume operation n three new usb interrupt vectors usb function interrupt start of frame suspend/resume n phase-locked loop 12 mbps or 1.5 mbps data rate n low clock mode n user-selectable configurations external wait state address range page mode n real-time wait function n 256-kbyte external code/data memory space n on-chip rom options 0, 8, or 16 kbytes n 1 kbyte on-chip data ram n four input/output ports 1 open-drain port 3 quasi-bidirectional ports n programmable counter array (pca) 5 capture/compare modules n serial i/o port (uart) n hardware watchdog timer n three flexible 16-bit timer/counters n power-saving idle and powerdown modes n register-based mcs ? 251 architecture 40-byte register file registers accessible as bytes, words, or doublewords n code compatible with mcs 51 and mcs 251 microcontrollers n 6 or 12 mhz crystal operation
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or oth- erwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. the product may contain design defects or errors known as errata. current characterized errata are available on request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation literature sales p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-548-4725 copyright ? intel corporation, 1997
iii contents 1.0 nomenclature overview ...................................................................................................... 3 2.0 pinout .................................................................................................................................. 4 3.0 signals ................................................................................................................................ 7 4.0 address map ..................................................................................................................... 10 5.0 electrical characteristics ................................................................................................... 11 5.1 operating frequencies ................................................................................................. 12 5.2 dc characteristics........................................................................................................ 13 5.3 definition of ac symbols.............................................................................................. 15 5.4 ac characteristics........................................................................................................ 16 5.4.1 system bus ac characteristics ............................................................................16 5.4.2 system bus timing diagrams, nonpage mode ....................................................18 5.4.3 system bus timing diagrams, page mode ...........................................................20 5.4.4 definition of real-time wait symbols ....................................................................22 5.4.5 real-time wait function ac characteristics .........................................................22 5.4.6 real-time wait function timing diagrams ...........................................................23 5.5 ac characteristics serial port, synchronous mode 0 ............................................. 27 5.6 external clock drive ..................................................................................................... 28 5.7 testing waveforms ...................................................................................................... 29 6.0 thermal characteristics .................................................................................................... 30 7.0 product reference ............................................................................................................ 30 7.1 external bus timing and peripheral timing affected by pllsel2:0 selection ........... 30 7.2 low clock mode frequency ......................................................................................... 30 7.3 setting ffrc bit clears only the oldest packet in the fifo ...................................... 30 7.4 series resistor requirement for impedance matching ................................................ 30 7.5 pullup requirement for full speed device and low speed device............................. 30 7.6 powerdown mode cannot be invoked before usb suspend ...................................... 30 8.0 specification supplement for 8 x 930a x 3 and 8 x 930a x 4.................................................... 31 8.1 six endpoint pairs functionality ................................................................................... 31 8.2 dc characteristics........................................................................................................ 31 8.3 extended data float (edf) ac timing feature ........................................................... 31 9.0 device errata .................................................................................................................... 34 10.0 datasheet revision history ............................................................................................... 34
8X930AX universal serial bus microcontroller iv figures 1. 8 x 930a x internal block diagram ..........................................................................................1 2. usb module block diagram.................................................................................................2 3. product nomenclature .........................................................................................................3 4. 8 x 930a x 68-pin plcc package...........................................................................................4 5. clock circuit .......................................................................................................................12 6. 8 x 930a x code fetch, nonpage mode ...............................................................................18 7. 8 x 930a x data read, nonpage mode ................................................................................19 8. 8 x 930a x data write, nonpage mode.................................................................................19 9. 8 x 930a x code fetch, page mode .....................................................................................20 10. 8 x 930a x data read, page mode.......................................................................................21 11. 8 x 930a x data write, page mode........................................................................................21 12. external code fetch/data read (nonpage mode, real-time wait state) .........................23 13. external data write (nonpage mode, real-time wait state) .............................................24 14. external data read (page mode, real-time wait state) ...................................................25 15. external data write (page mode, real-time wait state) ...................................................26 16. serial port waveform synchronous mode 0..................................................................27 17. external clock drive waveforms........................................................................................28 18. ac testing input, output waveforms.................................................................................29 19. float waveforms ................................................................................................................29 tables 1. description of product nomenclature...................................................................................3 2. proliferation options.............................................................................................................3 3. 68-pin plcc pin assignment...............................................................................................5 4. 68-pin plcc signal assignments arranged by functional category ..................................6 5. signal descriptions ..............................................................................................................7 6. memory signal selections (rd1:0) ....................................................................................10 7. 8 x 930a x address map .......................................................................................................10 8. frequency selection and operating frequency.................................................................12 9. dc characteristics at operating conditions.......................................................................13 10. ac timing symbol definitions............................................................................................15 11. ac characteristics at operating conditions.......................................................................16 12. real-time wait timing symbol definitions .........................................................................22 13. real-time wait ac timing specifications...........................................................................22 14. serial port timing synchronous mode 0 .......................................................................27 15. external clock drive...........................................................................................................28 16. thermal characteristics .....................................................................................................30 17. six endpoint pair feature ..................................................................................................31 18. effect of edf# on wait states .........................................................................................31 19. ac characteristics for 8X930AX3 and 8X930AX4 in compatibility mode ............................32 20. 8 x 930a x 3 and 8 x 930a x 4 default and extended data float timings.................................32 21. 8 x 930a x 3 and 8 x 930a x 4 real-time wait state ac timing specifications ........................33
advance information 1 8X930AX universal serial bus (usb) microcontroller figure 1. 8 x 930a x internal block diagram a4340-01 src2 (8) code address (24) code bus (16) ram rom watchdog timer timer/ counters pca serial i/o port 2 drivers p2.7:0 port 0 drivers p0.7:0 port 3 drivers p3.7:0 port 1 drivers p1.7:0 data address (24) data bus (8) memory address (16) system bus and i/o ports i/o ports and peripheral signals src1 (8) ib bus (8) peripheral interface interrupt handler clock & reset bus interface instruction sequencer dst (16) alu data memory interface memory data (16) register file usb ? usb ports microcontroller core ? for details, see the usb module block diagram.
2 advance information 8X930AX universal serial bus (usb) microcontroller figure 2. usb module block diagram d p0 transceiver control control control transmit/receive bus fifos d m0 a4231-03 data bus serial bus interface engine (sie) function interface unit (fiu) usb upstream port to cpu
advance information 3 8X930AX universal serial bus (usb) microcontroller 1.0 nomenclature overview figure 3. product nomenclature table 1. description of product nomenclature parameter options description temperature and burn-in no mark commercial operating temperature range (0 o c to 70 o c) with intel standard burn-in. packaging options n plastic leaded chip carrier (plcc) program memory options 0 without rom 3 with rom process and voltage information no mark chmos product family 930 advanced 8-bit microcontroller architecture with on-chip uni- versal serial bus (usb) function peripherals device speed no mark 6 or 12 mhz crystal table 2. proliferation options product name rom size ram size 80930ad 0 1 kbyte 83930ad 8 kbytes 1 kbyte 83930ae 16 kbytes 1 kbyte program memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed
4 advance information 8X930AX universal serial bus (usb) microcontroller 2.0 pinout figure 4. 8 x 930a x 68-pin plcc package figure 4 illustrates the 8 x 930a x plcc package. table 3 lists the pin assignments by pin number, and table 4 lists the pin assignments by functional categories. table 5 describes the signals. reserved reserved reserved reserved reserved d p0 d m0 ecap v ssp v ccp sof# reserved reserved reserved reserved reserved pllsel0 a8 / p2.0 a9 / p2.1 a10 / p2.2 a11 / p2.3 a12 / p2.4 a13 / p2.5 a14 / p2.6 a15 / p2.7 v ss v cc ea# ale psen# reserved reserved reserved reserved a4392-02 ad7 / p0.7 ad6 / p0.6 ad5 / p0.5 ad4 / p0.4 ad3 / p0.3 ad2 / p0.2 ad1 / p0.1 ad0 / p0.0 v ssp v ccp p3.0 / rxd p3.1 / txd p3.2 / int0# p3.3 / int1# p3.4 / t0 p3.5 / t1 p3.6 / wr# 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 view of component as mounted on pc board 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p3.7 / rd# / a16 p1.0 / t2 p1.1 / t2ex p1.2 / eci p1.3 / cex0 p1.4 / cex1 p1.5 / cex2 p1.6 / cex3 / wait# p1.7 / cex4 / a17 / wclk v cc v ss xtal1 xtal2 av cc rst pllsel1 pllsel2 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 note: reserved pins must be left unconnected.
advance information 5 8X930AX universal serial bus (usb) microcontroller table 3. 68-pin plcc pin assignment pin name pin name pin name 1v ss 24 p3.4/t0 47 reserved 2 a15/p2.7 25 p3.5/t1 48 reserved 3 a14/p2.6 26 p3.6/wr# 49 reserved 4 a13/p2.5 27 p3.7/rd#/a16 50 sof# 5 a12/p2.4 28 p1.0/t2 51 v ccp 6 a11/p2.3 29 p1.1/t2ex 52 v ssp 7 a10/p2.2 30 p1.2/eci 53 ecap 8 a9/p2.1 31 p1.3/cex0 54 d m 0 9 a8/p2.0 32 p1.4/cex1 55 d p 0 10 ad7/p0.7 33 p1.5/cex2 56 reserved 11 ad6/p0.6 34 p1.6/cex3/wait# 57 reserved 12 ad5/p0.5 35 p1.7/cex4/a17/wclk 58 reserved 13 ad4/p0.4 36 v cc 59 reserved 14 ad3/p0.3 37 v ss 60 reserved 15 ad2/p0.2 38 xtal1 61 reserved 16 ad1/p0.1 39 xtal2 62 reserved 17 ad0/p0.0 40 av cc 63 reserved 18 v ssp 41 rst 64 reserved 19 v ccp 42 pllsel1 65 psen# 20 p3.0/rxd 43 pllsel2 66 ale 21 p3.1/txd 44 pllsel0 67 ea# 22 p3.2/int0# 45 reserved 68 v cc 23 p3.3/int1# 46 reserved
6 advance information 8X930AX universal serial bus (usb) microcontroller table 4. 68-pin plcc signal assignments arranged by functional category address & data input/output usb name pin name pin name pin ad0/p0.0 17 p1.0/t2 28 pllsel0 44 ad1/p0.1 16 p1.1/t2ex 29 pllsel1 42 ad2/p0.2 15 p1.2/eci 30 pllsel2 43 ad3/p0.3 14 p1.3/cex0 31 sof# 50 ad4/p0.4 13 p1.4/cex1 32 ecap 53 ad5/p0.5 12 p1.5/cex2 33 d m 0 54 ad6/p0.6 11 p1.6/cex3/wait# 34 d p 0 55 ad7/p0.7 10 p1.7/cex4/a17/wclk 35 a8/p2.0 9 p3.0/rxd 20 processor control a9/p2.1 8 p3.1/txd 21 name pin a10/p2.2 7 p3.4/t0 24 p3.2/int0# 22 a11/p2.3 6 p3.5/t1 25 p3.3/int1# 23 a12/p2.4 5 ea# 67 a13/p2.5 4 bus control & status rst 41 a14/p2.6 3 name pin xtal1 38 a15/p2.7 2 p3.6/wr# 26 xtal2 39 p3.7/rd#/a16 27 p3.7/rd#/a16 27 p1.7/cex4/a17/wclk 35 ale 66 psen# 65 power & ground name pin v cc 36, 68 v ccp 19, 51 av cc 40 ea# 67 v ss 1, 37 v ssp 18, 52
advance information 7 8X930AX universal serial bus (usb) microcontroller 3.0 signals table 5. signal descriptions signal name type description alternate function a17 o 18th address bit (a17). output to memory as 18th exter- nal address bit (a17) in extended bus applications, depend- ing on the values of bits rd0 and rd1 in configuration byte uconfig0. see also rd#, psen#. p1.7/cex4/wclk a16 o address line 16 . see rd#. rd# a15:8 ? o address lines . upper address lines for the external bus. p2.7:0 ad7:0 ? i/o address/data lines . multiplexed lower address lines and data lines for external memory. p0.7:0 ale o address latch enable (ale) . ale signals the start of an external bus cycle and indicates that valid address informa- tion is available on lines a15:8 and ad7:0. an external latch can use ale to demultiplex the address from the address/data bus. prog# av cc pwr analog v cc . a separate v cc input for the phase-locked loop circuitry. cex2:0 cex3 cex4 i/o programmable counter array (pca) input/output pins . these are input signals for the pca capture mode and out- put signals for the pca compare mode and pca pwm mode. p1.5:3 p1.6/wait# p1.7/a17/wclk d m 0 i/o data minus . usb minus data line interface. d p 0 i/o data plus . usb plus data line interface. ea# i external access . directs program memory accesses to on-chip or off-chip code memory. for ea# strapped to ground, all program memory accesses are off-chip. for ea# strapped to v cc , program accesses on-chip rom if the address is within the range of the on-chip rom; otherwise, the access is off-chip. the value of ea# is latched at reset. for devices without on-chip rom, ea# must be strapped to ground. ecap i external capacitor . must be connected to a 1 f capacitor (or larger) to ensure proper operation of the differential line driver. the other lead of the capacitor must be connected to v ss . eci i pca external clock input . external clock input to the 16- bit pca timer. p1.2 int1:0# i external interrupts 0 and 1 . these inputs set bits ie1:0 in the tcon register. if bits it1:0 in the tcon register are set, bits ie1:0 are set by a falling edge on int1#/int0#. if bits int1:0 are clear, bits ie1:0 are set by a low level on int1:0#. p3.3:2 p0.7:0 i/o port 0 . this is an 8-bit, open-drain, bidirectional i/o port. ad7:0 ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration. if the chip is configured for page-mode operation, port 0 carries the lower address bits (a7:0), and port 2 car- ries the upper address bits (a15:8) and the data (d7:0).
8 advance information 8X930AX universal serial bus (usb) microcontroller p1.0 p1.1 p1.2 p1.5:3 p1.6 p1.7 i/o port 1 . this is an 8-bit, bidirectional i/o port with internal pullups. t2 t2ex eci cex2:0 cex3/wait# cex4/a17/wclk p2.7:0 i/o port 2 . this is an 8-bit, bidirectional i/o port with internal pullups. a15:8 p3.0 p3.1 p3.3:2 p3.5:4 p3.6 p3.7 i/o port 3 . this is an 8-bit, bidirectional i/o port with internal pullups. rxd txd int1:0# t1:0 wr# rd#/a16 pllsel2:0 i phase-locked loop select . three-bit code selects usb data rate (see table 8 on page 12). psen# o program store enable . read signal output. this output is asserted for a memory address range that depends on bits rd0 and rd1 in configuration byte uconfig0 (see rd#). rd# o read or 17th address bit (a16). read signal output to external data memory or 17th external address bit (a16), depending on the values of bits rd0 and rd1 in configura- tion byte uconfig0 (see psen#). p3.7/a16 rst i reset . reset input to the chip. holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an internal pulldown resistor which allows the device to be reset by connecting a capacitor between this pin and v cc . asserting rst when the chip is in idle mode or powerdown mode returns the chip to normal operation. rxd i/o receive serial data . rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2, and 3. p3.0 sof# o start of frame . start of frame pulse. active low, asserted for 8 states (see table 8 on page 12 for state versus xtal clock) when frame timer is locked to usb frame timing and sof token or artificial sof is detected. t1:0 i timer 1:0 external clock inputs . when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. p3.5:4 t2 i/o timer 2 clock input/output . for the timer 2 capture mode, this signal is the external clock input. for the clock-out mode, it is the timer 2 clock output. p1.0 table 5. signal descriptions (continued) signal name type description alternate function ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration. if the chip is configured for page-mode operation, port 0 carries the lower address bits (a7:0), and port 2 car- ries the upper address bits (a15:8) and the data (d7:0).
advance information 9 8X930AX universal serial bus (usb) microcontroller t2ex i timer 2 external input . in timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. in auto- reload mode, a falling edge causes the timer 2 registers to be reloaded. in the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. p1.1 txd o transmit serial data . txd outputs the shift clock in serial i/o mode 0 and transmits serial data in serial i/o modes 1, 2, and 3. p3.1 v cc pwr supply voltage . connect this pin to the +5v supply volt- age. v ccp pwr supply voltage for i/o buffers . connect this pin to the +5v supply voltage. v ss gnd circuit ground . connect this pin to ground. v ssp gnd circuit ground for i/o buffers . connect this pin to ground. wait# i real-time wait state input. the real-time wait# input is enabled by writing a logical 1 to the wcon.0 (rtwe) bit at s:a7h. during bus cycles, the external memory system can signal system ready to the microcontroller in real time by controlling the wait# input signal on the port 1.6 input. p1.6/cex3 wclk o wait clock output. the real-time wclk output is driven at port 1.7 (wclk) by writing a logical 1 to the wcon.1 (rtwce) bit at s:a7h. when enabled, the wclk output produces a square wave signal with a period of t clk . p1.7/cex4/a17 wr# o write . write signal output to external memory. p3.6 xtal1 i input to the on-chip, inverting, oscillator amplifier . to use the internal oscillator, a crystal/resonator circuit is con- nected to this pin. if an external oscillator is used, its output is connected to this pin. xtal1 is the clock source for inter- nal timing. xtal2 o output of the on-chip, inverting, oscillator amplifier . to use the internal oscillator, a crystal/resonator circuit is con- nected to this pin. if an external oscillator is used, leave xtal2 unconnected. table 5. signal descriptions (continued) signal name type description alternate function ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration. if the chip is configured for page-mode operation, port 0 carries the lower address bits (a7:0), and port 2 car- ries the upper address bits (a15:8) and the data (d7:0).
10 advance information 8X930AX universal serial bus (usb) microcontroller ? rd1:0 are bits 3:2 of configuration byte uconfig0. refer to figure 4-3 on page 4-5 in the 8X930AX uni- versal serial bus microcontroller users manual . 4.0 address map table 6. memory signal selections (rd1:0) rd1:0 ? a17/p1.7 /cex4/wclk a16/p3.7/rd# psen# wr# features 0 0 a17 a16 asserted for all addresses asserted for writes to all memory locations 256-kbyte external memory 0 1 p1.7/cex4/wclk a16 asserted for all addresses asserted for writes to all memory locations 128-kbyte external memory 1 0 p1.7/cex4/wclk p3.7 only asserted for all addresses asserted for writes to all memory locations 64-kbyte external memory one additional port pin 1 1 p1.7/cex4/wclk rd# asserted for addresses 7f:ffffh asserted for addresses 3 80:0000h asserted for all com- patible mcs 51 mem- ory locations compatible with mcs 51 microcon- trollers table 7. 8 x 930a x address map internal address description notes ff:ffffh ff:0000h external memory: the last eight bytes of the external address range ff:xff8hC ff:xfffh contain configuration byte information. 1, 2, 3 fe:ffffh fe:0000h external memory 2 fd:ffffh 02:0000h reserved addresses 4 01:ffffh 01:0000h external memory 2 00:ffffh 00:0420h external memory 5 00:041fh 00:0080h on-chip ram 5 00:007fh 00:0020h on-chip ram 6 00:001fh 00:0000h storage for r0Cr7 of register file 7, 8 notes: 1. eighteen address lines are bonded out (a15:0, a16:0, or a17:0 selected during chip configuration). 2. data in this area is accessible by indirect addressing only. 3. eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information. 4. this reserved area returns unspecified values and writes no data. 5. data is accessible by direct and indirect addressing. 6. data is accessible by direct, indirect, and bit addressing. 7. the special function registers (sfrs) and the register file have separate internal address spaces. 8. data is accessible by direct, indirect, and register addressing.
advance information 11 8X930AX universal serial bus (usb) microcontroller 5.0 electrical characteristics absolute maximum ratings ambient temperature under bias.................... -40c to +85c storage temperature ................................... -65c to +150c voltage on any pins to v ss ............................. -0.5 v to +6.5 v i ol per i/o pin ................................................................. 15 ma power dissipation .......................................................... 1.5 w operating conditions ? t a (ambient temperature under bias): commercial ........................................................ -0c to +70c v cc /v ccp (digital supply voltage) .................. 4.00 v to 5.25 v v ss / v ssp ............................................................................ 0 v av cc (analog supply voltage) ...................... 4.00 v to 5.25 v f osc .............................................................. 6 mhz or 12 mhz note: maximum power dissipation is based on package heat-transfer limitations, not device power consumption. notice: this document contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. ? warning : stressing the device beyond the absolute maximum ratings may cause perma- nent damage. these are stress ratings only. oper- ation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability.
12 advance information 8X930AX universal serial bus (usb) microcontroller 5.1 operating frequencies figure 5. clock circuit table 8. frequency selection and operating frequency pllsel2 pin 43 pllsel1 pin 42 pllsel0 pin 44 usb rate (low speed or full speed) 8 x 930a x internal frequency for cpu and peripherals (f clk ) (5) xtal1 external frequency (f osc ) number of xtal1 clocks (t osc ) in one statetime (4) comments 0 0 1 1.5 mbps (ls) 3 mhz 6 mhz 2 t osc /state pll off 1 0 0 1.5 mbps (ls) 6 mhz (3) 12 mhz 2 t osc /state pll off 1 1 0 12 mbps (fs) 12 mhz (3) 12 mhz 1 t osc /state pll on notes: 1. other pllsel x combinations are not valid. 2. the sampling rate is 4x the usb rate. 3. the 8 x 930a x cpu and peripherals frequency is 3 mhz (low clock mode) until firmware disables the low clock mode. 4. the number of xtal clocks in one state depends on the pllselx selections. when the cpu is oper- ating at low clock mode (3 mhz), there are four t osc per state for the pllsel2:1:0 = 100 and 110. 5. the ac timing specification (table 11) defines the following symbol: cpu frequency = f clk = 1/t clk . clock generator a5135-01 xtal1 xtal2 f osc (6 or 12 mhz) pcon.0 (idle mode) idl pcon.1 (powerdown) 0 1 pd 2 10 2 pllsel f clk cpu on-chip peripherals internal clock pcon.5 (low-clock mode) lc 0 1 3 mhz
advance information 13 8X930AX universal serial bus (usb) microcontroller 5.2 dc characteristics table 9. dc characteristics at operating conditions symbol parameter min typical (1) max units test conditions v il input low voltage (except ea#) -0.5 0.2 v cc C 0.1 v v il 1 input low voltage (ea#) 00.2 v cc C 0.3 v v ih input high voltage (except xtal1, rst) 0.2 v cc + 0.9 v cc + 0.5 v v ih 1 input high voltage (xtal1, rst) 0.7 v cc v cc + 0.5 v v ol output low voltage (port 1, 2, 3) 0.3 0.45 1.0 v i ol = 100 a (2, 3) i ol = 1.6 ma i ol = 3.5 ma v ol 1 output low voltage (port 0, ale, psen#, sof#) 0.3 0.45 1.0 v i ol = 200 a (2, 3) i ol = 3.2 ma i ol = 7.0 ma v oh output high voltage (port 1, 2, 3,ale, psen#, sof#) v cc C 0.3 v cc C 0.7 v cc C 1.5 v i oh = -10 a (4) i oh = -30 a i oh = -60 a v oh 1 output high voltage (port 0 in external address) v cc C 0.3 v cc C 0.7 v cc C 1.5 v i oh = -200 a (4) i oh = -3.2 ma i oh = -7.0 ma i il logical 0 input current (port 1,2,3) C150 a v in = 0.45 v i li input leakage current (port 0) 10 a 0.45 < v in < v cc note: 1. typical values are obtained using v cc = 5.0v, t a = 25c and are not guaranteed. 2. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i oh per port pin:10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1-3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 3. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive loading exceeds 100pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 4. capacitive loading on ports 0 and 2 cause the v oh on ale and psen to drop below the v cc specifica- tion when the address lines are stabilizing. 5. the abbreviations ls and fs indicate low speed and full speed, respectively.
14 advance information 8X930AX universal serial bus (usb) microcontroller i tl logical 1-to-0 transition current (port 1, 2,3) -650 a v in = 2.0 v r rst rst pulldown resistor 40 225 k w c io 10 pf f osc = 12 mhz t a = 25c i pd powerdown current normal powerdown usb suspend 25 145 50 175 a i dl (5) idle mode i cc 40 ma pllsel = 110 3mhz C fs (in low clock mode) 100 pllsel = 110 12mhz C fs (not in low clock mode) 30 pllsel = 001 3mhz C ls 55 pllsel = 100 6 mhz C ls table 9. dc characteristics at operating conditions (continued) symbol parameter min typical (1) max units test conditions note: 1. typical values are obtained using v cc = 5.0v, t a = 25c and are not guaranteed. 2. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i oh per port pin:10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1-3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 3. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive loading exceeds 100pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 4. capacitive loading on ports 0 and 2 cause the v oh on ale and psen to drop below the v cc specifica- tion when the address lines are stabilizing. 5. the abbreviations ls and fs indicate low speed and full speed, respectively.
advance information 15 8X930AX universal serial bus (usb) microcontroller 5.3 definition of ac symbols i cc (5) active i cc 60 ma pllsel = 110 3 mhz C fs (in low clock mode) 150 pllsel = 110 12 mhz C fs (not in low clock mode) 45 pllsel = 001 3 mhz C ls 75 pllsel = 100 6 mhz C ls table 10. ac timing symbol definitions signals conditions a address h high d data in l low l ale v valid q data out x hold r rd#/psen# z floating wwr# table 9. dc characteristics at operating conditions (continued) symbol parameter min typical (1) max units test conditions note: 1. typical values are obtained using v cc = 5.0v, t a = 25c and are not guaranteed. 2. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i oh per port pin:10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1-3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 3. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive loading exceeds 100pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 4. capacitive loading on ports 0 and 2 cause the v oh on ale and psen to drop below the v cc specifica- tion when the address lines are stabilizing. 5. the abbreviations ls and fs indicate low speed and full speed, respectively.
16 advance information 8X930AX universal serial bus (usb) microcontroller 5.4 ac characteristics test conditions: capacitive load on all pins = 50 pf, rise and fall times = 10 ns, f osc = 6 mhz or 12 mhz 5.4.1 system bus ac characteristics table 11. ac characteristics at operating conditions symbol parameter cpu frequency @ 12 mhz (m, n = 0) cpu frequency (f clk ) variable units min max t clk 1/(cpu frequency) 83.33 (typical) ns (1, 2) t lhll ale pulse width 34.66 (0.5+m)t clk C 7 ns (3) t avll address valid to ale low 26.66 (0.5+m)t clk C 17 ns (3) t llax address hold after ale low 4 4 ns (4) t rlrh (5) rd# or psen# pulse width 73.33 (1+n)t clk C 10 ns (6) t wlwh wr# pulse width 71.33 (1+n)t clk C 12 ns (6) t llrl (5) ale low to rd# or psen# low 8 8 ns t lhax ale high to address hold 40.33 (1+m)t clk C 43 ns (3) t rldv (5) rd# or psen# low to valid data/instruction in 50.33 (1+n)t clk C 33 ns (6) t rhdx (5) data/instruct. hold after rd# or psen# high 00 ns t rlaz (5) rd# or psen# low to address float 00ns t rhdz 1 (5) instruct. float after psen# high 10 10 ns t rhdz 2 (5) data float after rd# or psen# high 83.33 t clk ns t rhlh 1 (5) psen# high to ale high (instruction) 10 10 ns t rhlh 2 (5) rd# or psen# high to ale high (data) 83.33 t clk ns t whlh wr# high to ale high 88.33 t clk + 5 ns t avdv 1 address (p0) valid to valid data/instruction in 106.66 (2+m+n)t clk C 63 ns (3, 6) notes: 1. refer to table 8 on page 12 for cpu frequencies vs. xtal1 frequencies. 2. xtal1 frequency is 0.25% for full speed and 1.5% for low speed. 3. m= 0,1 is the extended ale state. 4. at 50 c, t llax = 8 ns 5. specifications for psen# are identical to those for rd#. 6. n= 0,1,2,3 is the rd#/psen#/wr# wait state.
advance information 17 8X930AX universal serial bus (usb) microcontroller t avdv 2 address (p2) valid to valid data/instruction in 118.66 (2+m+n)t clk C 48 ns (3, 6) t avdv 3 address (p2) valid to valid instruction in 23.33 (1+n)t clk C 60 ns (6) t avrl (5) address valid to rd# or psen# low 40.33 (1+m)t clk C 46 ns (3) t avwl 1 address (p0) valid to wr# low 40.33 (1+m)t clk C 46 ns (3) t avwl 2 address (p2) valid to wr# low 66.33 (1+m)t clk C 17 ns (3) t whqx data hold after wr# high 28.66 0.5 t clk C 13 ns t qvwh data valid to wr# high 68.33 (1+n)t clk C15 ns (6) t whax wr# high to address hold 70.33 t clk C 13 ns table 11. ac characteristics at operating conditions (continued) symbol parameter cpu frequency @ 12 mhz (m, n = 0) cpu frequency (f clk ) variable units min max notes: 1. refer to table 8 on page 12 for cpu frequencies vs. xtal1 frequencies. 2. xtal1 frequency is 0.25% for full speed and 1.5% for low speed. 3. m= 0,1 is the extended ale state. 4. at 50 c, t llax = 8 ns 5. specifications for psen# are identical to those for rd#. 6. n= 0,1,2,3 is the rd#/psen#/wr# wait state.
18 advance information 8X930AX universal serial bus (usb) microcontroller 5.4.2 system bus timing diagrams, nonpage mode figure 6. 8 x 930a x code fetch, nonpage mode ale rd#/psen# p0 a17/a16/p2 a5011-01 state 1 state 1 (next cycle) state 2 t lhll t llrl t rlrh t rlaz t llax t avll t avdv1 t avdv2 t lhax instruction in a7:0 a17/a16/a15:8 t rhdx t rhdz1 t rhlh1 t avrl t rldv
advance information 19 8X930AX universal serial bus (usb) microcontroller figure 7. 8 x 930a x data read, nonpage mode figure 8. 8 x 930a x data write, nonpage mode ale rd#/psen# p0 a17/a16/p2 a5025-02 state 1 state 3 state 2 t lhll t llrl t rlrh t rlaz t llax t rldv t avdv1 t avdv2 t lhax d7:0 a7:0 a17/a16/a15:8 t rhdx t rhdz2 t rhlh2 t avrl t avll t qvwh ale wr# p0 a17/a16/p2 a5026-02 state 1 state 3 state 2 t lhll t wlwh t llax t lhax d7:0 a7:0 a17/a16/a15:8 t whlh t avwl2 t avll t avwl1 t whax t whqx
20 advance information 8X930AX universal serial bus (usb) microcontroller 5.4.3 system bus timing diagrams, page mode figure 9. 8 x 930a x code fetch, page mode ale rd#/psen# p2 a17/a16/p0 a5028-02 state 1 state 2 t lhll t llrl t rlrh t rlaz t llax t avll t avdv1 t avdv2 t lhax instruction 1 in a15:8 a17/a16/a7:0 t rhdz1 t rhlh1 t avrl t rldv t rhdx instruction 2 in t avdv3 cycle 2, page hit state 1 cycle 1, page miss ? during a sequence of page hits, psen# remains low until the end of the last page hit cycle. ?
advance information 21 8X930AX universal serial bus (usb) microcontroller figure 10. 8 x 930a x data read, page mode figure 11. 8 x 930a x data write, page mode ale rd#/psen# p2 a17/a16/p0 a5029-02 state 1 state 3 state 2 t lhll t llrl t rlrh t rlaz t llax t rldv t avdv1 t avdv2 t lhax d7:0 a15:8 a17/a16/a7:0 t rhdx t rhdz2 t avrl t avll t rhlh2 t qvwh ale wr# p2 a17/a16/p0 a5030-02 state 1 state 3 state 2 t lhll t wlwh t llax t lhax d7:0 a15:8 a17/a16/a7:0 t whlh t avwl2 t avll t avwl1 t whax t whqx
22 advance information 8X930AX universal serial bus (usb) microcontroller 5.4.4 definition of real-time wait symbols 5.4.5 real-time wait function ac characteristics table 12. real-time wait timing symbol definitions signals conditions a address l low d data x hold c wclk v setup ywait# wwr# r rd#/psen# table 13. real-time wait ac timing specifications symbol parameter f clk variable (1) (2) units min typ max t clyv wait clock low to wait setup 0 0.5 t clk C 13 ns t clyx wait hold after wait clock low (w)t clk + 5 (0.5+w)t clk C 13 ns t rlyv psen# or rd# low to wait setup 0 0.5 t clk C 13 ns t rlyx wait hold after psen# or rd# low (w)t clk + 5 (0.5+w)t clk C 13 ns t wlyv wr# low to wait setup 0 0.5 t clk C 13 ns t wlyx wait hold after wr# low (w)t clk + 5 (0.5+w)t clk C 13 ns notes: 1. w = 0, 1, 2, ... is the number of real-time wait states. 2. real-time wait function has a critical timing for instruction read. it is not advisable to use this feature for instruction read during page mode.
advance information 23 8X930AX universal serial bus (usb) microcontroller 5.4.6 real-time wait function timing diagrams figure 12. external code fetch/data read (nonpage mode, real-time wait state) a7:0 wclk ale rd#/psen# wait# p0 p2 a15:8 a5000-02 state 1 state 2 state 3 state 1 (next cycle) t clyx min t clyv a7:0 d7:0 stretched a15:8 stretched rd#/psen# stretched t clyx max t rlyv t rlyx max t rlyx min
24 advance information 8X930AX universal serial bus (usb) microcontroller figure 13. external data write (nonpage mode, real-time wait state) a7:0 wclk ale wr# t wlyv wait# p0 p2 a5002-02 state 1 state 2 state 3 state 4 t clyx min t clyv d7:0 stretched a15:8 stretched wr# stretched t wlyx max t wlyx min t clyx max
advance information 25 8X930AX universal serial bus (usb) microcontroller figure 14. external data read (page mode, real-time wait state) a15:8 wclk ale rd#/psen# wait# p2 p0 a7:0 a5001-02 state 1 state 2 state 3 state 1 (next cycle) t clyx min t clyv a15:8 d7:0 stretched a7:0 stretched rd#/psen# stretched t clyx max t rlyv t rlyx max t rlyx min
26 advance information 8X930AX universal serial bus (usb) microcontroller figure 15. external data write (page mode, real-time wait state) a15:8 wclk ale wr# t wlyv wait# p2 p0 a5003-02 state 1 state 2 state 3 state 4 t clyx min t clyv d7:0 stretched a7:0 stretched wr# stretched t wlyx max t wlyx min t clyx max
advance information 27 8X930AX universal serial bus (usb) microcontroller 5.5 ac characteristics serial port, synchronous mode 0 figure 16. serial port waveform synchronous mode 0 table 14. serial port timing synchronous mode 0 symbol parameter min max units t xlxl serial port clock cycle time 6 t osc ns t qvsh output data setup to clock rising edge 5 t osc C 133 ns t shqx output data hold after clock rising edge t osc C 50 ns t xhdx input data hold after clock rising edge 0 ns t xhdv clock rising edge to input data valid 5 t osc C 133 ns valid valid valid valid valid valid valid valid rxd (in) rxd (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t xhdx t xhqx t xhdv a2592-02 set ti ? set ri ? ? ti and ri are set during s1p1 of the peripheral cycle following the shift of the eighth bit.
28 advance information 8X930AX universal serial bus (usb) microcontroller 5.6 external clock drive figure 17. external clock drive waveforms table 15. external clock drive symbol parameter min max units 1/t osc oscillator frequency (f osc )6 12mhz t chcx high time 0.35 t osc 0.65 t osc ns t clcx low time 0.35 t osc 0.65 t osc ns t clch rise time 10 ns t chcl fall time 10 ns 0.7 v cc a4119-01 0.45 v v cc C 0.5 0.2 v cc C 0.1 t chcl t clcx t clcl t clch t chcx
advance information 29 8X930AX universal serial bus (usb) microcontroller 5.7 testing waveforms figure 18. ac testing input, output waveforms figure 19. float waveforms ac inputs during testing are driven at v cc C 0.5v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 0.45 v inputs outputs a4118-01 v ih min v ol max v cc C 0.5 0.2 v cc + 0.9 0.2 v cc C 0.1 a min of v ih for a logic 1 and v ol for a logic 0. v load + 0.1 v v load C 0.1 v timing reference points v load v oh C 0.1 v v ol + 0.1 v for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol / i oh = 20 ma. a4117-01
30 advance information 8X930AX universal serial bus (usb) microcontroller 6.0 thermal characteristics this microcontroller operates over the commercial temperature range from 0 o c to 70 o c. all thermal impedance data (table 16) is approximate for static air conditions at 1 watt of power dissipation. values change depending on operating conditions and application requirements. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. the components quality and reliability handbook (order number 210997) provides quality and reliability information. 7.0 product reference this section lists design considerations for the 8X930AX universal serial bus microcontroller. 7.1 external bus timing and peripheral timing affected by pllsel2:0 selection pllsel2 (pin43), pllsel1 (pin 42), and pllsel0 (pin 44) determine the 8 x 930a x internal cpu operating frequency. the selected cpu operating frequency also influences all the peripherals. if the pllsel2:0 pins of the 8 x 930a x are set to 110, then the internal clock frequency is 12mhz, and one state time equals one clock time (please refer to table 8 on page 12). therefore, all internal and external instruction times for the timer, serial port, pca, are two times faster than with other pllsel2:0 selections. refer to the 8X930AX, 8x930hx universal serial bus microcontroller users manual for the new peripheral timing formulas. 7.2 low clock mode frequency in low clock mode, the cpu and peripherals run at 3 mhz. all external bus accesses are affected, including instruction fetch, data read/write, and peripheral timing. please refer to table 8 on page 12 for the relationship of 3 mhz cpu and peripheral timing (t clk ) to state times. one peripheral cycle is 6 state times. 7.3 setting ffrc bit clears only the oldest packet in the fifo if the receive fifo is set as a dual packet mode, it can receive two packets. setting ffrc to indicate fifo read complete will not flush the entire fifo, only the oldest packet will be flushed. the read marker will be advanced to the location of the read pointer. 7.4 series resistor requirement for impedance matching per the usb 1.0 specification (page 111, section 7.1.1.1), the impedance of the differential driver must be between 29 and 44 ohms. to match the cable impedance, a series resistor of 27 to 33 ohms should be connected to each usb line; i.e., on d p 0 (pin 55) and on d m 0 (pin 54). if the usb line is improperly terminated or not matched, signal fidelity will suffer. this can be seen on the scope as excessive overshoot and undershoot. this will potentially introduce bit errors. 7.5 pullup requirement for full speed device and low speed device the pullup is a usb requirement to allow the host to identify which devices are low speed and which are full speed in order to communicate at the appro- priate data rate. for full speed devices (12 mbps) use a 1.5k pullup resistor (to 3.0 v C 3.6 v) on the d p 0 line. for low speed devices (1.5mbps), use a 1.5k pullup resistor (to 3.0 v C 3.6 v) on the d m 0 line. 7.6 powerdown mode cannot be invoked before usb suspend if the 8 x 930a x is put into powerdown mode prior to receiving a usb suspend signal from the host, a usb resume will not properly wake up the 8 x 930a x from powerdown mode. table 16. thermal characteristics package type q ja q jc 68-pin plcc n/a n/a
advance information 31 8X930AX universal serial bus (usb) microcontroller 8.0 specification supplement for 8 x 930a x 3 and 8 x 930a x 4 all descriptions above apply to the 8 x 930a x and 8 x 930a x 2 microcontrollers. the following specifica- tions apply to recent steppings of the 8 x 930a x (8 x 930a x 3 and 8 x 930a x 4). this information is in addition to (or in place of) the specifications described above. 8.1 six endpoint pairs functionality in the default state, the sixeppen bit of 8 x 930a x 3s and 8 x 930a x 4s epconfig sfr is cleared and the 6 endpoint pair feature is disabled. in this state, the endpoint pairs of the 8 x 930a x 3 and 8 x 930a x 4 are similar to those of the 8 x 930a x and 8 x 930a x 2 devices. to enable the 6 endpoint pair feature, set epconfigs sixeppen bit. the 8 x 930a x 3 and 8 x 930a x 4 will then have the endpoint pairs shown in table 17. when the 6 endpoint pair feature is enabled, two additional sfrs the function interrupt enable register 1 (fie1) and the function interrupt flag register 1 (fiflg1) are enabled to manage interrupts for the additional endpoint pairs. see the 8X930AX, 8x930hx universal serial bus microcontroller users manual for additional infor- mation. 8.2 dc characteristics the v oh specification given in the dc character- istics section of this datasheet is changed to v oh = {min} v cc C 1.7 v when i oh = -60 a for the a3 stepping onward. 8.3 extended data float (edf) ac timing feature to provide a direct interface capability to slower memory without the use of tristate drivers, an extended data float (edf) option has been added to the 8 x 930a x 3 and 8 x 930a x 4. this option is controlled by the edf# bit (bit 3 in the uconfig1 configuration byte). if the edf# bit is configured to 1, the 8 x 930a x 3 and 8 x 930a x 4 behave per the current specification (some ac timings are different). this is known as "compatibility mode". table 19 on page 32 lists the ac characteristics in this "compatibility mode" that are different compared to the 8X930AX and 8X930AX2. parameters not listed in the table remain the same as for 8 x 930a x and 8 x 930a x 2. if the 8 x 930a x 3 and 8 x 930a x 4 are configured with edf# = 0, the device will have extended data float timings. this mode is known as the increased t rhdz 1 mode. table 20 on page 32 and table 21 on page 33 show the parameters that are affected when edf#= 0. configuring the device with edf# = 0 does not affect wait state a (all regions except 01:). wait state a can have 0, 1, 2, or 3 wait states. edf#=0 affects external wait state b (region 01:). the summary of the effect edf# has on wait states is listed in table 18. table 17. six endpoint pair feature epindex ffsz1:0 transmit fifo (bytes) receive fifo (bytes) 0xxx x000 xx 16 16 0xxx x001 00 256 256 0xxx x010 xx 32 32 0xxx x011 xx 32 32 0xxx x100 xx 32 32 0xxx x101 xx 16 16 table 18. effect of edf# on wait states edf# wsb#[1:0] wait-state (for page 01) 1 1 1 1 1 1 1 0 0 1 00 0 1 2 3 0 0 0 0 11 10 01 00 1 1 3 3
32 advance information 8X930AX universal serial bus (usb) microcontroller table 19. ac characteristics for 8X930AX3 and 8X930AX4 in compatibility mode symbol parameter 8X930AX3/8X930AX4 compatibility mode (ns) (edf# =1) (1) t avll address valid to ale low (0.5+m)t clk - 13 [min] t llax address hold after ale low 10 [min] t wlwh wr# pulse width (1+n)t clk - 10 [min] t llrl ale low to rd# or psen# low 10 [min] t lhax ale high to address hold (1+m)t clk - 27 [min] t rldv rd# or psen# low to valid data/inst. in (1+n)t clk - 30 [max] t rlaz rd# or psen# low to address float 3 max (2) t rhdz 2 data float after psen# or rd# high t clk + 10 [max] t rhlh 2 rd# or psen# high to ale high (data) t clk + 10 [min] t whlh wr# high to ale high t clk +10 [min] t avdv 2 address (demux'ed) valid to valid data/instr. in (2+m+n)t clk - 38 [max] t avrl address valid to rd# or psen# low (1+m)t clk - 40 [min] t avwl 1 address (mux'ed) valid to wr# low (1+m)t clk - 40 [min] notes: 1. device configured with default data float timing for fast memory interface. 2. typical value is 0 ns. table 20. 8 x 930a x 3 and 8 x 930a x 4 default and extended data float timings sym- bol parameter default data float timing (ns) compatibility mode (edf# =1) (1,2,4,5) extended data float timing (ns) increased t rhdz 1 mode (edf#=0) (1,3,4,5) t llax address hold after ale low 10 [min] 20 [min] t rlrh rd# or psen# pulse width (1+n)t clk - 10 [min] (1+n)t clk - 32 [min] t wlwh wr# pulse width (1+n)t clk - 10 [min] (1+n)t clk - 32 [min] t llrl ale low to rd# or psen# low 10 [min] 20 [min] t lhax ale high to address hold (1+m)t clk - 27 [min] (0.5+m)t clk + 15 [min] t rldv rd# or psen# low to valid data/inst. in (1+n)t clk - 30 [max] (1+n)t clk - 50 [max] t rhdz 1 instruct. float after psen# or rd# high 10 [max] (0.5)t clk - 5 [max] notes: 1. worst-case numbers based on silicon data collected to date. 2. device configured with default data float timing for fast memory interface. 3. device configured with extended data float timing for slow memory interface. 4. the values listed are for 12 mhz. for 6 mhz, the value of t clk will double and will equal 166.6 ns. 5. m=0,1 is the extended ale state; n= 0,1,2,3 is the rd#/psen#/wr# wait state.
advance information 33 8X930AX universal serial bus (usb) microcontroller t rhdz 2 data float after psen# or rd# high t clk + 10 [max] 1.5 t clk - 5 [max] t rhlh 2 rd# or psen# high to ale high (data) t clk + 10 [min] (1.5)t clk - 7 [min] t rhlh 1 psen# high to ale high (inst.) 10 [min] (0.5)t clk - 7 [min] t whlh wr# high to ale high t clk + 10 [min] (1.5)t clk - 7 [min] t avdv 1 address (mux'ed) valid to valid data/inst. in (2+m+n)t clk - 60 [max] (1.5+m+n)t clk - 28 [max] t avrl address valid to rd# or psen# low (1+m)t clk - 40 [min] (0.5+m)t clk + 10 [min] t avwl 1 address (mux'ed) valid to wr# low (1+m)t clk - 40 [min] (0.5+m)t clk + 10 [min] t avwl 2 address (demux'ed) valid to wr# low (1+m)t clk - 17 [min] (1+m)t clk + 10 [min] table 21. 8 x 930a x 3 and 8 x 930a x 4 real-time wait state ac timing specifications symbol (parameter) f clk variable default data float timing (ns) (edf#=1) f clk variable extended data float timing (ns) (edf#=0) m i n t y p m a x m i n t y p m a x t rlyv (psen# or rd# low to wait setup) 00.5 t clk - 13 0 0.5 t clk - 35 t wlyv (wr# low to wait setup) 0 0.5 t clk - 13 0.5 t clk - 35 table 20. 8 x 930a x 3 and 8 x 930a x 4 default and extended data float timings (continued) sym- bol parameter default data float timing (ns) compatibility mode (edf# =1) (1,2,4,5) extended data float timing (ns) increased t rhdz 1 mode (edf#=0) (1,3,4,5) notes: 1. worst-case numbers based on silicon data collected to date. 2. device configured with default data float timing for fast memory interface. 3. device configured with extended data float timing for slow memory interface. 4. the values listed are for 12 mhz. for 6 mhz, the value of t clk will double and will equal 166.6 ns. 5. m=0,1 is the extended ale state; n= 0,1,2,3 is the rd#/psen#/wr# wait state.
34 advance information 8X930AX universal serial bus (usb) microcontroller 9.0 device errata the 8 x 930a x may contain design defects or errors known as errata. characterized errata that may cause the 8 x 930a x s behavior to deviate from published specifications are documented in a speci- fication update. refer to the 8X930AX (8x930ad, 8x930ae) specification update (order number 272940, revision 007 or later). specification updates can be obtained from your local intel sales office or from the world wide web (www.intel.com). 10.0 datasheet revision history this datasheet is valid for a-2 through a-4 step devices. datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. this (-003) revision of the 8 x 930a x datasheet replaces earlier product information. the following changes were made in this version: 1. added specification supplement for 8X930AX3 and 8X930AX4 on page 31. 2. the following ac characteristics were changed: t avll , t avdv 1, t avrl , t avwl 1. 3. i cc characteristics updated.

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