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| em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 1 www.emmicroelectronic.com ultra low power multi i/o microcontroller features ? low power - typical 1.8a active mode - typical 0.35a standby mode - typical 0.1a sleep mode @ 1.5v, 32khz, 25 c ? low voltage - 1.2 to 3.6 v ? buzzer - three tone ? rom - 2k 16 (mask programmed) ? ram - 96 4 (user read/write) ? 2 clocks per instruction cycle ? risc architecture ? 4 software configurable 4-bit ports ? up to 16 inputs (4 ports) ? up to 12 outputs (3 ports) ? serial (output) write buffer - swb ? voltage level detection ? analogue watchdog ? timer watchdog ? 8 bit timer / event counter ? internal interrupt sources (timer, event counter, prescaler, swb) ? external interrupt sources (porta + portc) description the em6603 is an advanced single chip low cost, mask programmed - cmos 4-bit microcontroller. it contains rom, ram, watchdog timer, oscillation detection circuit, combined timer / event counter, prescaler, voltage level detector and a number of clock functions. its low voltage and low power operation make it the most suitable controller for battery, stand alone and mobile equipment. the em66xx series is manufactured using em microelectronic?s advanced low power cmos process. typical applications ? sensor interfaces ? domestic appliances ? security systems ? bicycle computers ? automotive controls ? tv & audio remote controls ? measurement equipment ? r/f and ir. control figure 1.architecture figure 2.pin configuration em microelectronic - marin sa
em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 2 www.emmicroelectronic.com em6603 at a glance ? power supply - low voltage, low power architecture including internal voltage regulator - 1.2v ... 3.6 v battery voltage - 1.8 a in active mode - 0.35 a in standby mode - 0.1 a in sleep mode @ 1.5v, 32khz, 25 c - 32 khz oscillator ? ram - 96 x 4 bit, direct addressable ? rom - 2048 x 16 bit metal mask programmable ? cpu - 4 bit risc architecture - 2 clock cycles per instruction - 72 basic instructions ? main operating modes and resets - active mode (cpu is running) - standby mode (cpu in halt) - sleep mode (no clock, reset state) - initial reset on power-on (por) - external reset pin - watchdog timer (time-out) reset - oscillation detection watchdog reset - reset with input combination on porta (metal option) ? 4-bit input porta - direct input read - debounced or direct input selectable (reg.) - interrupt request on input?s rising or falling edge, selectable by register. - pull-down or none, selectable by metal mask - software test variables for conditional jumps - pa3 input for the event counter - reset with input combination on porta (metal option) ? 4-bit input/output portb - separate input or output selection by register - pull-up, pull-down or none, selectable by metal mask if used as input - buzzer output on pb0 ? 4-bit input/output portc - input or output port as a whole port - debounced or direct input selectable (reg.) - interrupt request on input?s rising or falling edge, selectable by register. - pull-up, pull-down or none, selectable by metal mask if used as input - cmos or n-channel open drain mode ? 4-bit input/output portd - input or output port as a whole port - pull-up, pull-down or none, selectable by metal mask if used as input - cmos or n-channel open drain mode - serial write buffer clock and data output ? serial (output) write buffer - max. 256 bits long clocked with 16/8/2/1khz - automatic send mode - interactive send mode : interrupt request when buffer is empty ? buzzer output - if used output on pb0 - 3 tone buzzer - 1khz, 2khz, 2.66khz ? prescaler - 32khz output possible on the stb/rst pin - 15 stage system clock divider down to 1 hz - 3 interrupt requests : 1hz/8hz/32hz - prescaler reset (from 8khz to 1hz) ? 8-bit timer / event counter - 8-bit auto-reload count-down timer - 6 different clocks from prescaler - or event counter from the pa3 input - parallel load - interrupt request when comes to 00 hex. ? supply voltage level detector - 3 software selectable levels (1.3v, 2.0v, 2.3v or user defined between 1.3v and 3.0v) - busy flag during measure - active only on request during measurement to reduce power consumption ? interrupt controller - 8 external interrupt sources: 4 from port a and 4 from port c - 3 internal interrupt sources, prescaler, timer and serial write buffer - each interrupt request is individually maskable - interrupt request flag is cleared automatically on register read em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 3 www.emmicroelectronic.com table of contents 1 operating modes 5 1.1 standby m ode 5 1.2 sleep mode 5 2 power supply 5 3 reset 6 3.1 o scillation detection circuit 6 3.2 r eset p in 6 3.3 i nput port (pa0..pa3) reset 7 3.4 w atchdog t imer reset 7 3.5 cpu s tate after reset 7 4 oscillator 8 4.1 p rescaler 8 5 watchdog timer 8 6 input and output ports 9 6.1 p ort a9 6.2 p ort a registers 10 6.3 p ort b11 6.4 p ort b registers 11 6.5 p ort c12 6.6 p ort c registers 12 6.7 p ort d14 6.8 p ort d registers 14 7 buzzer 15 7.1 b uzzer r egister 15 8 timer/event counter 16 8.1 t imer /c ounter registers 17 9 interrupt controller 18 9.1 i nterrupt control registers 18 10 supply voltage level detector (svld) 20 10.1 svld register 20 11 serial (output) write buffer ? swb 21 11.1 swb a utomatic send mode 23 11.2 swb i nteractive send mode 25 12 strobe / reset output 26 13 test at em - active supply current test 26 14 metal mask options 27 15 28 15 peripheral memory map 28 16 electrical specifications 30 16.1 a bsolute maximum ratings 30 16.2 s tandard o perating c onditions 30 16.3 h andling p rocedures 30 16.4 dc characteristics - p ower s upply p ins 30 16.5 dc characteristics - i nput /o utput p ins 31 16.6 dc characteristics - s upply v oltage d etector l evels 32 16.7 o scillator 33 16.8 i nput t iming characteristics 33 17 pad location diagram 34 18 package and ordering information 34 18.1 o rdering i nformation 36 18.2 p ackage m arking 36 18.3 c ustomer m arking 36 19 specification change 37 table of figures figure 1.architecture 1 figure 2.pin configuration 1 figure 3.typical configuration 4 figure 4.mode transition diagram 5 figure 5.system reset generation 6 figure 6.port a 10 figure 7.port b 11 figure 8.port c 13 figure 9.port d 14 figure 10.timer / event counter 16 figure 11.interrupt request generation 19 figure 12.serial write buffer 22 figure 13.automatic serial write buffer transmission 23 figure 14.interactive serial write buffer transmission 25 figure 15. em6603 pad location diagram 34 figure 16. dimensions of pdip24 pack. - pack. type ?a? 34 figure 17. dimensions of tssop24 pack. - pack. type ?f? 35 figure 18. dimensions of sop24 pack. soic ? pack. type ?b? 35 table of tables table 1. pin description 4 table 2.standby and sleep activities 5 table 3. porta inputs reset options (metal hardware option) 7 table 4. watchdog-timer option (software option) 7 table 5. initial value after reset 7 table 6.prescaler interrupt source 8 table 7. prescaler control register - presc 8 table 8.watchdog register - wd 8 table 9.input / output ports overview 9 table 10.option register - option 9 table 11.porta input status register - porta 10 table 12.porta interrupt request register - irqpa 10 table 13.porta interrupt mask register - mporta 10 table 14.portb input status register - portb 11 table 15.portb input/output control register - cioportb 11 table 16.ports a&c interrupt request 12 table 17.portc input/output register - portc 12 table 18.portc interrupt request register - irqpc 12 table 19.portc interrupt mask register - mportc 12 table 20.portd input/output register - portd 14 table 21.ports control register - cpiob 14 table 22.buzzer frequency selection 15 table 23.buzzer control register - beep 15 table 24.timer clock selection 17 table 25.timer control register - timctr 17 table 26.low timer load/status register -ltimls (4 low bits) 17 table 27.high timer load/status register-htimls (4 high bits) 17 table 28.pa3 counter input selection register - pa3cnt 17 table 29.pa3 counter input selection 17 table 30.main interrupt request register - intrq (read only)* 18 table 31.register - cirqd 19 table 32. svld level selection 20 table 33.svld control register - svld 20 table 34.swb clock selection 21 table 35.swb clock selection register - clkswb 21 table 36.portd status 21 table 37.swb buffer register - swbuff 22 table 38.swb low size register - lowswb 22 table 39.swb high size register - highswb 22 table 40 input/output ports 27 table 41 porta reset option 27 table 42 svld levels 27 em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 4 www.emmicroelectronic.com table 1. pin description pin number pin name function remarks 1 port a, 0 input 0 port a interrupt request; tvar 1 2 port a, 1 input 1 port a interrupt request; tvar 2 3 port a, 2 input 2 port a interrupt request; tvar 3 4 port a, 3 input 3 port a interrupt request; event counter input 5 port b, 0 input / output 0 port b buzzer output 6 port b, 1 input / output 1 port b 7 port b, 2 input / output 2 port b 8 port b, 3 input / output 3 port b 9 test test input terminal for em test purpose only (internal pull-down) 10 qout/osc 1 crystal terminal 1 11 qin/osc 2 crystal terminal 2 (input) can accept trimming capacitor tw. vss 12 vss negative power supply terminal 13 stb/rst strobe / reset status c reset state + port b, c, d write 14 port c, 0 input / output 0 port c interrupt request 15 port c, 1 input / output 1 port c interrupt request 16 port c, 2 input / output 2 port c interrupt request 17 port c, 3 input / output 3 port c interrupt request 18 port d, 0 input / output 0 port d swb serial clock output 19 port d, 1 input / output 1 port d swb serial data output 20 port d, 2 input / output 2 port d 21 port d, 3 input / output 3 port d 22 reset reset terminal active high (internal pull-down) 23 vreg internal voltage regulator needs typ. 100nf capacitor tw. vss 24 vdd positive power supply terminal figure 3.typical configuration for vdd less then 1.4v it is recommended that vdd is connected directly to vreg for vdd>1.8v then the configuration shown in fig.3 should be used. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 5 www.emmicroelectronic.com 1 operating modes the em6603 has two low power dissipation modes: standby and sleep. figure 4 is a transition diagram for these modes. 1.1 standby mode executing a halt instruction puts the em6603 into standby mode. the voltage regulator, oscillator, watchdog timer, interrupts and timer/event counter are operating. however, the cpu stops since the clock related to instruction execution stops. registers, ram, and i/o pins retain their states prior to standby mode. standby is cancelled by a reset or an interrupt request if enabled. 1.2 sleep mode writing to the sleep* bit in the intrq* register puts the em6603 in sleep mode. the oscillator stops and most functions of the em6603 are inactive. to be able to write the sleep bit, the slmask bit must first be set to 1. in sleep mode only the voltage regulator and reset input are active. the ram data integrity is maintained. sleep mode may be cancelled only by a reset at the terminal pin of the em6603. the reset must be high for at least 2sec. figure 4.mode transition diagram table 2 : shows the state of the em6603 functions in standby and sleep modes. table 2.standby and sleep activities function standby sleep oscillator active stopped instruction execution stopped stopped registers and flags retained reset interrupt functions active stopped ram retained retained timer/counter active stopped watchdog active stopped i/o pins active high-z or retained supply vld stopped stopped reset pin active active due to the cold start characteristics of the oscillator, waking up from sleep mode may take some time to guarantee that the oscillator has started correctly. during this time the circuit is in reset and the strobe output stb/rst is high. waking up from sleep mode clears the sleep flag but not the slmask bit. by reading slmask one can therefore determine if the em6603 was powered up ( slmask = 0), or woken from sleep mode ( slmask = 1). 2 power supply the em6603 is supplied by a single external power supply between vdd and vss, the circuit reference being at vss (ground). a built-in voltage regulator generates vreg providing regulated voltage for the oscillator and internal logic. output drivers are supplied directly from the external supply vdd. a typical connection configuration is shown in figure 3. for vdd less then 1.4v it is recommended that vdd is connected directly to vreg for vdd>1.8v then the configuration shown in fig.3 should be used. *registers are marked in bold and underlined like intrq * bits/flags in registers are marked in bold only like sleep em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 6 www.emmicroelectronic.com 3 reset to initialize the em6603, a system reset must be executed. there are four methods of doing this: (1) initial reset from the oscillation detection circuit. (2) external reset from the reset pin. (3) external reset by simultaneous high input to terminals pa0..pa3. (combinations defined by metal option) (4) watchdog reset (software option). during any of these reset?s the stb/rst output pin is high. figure 5.system reset generation 3.1 oscillation detection circuit at power on, the built-in voltage regulator starts to follow the supply voltage until vdd becomes higher than vreg. since it is vreg which supplies the oscillator and this needs time to stabilise, power-on-reset with the oscillation detection circuit therefore counts the first 32768 oscillator clocks after power-on and holds the system in reset. the system will consequently remain in reset for at least one second after power up. after power up the analogue watchdog circuit monitors the oscillator. if it stops for any reason other then sleep mode, then a reset is generated and the stb/rst pin is driven high. 3.2 reset pin during active or standby mode the reset terminal has a debouncer to reject noise and therefore must be active high for at least 2ms or 16ms (clk = 32khz) - software selectable by debck in cirqd register. (see table 31) at power on, or when cancelling sleep mode, the debouncer is not active and so reset must satisfy the filter time constant (typ. 1sec) such that the reset must be active high for at least 2sec. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 7 www.emmicroelectronic.com 3.3 input port (pa0..pa3) reset with a mask option it is possible to choose from four porta reset combinations. the selected ports must be simultaneously high for at least 2ms/16ms (clk = 32khz) due to the presence of debouncers. note also, that reset with port a is not possible during sleep mode. below are the combinations of port a (pa0..pa3) inputs, which can be used to generate a reset. they can be selected by metal ? porta reset ? mask option, described in chapter 14. table 3. porta inputs reset options (metal hardware option) function opt. code option a no inputs reset ra0 option b reset = pa0 * pa1 ra1 option c reset = pa0 * pa1 * pa2 ra2 option d reset = pa0 * pa1 * pa2 * pa3 ra3 3.4 watchdog timer reset the watchdog timer reset is a software option and if used it will generate a reset if it is not cleared. see section 5. watchdog timer for details. table 4. watchdog-timer option (software option) watchdog function nowd bit in option register without watchdog time-out reset 1 with watchdog time-out reset 0 3.5 cpu state after reset reset initialises the cpu as shown in the table 5 below. table 5. initial value after reset name bits symbol initial value program counter 0 12 pc0 $000 (as a result of jump 0) program counter 1 12 pc1 undefined program counter 2 12 pc2 undefined stack pointer 2 sp sp(0) selected index register 7 ix undefined carry flag 1 cy undefined zero flag 1 z undefined halt 1 halt 0 instruction register 16 ir jump 0 periphery registers 4 see peripheral memory map em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 8 www.emmicroelectronic.com 4 oscillator a built-in crystal oscillator circuit generates the system operating clock for the cpu and peripheral circuits from an externally connected crystal (typ. 32.768khz) and trimmer capacitor (from qin tw. vss). the oscillator circuit is supplied by the regulated voltage, vreg. in sleep mode the oscillator is stopped. with fout bit in pa3cnt register we can put the system 32.768 hz frequency on stb/rst pin as output. 4.1 prescaler the input to the prescaler is the system clock signal. the prescaler consists of a fifteen (15) element divider chain which delivers clock signals for the peripheral circuits such as the timer/counter, buzzer, i/o debouncers and edge detectors, as well as generating prescaler interrupts. table 6.prescaler interrupt source interrupt frequency psf1 psf0 mask(no interrupt) 0 0 1 hz 0 1 8 hz 1 0 32 hz 1 1 the frequency of prescaler interrupts is software selectable, as shown in table 6. table 7. prescaler control register - presc bit name reset r/w description 3 mtim 0 r/w timer/counter interrupt mask 2 prst - r/w prescaler reset 1 psf1 0 r/w prescaler interrupt select 1 0 psf0 0 r/w prescaler interrupt select 0 5 watchdog timer if for any reason the cpu crashes, then the watchdog timer can detect this situation and output a system reset signal. this function can be used to detect program overrun. for normal operation the watchdog timer must be reset periodically by software at least once every three seconds (clk = 32khz) or a system reset signal is generated to cpu and periphery. the watchdog is active during standby. the watchdog reset function can be deactivated by setting the nowd bit to 1 in the option register. in worst case because of prescaler reset function wd time-out can come down to 2 seconds. the watchdog timer is reset by writing 1 to the wdrst bit. writing 0 to wdrst has no effect. the watchdog timer also operates in standby mode. it is therefore necessary to reset it if this mode continues for more than three seconds. one method of doing this is to use the prescaler 1hz interrupt such, that the watchdog is reset every second. table 8.watchdog register - wd bit name reset r/w description 3 wdrst - r/w watchdog timer reset 2 slmask - r/w sleep mask bit 1 wd1 0 r wd timer data 1/4 hz 0 wd0 0 r wd timer data 1/2 hz em6603 03/02 rev. g/439 copyright ? 2001, em microelectronic-marin sa 9 www.emmicroelectronic.com 6 input and output ports the em6603 has four independent 4-bit ports, as shown in table 9 table 9.input / output ports overview port mode mask options function(s) pa(0:3) input pull-up/down ( * )debouncer ( * ) + or ? irq edge reset combination input interrupt software test variable pa3 input for event counter reset input(s) pb(0:3) individual input or output nch open drain output pull-up/down on input input or output pb0 for buzzer output pc(0:3) port input or output pull-up/down ( * )+ or ? irq edge ( * )debouncer nch open drain output input or output port interrupt pd(0:3) port input or output pull-up/down on input nch open drain output input or output port pd0 -swb serial clock output pd1 -swb serial data output ( * ) some options can be set also by option register . table 10.option register - option bit name reset r/w description 3 irqedger 0 r/w rising edge interrupt for porta&c 2 debpcn 0 r/w portc without/with debouncer 1 debpan 0 r/w porta without/with debouncer 0 nowd 0 r/w watchdog timer off irqedger - valid for both porta and portc input interrupt edge. at reset it is cleared to 0 selecting the falling edge at the input as the interrupt source. when set to 1 the rising edge is active. (option 3 on fig 6 and fig 8) debpan - by default after reset it is 0 enabling the debouncers on whole porta. writing it to 1 removes the debouncers from the porta. (option 2 on figure 6) debpcn - by default after reset it is 0 enabling the debouncers on whole portc. writing it to 1 removes the debouncers from the portc. (option 2 on figure 8) nowd - by default after reset it is 0 = watchdog timer is on. writing it to 1 removes the watchdog timer. 6.1 porta the em6603 has one four bit general purpose input port. each of the input port terminals pa3..pa0 has an internal pull-up/down resistor which can be selected with mask options. port information is read directly from the pin into a register. on inputs pa0, pa1, pa2 and pa3 debouncers for noise rejection are added by default. for interrupt generation, one can choose between either direct input or debounced input. with the debpan bit at 0 in the option register all the porta inputs are debounced and with the debpan bit at 1 none of the porta inputs are debounced. with the debouncer selected the input must be stable for two rising edges of 1024hz or 128hz clocks (at 32khz). this corresponds to a worst case of 1.95ms or 15.62msec. porta terminals pa0, pa1 and pa2 are also used as input conditions for conditional software branches as shown on the next page: em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 10 www.emmicroelectronic.com debounced pa0 is connected to cpu testvar1 debounced pa1 is connected to cpu testvar2 debounced pa2 is connected to cpu testvar3 figure 6.port a additionally, pa3 can also be used as the input terminal for the event counter (see section 8). the input port pa(0:3) also has individually selectable interrupts. each port has its own interrupt mask bit in the mporta register. when an interrupt occurs inspection of the irqpa and the intrq registers allows the source of the interrupt to be identified. the irqpa register is automatically cleared by a reset, by reading the register. reading irqpa register also clears the intpa flag in intrq register. at initial reset the mporta is set to 0, thus disabling any input interrupts. see also section 9 for further details about the interrupt controller. 6.2 porta registers table 11.porta input status register - porta bit name reset r/w description 3 pa3 - r pa3 input status 2 pa2 - r pa2 input status 1 pa1 - r pa1 input status 0 pa0 - r pa0 input status table 12.porta interrupt request register - irqpa bit name reset r/w description 3 irqpa3 0 r input pa3 interrupt request flag 2 irqpa2 0 r input pa2 interrupt request flag 1 irqpa1 0 r input pa1 interrupt request flag 0 irqpa0 0 r input pa0 interrupt request flag table 13.porta interrupt mask register - mporta bit name reset r/w description 3 mpa3 0 r/w interrupt mask for input pa3 2 mpa2 0 r/w interrupt mask for input pa2 1 mpa1 0 r/w interrupt mask for input pa1 0 mpa0 0 r/w interrupt mask for input pa0 em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 11 www.emmicroelectronic.com 6.3 portb the em6603 has one four bit general purpose i/o port. each bit pb(0:3) can be separately configured by software to be either input or output by writing to the corresponding bit of the cioportb control register. the portb register is used to read data when in input mode and to write data when in output mode. on each terminal pull-up/down resistor can be selected by metal option which are active only when selected as input. input mode is set by writing 0 to the corresponding bit in the cioportb register. this results in a high impedance state with the status of the pin being read from register portb. output mode is set by writing 1 to the corresponding bit in the cioportb register. consequently the output terminal follows the status of the bits in the portb register. at initial reset the cioportb register is set to 0, thus setting the port to an input. additionally, pb0 can also be used as a three tone buzzer output. for details see section 7. 6.4 portb registers table 14.portb input status register - portb bit name reset r/w description 3 pb3 - r/w pb3 i/o data 2 pb2 - r /w pb2 i/o data 1 pb1 - r/w pb1 i/o data 0 pb0 - r /w pb0 i/o data table 15.portb input/output control register - cioportb bit name reset r/w description 3 ciopb3 0 r/w pb3 input/output select 2 ciopb2 0 r/w pb2 input/output select 1 ciopb1 0 r/w pb1 input/output select 0 ciopb0 0 r/w pb0 input/output select figure 7.port b if metal mask option 5y (input blocked when output) is used and the port is declared as the output ( cioportb = 1111b) the real port information cannot be read directly. in this case no direct logic operations (like and portb ) on output ports are possible. this logic operation can be made with an image of the port saved in the ram which we store after on the output port. this is valid for portb, portc and portd when declared as output and the metal option 5y is used. in the case of metal option 5n selected direct logic operations on output ports are possible. if metal mask option 6y (output hi-z in sleep mode) the active output will go tristate when the circuit goes into sleep mode. in the case of 6n output stay active also in the sleep mode. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 12 www.emmicroelectronic.com 6.5 portc this port can be configured as either input or output (not bitwise selectable). when in input mode it implements the identical interrupt functions as porta. the portc register is used to read data when input mode and to write data when in output mode. input mode is set by writing 0 to the i/o control bit ciopc in register cpiob and the input becomes high impedance. on each terminal pull-up/down resistor can be selected by metal option which are active only when selected as input. the output mode is selected by writing 1 to ciopc bit, and the terminal follows the bits in the portc register. when portc is used as an input, interrupt functions as described for porta can be enabled. input to the interrupt logic can be direct or via a debounced input. with the debpcn bit at 0 in the option register all the portc inputs are debounced and with the debpcn bit at 1 none of the portc inputs are debounced. mportc is the interrupt mask register for this port and irqpc is the portc interrupt request register. see also section 9. by writing the pa&c bit in the cpiob data register it is possible to combine porta and portc interrupt requests (logic and) as shown in table 16. at initial reset, the cpioc control register is set to 0, and the port is in input mode. the mportc register is also set to 0, therefore disabling interrupts. table 16.ports a&c interrupt request irqpa irqpc pa&c request to cpu 00xno 010yes 100yes 110yes 011no 101no 111yes 6.6 portc registers table 17.portc input/output register - portc bit name reset r/w description 3 pc3 - r/w pc3 i/o data 2 pc2 - r /w pc2 i/o data 1 pc1 - r/w pc1 i/o data 0 pc0 - r /w pc0 i/o data table 18.portc interrupt request register - irqpc bit name reset r/w description 3 irqpc3 0 r input pc3 interrupt request flag 2 irqpc2 0 r input pc2 interrupt request flag 1 irqpc1 0 r input pc1 interrupt request flag 0 irqpc0 0 r input pc0 interrupt request flag table 19.portc interrupt mask register - mportc bit name reset r/w description 3 mpc3 0 r/w interrupt mask for input pc3 2 mpc2 0 r/w interrupt mask for input pc2 1 mpc1 0 r/w interrupt mask for input pc1 0 mpc0 0 r/w interrupt mask for input pc0 em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 13 www.emmicroelectronic.com figure 8.port c for portc and portd metal options 5y/n and 6y/n are port-wise (for the whole port). for portb these options are bit-wise (every terminal can have individual mask set-up for the options 5y/n and 6y/n ). em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 14 www.emmicroelectronic.com 6.7 portd the em6603 has one all purpose i/o port similar to portc but without interrupt capability. the portd register is used to read input data when an input and to write output data for output. the input line can be pulled up/down (metal option) when the port is used as input. input mode is set by writing 0 to the i/o control bit ciopd in register cpiob , and the terminal becomes high impedance. on each terminal pull-up/down resistor can be selected by metal option which are active only when selected as input. output mode is set by writing 1 to the control bit ciopd. consequently, the terminal follows the status of the bits in the portd register. if serial write buffer function is enabled pd0 and pd1 terminals of portd output serial clock and serial data respectively. for details see 11.0 serial write buffer . 6.8 portd registers table 20.portd input/output register - portd bit name reset r/w description 3 pd3 0 r/w pd3 i/o data 2 pd2 0 r/w pd2 i/o data 1 pd1 0 r/w pd1 i/o data 0 pd0 0 r/w pd0 i/o data table 21.ports control register - cpiob bit name reset r/w description 3 - - r/w not used 2 ciopd 0 r/w i/o portd select 1 ciopc 0 r/w i/o portc select 0 pa&c 0 r/w logical and of irq?s from porta & portc figure 9.port d em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 15 www.emmicroelectronic.com 7 buzzer the em6603 has one 50% duty cycle output with three different frequencies which can be used to drive a buzzer. i/o terminal pb0 is used for this function when the buzzer is enabled by setting the buen bit to 1 . table 22 below shows how to select the frequency by writing to the bcf1 and bcf0 control flags in the beep register. after writing to the buzzer control register beep, the chosen frequency (or silence) is selected immediately. with the buen bit set to 1, the selected frequency is output at pb0. when the buen is set to 0 pb0 is used as a normal i/o terminal of portb. the buen bit has a higher priority over the i/o control bit ciopb0 in the cioportb register. table 22.buzzer frequency selection tone frequency bcf1 bcf0 silence 0 0 1024 hz 0 1 2048 hz 1 0 2667 hz 1 1 7.1 buzzer register table 23.buzzer control register - beep bit name reset r/w description 3 timen 0 r/w timer/counter enable 2 buen 0 r/w buzzer enable 1 bcf1 0 r/w buzzer frequency control 0 bcf0 0 r/w buzzer frequency control em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 16 www.emmicroelectronic.com 8 timer/event counter the em6603 has a built-in 8 bit countdown auto-reload timer/event counter that takes an input from either the prescaler or port pa3. if the timer/event counter counts down to $00 the interrupt request flag inttim is set to 1. if the timer/event counter interrupt is enabled by setting the mask flag mtimc set to 1, then an interrupt request is generated to the cpu. see also section 9. if used as an event counter, pulses from the pa3 terminal are input to the event counter. see figure 10 and tables 28 and 29 on the next page for pa3 source selection (debounced or not, rising/falling edge). by default rising and debounced pa3 input is selected. the timer control register timctr selects the auto-reload function and input clock source. at initial reset this bit is cleared to 0 selecting no auto-reload. to enable auto-reload timauto must be set to 1. the timer/event counter can be enabled or disabled by writing to the timen control bit in the beep register. at initial reset it is cleared to 0. when used as timer, it is initialised according to the data written into the timer load/status registers ltimls (low 4 bits) and htimls (high four bits). the timer starts to count down as soon as the ltimls value is written. when loading the timer/event counter registers the correct order must be respected: first, write either the control register timctr or the high data nibble htimls . the last register written should be the low data nibble ltimls . during count down, the timer can always be reloaded with a new value, but the high four bits will only be accepted during the write of the low four bits. in the case of the auto-reload function, the timer is initialised with the value of the load registers ltimls and htimls . counting with the auto-reload function is only enabled during the write to the low four bits, (writing timauto to 1 does not start the timer counting down with the last value in the timer load registers but it waits until a new ltimls load). the timer counting to $00 generates a timer interrupt event and reloads the registers before starting to count down again. to stop the timer at any time, a write of $00 can be made to the timer load registers, this sets the timauto flag to 0. if the timer is stopped by writing the timen bit to 0, the timer status can be read. the current timer status can be always obtained by reading the timer registers ltimls and htimls . for proper operation read ordering should be respected such that the first read should be of the ltimls register followed by the htimls register. example: to have continuos 1sec timer irq with 128hz one has to write 128dec (80hex) in timer registers with auto-reload. using the timer/event counter as the event counter allows several possibilities: 1.) firstly, load the number of pa3 input edges expected into the load registers and then generate an interrupt request when counter reaches $00. 2.) the second is to write timer/counter to $ff, then select the event counter mode, and lastly enable the event counter by setting the timen bit to 1, which starts the count. because the counter counts down, a binary complement has to be done in order to get the number of events at the pa3 input. 3) another option is to use the timer/event counter in conjunction with the prescaler interrupt, such that it is possible to count the number of the events during two consecutive 32hz, 8hz or 1hz prescaler interrupts. figure 10.timer / event counter em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 17 www.emmicroelectronic.com table 24 shows the selection of inputs to the timer/event counter. table 24.timer clock selection tec2 tec1 tec0 timer/counter clock source 0 0 0 not active 0 0 1 2048 hz from prescaler 0 1 0 512 hz from prescaler 0 1 1 128 hz from prescaler 1 0 0 32 hz from prescaler 1 0 1 8 hz from prescaler 1 1 0 1 hz from prescaler 1 1 1 pa3 input terminal (see tables 28 and 29) 8.1 timer/counter registers table 25.timer control register - timctr bit name reset r/w description 3 timauto 0 r/w timer/counter auto reload 2 tec2 0 r/w timer/counter mode 2 1 tec1 0 r/w timer/counter mode 1 0 tec0 0 r/w timer/counter mode 0 table 26.low timer load/status register - ltimls (4 low bits) bit name reset r/w description 3 tl3/ts3 0 r/w timer load/status bit 3 2 tl2/ts2 0 r/w timer load/status bit 2 1 tl1/ts1 0 r/w timer load/status bit 1 0 tl0/ts0 0 r/w timer load/status bit 0 table 27.high timer load/status register - htimls (4 high bits) bit name reset r/w description 3 tl7/ts7 0 r/w timer load/status bit 7 2 tl6/ts6 0 r/w timer load/status bit 6 1 tl5/ts5 0 r/w timer load/status bit 5 0 tl4/ts4 0 r/w timer load/status bit 4 table 28.pa3 counter input selection register - pa3cnt bit name reset r/w description 3 - - - empty 2 - - - empty 1 fout 0 r/w system freq. output on stb/rst pad 0 pa3cntin 0 r/w pa3 input status table 29.pa3 counter input selection pa3cntin debpan irqedger counter source 0 x x pa3 debounced rising edge 1 0 0 pa3 debounced falling edge 1 0 1 pa3 debounced rising edge 1 1 0 pa3 not debounced falling edge 1 1 1 pa3 not debounced rising edge x ( don?t care) em6603 03/02 rev. g/439 copyright ? 2001, em microelectronic-marin sa 18 www.emmicroelectronic.com 9 interrupt controller the em6603 has six different interrupt sources, each of which is maskable. these are: external (3) - porta pa3..pa0 inputs - portc pc3..pc0 inputs - combined and of porta * portc internal (3) - prescaler (32hz / 8hz / 1hz) - timer/event counter - swb in interactive mode for an interrupt to the cpu to be generated, the interrupt request flag must be set ( intxx ), and the corresponding mask register bit must be set to 1 ( mxx ), the general interrupt enable flag ( inten ) must also be set to 1. the interrupt request can be masked by the corresponding interrupt mask registers mport x for each input interrupt and by psf0 , psf1 and mtim for internal interrupts. at initial reset the interrupt mask bits are set to 0. inten bit is set automatically to 1 by halt instruction except when starting the automatic swb transfer (see serial write buffer (swb) chapter 11) the cpu is interrupted when one of the interrupt request flags is set to 1 in register intrq and the inten bit is enabled in the control register cirqd . intte and intpr flags are cleared automatically after a read of the intrq register. the other two interrupt flags intpa (irq from porta) and intpc (irq from portc) in the intrq register are cleared only after reading the corresponding port interrupt request registers irqpa and irqpc . at the power on reset and in sleep mode the inten bit is also set to 0 therefore not allowing any interrupt requests to the cpu until it is set to 1 by software. since the cpu has only one interrupt subroutine and because the intrq register is cleared after reading, the cpu does not miss any of the interrupt requests which come during the interrupt service routine. if any occur during this time a new interrupt will be generated as soon as the cpu comes out of the current interrupt subroutine. interrupt priority can be controlled through software by deciding which flag in the intrq register should be serviced first. for swb interactive mode interrupt see section 11.0 serial write buffer. 9.1 interrupt control registers table 30.main interrupt request register - intrq (read only)* bit name reset r/w description 3 intpr 0 r prescaler interrupt request 2 intte 0 r timer/counter interrupt request 1 intpc 0 r portc interrupt request 0 intpa 0 r porta interrupt request 2 sleep 0 w* sleep mode flag * write bit 2 only if slmask =1 if the sleep flag is written with 1 then the em6603 goes immediately into sleep mode ( slmask was at 1). em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 19 www.emmicroelectronic.com table 31.register - cirqd bit name reset r/w description 3 reserved - - - 2 reserved - - - 1 debck 0 r/w debouncer clock select (0=2ms : 1=16ms) 0 inten 0 r/w enable interrupt to cpu (1=enabled) figure 11.interrupt request generation irq mask bit which can be written to 0 or 1 (1 to enable an interrupt) interrupt request flag which is set on the input rising edge. timer irq flag intte and prescaler irq flag intpr arrive independent of their mask bits not to loose any timing information. but the processor will be interrupted only with mask set to 1. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 20 www.emmicroelectronic.com 10 supply voltage level detector (svld) the em6603 has a software configurable built-in supply voltage level detector. three levels can be defined between vddmin + 100mv and vddmax - 600mv in steps of 100mv. during sleep mode this function is disabled. the required voltage compare level is selected by writing the bits vlc1 and vlc2 in the svld control register which also activates the compare measurement. since the measurement is not immediate the busy flag remains high during the measurement and is automatically cleared low when the measurement is finished. the result is indicated by inspection of the vldr flag. if the result is 0 then the voltage level is higher than the selected compare level. and if 1 is lower than the compare level. the result vldr of the last measurement remains until the new one is finished. the new result overwrites the previous one. table 32. svld level selection during the svld operation power consumption increases by approximately 3 a for 3.9msec. the measurement internally starts with the rising 256hz edge following the svld test command. the additional svld consumption stops after the falling edge of the 256hz internal clock. table 32 lists the possible voltage levels 10.1 svld register table 33.svld control register - svld bit name reset r/w description 3 vldr 0 r svld result (0=higher 1=lower) 2 busy 0 r measurement in progress 1 vlc1 0 r/w svld level control 1 0 vlc0 0 r/w svld level control 0 evaluation voltage vlc1 vlc0 not active 0 0 vl1 (low level) 0 1 vl2 1 0 vl3 (high level) 1 1 em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 21 www.emmicroelectronic.com 11 serial (output) write buffer ? swb the em6603 has a simple serial write buffer (swb) which outputs serial data and serial clock. the swb is enabled by setting the bit v03 in the clkswb register as well as setting port d to output mode. the combination of the possible portd mode is shown in table 34. in swb mode the serial clock is output on port d0 and the serial data is output on port d1. the signal testvar[3], which is used by the processor to make conditional jumps, indicates "transmission finished" in automatic send mode or "swbbuffer empty" in interactive send mode. in interactive mode, testvar[3] is equivalent to the interrupt request flags stored in intrq register : it permits to recognize the interrupt source. (see also the interrupt handling section 9.interrupt controller for further information). to serve the "swbbuffer empty " interrupt request, one only has to make a conditional jump on testvar[3]. table 34.swb clock selection the serial write buffer output clock frequency is selected by bits clkswb0 and clkswb1 in the clkswb register. the possible values are 1khz (default), 2khz, 8khz or 16khz and are shown in table 34. table 35.swb clock selection register - clkswb bit name reset r/w description 3 v03 0 r/w serial write buffer selection 2 - 0 r reserved - read 0 1 ckswb1 0 r/w swb clock selector 1 0 ckswb0 0 r/w swb clock selector 0 table 36.portd status portd status ciopd v03 pd0 pd1 pd2 pd3 ? normal ? 0 0 input input input input ? normal ? 0 1 input input input input ? normal ? 1 0 output pd0 output pd1 output pd2 output pd3 ? swb ? 1 1 serial clock out swb serial data output pd2 output pd3 when the swb is enabled by setting the bit v03 testvar[3], which is used to make conditional jumps, is reassigned to the swb and indicates either "swbbuffer empty " interrupt or "transmission finished" . after power-on-reset v03 is cleared at "0" and testvar[3] is consequently assigned to pa2 input terminal. the swb data is output on the rising edge of the clock. consequently, on the receiver side the serial data can be evaluated on falling edge of the serial clock edge. swb clock output ckswb1 ckswb0 1024 hz 0 0 2048 hz 0 1 8192 hz 1 0 16384 hz 1 1 em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 22 www.emmicroelectronic.com figure 12.serial write buffer table 37.swb buffer register - swbuff bit name reset r/w description 3 buff3 1 r/w swb buffer d3 2 buff2 1 r/w swb buffer d2 1 buff1 1 r/w swb buffer d1 0 buff0 1 r/w swb buffer d0 table 38.swb low size register - lowswb bit name reset r/w description 3 size[3] 0 r/w auto mode buffer size bit3 2 size[2] 0 r/w auto mode buffer size bit2 1 size[1] 0 r/w auto mode buffer size bit1 0 size[0] 0 r/w auto mode buffer size bit0 table 39.swb high size register - highswb bit name reset r/w description 3 autoswb 0 r/w swb automatic mode select 2 stswb 0 r/w swb start interactive mode 1 size[5] 0 r/w auto mode buffer size bit5 0 size[4] 0 r/w auto mode buffer size bit4 the swb has two operational modes, automatic mode and interactive mode. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 23 www.emmicroelectronic.com 11.1 swb automatic send mode automatic mode enables a buffer on a predefined length to be sent at high transmission speeds ( up to 16khz). in this mode user prepares all the data to be sent (minimum 8 bits, maximum 256 bits) in ram. the user then selects the clock speed, sets the number of data nibbles to be sent, selects automatic transmission mode ( autoswb bit set to 1) and enters standby mode by executing a halt instruction. once the halt instruction is activated the swb peripheral module sends the data in register swbuff followed by the data in the ram starting at address 00 up to the address specified by the bits size[5:0 ] located in the lowswb, highswb registers. during automatic transmission the general inten bit is disabled automatically to prevent other interrupts to reset the standby mode. at the end of automatic transmission em6603 leaves standby mode and sets testvar[3] high. testvar[3] = 1 is signaling swb transmission is terminated. once the transmission is finished, do not forget to enable the general inten bit if necessary. the data to be sent must be prepared in the following order: first nibble to be sent must be written in the swbuff register . the other nibbles must be loaded in the ram from address 0 (second nibble at adr.0, third at adr.1,...) up to the address with last nibble of data to be send = "size" address. max. address space for swb is 3e ("size" 3e hex) what gives with swbuff up to 64 nibbles (256 bits) of possible data to be sent. the minimum possible data length we can send in automatic swb mode is 8 bits when the last ram address to be sent is 00 ("size" = 00) once data are ready in the ram and in the swbuff , user has to load the "size" (adr. of the last nibble to be send - bits size[5:0] ) into the lowswb and highswb register together with autoswb bit = 1. now everything is ready for serial transmission. to start the transmission one has to put the em6603 in standby mode with the halt instruction. with this serial transmission starts. when transmission is finished the testvar[3] (can be used for conditional jumps) becomes active high, the autoswb bit is cleared, the processor is leaving the standby mode and inten is switched on. figure 13.automatic serial write buffer transmission em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 24 www.emmicroelectronic.com the processor now starts to execute the first instruction placed after the halt instruction (for instance write of swbuff register to clear testvar[3]), except if there was a irq during the serial transmission. in this case the cpu will go directly in the interrupt routine to serve other interrupt sources. testvar[3] stays high until swbuff is rewritten. before starting a second swb action this bit must be cleared by performing a dummy write on swbuff address. because the data in the ram are still present one can start transmitting the same data once again only by recharging the swbuff , lowswb and highswb register together with autoswb bit and putting the em6603 in halt mode will start new transmission. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 25 www.emmicroelectronic.com 11.2 swb interactive send mode in interactive swb mode the reloading of the data transmission register swbbuff is performed by the application program. this means that it is possible to have an unlimited length transmission data stream. however, since the application program is responsible for reloading the data a continuous data stream can only be achieved at 1khz or 2khz transmission speeds. for the higher transmission speeds a series of writes must be programmed and the serial output clock will not be continuous. serial transmission using the interactive mode is detailed in figure 14. programming of the swb in interactive is achieved in the following manner: select the transmission clock speed using the bits clksw0 and clksw1 in the clkswb register. load the first nibble of data into the swb data register swbbuff start serial transmission by selecting the bit stswb in the register highswb register. once the data has been transferred into the serial transmission register a non maskable interrupt (swbempty) is generated and testvar[3] goes high. the cpu goes in the interrupt routine, with the jpv3 as first instruction in the routine one can immediately jump to the swb update routine to load the next nibble to be transmitted into the swbuff register. if this reload is performed before all the serial data is shifted out then the next nibble is automatically transmitted. this is only possible at the transmission speeds of 1khz or 2khz due to the number of instructions required to reload the register. at the higher transmission speeds of 8khz and 16khz the application must restart the serial transmission by writing the stswb in the high swbhigh register after writing the next nibble to the swbbuff register. each time the swbuff register is written the "swbbuffer empty interrupt" and testvar[3] are cleared to "0". for proper operation the swbuff register must be written before the serial clock drops to low during sending the last bit (msb) of the previous data. figure 14.interactive serial write buffer transmission after loading the last nibble in the swbbuff register a new interrupt is generated when this data is transferred to an intermediate shift register. precaution must be made in this case because the swb will give repetitive interrupts until the last data is sent out completely and the stswb bit goes low automatically. one possibility to overcome this is to check in the interrupt subroutine that the stswb bit went low before exiting interrupt. be careful because if stswb bit is cleared by software transmission is stopped immediately. at the end of transmission a dummy write of swbuff must be done to clear testvar[3] and "swbbuffer empty interrupt" or the next transmission will not work. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 26 www.emmicroelectronic.com 12 strobe / reset output the stb/rst output pin is used to indicate the em6603 reset condition as well as write operations to ports b, c and d. for a portb, portc and portd write operation the strobe signal goes high for half of the system clock period. write is effected on falling edge of the strobe signal and it can this be used to indicate when data changes at the output port pins. in addition, any em6603 internal reset condition is indicated by a continuous high level on stb/rst for the period of the reset. 13 test at em - active supply current test for this purpose, five instructions at the end of the rom will be added. testloop: sti 00h, 0ah ldr 1bh nxorx jpz testloop jmp 00h to stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop: 1bh: 0101b 32h: 1010b 6eh: 0010b 6fh: 0011b free space after last instruction: jmp 00h (0000) remark: empty space within the program are filled with nop (foff). em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 27 www.emmicroelectronic.com 14 metal mask options the following options can be selected at the time of programming the metal mask rom. table 40 input/output ports pull-up y es / n o pull-down y es / n o nch-open drain y es / n o input blocked when output y es / n o output hi-z in sleep mode y es / n o 0 1 4 5 * 1 6 * 2 a0 pa0 input a1 pa1 input a2 pa2 input a3 pa3 input b0 pb0 in/out b1 pb1 in/out b2 pb2 in/out b3 pb3 in/out c0 pc0 in/out c1 pc1 in/out c2 pc2 in/out c3 pc3 in/out d0 pd0 in/out d1 pd1 in/out d2 pd2 in/out d3 pd3 in/out put one letter (y, n, r, f)in each box from proposed for the column. *1 port wise for portc and portd (one possibility for the whole port); portb bit-wise *2 port-wise for portc and portd (one possibility for the whole port); portb bit-wise table 41 porta reset option - one option must be selected no porta reset combination pa0 & pa1 logic and input reset pa0 & pa1 & pa2 logic and input reset pa0 & pa1 & pa2 & pa3 logic and input reset 0 1 2 3 ra porta reset table 42 svld levels ? see 16.6 dc characteristics ?sv detector levels ? write typ. value of used levels typ. vl1 level [v] typ. vl2 level [v] typ. vl3 level [v] vl svld level in volts software name is : ______________ .bin, dated ______________ the customer should specify the required options at the time of ordering. a copy of this sheet, as well as the ? software rom characteristic file ? generated by the assembler (*.sta) should be attached to the order. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 28 www.emmicroelectronic.com 15 peripheral memory map the following table shows the peripheral memory map of the em6603. the address space is between $00 and $7f (hex). any addresses not shown can be considered to be reserved. register name add hex add dec power up value write_bits read_bits remarks b'3210 read/write_bits ram 00- 5f 0-95 xxxx 0: d0 1: d1 2: d2 3: d3 direct addressing ltimls 60 96 0000 0: tl0 1: tl1 2: tl2 3: tl3 0: ts0 1: ts1 2: ts2 3: ts3 low nibble of 8bit timer load and status register htimls 61 97 0000 0: tl4 1: tl5 2: tl6 3: tl7 0: ts4 1: ts5 2: ts6 3: ts7 high nibble of 8bit timer load and status register timctr 62 98 0000 0: tec0 1: tec1 2: tec2 3: timauto timer control register with frequency selector option 63 99 0000 0: nowd 1: debpan 2: debpcn 3:irqedger option register pa3cnt 65 101 xxx0 0: pa3cntin 1: fout 2: - 3: - pa3 counter input frequency output on strb clkswb 68 104 0000 0: ckswb0 1: ckswb1 2: - 3: v03 clock selector for swb swbuff 69 105 1111 0: buff0 1: buff1 2: buff2 3: buff3 swb intermediate buffer lowswb 6a 106 0000 0: size[0] 1: size[1] 2: size[2] 3: size[3] low nibble to define the size of data to be send in automatic mode highswb 6b 107 0000 0: size[4] 1: size[5] 2: stswb 3:autoswb the size of the data to be sent & swb control svld 6c 108 0000 0: vlc0 1: vlc1 2: - 3: - 0: vlc0 1: vlc1 2: busy 3: vldr voltage level detector control cirqd 6d 109 xx00 0: inten 1: debck 2: - 3: - global interrupt enable debouncer clock index low 6e 110 xxxx internally used for index register index high 6f 111 xxxx internally used for index register em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 29 www.emmicroelectronic.com register name add hex add dec power up value write_bits read_bits remarks b'3210 read/write_bits intrq 70 112 0000 0: - 1: - 2: sleep 3: - 0: intpa 1: intpc 2: intte 3: intpr interrupt requests sleep mode wd 71 113 0000 0: - 1: - 2: slmask 3: wdrst 0: wd0 1: wd1 2: slmask 3: 0 watchdog timer control and sleep mask porta 72 114 xxxx 0: pa0 1: pa1 2: pa2 3: pa3 port a status irqpa 73 115 0000 0: irqpa0 1: irqpa1 2: irqpa2 3: irqpa3 port a interrupt request mporta 74 116 0000 0: mpa0 1: mpa1 2: mpa2 3: mpa3 port a mask portb 75 117 xxxx 0: pb0 1: pb1 2: pb2 3: pb3 port b input/output cioportb 76 118 0000 0: ciopb0 1: ciopb1 2: ciopb2 3: ciopb3 port b input/output individual control portc 77 119 xxxx 0: pc0 1: pc1 2: pc2 3: pc3 port c input/output irqpc 78 120 0000 0: irqpc0 1: irqpc1 2: irqpc2 3: irqpc3 port c interrupt request mportc 79 121 0000 0: mpc0 1: mpc1 2: mpc2 3: mpc3 port c mask portd 7a 122 xxxx 0: pd0 1: pd1 2: pd2 3: pd3 port d input/output cpiob 7c 124 x000 0: pa&c 1: ciopc 2: ciopd 3: - portairq and portcirq portc in/out portd in/out presc 7d 125 0000 0: psf0 1: psf1 2: prst 3: mtim 0: psf0 1: psf1 2: 0 3: mtim prescaler control timer mask beep 7e 126 0000 0: bcf0 1: bcf1 2: buen 3: timen buzzer control timer enable regtestem 7f 127 ---- ---- ---- reserved em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 30 www.emmicroelectronic.com 16 electrical specifications 16.1 absolute maximum ratings min. max. unit supply voltage vdd-vss - 0.2 + 3.6 v input voltage vss - 0.2 vdd+0.2 v storage temperature - 40 + 125 c stresses above these listed maximum ratings may cause permanent damage to the device. exposure beyond specified electrical characteristics may affect device reliability or cause malfunction . 16.2 standard operating conditions parameter value description temperature -20c...+85c vdd_range1 +1.4 ...+3.6v with internal voltage regulator vdd_range2 (vreg = vdd) * +1.2 ...+1.8v without internal voltage regulator vss 0 v (reference) cvreg min. 100nf regulated voltage capacitor tow. vss fq 32768 hz nominal frequency rqs 35 kohm typical quartz serial resistor cl 8.2pf typical quartz load capacitance df/f +/- 30 ppm quartz frequency tolerance 16.3 handling procedures this device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other cmos component. unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 16.4 dc characteristics - power supply pins vdd=vreg=1.5v, t=25c (note4) (unless otherwise specified) parameter conditions symb. min. typ. (note1) max. unit active supply current +25c (note2) i vdda 1.8 3.0 a active supply current (in active mode) (note2) (note2) -20c...+85c i vdda 4.5 a standby supply current +25c i vddh 0.35 0.6 a standby supply current (in halt mode) (note3) -20c...+85c i vddh 1.8 a sleep supply current +25c i vdds 0.1 0.2 a sleep supply current (sleep =1) (note3) -20c...+85c i vdds 1.2 a por voltage v por 0.7 1.1 v ram data retention vrd 1.1 v regulated voltage vreg not at vdd vreg 1.1 1.5 v em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 31 www.emmicroelectronic.com vdd=3.0v, t=25c (note4) (unless otherwise specified), vreg not shorted to vdd parameter conditions symb. min. typ. (note1) max. unit active supply current +25c (note2) i vdda 1.8 3.0 a active supply current (in active mode) (note2) (note3) -20c...+85c i vdda 4.5 a standby supply current +25c i vddh 0.35 1.0 a standby supply current (in halt mode) (note3) -20c...+85c i vddh 1.8 a sleep supply current +25c i vdds 0.1 0.4 a sleep supply current (sleep =1) (note3) -20c...+85c i vdds 1.2 a regulated voltage -20c...+85c vreg 1.1 1.85 v * because of the voltage regulator drop at low voltages vreg = vdd when vdd<1.4v note1: for current measurement typical quartz described in operating conditions is used. all i/o pins without internal pull up/down are pulled to vdd externally. note2: test loop with successive writing and reading of two different addresses with an inverted values (five instructions should be reserved for this measurement), note3: not tested if delivered in chip form. note4: test conditions for active and standby supply current mode are: qin = external square wave, from rail to rail of vreg (regulated voltage) with 100nf capacitor on vreg. fqin = 33khz. 16.5 dc characteristics - input/output pins vdd=1.5v / 3.0v, -20c em6603 03/02 rev. g/439 copyright ? 2001, em microelectronic-marin sa 35 www.emmicroelectronic.com figure 17. dimensions of tssop24 package tssop24 (0.65mm pitch, 4.4mm body width) figure 18. dimensions of sop24 package soic (1.27mm pitch, 300mils body width) sop-24 em6603 03/02 rev. g/439 copyright ? 2001, em microelectronic-marin sa 36 www.emmicroelectronic.com 18.1 ordering information note 1: please contact em microelectronic-marin s.a. for availability of dip package. ordering part number (selected examples) part number package/die form delivery form/ thickness em6603%%%so24a 24 pin soic stick em6603%%%so24b 24 pin soic tape&reel em6603%%%tp24b 24 pin tssop tape&reel em6603%%%ws11 sawn wafer 11 mils em6603%%%wp11 die in waffle pack 11 mils please make sure to give the complete part number when ordering, including the 3-digit version. the version is made of 3 digits %%%: the first one is a letter and the last two are numbers, e.g. p01 , p12, etc. 18.2 package marking dip and soic marking: tssop marking: first line: em6603 0 %%y em66 0 3%% second line: ppppppppppp p p p p p p p p third line: ccccccccccc c c c c y p where: %% = last two-digits of the customer-specific number given by em (e.g. 05, 12, etc.) y = year of assembly pp?p = production identification (date & lot number) of em microelectronic cc?c = customer specific package marking on third line, selected by customer 18.3 customer marking there are 11 digits available for customer marking on pdip24 and so24 . there are 4 digits available for customer marking on tssop24 . please specify below the desired customer marking. packaged device: device in die form: customer version: customer version: customer-s p ecific numbe r customer-s p ecific numbe r given by em microelectronic given by em microelectronic packa g e: die form: so24 = 24 p in soic ww = wafe r tp24 = 24 p in tssop ws = sawn wafer/frame dl24 = 24 p in dip ( note 1 ) wp = waffle pack thickness: deliver y form: 11 = 11 mils ( 280um ) , b y default a = stick 27 = 27 mils ( 686um ) , not backla pp ed b = ta p e&reel ( for so24 and tp24 onl y) ( for other thickness, contact em ) em6603 %%% ws 11 so24 b %%% em6603 em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 37 www.emmicroelectronic.com specification change date version chapter (page) old text new text 9/11/99 ver.2.2 all new specifications (paper format only) 27/6/97 b/151 all version 2.2 b/151 new version in doc control 27/6/97 b/151 all new pagination & new table nb. 27/6/97 b/151 (1,2) 16.4(30,31) typical 2.7 a active mode typical 0.3 a standby mode typical 1.8 a active mode typical 0.35 a standby mode 27/6/97 b/151 (4) 2 (5) for vdd less then 1.4v it is recommended that vdd is connected directly to vreg for vdd>1.8v then the configuration shown in fig.3 should be used. 27/6/97 b/151 6 (9) table 10 option register ? option new table and text describing option register 27/6/97 b/151 6.4 (11) below figure 7. portb new explanation of mask options 27/6/97 b/151 6.6 (13) below figure 8. portc new explanation of mask options 27/6/97 b/151 8 (16) first paragraph changed due to new counter feature added ? pa3 clk source (debounced or not, rising/falling) 27/6/97 b/151 8 (16) pa3 input terminal pa3 input terminal (see tables 28 and 29) added in table 24. timer clock selection 27/6/97 b/151 8.1 (17) table 28 pa3 counter input selection ? pa3cnt table 29 pa3 counter input selection new tables describing pa3cnt register figure 10 timer/event counter adapted 27/6/97 b/151 9.1 (19) new description below figure 11 interrupt request generation 27/6/97 b/151 10 (20) new formulation and more precise explanation of svld (no functional change) 27/6/97 b/151 11 (22) figure 12. serail write buffer 1024 hz input added in mux 27/6/97 b/151 11.1 (23) new explanation of swb concerning length and irq 27/6/97 b/151 11.2 (25) new explanation of swb in interactive mode 27/6/97 b/151 14 (27) new explanation of metal mask options below table 40 input/output ports 27/6/97 b/151 14 (27) table 39 watchdog metal option removed (software controlled) 27/6/97 b/151 15 (28) new register pa3cnt at address 65 hex 27/6/97 b/151 16.2 (30) vdd vdd_range 1 / +1.4 ..+3.6v vdd_range 2 (vreg=vdd) / +1.2 ..+1.8v 27/6/97 b/151 16.2 (30) vdd vdd_range 1 / +1.4 ..+3.6v vdd_range 2 (vreg=vdd) / +1.2 ..+1.8v 27/6/97 b/151 16.5 (31) v ol = f(i ol ,vdd), v oh = f(i oh ,vdd), new way of specifying i ol = f(v ol ,vdd), i oh = f(v oh ,vdd), 27/6/97 b/151 16.5 (32) input pull-up/down resistor expressed by currents new way of specifying resistors [k ? ] instead with currents 27/6/97 b/151 16.6 (32) absolute svld levels 2.50v, 2.00v, 1.25v new relative way of specifying svld precision and range for 3 levels x% 27/6/97 b/151 16.7 (33) max c qin 8.5 pf max c qout 15.9 pf max c qin 10.0 pf max c qout 20.0 pf em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 38 www.emmicroelectronic.com date version chapter (page) old text new text 27/8/99 c/242 all b/151 c/242 new version in doc. control 27/8/99 c/242 (1) 2.0 to 5.5 v removed 2.0 to 5.5 v 27/8/99 c/242 (1) internal interrupt sources (timer, event counter, prescaler) internal interrupt sources (timer, event counter, prescaler, swb) 27/8/99 c/242 (2) 4 external interrupt sources from porta 8 external interrupt sources: 4 from porta and 4 from portc 27/8/99 c/242 (4) for em test purpose only for em test purpose only (internal pull- down) 27/8/99 c/242 (4) in table1 pin number 22 active high (internal pull-down) 27/8/99 c/242 (4) in table1 pin number 23 needs typ. 100nf capacitor tw. vss 27/8/99 c/242 2 (5) added at the bottom of the page *registers are marked in bold and underlined like intrq * bits/flags in registers are marked in bold only like sleep 27/8/99 c/242 all new register and bits/flags marking (see line above) 27/8/99 c/242 6 (9) pull-down pull-up/down 27/8/99 c/242 6 (9) (option 2 on fig 6 and fig 8 ) (option 3 on fig 6 and fig 8 ) 27/8/99 c/242 6.7 (14) the input line can be pulled down ( ... the input line can be pulled up/down ( ... 27/8/99 c/242 8.1 (17) fout / 0 / r/w / system freq. output on stb/rst pad added in table 28. pa3 counter input ? 27/8/99 c/242 9 (18) inttim and intpr flags are cleared .. intte and intpr flags are cleared ? 27/8/99 c/242 11. (23:25) new explanation of swb to be as close as possible to other em66xx (no functional change) 27/8/99 c/242 14 (27) column 2 & 3 in table 40 input/output ports removedcolumn 2 & 3 in table 40 input/output ports ? and notes *3,*4,*5 27/8/99 c/242 15 (28) fout / frequency selector on stb/rst added in register pa3cnt 27/8/99 c/242 16.1 (30) max. supply voltage +5.5v max. supply voltage +3.6v 27/8/99 c/242 16.7 (33) qin to qout impedance on pcb min 5 m ? , typ 10 m ? 27/8/99 c/242 17 (34) 17 package and ordering information new chapter: 17 pad location diagram. new figure 15. 27/8/99 c/242 18 (34,35) 18 package and ordering information new figure 16, 17, 18 27/8/99 c/242 18.1 (36) 18.1 chip marking ? new description 27/8/99 c/242 18.2 (36) 18.2 customer marking ? new 27/8/99 c/242 18.3 (36) 18.3 ordering information ? new 27/8/99 c/242 19 (37,38) 19 spec update - new 21/6/00 d/295 34 vddca, vbat (in figure 15.) vreg, vdd 21/6/00 d/295 34 (in figure 15.) substrate of the die is at vss 21/6/00 d/295 16 (30,31) ivdda, ivddh, ivdds max. over temperature change in 16.4 dc characteristics. 16.4. dc characteristics - power supply pins - new values for ivdda, ivddh, ivdds max. + 2 graphs iddrun = f(t) and iddhalt = f(t). 19.09.01 e/374 13 (26) new testloop 19.09.01 e/374 16.4 (30) ivdda, ivddh, ivdds max. over temperature change in 16.4 dc characteristics. 16.4 dc characteristics - power supply pins - new values for ivdda, ivddh, ivdds max. em6603 03/02 rev. g/439 copyright ? 2002, em microelectronic-marin sa 39 www.emmicroelectronic.com date version chapter (page) old text new text 01/11/01 e/374 all - change heater & footer add url. 11/02/02 f/374 24 - inten must be re-enable after auto swb 22/03/02 g/439 34 & 36 - modify pad location diagram & chip marking. |
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