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www.fa irchildsemi.com ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 AN-9750 high-power factor flyback converter for led driver with fl7732 psr controller introduction this highly integrated pwm controller, fl7732, provides several features to enhance the performance of low-power flyback converters. the proprietary topology enables simplified circuit design for led lighting applications. by using single-stage topology with primary-side regulation, a led lighting board can be implemented with few external components and minimized cost, without requiring an input bulk capacitor and feedback circuitry. to implement high power factor and low thd, constant on-time control utilizes an external capacitor connected at the comi pins. precise constant-current cont rol regulates accurate output current across changes in input voltage and output voltage. the operating frequency is proportionally changed by the output voltage to guarantee dcm operation with higher efficiency and simple design. fl7732 provides protection functions such as open-led, short-led and over- temperature protection. the current-limit level is automatically reduced to mi nimize the output current and protect external components in short-led condition. this application note presents practical design consideration for an led driver employing fairchild semiconductor pwm psr controller fl7732. it includes designing the transformer, selecting the components, and implementing constant current regulation. the step-by-step design procedure helps engineers design a power supply. the design procedure is verified through an experimental prototype converter. figure 1 shows the typical application circuit of primary-side controlled flyback converter using fl7732 created in the design example. figure 1. typical application circuit
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 2 basic operation generally, discontinuous conduction mode (dcm) operation is preferred for prim ary-side regulation because it allows better output regulation. the operation principles of dcm flyback converter are as follows: mode i during the mosfet turn-on time ( t on ), input voltage ( v in.pk ) is applied across the primary-side inductor ( l m ). then, drain current ( i ds ) of the mosfet increases linearly from zero to the peak value ( i pk ), as shown in figure 2. during this time, the energy is drawn from the input and stored in the inductor. mode ii when the mosfet ( q ) is turned off, th e energy stored in the inductor forces the rectifier diode ( d ) to be turned on. i ds v in nv out mode i mode ii mode iii i o i ds i d i m v ds v gate t dis t s v a i d o s a v n n ? figure 2. basic function of dcm mode flyback v out v in.peak q lm i m n:1 i ds c o d v ds + - v d + - i d + - figure 3. mode i: q[on], d[off] figure 4. mode ii: q[off], d[on] figure 5. mode iii: q[off], d[off] while the diode is conducting, output voltage (v out ), together with diode forward-voltage drop (v f ), is applied across the secondary-side inductor and diode current (i d ) decreases linearly from the peak value (i pk ? n p /n s ) to zero. at the end of inductor current discharge time (t dis ), all energy stored in the inductor has been delivered to the output. mode iii when the diode current reach es zero, the transformer auxiliary winding voltage begins to oscillate by the resonance between the primary-side inductor ( l m ) and the effective capacitor load ed across mosfet (q).
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 3 constant current regulation the output current ( i o ) can be estimated by using the peak drain current ( i pk ) of mosfet and discharging time ( t dis ) of inductor current becau se output current ( i o ) is same as the average of the diode current ( i d ) in steady state. the output current estimator identifies th e peak value of the drain current with a peak-detecti on circuit and calculates the output current using the inductor discharging time and switching period ( t s ). this output information is compared with an internal precise refere nce to generate error voltage ( v comi ), which determines the dut y cycle of the mosfet in constant current mode. with fairchild?s innovative truecurrent ? technique, the constant output current can be precisely controlled. sense r s n p n cs v t t o i s dis 1 2 1 ? ? ? ? ? (1) truecurrent ? calculation makes a precise output current prediction. figure 6. detection for truecurrent ? calculation figure 7. truecurrent ? calculation principle linear frequency control as mentioned above, dcm should be guaranteed for high power factor in flyback topology. to maintain dcm in the wide range of output voltage, frequency is linearly changed by the output voltage in linear frequency control. output voltage is detected by the auxiliary winding and resistive divider connected to the vs pin, as shown in figure 7. osc linear frequency controller v s freq. 6 vs v out figure 8. linear frequency control when output voltage decreases, secondary diode conduction time is increased and the linear frequency control lengthens the switching period, which retains dcm operation in the wide output voltage range, as shown in figure 8. the frequency control also lowers primary rms current with better power efficiency in full-load condition. l m nv o dis t lm v 4 3 n o dis t 3 4 lm v 5 3 n o dis t 3 5 t t 3 4 t 3 5 figure 9. primary and secondary current bcm control the end of secondary diode conduction time is possibly over a switching period set by linear frequency control. in this case, fl7732 doesn?t allow ccm and the operation mode changes from dcm to bcm. therefore, fl7732 originally eliminates sub-harmonic distortion in ccm.
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 4 protections the fl7732 have several self-pro tection functions, such as over-voltage protection, over-t emperature protection, and pulse-by-pulse current limit. all the protections are implemented as auto-restart mode. open-led protection fl7732 protects external components, such as diode and capacitor at secondary side, in open-led condition. during switch-off, the v dd capacitor is charged up to the auxiliary winding voltage, which is applied as the reflected output voltage. because the v dd voltage has output voltage information, the internal voltage comparator at the v dd pin can trigger output over-voltage protection (ovp), as shown in figure 9. when at least one led is open-circuited, output load impedance becomes very high and output capacitor is quickly charged up to v ovp x n s / n a . then switching is shut down and the v dd block goes into ?hiccup mode? until the open-led condition is removed, as shown in figure 10. 4 internal bias vdd + - v ovp v dd good shutdown gate driver s r q v dd good figure 10. internal ovp block under voltage lockout (uvlo) the turn-on and turn-off threshol ds are fixed internally at 16v and 7.5v, respectively. during startup, the v dd capacitor must be charged to 16v. the v dd capacitor continues to supply v dd until power can be delivered from the auxiliary winding of the main transformer. v dd is not allowed to drop below 7.5v during this startup process. this uvlo hysteresis window ensures that v dd capacitor properly supplies v dd during startup. figure 11. waveforms at open-led condition short-led protection (ocp) in case of short-led condition, the switching mosfet and secondary diode are usually stressed by the high powering current. however, fl7732 changes the ocp level in the short led condition. when v s voltage is lower than 0.4v, ocp level changes to 0.2v from 0.7v, as shown in figure 12 so that powering is limited and external components current stress is relieved. figure 12. internal ocp block figure 13 shows operational waveforms at short-led condition. output voltage is quickly lowered to 0v right after the led-short event. then, the reflected auxiliary voltage is also 0v making v s voltage less than 0.4v. 0.2v ocp level limits primary-side current and v dd hiccups up and down in between uvlo hysteresis.
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 5 figure 13. waveforms at short-led condition at short-led condition, v s is low due to low output voltage. then, ocp level is changed to 0.2v to reduce output current. over-voltage protection (ovp) the ovp prevents damage in over-voltage conditions. if the v dd voltage exceeds 23v at open-loop feedback condition, the ovp is triggered and the pwm switching is disabled. at open-led condition, v dd reaches v dd_ovp . then, auto- restart sequence causes a delay, limiting output voltage. over-temperature protection (otp) the built-in temperature-sensing circuit shuts down pwm output if the junction temper ature exceeds 150c. there is hysteresis of 10c.
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 6 design procedure in this section, a design procedure a of single-stage flyback using fl7732 is presented using the schematic of figure 1 as a reference. an offlin e led driver with 16.8w (24v/0.7a) output has been selected as a design example. the design specifications are as follows: ? input voltage range: 90 ~ 264v ac and 50 ~ 60hz ? nominal output voltage and current: 24v/0.7a ? minimum efficiency: 87% ? maximum switching frequency: 65khz step 1. inductor selection (l m ) fl7732 operates with constant turn-on and turn-off time, as shown figure 14. when mosfet turn-on time ( t on ) and switching period ( t s ) are constant, i in is proportional to v in and can implement high power factor. figure 14. theoretical waveform the single-stage flyback using fl7732 is assumed to operate in dcm due to constant t on and t s . input voltage is applied across the magnetizing inductance ( l m ) during t on , charging the magnetic energy in l m . therefore, the maximum peak switch current ( i sw.pk ) of mosfet occurs at peak point of line voltage, as shown figure 14. the peak input current ( i in.pk ) is also shown at the peak input voltage of one line cycle. once the maximum t on is decided, i sw.pk of mosfet is obtained at the minimum line input voltage and full-load condition as: m pk in on pk sw l v t i min . . ? ? (2) where v in.min.pk and t on are the peak input voltage and the maximum turn-on time at the minimum line input voltage, respectively. using equation 2, the peak input current is obtained by: s m f t l v t i on pk in on pk in ? ? ? ? ) )( ( 2 1 . min . . (3) then i in.pk and v in.min.pk can be expressed as: rms in pk in i i . . 2 ? ? (4) rms in pk in v v . . min . 2 ? ? (5) where the i in.rms and v in.rms are rms line input current and voltage, respectively. t on is required to calculate reasonable l m value. with equation (2) ~ (5), the turn-on time, t on , is obtained as: s rms n i rms in m on f v i l t ? ? ? . . 2 2 (6) the input power is given as: ? o rms in in p i p ? ? . (7) with equation (6) and (7), the l m value is obtained as: o on s rms in p t f v lm 2 ) ( 2 2 . ? ? ? ? ? (8) (design example) since the minimum input voltage is 90v ac , the maximum t on occurs at full-load condition. assuming the maximum t on is 7.4s at 65khz of the maximum frequency, the magnetizing inductance is obtained as: h l m 743 8 . 16 2 ) 10 4 . 7 ( 10 65 90 87 . 0 2 6 3 2 ? ? ? ? ? ? ? ? ? the maximum peak current of mosfet at nominal output power is calculated as: a i pk sw 26 . 1 10 743 90 2 10 4 . 7 6 6 . ? ? ? ? ? ? ? ? step 2. sensing resistor and n ps selection since fl7732 adopts truecurrent ? calculation method to regulate constant output current ( i o ), as defined in equation 1. the output current is proportional to turn ratio n ps between the primary and secondary windings of the transformer and inversely proportional to sensing resistor ( r s ). the fl7732 also implements cycle-by-cycle current limitation by detecting v cs to protect system from output short or overload. therefore, v cs level to handle rated system power without the current limitation should be considered. it is typical to set the cycle-by-cycle limit level (typical: 0.67v) at 20~30 % higher than cs peak voltage ( v cs.pk ) at full-load condition. mosfet peak current ( i sw.pk ) is converted into v cs,pk as: s pk sw pk cs r i v ? ? . . (9)
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 7 according to equation (1), the transformer turn ratio is determined by the sensing resistor and nominal output current as: s o ps r i n ? ? ? 5 . 10 (10) where: 5 . 10 1 2 1 ? ? ? cs s dis v t t (11) (design example) once v cs,pk is set as 0.5v, the sensing resistor value is obtained as: 396 . 0 26 . 1 5 . 0 . . ? ? ? pk sw pk cs s i v r 91 . 2 396 . 0 7 . 0 5 . 10 ? ? ? ? ps n step 3. n as selection when v dd voltage is 23v, fl7732 stops switching operation due to over-voltage protection (ovp). so n as can be determined as follows: ovp o ovp o ovp dd as v v v n . . . 23 ? ? (12) where ( n as = n a /n s ) is the turns ratio the of secondary to auxiliary of transformer. therefore, v o.ovp can be set by changing the n as value. (design example) once output over-voltage level is set as 30v, n as is obtained as: 77 . 0 30 23 ? ? as n step 4. resistor selection ( r vs1 and r vs2 ) the first consideration for r vs1 and r vs2 selection is that v s is 2.35v at the end of diode current conduction time to operate at maximum switching frequency at rated power. the second consideration is v s blanking, as explained below. the output voltage is detected by auxiliary winding and a resistive divider connected to the vs pin, as shown in figure 7. however, in a single-stage flyback without dc link capacitor, auxiliary windi ng voltage cannot be clamped to reflected output voltage due to the small l m current, which induces v s voltage sensing error. then, frequency decreases rapidly at the zero-crossing point of line voltage, which can cause flicker. to maintain constant frequency over the whole sinusoidal line voltage, fl7732 has v s blanking to disable sampling of v s voltage at less than a particular line voltage by sensing the auxiliary winding. considering the maximum switching frequency at rated power and v s blanking level, r vs1 and r vs2 are obtained as: max max . . ) ( vs vs as f o vs v v n v v r ? ? ? (13) 2 1 vs vs vs r r r ? ? (14) where v vs.max is the v s value to set the maximum switching frequency for constant output current in rated power and v f is secondary diode forward voltage. ) 545 . 0 545 . 0 ( 10 100 1 6 2 vs ap bnk in vs r n v r ? ? ? ? ? ? ? (15) where v in.bnk and n ap are the blanking level of input voltage and the turn ratio of auxiliary to primary, respectively. the n ap can be calculated as the ratio of n as to n ps . (design example) the voltage divider network is determined as: 06 . 7 35 . 2 35 . 2 77 . 0 ) 7 . 0 24 ( ? ? ? ? ? vs r once v in.bnk level is set to 50v, r vs2 is obtained as. ? ? ? ? ? ? ? ? ? k r vs 86 . 24 ) 06 . 7 91 . 2 77 . 0 50 545 . 0 545 . 0 ( 10 100 1 6 2 then r vs1 is determined to be 175.5 k . it is recommended to place a bypass capacitor of 10 ~ 30pf closely between the vs pin and the gnd pin to bypass the switching noise and keep the accuracy of the v s sensing for cc regulation. the value of the capacitor affects constant- current regulation. if a high value of v s capacitor is selected, the discharge time t dis becomes longer and the output current is lower, compared to small v s capacitor. step 5. design the transformer the number of primary turns is determined by faraday?s law. n p,min is fixed by the peak value of the minimum line input voltage across the primary winding and the maximum on time. the minimum number of turns for the transformer primary side to avoid the core saturation is given by: e sat on pk in p a b t v n ? ? ? . min . min , (16) where a e is the cross-sectiona l area of the core in m 2 and b sat is the saturation flux density in tesla. since the saturation flux density decreases as the temperature rises, the high- temperature characteristics should be considered when it is used in an enclosed case.
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 8 (design example) an rm8 core is selected for the transformer and the minimum number of turns for the transformer primary side to avoid the core saturation is given by: t n p 5 . 54 10 64 27 . 0 10 4 . 7 90 2 6 6 min , ? ? ? ? ? ? ? ? ? considering the tolerance of the transformer and high ambient temperature, n p should be selected with a margin about 5% ~ 10% to avoid core saturation: t n p 95 . 59 1 . 1 5 . 54 ? ? ? once the turn number of the primary side ( n p ) is determined as 60 t , the turn number of the secondary side ( n s ) is obtained by: t n s 5 . 20 91 . 2 60 ? ? ? once the turn number of the secondary side ( n s ) is determined as 20t, the auxiliary winding turns ( n a ) is obtained by: t n a 4 . 15 77 . 0 20 ? ? ? n a is determined to be 15t. step 6. calculate the voltage and current of the switching devices primary-side mosfet : the voltage stress of the mosfet was discussed when determining the transformer turns ratio. assuming the drain voltage overshoot is the same as the reflected output voltage, the maximum drain voltage is given as: os f o s p pk in ds v v v n n v v ? ? ? ? ) ( . max . (max) (17) where v in.max.pk is the maximum line peak voltage. the rms current ( i sw.rms ) though the mosfet is given as: 6 . s on pk rms sw f t i i ? ? ? (18) figure 15. drain voltage of mosfet ( design example ) assuming that drain voltage overshoot is the same as the reflected output voltage, the maximum drain voltage across the mosfet is calculated as: v v ds 522 2 ) 7 . 0 24 ( 20 60 374 (max) ? ? ? ? ? ? the rms current though the mosfet is a i rms sw 357 . 0 6 065 . 0 4 . 7 26 . 1 . ? ? ? ? secondary-side diode : the maximum reverse voltage and rms current of the rectifier diode are obtained as: pk in p s o d v n n v v . max . ? ? ? (19) s p ro pk in rms sw rms d n n v v i i ? ? ? ? 2 . min . . . (20) ( design example ) the diode voltage and current are obtained as: v v d 7 . 148 374 60 20 24 ? ? ? ? a i rms d 991 . 0 20 60 1 . 74 2 127 357 . 0 . ? ? ? ? ?
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 9 step 7. design rcd snubber in primary side when the power mosfet is tu rned off, there is a high- voltage spike on the drain due to the transformer leakage inductance. this excessive voltage on the mosfet may lead to an avalanche breakdown and eventually failure of the device. therefore, it is nece ssary to use an additional network to clamp the voltage. the rcd snubber circuit and its waveform are shown in figure 16 and figure 17, respectively. the rcd snubber network absorbs the current in the leakage inductance by turning on the snubber diode ( d sn ) once the mosfet drain voltage exceeds the cathode voltage of snubber diode. in the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching cycle. the snubber capacitor should be ceramic or a material that offers low esr. electrolytic or tantalum capacitors are unacceptable for these reasons. figure 16. snubber circuit figure 17. snubber waveforms snubber capacitor voltage at full-load condition is given as: os ro sn v v v ? ? (21) the power dissipated in the snubber network is obtained as: s ro sn sn pk lk sn sn sn f v v v i l r v p ? ? ? ? ? ? 2 2 2 1 (22) where l lk is leakage inductance, v sn is the snubber capacitor voltage at full load, and r sn is the snubber resistor. the leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted. then, the snubber resistor with proper rated wattage should be chosen based on the power loss. the maximum ripple of the snubber capacitor voltage is obtained as: s sn sn sn sn f r c v v ? ? ? ? (23) in general, 5 ~ 20% ripple of the selected capacitor voltage is reasonable. in this snubber design, neither the lossy discharge of the inductor nor stray capacitance is considered. ( design example ) since the voltage overshoot of drain voltage has been determined to be the same as the reflected output voltage, the snubber voltage is: v v v v os ro sn 150 ? ? ? the leakage inductance is measured as 10h. then the loss in snubber networking is given as: w p sn 03 . 1 10 65 75 150 150 26 . 1 10 10 2 1 3 2 6 ? ? ? ? ? ? ? ? ? ? ? ? k r sn 84 . 21 03 . 1 150 2 to allow 7% ripple on the snubber voltage (150v): nf c sn 06 . 10 10 65 10 84 . 21 150 07 . 0 150 3 3 ? ? ? ? ? ? ?
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 10 lab notes 1. before modifying or soldering/desoldering the power supply, discharge the primary capacitors through the external bleeding resistor. otherwise, the pwm ic may be destroyed by external high-voltage during the process. this device is sensitive to electrostatic discharge (esd). to improve the yield, the production line should be esd protected as required by ansi esd s1.1, esd s1.4, esd s7.1, esd stm 12.1, and eos/esd s6.1 standards. 2. in case of led-short condition, v dd voltage charged at v dd capacitor should touch v dd off level rapidly to stop switching. therefore, v dd capacitor value is recommended under 22f.
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 11 schematic of design example figure 18 shows the schematic of the 16.8w led driver design example. rm8 core is used for the transformer. figure 19 shows the transformer information. figure 18. schematic of the fl7732 17w design example figure 19. transformer winding structure no. winding pin (s f) wire turns winding method 1 np1 12 ? 1 0.25 30 ts solenoid winding 2 insulation: polyester tape t = 0.025mm, 3-layer 3 ns 7- ? 8 0.5 (tiw) 20 ts solenoid winding 4 insulation: polyester tape t = 0.025mm, 3-layer 5 np2 1 ? 2 0.25 30 ts solenoid winding 6 insulation: polyester tape t = 0.025mm, 3-layer 7 na 6 ? 5 0.25 15 ts solenoid winding 8 insulation: polyester tape t = 0.025mm, 3-layer pin specification remark inductance 12? 2 750h 10% 60khz, 1v leakage 1? 2 6h 60khz, 1v short all output pins
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 12 bill of materials item no. part reference part number qty description manufacturer 1 bd1 df06s 1 1.5a/600v bridge diode fairchild 2 cf1 mpx ac275v 104k 1 104/ ac275v x-capacitor carli 3 cf2 mpx ac275v 473k 1 473/ ac275v x-capacitor carli 4 cs1 c1206c103kdractu 1 103/1kv smd capacitor 3216 kemet 5 cy1 scfz2e472m10bw 1 472/ 250v y-capacitor samwha 6 co1,co2 kmg 470f/35v 2 470uf/35v electrolytic capacitor samyoung 7 c1 mpe 630v104k 14s 1 104/630v mpe film capacitor sungho 8 c2 kmg 22f/50v 1 22uf/35v el ectrolytic capacitor samyoung 9 c3 c0805c104k5ractu 1 104/50v smd capacitor 2012 kemet 10 c4 c0805c200j5gactu 1 200/50v smd capacitor 2012 kemet 11 c5 c0805c225z3vactu 1 225/25v smd capacitor 2012 kemet 12 ds1 rs1m 1 1000v/1a ultra fast recovery diode fairchild 13 do1 es3d 1 200v/3a, fast rectifier fairchild 14 d1 1n4003 1 200v/1a, general purpose rectifier fairchild 15 f1 ss-5-1a 1 250v/1a fuse bussmann 16 lf1 r10402kt00 1 4mh inductor, 10? bosung 17 mov1 svc 471 d-07a 1 metal oxide varistor samwha 18 q1 fdd5n60nz 1 600v/4a, n-channel mosfet fairchild 19 rg1, r6 rc1206jr-0710l 2 10 ? smd resistor 3216 yageo 20 rs1,rs2 rc1206jr-07100kl 2 100k ? smd resistor 3216 yageo 21 rcs1,rcs2 rc1206jr-071rl 2 1 ? smd resistor 3216 yageo 22 rcs3 rc1206jr-072r4l 1 2.4 ? smd resistor 3216 yageo 23 ro1 rc1206jr-0720kl 1 20k ? smd resistor 3216 yageo 24 r4 rc1206jr-07150kl 1 150k ? smd resistor 3216 yageo 25 r1,r2,r3 rc1206jr-0768kl 3 68k ? smd resistor 3216 yageo 26 r5 rc1206jr-0724kl 1 24k ? smd resistor 3216 yageo 27 t1 rm8 core 1 12pin, transformer tdk 28 u1 fl7732m_f116 1 main psr controller fairchild
AN-9750 application note ? 2011 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.3 ? 5/15/12 13 related datasheets fl7732 ? single-stage pfc primary-si de-regulation offline led driver reference designs ? http://www.fairchildsemi.com/referencedesign/ disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fa irchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as criti cal components in life support devices or systems without the express written approval of the preside nt of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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