1 ? fn9254.2 isl8011 1.2a integrated fets, high efficiency synchronous buck regulator isl8011 is an integrated fe t, 1.2a synchronous buck regulator for general purpose point-of load applications . it is optimized for generating low out put voltages down to 0.8v. the supply voltage range is from 2.7v to 5.5v allowing the use from common 3.3v or 5v supply rails and lithium ion battery inputs. it has guaranteed minimum output current of 1.2a. 1.5mhz pulse-width modulation (pwm) switching frequency allowing the use of small external components. the isl8011 includes a pair of low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external component count. 100% duty-cycle operation allows less than 200mv dropout voltage at 1.2a. the isl8011 offers a 200ms power-on-reset (por) timer at power-up. when shutdown, the isl8011 discharges the output capacitor. other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. the isl8011 is offered in a 10 ld 3mmx3mm dfn package with 1mm maximum height. the complete converter occupies less than 1cm 2 area. features ? high efficiency synchronous buck regulator with up to 95% efficiency ? 2.7v to 5.5v supply voltage ? 1.2a output current ? 100% maximum duty cycle ? peak current limiting, short circuit protection ? 200ms power-on reset ? 3% output accuracy ov er-temperature/load/line ? less than 1a logic controlled shutdown current ? internal loop compensation ? internal digital soft-start ? over-temperat ure protection ? enable ? small 10 ld 3mmx3mm dfn ? pb-free (rohs compliant) applications ? dc/dc pol modules ? c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ? portable instruments ? test and measurement systems pinout isl8011 (10 ld 3x3 dfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8011IRZ 011z -40 to +85 10 ld 3x3 dfn l10.3x3c ISL8011IRZ-t* 011z -40 to +85 10 ld 3x3 dfn tape and reel l10.3x3c *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2 3 4 1 5 9 8 7 10 6 pvin vcc en por gnd phase pgnd sgnd fb n/c data sheet august 4, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006, 2007, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9254.2 august 4, 2009 absolute maxi mum ratings (reference to sgnd) thermal information supply voltage (pvin, v cc ) . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v en, mode, phase, por . . . . . . . . . . . . . . . . . . -0.3v to v cc +0.3v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v recommended operating conditions pvin supply voltage range . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.2a ambient temperature range . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (notes 1, 2) ja (c/w) jc ( c /w) 10 ld 3x3 dfn package . . . . . . . . . . . 48 5 junction temperature range. . . . . . . . . . . . . . . . . .-55c to +125c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp aution: do not operate at or near the maximum ratings listed fo r extended periods of time. expos ure to such conditions may adve rsely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. see tech brief tb379. electrical specifications t a = +25c, v pvin = v vcc = 3.6v, en = v cc , l = 1.8h, c 1 = 10f, c 2 = 10f, i out = 0a (see ?typical applications? on page 6); parameters with min and/or m ax limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. parameter symbol test conditions min typ max units supply v cc undervoltage lockout threshold v uvlo rising - 2.5 2.7 v falling 2.2 2.4 - v quiescent supply current i pvin no load at the output - 5 8 ma shut down supply current i sd v cc = pvin = 5.5v, en = low - 0.1 2 a output regulation fb regulation voltage v fb t a = 0c to +85c 0.784 0.8 0.816 v t a = -40c to +85c 0.78 0.8 0.82 v fb bias current i fb fb = 0.75v - 0.1 - a output voltage accuracy pvin = v o + 0.5v to 5.5v, i o = 0a to 1.2a, t a = -40c to +85c -3 - 3 % line regulation pvin = v o + 0.5v to 5.5v (minimal 2.7v) - 0.2 - %/v maximum output current 1.2 - - a compensation error amplifier trans-conduct ance adjustable version, design info only - 20 - a/v phase p-channel mosfet on-resistance pvin = 3.6v, i o = 200ma - 0.12 0.22 pvin = 2.7v, i o = 200ma - 0.16 0.27 n-channel mosfet on-resistance pvin = 3.6v, i o = 200ma - 0.11 0.22 pvin = 2.7v, i o = 200ma - 0.15 0.27 p-channel mosfet peak current limit i pk 1.5 2.1 2.6 a phase maximum duty cycle - 100 - % pwm switching frequency f s t a = -40c to +85c 1.35 1.6 1.75 mhz phase minimum on time - - 140 ns soft start-up time -1.1- ms isl8011
3 fn9254.2 august 4, 2009 por output low voltage sinking 1ma, fb = 0.7v - - 0.3 v delay time 150 200 275 ms por pin leakage current por = v cc = 3.6v - 0.01 0.1 a minimum supply voltage for valid por signal 1.2 - - v internal pgood low rising threshold percent age of nominal regulation voltage 89.5 92 94.5 % internal pgood low falling threshold percent age of nominal regulation voltage 85 88 91 % internal pgood high rising threshold percentage of nominal regulation voltage 105.5 108 110.5 % internal pgood high falling threshold perc entage of nominal regulation voltage 102 105 108 % internal pgood delay time -50- s en logic input low --0.4v logic input high 1.4 - - v logic input leakage current pulled up to 5.5v - 0.1 1 a thermal shutdown - 150 - c thermal shutdown hysteresis -25-c electrical specifications t a = +25c, v pvin = v vcc = 3.6v, en = v cc , l = 1.8h, c 1 = 10f, c 2 = 10f, i out = 0a (see ?typical applications? on page 6); parameters with min and/or m ax limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. (continued) parameter symbol test conditions min typ max units typical operating performance figure 1. efficiency vs load current (v in = 5.0v) figure 2. v out vs load current (v in = 5v) 60 70 80 90 100 50 200 350 500 650 800 950 1100 load current (ma) efficiency (%) v out = 3.3v v out = 1.8v v out = 2.5v 2.40 2.45 2.50 2.55 2.60 50 250 450 650 850 1050 load current (ma) v out (v) isl8011
4 fn9254.2 august 4, 2009 figure 3. i q vs v in figure 4. switching frequency vs v in figure 5. line regulation (io = 1a) figure 6. load regulation (v in = 3.6v) figure 7. soft-start figure 8. steady-state (v in = 3.6v; v o = 1.6v; i o = 1a) typical operating performance (continued) 0 1 2 3 4 5 6 7 2.9 3.4 3.9 4.4 4.9 5.4 v in voltage range (2.9v to 5.5v) input current (ma) v o = 2.8v 1.570 1.575 1.580 1.585 1.590 1.595 1.600 1.605 2.7 3.2 3.7 4.2 4.7 5.2 v in (v) switching frequency (mhz) 1.600 1.602 1.604 1.606 1.608 1.610 2.7 3.7 4.7 v in (v) v o (v) 5.7 1.590 1.595 1.600 1.605 1.610 0 200 400 600 800 1000 i o (ma) v o (v) v out en v out i l v out v phase i l isl8011
5 fn9254.2 august 4, 2009 pin descriptions pvin input supply voltage. connect a 10f ceramic capacitor to power ground. vcc supply voltage for internal analog and digital control circuits, delivered from pvin. bypass with 0.1f ceramic capacitor to signal ground. en regulator enable pin. force this pin above 1.4v enable the chip. force this pin below 0.4v shutdown the chip and discharge output capacitor when driven to low. do not leave this pin floating. por 200ms timer output. at power-up or en hi, this output is a 200ms delayed power-good signal for the output voltage. gnd ground. connect this pin to the exposed pad and sgnd. phase switching node connection. connect to one terminal of inductor. pgnd power ground. connect all power grounds to this pin. sgnd analog ground. sgnd and pg nd should only have one point connection. fb buck regulator output feedba ck. connect to the output through a resistor divider for adjustable the output voltage. exposed pad the exposed pad must be connected to the pgnd pin for proper electrical performance and optimal thermal performance. nc nc is the no connect pin. tie this pin to sgnd to prevent noise. figure 9. load transient (v in = 3.6v; v o = 1.6v; i o = 0a to ~1a) typical operating performance (continued) v phase i l v out i o isl8011
6 fn9254.2 august 4, 2009 typical applications block diagram figure 10. typical application for adjustable version phase pgnd sgnd fb l c2 10f r2 61.9k vout 1.3v, 1.2v r3 100k gnd por en vcc pvin vin 2.7v to 5.5v c3 0.1f r1 100k c1 10f 1.8h isl8011 figure 11. functional block diagram ea bandgap soft-start comp pwm control and drivers csa1 phase pvin pgnd vcc 50 slope compensation ocp 0.8v en fb 200ms delay por 0.864v 0.736v scp 270k 30pf 0.85v sgnd gnd shutdown 0.2v shutdown oscillator csa2 z c + - + - + - + - + - + - - + + - + isl8011
7 fn9254.2 august 4, 2009 theory of operation isl8011 is an integrated fet, 1.2a synchronous buck regulator for general purpose po int-of load applications. the regulator operates at 1.5m hz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. the supply current is typically only 0.1a when the regulator is shut down. pwm control scheme the isl8011 employs the current-mode pulse-width modulation (pwm) control sc heme for fast transient response and pulse-by-pulse current limiting. figure 11 shows the block diagram. the current loop consists of the oscillator, the pwm comparator comp, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current sense amplifier (csa1). the gain for the current sensing circuit is typically 0.4v/a. the control reference for the current loops comes from the error amplifier eamp of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the csa1 and the compensation slope (0.675v/s) reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channel mosfet. the n-mosfet stays on until the end of th e pwm cycle. figure 12 shows the typical operating waveforms during the pwm operation. the dotted lines illustrate the sum of the compensation ramp and the csa1 output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage control loop. the feedback signal comes from the fb pin. the soft-start block only affects the operation during the start-up and will be discussed separately shortly. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 25pf and 400k rc network. the maximum eamp voltage output is precisely clamped to the bandgap voltage (1.172v). overcurrent protection the overcurrent protection is realized by monitoring the csa1 output with the ocp comparator, as shown in figure 11. the current sensing circuit has a gain of 0.4v/a, from the n-mosfet current to the csa1 output. when the csa1 output reaches 1v, which is equivalent to 2.5a for the switch current, the ocp comparat or is tripped to turn off the p-mosfet immediately. short-circuit protection a short-circuit protection (scp) comparator monitors the fb pin voltage for output short-circuit protection. when the fb is lower than 0.2v, the scp comparator forces the pwm oscillator frequency to drop to 1/3 of the normal operation value. this comparator is effective during start-up or an output short-circuit event. por signal the isl8011 offers a power-on reset (por) signal for resetting the microprocessor at the power-up. when the output voltage is not within a power-good window, the por pin outputs an open-drain low signal to reset the microprocessor. the output voltage is monitored through the fb pin. when the voltage of the monitored node is within the window of 0.736v and 0.864v, a power-good signal is issued to turn off the open-drain por pin. the rising edge of the por output is delayed by 200ms. uvlo when the input voltage is below the undervoltage lock out (uvlo) threshold, the regulator is disabled. soft start-up the soft start-up eliminates the inrush current during the start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the start-up, the output voltage is less than 0.2v; hence the pwm operating frequency is 1/3 of the norma l frequency. figure 7 shows the start-up waveforms. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-mosfet is typically 150m and the on-resistance for the n-mosfet is typically 150m . 100% duty cycle the isl8011 featur es 100% duty cycle operation to maximize the battery life. when the battery voltage drops to figure 12. pwm operation waveforms v eamp v csa1 duty cycle i l v out isl8011
8 fn9254.2 august 4, 2009 a level that the isl8011 can no longer maintain the regulation at the output, the regulator completely turns on the p-mosfet. the maximum drop out voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. enable the enable (en) input allows user to control the turning on or off the regulator for purposes such as power-up sequencing. the the regulator is enabled, there is typically a 300s delay for waking up the bandgap reference. then the soft start-up begins. when the regulator is disabled, the p-mosfet is turned off immediately and the n-mosfet is turned on. thermal shut down the isl8011 has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shut down. as the temperature drops to +130c, the isl8011 resumes operation by stepping through a soft start-up. v cc by-passing the v cc is voltage is the supply to the internal control circuit and is derived from the pvin pin. an internal 5 resistor connects the two pins and also serves as an filtering resistor. an external 0.1f ceramic capacitor is recommended to by-pass the v cc supply. applications information output inductor and capacitor selection to consider state steady and transient operation, isl8011 typically uses a 1.8h output inductor. higher or lower inductor values can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased as shown in table 1. the inductor ripple current can be expressed as shown in equation 1: the inductor?s saturation current rating needs be at least larger than the peak current. the maximum peak current of isl8011 is 2.1a. the saturation current needs be over 2.1a for maximum output current application. isl8011 uses internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended minimum output capacitor values are shown in table 1. in table 1, the minimum output capacitor value is given for different output voltage to make sure the whole converter system stable. due to the lim itation on power dissipation when the regulator disable and discharge output capacitor, there is the maximum output capacitor value. the maximum output capacitor value is variable with the output voltage. the plot curve is shown in figure 13. input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the supply rail. a 10f x5r or x7r ceramic capacitor is a good starting point for the input capacitor selection. output voltage setting resistor selection the resistors r 2 and r 3 shown in figure 10 set the output voltage for the adjustable vers ion. the output voltage can be calculated by using equation 2: where the 0.8v is the reference voltage. to minimize the accuracy impact on the out put voltage, select the r 2 and r 3 no larger than 100k . i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) table 1. output capacitor value vs v out v out c out l 0.8v 10f 1.0h~2.2h 1.2v 10f 1.2h~2.2h 1.6v 10f 1.8h~2.2h 1.8v 10f 1.8h~3.3h 2.5v 10f 1.8h~3.3h 3.3v 6.8f 1.8h~4.7h 3.6v 4.7f 1.8h~4.7h 600 505 410 315 220 125 30 output capacitor value (f) 1.27 0.8 1.73 2.2 2.67 3.13 3.6 output voltage (v) figure 13. the maximum cap vs the output voltage v o 0.8 1 r 2 r 3 ------ - + ?? ?? ?? ? = (eq. 2) isl8011
9 fn9254.2 august 4, 2009 layout recommendation the layout is a very important converter design step to make sure the designed converter works well. for isl8011 buck converter, the power loop is com posed of the output inductor l, the output capacitor c out , phase pin and pgnd pin. it is necessary to make the power loop as small as possible. in order to make the output voltage regulate well and avoid the noise coupling from the power loop, sgnd pin should be connected with pgnd pin at t he terminals of the load. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for emi performance. isl8011
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9254.2 august 4, 2009 isl8011 dual flat no-lead plastic package (dfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.10 2x e a b c 0.10 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k 9 l m l10.3x3c 10 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.85 0.90 0.95 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 5, 8 d 3.00 bsc - d2 2.33 2.38 2.43 7, 8 e 3.00 bsc - e2 1.59 1.64 1.69 7, 8 e 0.50 bsc - k0.20 - - - l 0.35 0.40 0.45 8 n102 nd 5 3 rev. 1 4/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for dimensions e2 & d2.
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