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cy7c144 cy7c145 8k x 8/9 dual-port static ram with sem, int, busy cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06034 rev. *h revised december 2, 2010 features true dual-ported memory cells that enable simultaneous reads of the same memory location 8k x 8 organization (cy7c144) 8k x 9 organization (cy7c145) 0.65-micron complementary metal oxide semiconductor (cmos) for optimum speed and power high speed access: 15 ns low operating power: i cc = 160 ma (max.) fully asynchronous operation automatic power-down transistion transistor logic (ttl) compatible master/slave select pin enables bus width expansion to 16/18 bits or more busy arbitration scheme provided semaphores included to permit software handshaking between ports int flag for port-to-port communication available in 68-pin plastic leaded chip carrier (plcc), 64-pin and 80-pin thin quad plastic flatpack (tqfp) pb-free packages available functional description the cy7c144 and cy7c145 are high speed cmos 8k x 8 and 8k x 9 dual-port static rams. va rious arbitration schemes are included on the cy7c144/5 to handle situations when multiple processors access the same piece of data. two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. the cy7c144/5 can be used as a standalone 64/72-kbit dual-port static ram or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multiprocessor des igns, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags, busy and int , are provided on each port. busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semap hore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power down feature is controlled independently on each port by a chip enable (ce ) pin or sem pin. r/w l ce l oe l a 12l a 0l a 0r a 12r r/w r ce r oe r ce r oe r ce l oe l r/w l r/w r i/o 7l i/o 0l i/o 7r i/o 0r interrupt semaphore arbitration control i/o control i/o memory array address decoder address decoder sem l sem r busy l busy r int l int r m/s (7c145) i/o 8l i/o 8r (7c145) [1, 2] [2] [1, 2] [2] logic block diagram notes 1. busy is an output in master mode and an input in slave mode. 2. interrupt: push-pull output and requires no pull-up resistor. [+] feedback
cy7c144 cy7c145 document #: 38-06034 rev. *h page 2 of 23 contents pin configuration ............................................................. 3 architecture ...................................................................... 5 functional description ..................................................... 5 write operation ........................................................... 5 read operation ........................................................... 5 interrupts ..................................................................... 5 busy ............................................................................ 5 master/slave ............................................................... 5 semaphore operation ............ .............. .............. ......... 5 maximum ratings ............................................................. 7 operating range ............................................................... 7 electrical characteristics ................................................. 7 electrical characteristics ................................................. 8 capacitance ...................................................................... 8 switching characteristics ................................................ 9 switching waveforms .................................................... 11 ordering information ...................................................... 18 ordering code definitions ..... .................................... 18 package diagrams .......................................................... 19 acronyms ........................................................................ 21 document conventions ................................................. 21 units of measure ....................................................... 21 document history page ................................................. 22 sales, solutions and legal information ....................... 23 worldwide sales and design s upport ......... .............. 23 products .................................................................... 23 psoc solutions ......................................................... 23 [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 3 of 23 pin configuration figure 1. 68-pin plcc (top view) figure 2. 64-pin tqfp (top view) figure 3. 80-pin tqfp (top view) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 60 59 58 57 56 55 54 53 52 51 50 49 48 3132 33 34 35 36 37 38 39 40 41 42 43 5 4 3 2 1 68 66 65 64 63 62 61 a a 4l a 3l a 2l a 1l a 0l int l busy l gnd m/s busy r int r a 0r io 2l io 3l io 4l io 5l gnd io 6l io 7l v cc gnd io 0r io 1r io 2r v cc a 2728 29 30 98 7 6 47 46 45 44 a 1r a 2r a 3r a 4r io 3r io 4r io 5r io 6r 25 26 6l 7l a 8l a 9l a a 10l 11l v cc nc nc ce l sem l r/w l oe l nc io io 1l 0l a a 6r 7r a 8r a 9r a 10r nc nc ce r sem r r/w r oe r io 7r gnd a 11r a 5r a 5l nc a 12l a 12r cy7c144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 gnd oe r io 2l io 3l io 4l io 5l io 6l io 7l v cc gnd io 0r io 1r io 2r io 3r io 4r io 5r io 6r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r io 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r nc ce r sem r r/w r v cc oe l io 1l io 0l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l nc ce l sem l r/w l cy7c144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 36 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 44 45 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 64 65 63 62 61 i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r 2r i/o 3r i/o 4r 5r gnd v cc v cc oe l i/o 0l i/o 8l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l ce l sem l r/w l a 4l a 3l a 2l a 1l a 0l gnd busy l m/s a 0r a 1r a 2r a 3r a 4r int l gnd oe r i/o 6r a 12r a 11r a 10r a 9r a 8r a 7r a 6r nc ce r sem r r/w r cy7c145 busy r int r i/o 8r nc nc nc nc nc nc nc nc nc nc nc nc nc a 5r i/o 7r nc i/o i/o nc i/o 1l [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 4 of 23 table 1. selection guide description 7c144-15 7c145-15 7c144-25 7c144-55 unit maximum access time 15 25 55 ns maximum operating current 220 180 160 ma maximum standby current for i sb1 60 40 30 ma table 2. pin definitions left port right port description i/o 0l ? 7l(8l) i/o 0r ? 7r(8r) data bus input/output a 0l ? 12l a 0r ? 12r address lines ce l ce r chip enable oe l oe r output enable r/w l r/w r read/write enable sem l sem r semaphore enable. when asserted low, allows acce ss to eight semaphores. the three least significant bits of the address lines will determine wh ich semaphore to write or read. the i/o 0 pin is used when writing to a semaphore. semaphores are requested by writing a 0 into the respective location. int l int r interrupt flag. int l is set when right port writes location 1ffe and is cleared when left port reads location 1ffe. int r is set when left port writes location 1fff and is cleared when right port reads location 1fff. busy l busy r busy flag m/s master or slave select v cc power gnd ground [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 5 of 23 architecture the cy7c144/5 consists of a an array of 8 k words of 8/9 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes or reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be used for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the cy7c144/5 can functi on as a master (busy pins are outputs) or as a slave (busy pins are inputs). the cy7c144/5 has an automatic power down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w to guarantee a valid write. a write operation is controlled by either the oe pin (see figure 8 on page 12 ) or the r/w pin (see write cycle no. 2 waveform). data can be written to the device t hzoe after the oe is deasserted or t hzwe after the falling edge of r/w . required inputs for non-contention operations are summarized in table 3 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe are asserted. if the user of the cy7c144/5 wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin. interrupts the interrupt flag (int ) permits communications between ports.when the left port writes to location 1fff, the right port?s interrupt flag (int r ) is set. this flag is cleared when the right port reads that same location. settin g the left port?s interrupt flag (int l ) is accomplished when the right port writes to location 1ffe. this flag is cleared when the left port reads location 1ffe. the message at 1fff or 1ffe is user-defined. see ta b l e 4 for input requirements for int . int r and int l are push-pull outputs and do not require pull-up resistors to operate. busy the cy7c144/5 provides on-chip arbitration to alleviate simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other the busy logic determines which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. busy will be asserted t bla after an address match or t blc after ce is taken low. busy l and busy r in master mode are push-pull outputs and do not require pull-up resistors to operate. master/slave an m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this enables the device to interface to a master device with no external components.writing of slave devices must be delayed until after the busy input has settled. ot herwise, the slave chip may begin a write cycle during a contention situation.when presented a high input, the m/s pin allows the device to be used as a master and therefore the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c144/5 provides eight semaphore latches which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports.the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a 0 to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it assume s the right port has control and continues to poll the semaphore.when the right side has relinquished control of the sema phore (by writing a 1), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaphore, a 1 is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip enable for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access.when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only i/o 0 is used. if a 0 is written to the left port of an unused se maphore, a 1 appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing 0 (the left port in this case). if the left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both sides. however, if the right port had requested the semaphore (written a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. table 5 shows sample semaphore operations. when reading a semaphore, all eight/nine data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. initialization of the semaphore is not automatic and must be reset during initialization program at power-up. all semaphores on both sides should have a one written into them at initialization from both sides to assure that they are free when needed. [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 6 of 23 table 3. non-contending read/write inputs outputs operation ce r/w oe sem i/o 0 ? 7/8 h x x h high z power-down h h l l data out read data in semaphore x x h x high z i/o lines disabled h x l data in write to semaphore lhl hdata out read l l x h data in write l x x l illegal condition table 4. interrupt operation example (assumes busy l = busy r = high) function left port right port r/w ce oe a 0 ? 12 int r/w ce oe a 0 ? 12 int set left int xxxx l l l x1ffex reset left int xll1ffeh xl l x x set right int llx1fffx xxx x l reset right int xxxxxxll1fffh table 5. semaphore operation example function i/o 0-7/8 left i/o 0-7/8 right status no action 1 1 semaphore free left port writes semaphore 0 1 left port obtains semaphore right port writes 0 to semaphore 0 1 right side is denied access left port writes 1 to semaphore 1 0 rig ht port is granted access to semaphore left port writes 0 to semaphore 1 0 no change. left port is denied access right port writes 1 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore address right port writes 0 to semaphore 1 0 right port obtains semaphore right port writes 1 to semaphore 1 1 no port accessing semaphore left port writes 0 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 7 of 23 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. [3] storage temperature ????????????????????????????????????? 65 ? c to +150 ? c ambient temperature with power applied ????????????????????????????????????????????????? ? 55 ?? c to +125 ?? c supply voltage to ground potential ???????????????? ? 0.5 v to +7.0 v dc voltage applied to outputs in high z state ??????????????????????????????????????????????????? ? 0.5 v to +7.0 v dc input voltage [4] ???????????????????????????????????????????? ? 0.5 v to +7.0 v output current into outputs (low) .............................. 20 ma static discharge voltage........................................... >2001 v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ?? c 5 v ? 10% industrial ? 40 ? c to +85 ? c 5 v ? 10% electrical characteristics over the operating range parameter description test conditions 7c144-15 7c145-15 7c144-25 unit min max min max v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 ? 2.4 ? v v ol output low voltage v cc = min., i ol = 4.0 ma ? 0.4 ? 0.4 v v ih input high voltage 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 v i ix input leakage current gnd < v i < v cc ? 10 +10 ? 10 +10 ? a i oz output leakage current outputs disabled, gnd < v o < v cc ? 10 +10 ? 10 +10 ? a i cc operating current v cc = max., i out = 0 ma outputs disabled commercial ? 220 ? 180 ma industrial ??? 190 i sb1 standby current (both ports ttl levels) ce l and ce r > v ih , f = f max [5] commercial ? 60 ? 40 ma industrial ??? 50 i sb2 standby current (one port ttl level) ce l or ce r > v ih , f = f max [5] commercial ? 130 ? 110 ma industrial ??? 120 i sb3 standby current (both ports cmos levels) both ports ce and ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 [5] commercial ? 15 ? 15 ma industrial ??? 30 i sb4 standby current (one port cmos level) one port ce l or ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, active port outputs, f = f max [5] commercial ? 125 ? 100 ma industrial ??? 115 notes 3. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 4. pulse width < 20 ns. 5. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 8 of 23 electrical characteristics over the operating range (continued) parameter description test conditions 7c144-55 unit min max v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 ? v v ol output low voltage v cc = min., i ol = 4.0 ma ? 0.4 v v ih input high voltage 2.2 ? v v il input low voltage ? 0.8 v i ix input leakage vurrent gnd < v i < v cc ? 10 +10 ? a i oz output leakage current outputs disabled, gnd < v o < v cc ? 10 +10 ? a i cc operating current v cc = max., i out = 0 ma outputs disabled commercial ? 160 ma industrial ? 180 i sb1 standby current (both ports ttl levels) ce l and ce r > v ih , f = f max [6] commercial ? 30 ma industrial ? 40 i sb2 standby current (one port ttl level) ce l or ce r > v ih , f = f max [6] commercial ? 100 ma industrial ? 110 i sb3 standby current (both ports cmos levels) both ports ce and ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 [6] commercial ? 15 ma industrial ? 30 ? i sb4 standby current (one port cmos level) one port ce l or ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, active port outputs, f = f max [6] commercial ? 90 ma industrial ? 100 ? capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 10 pf c out output capacitance 15 pf figure 4. ac test loads and waveforms note 6. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 3.0 v gnd 90% 90% 10% ? 3ns ? 3 ns 10% all input pulses (a) normal load (load1) 5 v output c= 30 pf v th = 1.4 v output c = 30pf (b) th venin equivalent (load 1) (c) three-state delay (load 3) c = 30 pf output load (load 2) 5 v output c= 5pf r1 = 893 ? r2 = 347 ? r th = 250 ? r1 = 893 ? r = 347 ? [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 9 of 23 switching characteristics over the operating range [7] parameter description 7c144-15 7c145-15 7c144-25 7c144-55 unit min max min max min max read cycle t rc read cycle time 15 ? 25 ? 55 ? ns t aa address to data valid ? 15 ? 25 ? 55 ns t oha output hold from address change 3 ? 3 ? 3 ? ns t ace ce low to data valid ? 15 ? 25 ? 55 ns t doe oe low to data valid ? 10 ? 15 ? 25 ns t lzoe [8, 9,10] oe low to low z 3 ? 3 ? 3 ? ns t hzoe [8, 9,10] oe high to high z ? 10 ? 15 ? 25 ns t lzce [8, 9,10] ce low to low z 3 ? 3 ? 3 ? ns t hzce [8, 9,10] ce high to high z ? 10 ? 15 ? 25 ns t pu [10] ce low to power-up 0 ? 0 ? 0 ? ns t pd [10] ce high to power-down ? 15 ? 25 ? 55 ns write cycle t wc write cycle time 15 ? 25 ? 55 ? ns t sce ce low to write end 12 ? 20 ? 45 ? ns t aw address set-up to write end 12 ? 20 ? 45 ? ns t ha address hold from write end 2 ? 2 ? 2 ? ns t sa address set-up to write start 0 ? 0 ? 0 ? ns t pwe write pulse width 12 ? 20 ? 40 ? ns t sd data set-up to write end 10 ? 15 ? 25 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe [9,10] r/w low to high z ? 10 ? 15 ? 25 ns t lzwe [9,10] r/w high to low z 3 ? 3 ? 3 ? ns t wdd [11] write pulse to data delay ? 30 ? 50 ? 70 ns t ddd [11] write data valid to read data valid ? 25 ? 30 ? 40 ns notes 7. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 8. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 9. test conditions used are load 3. 10. this parameter is guaranteed but not tested. 11. for information on part-to-part delay through ram cells from writing port to reading port, refer to read timing with port-to -port delay waveform. [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 10 of 23 busy timing [12] t bla busy low from address match ? 15 ? 20 ? 30 ns t bha busy high from address mismatch ? 15 ? 20 ? 30 ns t blc busy low from ce low ? 15 ? 20 ? 30 ns t bhc busy high from ce high ? 15 ? 20 ? 30 ns t ps port set-up for priority 5 ? 5 ? 5 ? ns t wb r/w low after busy low 0 ? 0 ? 0 ? ns t wh r/w high after busy high 13 ? 20 ? 30 ? ns t bdd busy high to data valid ? 15 ? 25 ? 55 ns interrupt timing [12] t ins int set time ? 15 ? 25 ? 35 ns t inr int reset time ? 15 ? 25 ? 35 ns semaphore timing t sop sem flag update pulse (oe or sem )10 ? 10 ? 20 ? ns t swrd sem flag write to read time 5 ? 5 ? 5 ? ns t sps sem flag contention window 5 ? 5 ? 5 ? ns switching characteristics (continued) over the operating range [7] parameter description 7c144-15 7c145-15 7c144-25 7c144-55 unit min max min max min max note 12. test conditions used are load 2. [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 11 of 23 switching waveforms figure 5. read cycle no. 1 (either port address access) [13, 14] figure 6. read cycle no. 2 (either port ce /oe access) [13, 15, 16] figure 7. read timing with port-to-port delay (m/s =l) [17, 18] t rc t aa t oha data valid previous data valid data out address t ace t lzoe t doe t hzoe t hzce data valid data out sem or ce oe t lzce t pu i cc i sb t pd valid t ddd t wdd match match r/w r data in r data out l t wc address r t pwe valid t sd t hd address l notes 13. r/w is high for read cycle. 14. device is continuously selected ce = low and oe = low. this waveform cannot be used for semaphore reads. 15. address valid prior to or coincident with ce transition low. 16. ce l = l, sem = h when accessing ram. ce = h, sem = l when accessing semaphores. 17. busy = high for the writing port. 18. ce l = ce r = low. [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 12 of 23 figure 8. write cycle no. 1: oe three-state data i/os (either port) [19, 20, 21] figure 9. write cycle no. 2: r/w three-state data i/os (either port) [19, 21, 22] switching waveforms (continued) t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha t hzoe t lzoe sem or ce r/w address oe data out data in t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance sem or ce r/w address data out data in t lzwe data valid notes 19. the internal write time of the memory is defined by the overlap of ce or sem low and r/w low. both signals must be low to initiate a write, and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 20. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during a r/w controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified t pwe . 21. r/w must be high during all address transitions. 22. data i/o pins enter high impedance when oe is held low during write. [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 13 of 23 figure 10. semaphore read after write timing, either side [23] figure 11. semaphore contention [24, 25, 26] switching waveforms (continued) t sop t aa sem r/w oe i/o 0 valid address valid address t hd data in valid data out valid t oha a 0 ? a 2 t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle match t sps a 0l ? a 2l match r/w l sem l a 0r ? a 2r r/w r sem r notes 23. ce = high for the duration of the above timing (both write and read cycle). 24. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high 25. semaphores are reset (available to both ports) at cycle start. 26. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will con trol the semaphore. [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 14 of 23 figure 12. read with busy (m/s=high) [27] figure 13. write timing with busy input (m/s =low) note 27. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l t pwe r/w busy t wb t wh [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 15 of 23 figure 14. busy timing diagram no. 1 (ce arbitration) [28] figure 15. busy timing diagram no. 2 (address arbitration) [28] switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc address l,r busy r ce l ce r busy l ce r ce l address l,r ce l valid first: ce r valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r left address valid first: right address valid first: note 28. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 16 of 23 figure 16. interrupt timing diagrams switching waveforms (continued) write 1fff t wc t ha left side sets int r : address l r/w l ce l int r t ins [29] [30] right side clears int r : read 1fff t rc t inr write 1ffe t wc right side sets int l : left side clears int l : read 1ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r t ha t ins [30] [29] [30] [30] notes 29. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 30. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 17 of 23 figure 17. typical dc and ac characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 ? 55 25 125 1.2 1.0 120 80 0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambient temperature (c) output voltage (v) output source current vs. output voltage 0.0 0.8 0.8 0.6 0.6 normalized i cc , i sb v cc = 5.0 v v in = 5.0 v 0 i cc i cc 1.6 1.4 1.2 1.0 0.8 ? 55 125 normalized t aa normalized access time vs. ambient temperature ambient temperature (c) 1.4 1.3 1.2 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage t a = 25 c 0.6 0.8 1.25 1.0 0.75 10 normalized i cc 0.50 normalized i cc vs. cycle time cycle frequency (mhz) normalized t pc 25.0 30.0 20.0 10.0 5.0 0 200 400 600 800 delta t aa (ns) 0 15.0 supply voltage (v) typical power-on current vs. supply voltage capacitance (pf) typical access time change vs. output loading 1000 28 0.2 0.6 1.2 i sb3 normalized i cc , i sb 0.2 0.4 i sb3 25 1.1 5.0 v cc = 5.0 v t a = 25 c 40 160 200 5.0 40 66 1.00 0.25 0 1.0 2.0 3.0 5.0 0.0 4.0 0.50 0.75 v cc = 5.0 v v cc = 5.0 v t a = 25 c v cc = 4.5 v t a = 25 c v in = 5.0 v t a = 25 c v cc = 5.0 v [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 18 of 23 ordering information 8 k 8 dual-port sram speed (ns) ordering code package diagram package type operating range 15 cy7c144-15axc 51-85046 64-pin thin quad flat pack (pb-free) commercial cy7c144-15jxi 51-85005 68-pin plastic le aded chip carrier (pb-free) industrial cy7c144-15axi 51-85046 64-pin thin quad flat pack (pb-free) 25 cy7c144-25axc 51-85046 64-pin thin quad flat pack (pb-free) commercial 55 cy7c144-55axc 51-85046 64-pin thin quad flat pack (pb-free) commercial cy7c144-55jxc 51-85005 68-pin plastic leaded chip carrier (pb-free) 8 k 9 dual-port sram 15 CY7C145-15AXC 51-85065 80-pin thin quad flat pack (pb-free) commercial ordering code definitions temperature range: x = c or i c = commercial; i = industrial x: a= tqfp or j = plcc x: pb-free (rohs compliant) xx = speed = 15 or 25 or 55 ns 14x = 144 or 145 = part number identifier cy7c = cypress srams 14x cy7c - xx x x x [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 19 of 23 package diagrams figure 18. 64-pin thin plastic quad flat pack (14 x 14 x 1.4 mm), 51-85046 51-85046 *d [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 20 of 23 figure 19. 80-pin thin plastic quad flat pack, 51-85065 figure 20. 68-pin plastic leaded chip carrier, 51-85005 package diagrams (continued) 51-85065 *c 51-85005 *b [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 21 of 23 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor tqfp thin quad plastic flatpack i/o input/output sram static random access memory plcc plastic leaded chip carrier ttl transistion transistor logic symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes ? ohms mv milli volts mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback cy7c144 cy7c145 document #: 38-06034 rev. *h page 22 of 23 document history page document title: cy7c144, cy7c145 8k x 8/9 dual-port static ram with sem, int, busy document number: 38-06034 rev. ecn no. orig. of change submission date description of change ** 110175 szv 09/29/01 change from spec number: 38-00163 to 38-06034 *a 122285 rbi 12/27/02 power up requirements added to maximum ratings information *b 236752 ydt see ecn removed cross information from features section, added cy7c144-15ai to ordering information section *c 393320 yim see ecn added pb-free logo added pb-free parts to ordering information: cy7c144-15axc, cy7c144-15jxc, cy7c144-15axi, cy7c144-25axc, cy7c144-55axc, cy7c144-55jxc, CY7C145-15AXC, cy7c145-35jxc *d 2623658 vkn/pyrs 12/17/2008 added cy7c144-15j xi in the ordering information table *e 2699693 vkn/pyrs 04/29/2009 corrected defective logic block diagram, pinouts and package diagrams *f 2896210 rame 03/22/2010 updated ordering information updated package diagrams *g 3054633 admu 10/11/2010 updated ordering information and added ordering code definitions . *h 3099184 admu 12/02/2010 removed part s: cy7c144-55ac & cy7c144-55jc removed speed bin -35 updated as per new template added acronyms and units of measure table added ordering code definitions updated all footnotes as per new template [+] feedback document #: 38-06034 rev. *h revised december 2, 2010 page 23 of 23 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c144 cy7c145 ? cypress semiconductor corporation, 2009-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback |
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