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| document number: 319970-007 intel ? 4 series chipset family datasheet for the intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 graphics and memory controller hub (gmch) and the intel ? 82p45, 82p43 memory controller hub (mch) march 2010
2 datasheet information in this document is provided in connection with in tel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by th is document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or ot her intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical contro l or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no respon sibility whatsoever for conf licts or incompatibilities arising from future changes to them. the intel ? 4 series chipset family may contain design defects or errors known as errata, which may cause the product to deviate from publ ished specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. i 2 c is a two-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, in cluding philips electronics n.v. and north american philips corporation. intel? active management technology requires the platform to have an intel? amt-enabled chipset, network hardware and software, connection with a power source and a network connection. no computer system can provide absolute security under all cond itions. intel? trusted execution technology (intel? txt) is a se curity technology under development by intel and requires for operation a computer system with intel? virtualization technology, a intel? trusted execution technology- enabled intel processor, chipset, bios, authenticated code modules, and an intel or other intel? trusted execution technology c ompatible measured virtual machine monitor. in addition, intel? trusted execution technology requires the system to contain a tpmv1.2 as defined b y the trusted computing group and specific software for some uses. intel? virtualization technology requires a computer system with an enabled intel? processor, bios, virtual machine monitor (vm m) and, for some uses, certain computer system software enabled for it. functionality, performance or other benefits will vary depending on hard ware and software configurations and may require a bios update . software applications may not be compatible with all operating systems. please ch eck with your application vendor. intel, pentium, intel core, and the intel logo are trademar ks of intel corporation in the u.s. and other countries. *other names and brands may be claimed as the property of others. copyright ? 2010, intel corporation datasheet 3 contents 1introduction ............................................................................................................ 21 1.1 terminology ..................................................................................................... 27 1.2 (g)mch system overview .................................................................................. 30 1.2.1 host interface........................................................................................ 30 1.2.2 system memory interface ....................................................................... 31 1.2.3 direct media interface (dmi).................................................................... 31 1.2.4 multiplexed pci express* graphics interface and intel? sdvo/dvi/hdmi/dp interface ............................................................................................... 32 1.2.4.1 pci express* interface .............................................................. 32 1.2.4.2 sdvo multiplexed interface (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only)........................................................ 33 1.2.4.3 hdmi/dvi/dp multiplexed interface (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only)............................................. 33 1.2.5 graphics features (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) .................................................................................................... 33 1.2.6 (g)mch clocking .................................................................................... 33 1.2.7 power management ................................................................................ 34 1.2.8 thermal sensor ..................................................................................... 34 2 signal description ................................................................................................... 35 2.1 host interface signals........................................................................................ 36 2.2 system memory (ddr2/ddr3) interface signals ................................................... 39 2.2.1 system memory channel a interface signals.............................................. 39 2.2.2 system memory channel b interface signals.............................................. 40 2.2.3 system memory miscellaneous signals ...................................................... 41 2.3 pci express* interface signals ............................................................................ 41 2.4 controller link interface signals .......................................................................... 42 2.5 analog display signals ..... (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ............................................................................................................... 42 2.6 clocks, reset, and miscellaneous ......................................................................... 43 2.7 direct media interface........................................................................................ 44 2.8 serial dvo interface ............................................................................................. (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ......................... 45 2.9 hdmi interface (intel ? 82g45, 82g43, 82g41, 82b43 gmch only) ......................... 48 2.10 display port interface (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ......................... 49 2.11 intel ? high definition audio intel ? 82q45, 82q43, 82b43,82g45, 82g43, 82g41 gmch only) ............................................................................................................... 50 2.12 power and grounds ........................................................................................... 51 3 system address map ............................................................................................... 53 3.1 legacy address range ....................................................................................... 57 3.1.1 dos range (0h ? 9_ffffh) .... .......... ...................... ............ ......... ............ 57 3.1.2 legacy video area (a_0000h?b_ffffh)......... ........... ............ ......... ............ 57 3.1.3 expansion area (c_0000h-d_ffffh) ........... .......... ...................... ........ ...... 59 3.1.4 extended system bios area (e_0000h?e_f fffh) ............ .......... ........... ...... 59 3.1.5 system bios area (f_0000h?f_ffffh) ..................................................... 60 3.1.6 pam memory area details........................................................................ 60 3.2 main memory address range (1mb ? tolud)........................................................ 60 3.2.1 isa hole (15 mb ?16 mb) ........................................................................ 61 3.2.2 tseg .................................................................................................... 62 3.2.3 pre-allocated memory ............................................................................. 62 4 datasheet 3.3 pci memory address range (tolud ? 4 gb) .........................................................63 3.3.1 apic configuration space (fec0_0000h?fec f_ffffh) .................................65 3.3.2 hseg (feda_0000h?fedb_ffffh) . ........... ............ ........... .......... ...............65 3.3.3 fsb interrupt memory space (fee0_0000?feef_ffff) ................................65 3.3.4 high bios area ......................................................................................65 3.4 main memory address space (4 gb to touud) ......................................................66 3.4.1 memory re-claim background ..................................................................67 3.4.2 memory reclaiming.................................................................................67 3.5 pci express* configuration address space ............................................................67 3.6 pci express* address space ...............................................................................68 3.7 graphics memory address ranges (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ......................................................................................................69 3.8 system management mode (smm) .......................................................................69 3.8.1 smm space definition..............................................................................69 3.8.2 smm space restrictions ...........................................................................70 3.8.3 smm space combinations ........................................................................70 3.8.4 smm control combinations.......................................................................70 3.8.5 smm space decode and transaction handling.............................................71 3.8.6 processor wb transaction to an enabled smm address space .......................71 3.8.7 smm access through gtt tlb (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only).................................................................................71 3.9 memory shadowing............................................................................................72 3.10 i/o address space .............................................................................................72 3.10.1 pci express* i/o address mapping............................................................73 3.11 (g)mch decode rules and cross-bridge address mapping .......................................73 3.11.1 legacy vga and i/o range decode rules ..................................................73 4 register description ................................................................................................75 4.1 register terminology .........................................................................................76 4.2 configuration process and registers .....................................................................77 4.2.1 platform configuration structure............. ..................................................77 4.3 configuration mechanisms ........................... .......................................................78 4.3.1 standard pci configuration mechanism......................................................78 4.3.2 pci express* enhanced configuration mechanism .......................................78 4.4 routing configuration accesses ...........................................................................80 4.4.1 internal device configuration accesses ......................................................81 4.4.2 bridge related configuration accesses.......................................................81 4.4.2.1 pci express* configuration accesses ...........................................81 4.4.2.2 dmi configuration accesses ........................................................82 4.5 i/o mapped registers.........................................................................................82 4.5.1 config_address?configuration address register ....................................82 4.5.2 config_data?configuration data register ..............................................84 5 dram controller registers (d0:f0) ..........................................................................85 5.1 dram controller registers (d0:f0) ......................................................................85 5.1.1 vid?vendor identification .......................................................................87 5.1.2 did?device identification .......................................................................87 5.1.3 pcicmd?pci command ..........................................................................88 5.1.4 pcists?pci status ................................................................................89 5.1.5 rid?revision identification ................... ..................................................90 5.1.6 cc?class code ......................................................................................91 5.1.7 mlt?master latency timer......................................................................91 5.1.8 hdr?header type .................................................................................92 5.1.9 svid?subsystem vendor identification .....................................................92 5.1.10 sid?subsystem identification..................................................................92 5.1.11 capptr?capabilities pointer ... ............ ...................... ............ ........... ........93 datasheet 5 5.1.12 pxpepbar?pci express egress port base address...................................... 93 5.1.13 mchbar?(g)mch memory mapped register range base ............................ 94 5.1.14 ggc?gmch graphics control register (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ..................................................................... 95 5.1.15 deven?device enable............................................................................ 97 5.1.16 pciexbar?pci express register range base address................................. 99 5.1.17 dmibar?root complex register range base address............................... 101 5.1.18 pam0?programmable attribute map 0 .................................................... 102 5.1.19 pam1?programmable attribute map 1 .................................................... 103 5.1.20 pam2?programmable attribute map 2 .................................................... 104 5.1.21 pam3?programmable attribute map 3 .................................................... 105 5.1.22 pam4?programmable attribute map 4 .................................................... 106 5.1.23 pam5?programmable attribute map 5 .................................................... 107 5.1.24 pam6?programmable attribute map 6 .................................................... 108 5.1.25 lac?legacy access control .................................................................. 109 5.1.26 remapbase?remap base address register ............................................ 111 5.1.27 remaplimit?remap limit address register............................................ 111 5.1.28 smram?system management ram control ............................................. 112 5.1.29 esmramc?extended system management ram control............................ 113 5.1.30 tom?top of memory............................................................................ 114 5.1.31 touud?top of upper usable dram ....................................................... 115 5.1.32 gbsm?graphics base of stolen memory (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ................................................................... 116 5.1.33 bgsm?base of gtt stolen memory (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ................................................................... 116 5.1.34 tsegmb?tseg memory base ................................................................ 117 5.1.35 tolud?top of low usable dram........................................................... 117 5.1.36 errsts?error status ........................................................................... 118 5.1.37 errcmd?error command..................................................................... 120 5.1.38 smicmd?smi command....................................................................... 121 5.1.39 skpd?scratchpad data ........................................................................ 122 5.1.40 capid0?capability identifier .. .......... ...................... ............ ......... .......... 122 5.2 mchbar ........................................................................................................ 123 5.2.1 chdecmisc?channel decode miscellaneous ........................................... 125 5.2.2 c0drb0?channel 0 dram rank boundary address 0 ............................... 126 5.2.3 c0drb1?channel 0 dram rank boundary address 1 ............................... 128 5.2.4 c0drb2?channel 0 dram rank boundary address 2 ............................... 128 5.2.5 c0drb3?channel 0 dram rank boundary address 3 ............................... 129 5.2.6 c0dra01?channel 0 dram rank 0,1 attribute ........................................ 130 5.2.7 c0dra23?channel 0 dram rank 2,3 attribute ........................................ 131 5.2.8 c0cyctrkpchg?channel 0 cyctrk pchg ............................................. 131 5.2.9 c0cyctrkact?channel 0 cyctrk act .................................................. 132 5.2.10 c0cyctrkwr?channel 0 cyctrk wr.................................................... 133 5.2.11 c0cyctrkrd?channel 0 cyctrk read ................................................. 134 5.2.12 c0cyctrkrefr?channel 0 cyctrk refr............................................... 135 5.2.13 c0ckectrl?channel 0 cke control ....................................................... 135 5.2.14 c0refrctrl?channel 0 dram refresh control ....................................... 137 5.2.15 c0odtctrl?channel 0 odt control ...................................................... 139 5.2.16 c1drb1?channel 1 dram rank boundary address 1 ............................... 139 5.2.17 c1drb2?channel 1 dram rank boundary address 2 ............................... 140 5.2.18 c1drb3?channel 1 dram rank boundary address 3 ............................... 140 5.2.19 c1dra01?channel 1 dram rank 0,1 attributes....................................... 141 5.2.20 c1dra23?channel 1 dram rank 2,3 attributes....................................... 141 5.2.21 c1cyctrkpchg?channel 1 cyctrk pchg ............................................. 142 5.2.22 c1cyctrkact?channel 1 cyctrk act .................................................. 143 6 datasheet 5.2.23 c1cyctrkwr?channel 1 cyctrk wr .................................................... 144 5.2.24 c1cyctrkrd?channel 1 cyctrk read .................................................. 145 5.2.25 c1ckectrl?channel 1 cke control ....................................................... 145 5.2.26 c1refrctrl?channel 1 dram refresh control........................................ 147 5.2.27 c1odtctrl?channel 1 odt control....................................................... 149 5.2.28 epc0drb0?ep channel 0 dram rank boundary address 0 ........................ 149 5.2.29 epc0drb1?ep channel 0 dram rank boundary address 1 ........................ 150 5.2.30 epc0drb2?ep channel 0 dram rank boundary address 2 ........................ 150 5.2.31 epc0drb3?ep channel 0 dram rank boundary address 3 ........................ 150 5.2.32 epc0dra01?ep channel 0 dram rank 0,1 attribute................................. 151 5.2.33 epc0dra23?ep channel 0 dram rank 2,3 attribute................................. 151 5.2.34 epdcyctrkwrtpre?epd cyctrk wrt pre............................................ 152 5.2.35 epdcyctrkwrtact?epd cyctrk wrt act ........................................... 152 5.2.36 epdcyctrkwrtwr?epd cyctrk wrt wr ............................................. 153 5.2.37 epdcyctrkwrtref?epd cyctrk wrt ref ............................................ 153 5.2.38 epdcyctrkwrtrd?epd cyctrk wrt read........................................... 154 5.2.39 epdckeconfigreg?epd cke related conf iguration registers................... 155 5.2.40 epdrefconfig?ep dram refresh configurat ion...................................... 156 5.2.41 tsc1?thermal sensor control 1 ............................................................ 158 5.2.42 tsc2?thermal sensor control 2 ............................................................ 159 5.2.43 tss?thermal sensor status .................................................................. 161 5.2.44 tsttp?thermal sensor temperature trip point........................................ 162 5.2.45 tco?thermal calibration offset ............................................................. 163 5.2.46 therm1?hardware throttle control ....................................................... 164 5.2.47 tis?thermal interrupt status................................................................ 165 5.2.48 tsmicmd?thermal smi command ......................................................... 167 5.2.49 pmsts?power management status......................................................... 168 5.3 epbar............................................................................................................ 169 5.3.1 epesd?ep element self description........................................................ 169 5.3.2 eple1d?ep link entry 1 description ....................................................... 170 5.3.3 eple1a?ep link entry 1 address............................................................ 170 5.3.4 eple2d?ep link entry 2 description ....................................................... 171 5.3.5 eple2a?ep link entry 2 address............................................................ 172 6 host-pci express* registers (d1:f0) ..................................................................... 173 6.1 host-pci express* register description (d1:f0) .................................................. 175 6.1.1 vid1?vendor identification ................................................................... 175 6.1.2 did1?device identification.................................................................... 175 6.1.3 pcicmd1?pci command ...................................................................... 176 6.1.4 pcists1?pci status............................................................................. 178 6.1.5 rid1?revision identification ................................................................. 179 6.1.6 cc1?class code .................................................................................. 180 6.1.7 cl1?cache line size ............................................................................ 180 6.1.8 hdr1?header type.............................................................................. 181 6.1.9 pbusn1?primary bus number ............................................................... 181 6.1.10 sbusn1?secondary bus number ........................................................... 181 6.1.11 subusn1?subordinate bus number ....................................................... 182 6.1.12 iobase1?i/o base address .................................................................. 182 6.1.13 iolimit1?i/o limit address .................................................................. 183 6.1.14 ssts1?secondary status...................................................................... 183 6.1.15 mbase1?memory base address ............................................................. 184 6.1.16 mlimit1?memory limit address ............................................................ 185 6.1.17 pmbase1?prefetchable memory base address ......................................... 186 6.1.18 pmlimit1?prefetchable memory limit address......................................... 187 6.1.19 pmbaseu1?prefetchable memory base address upper .............................. 188 datasheet 7 6.1.20 pmlimitu1?prefetchable memory limit address upper ............................. 189 6.1.21 capptr1?capabilities pointer. .......... ...................... ............ ......... .......... 189 6.1.22 intrline1?interrupt line .................................................................... 190 6.1.23 intrpin1?interrupt pin........................................................................ 190 6.1.24 bctrl1?bridge control ........................................................................ 191 6.1.25 pm_capid1?power management capabilities . ................ .......... ........... .... 193 6.1.26 pm_cs1?power management control/status ........................................... 194 6.1.27 ss_capid?subsystem id and vendor id capabilities ..... ................ .......... 195 6.1.28 ss?subsystem id and subsystem vendor id .......................................... 196 6.1.29 msi_capid?message signaled interrupts capability id .......... ............ ...... 196 6.1.30 mc?message control............................................................................ 197 6.1.31 ma?message address........................................................................... 198 6.1.32 md?message data ............................................................................... 198 6.1.33 peg_capl?pci express-g capability list .... .......... ...................... ............ 198 6.1.34 peg_cap?pci express-g capa bilities ......... .......... ...................... ............ 199 6.1.35 dcap?device capabilit ies ............. ............ .......... ...................... ............ 199 6.1.36 dctl?device control ........................................................................... 200 6.1.37 dsts?device status ............................................................................ 201 6.1.38 lcap?link capabilities ......................................................................... 202 6.1.39 lctl?link control ............................................................................... 204 6.1.40 lsts?link status ................................................................................ 206 6.1.41 slotcap?slot capabilities... ............ ...................... ............ ......... .......... 208 6.1.42 slotctl?slot control .......................................................................... 209 6.1.43 slotsts?slot status........................................................................... 210 6.1.44 rctl?root control .............................................................................. 211 6.1.45 rsts?root status ............................................................................... 212 6.1.46 dcap2?device capab ilities 2................... ............ ...................... ............ 212 6.1.47 dctl2?device control 2....................................................................... 212 6.1.48 dsts2?device status 2 ....................................................................... 213 6.1.49 lcap2?link capabilit ies 2........... ................ ........... ............ ......... .......... 213 6.1.50 lctl2?link control 2 ........................................................................... 214 6.1.51 lsts2?link status 2............................................................................ 216 6.1.52 scap2?slot capabilities 2... ........................ ........... ............ ......... .......... 217 6.1.53 sctl2?slot control 2........................................................................... 217 6.1.54 ssts2?slot status 2............................................................................ 217 6.1.55 peglc?pci express-g legacy control .................................................... 218 7 direct memory interface registers (dmibar) ....................................................... 219 7.1 dmivcech?dmi virtual channel enhanced capab ility ............. ............ ........... ...... 220 7.2 dmipvccap1?dmi port vc capability register 1 . .......... ........... .......... ........... ...... 220 7.3 dmipvccap2?dmi port vc capability register 2 . .......... ........... .......... ........... ...... 221 7.4 dmipvcctl?dmi port vc control...................................................................... 221 7.5 dmivc0rcap?dmi vc0 resource ca pability ......... ............ ...................... ............ 222 7.6 dmivc0rctl0?dmi vc0 resource control ......................................................... 222 7.7 dmivc0rsts?dmi vc0 resource status............................................................ 223 7.8 dmivc1rcap?dmi vc1 resource ca pability ......... ............ ...................... ............ 224 7.9 dmivc1rctl1?dmi vc1 resource control ......................................................... 224 7.10 dmivc1rsts?dmi vc1 resource status............................................................ 226 7.11 dmilcap?dmi link capabilities ... ............ ........... ............ ...................... ............ 227 7.12 dmilctl?dmi link control .............................................................................. 228 7.13 dmilsts?dmi link status ............................................................................... 228 8 host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 229 8.1 vid1?vendor identification.............................................................................. 231 8.2 did1?device identification .............................................................................. 232 8.3 pcicmd1?pci command ................................................................................. 232 8 datasheet 8.4 pcists1?pci status........................................................................................ 234 8.5 rid1?revision identification ............................................................................ 235 8.6 cc1?class code ............................................................................................. 235 8.7 cl1?cache line size ....................................................................................... 236 8.8 hdr1?header type......................................................................................... 236 8.9 pbusn1?primary bus number .......................................................................... 236 8.10 sbusn1?secondary bus number ...................................................................... 237 8.11 subusn1?subordinate bus number .................................................................. 237 8.12 iobase1?i/o base address ............................................................................. 238 8.13 iolimit1?i/o limit address ........................ ..................................................... 238 8.14 ssts1?secondary status................................................................................. 239 8.15 mbase1?memory base address ........................................................................ 240 8.16 mlimit1?memory limit address ....................................................................... 241 8.17 pmbase1?prefetchable memory base address upper ........................................... 242 8.18 pmlimit1?prefetchable memory limit address.................................................... 243 8.19 pmbaseu1?prefetchable memory base address upper ......................................... 244 8.20 pmlimitu1?prefetchable memory limit address upper ........................................ 245 8.21 capptr1?capabilities pointer ........ ............ ........... ............ ........... ........ ............. 246 8.22 intrline1?interrupt line ................................................................................ 246 8.23 intrpin1?interrupt pin ................................................................................... 246 8.24 bctrl1?bridge control ................................................................................... 247 8.25 pm_capid1?power management capabilities ........ ............ ........... .......... ............. 248 8.26 pm_cs1?power management control/status ...................................................... 249 8.27 ss_capid?subsystem id and vendor id capabilit ies ..................... ........ ............. 250 8.28 ss?subsystem id and subsystem vendor id...................................................... 250 8.29 msi_capid?message signaled interrupts capab ility id ........... ............ ........... ...... 251 8.30 mc?message control ....................................................................................... 251 8.31 ma?message address ...................................................................................... 252 8.32 md?message data .......................................................................................... 252 8.33 pe_capl?pci express* capability list ...... ........... ............ ........... .......... ............. 252 8.34 pe_cap?pci express* capabilitie s ............. ........... ............ ........... ........ ............. 253 8.35 dcap?device capabilities . ................ ............ ...................... ............ ........... ...... 253 8.36 dctl?device control....................................................................................... 254 8.37 dsts?device status ....................................................................................... 255 8.38 lcap?link capabilities... .......... ........... .......... ...................... ............ ........... ...... 256 8.39 lctl?link control........................................................................................... 257 8.40 lsts?link status............................................................................................ 259 8.41 slotcap?slot capabilities ....... ........... .......... ...................... ............ ........... ...... 261 8.42 slotctl?slot control ..................................................................................... 262 8.43 slotsts?slot status ...................................................................................... 264 8.44 rctl?root control.......................................................................................... 265 8.45 rsts?root status .......................................................................................... 266 8.46 pelc?pci express legacy control ..................................................................... 266 8.47 vcech?virtual channel enhanced capability head er.......... ........... .......... ............. 267 8.48 pvccap1?port vc capability register 1 .......... ...................... ............ ........... ...... 267 8.49 pvccap2?port vc capability register 2 .......... ...................... ............ ........... ...... 268 8.50 pvcctl?port vc control .................................................................................. 268 8 .51 vc0rcap?vc0 resource capability . ............ .............. ........... ............ ........... ...... 269 8.52 vc0rctl?vc0 resource control ....................................................................... 270 8.53 vc0rsts?vc0 resource status ........................................................................ 271 8.54 rcldech?root complex link de claration enhanced ............................................ 271 8.55 esd?element self description .......................................................................... 272 8.56 le1d?link entry 1 description.......................................................................... 272 8.57 le1a?link entry 1 address .............................................................................. 273 datasheet 9 9 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) .................................................................................... 275 9.1 integrated graphics registers (d2:f0) ............................................................... 275 9.1.1 vid2?vendor identification................................................................... 277 9.1.2 did2?device identification ................................................................... 277 9.1.3 pcicmd2?pci command ...................................................................... 278 9.1.4 pcists2?pci status ............................................................................ 279 9.1.5 rid2?revision identification ................. ................................................ 280 9.1.6 cc?class code.................................................................................... 280 9.1.7 cls?cache line size............................................................................ 281 9.1.8 mlt2?master latency timer ................................................................. 281 9.1.9 hdr2?header type ............................................................................. 281 9.1.10 gttmmadr?graphics translation table, memory mapped range address ... 282 9.1.11 gmadr?graphics memory range address............................................... 283 9.1.12 iobar?i/o base address ..................................................................... 284 9.1.13 svid2?subsystem vendor identification................................................. 284 9.1.14 sid2?subsystem identification ............................................................. 285 9.1.15 romadr?video bios rom base address................................................ 285 9.1.16 cappoint?capabilities pointe r ............ ............ ........... .......... ........... ...... 285 9.1.17 intrline?interrupt line ...................... ................................................ 286 9.1.18 intrpin?interrupt pin ......................................................................... 286 9.1.19 mingnt?minimum grant...................................................................... 286 9.1.20 maxlat?maximum latency .................................................................. 287 9.1.21 capid0?capability identifier .. .......... ...................... ............ ......... .......... 287 9.1.22 mggc?gmch graphics control register ................................................. 288 9.1.23 deven?device enable.......................................................................... 290 9.1.24 ssrw?software scratch read write ...................................................... 292 9.1.25 bsm?base of stolen memory ................................................................ 292 9.1.26 hsrw?hardware scratch read write ......... ............................................ 292 9.1.27 mc?message control............................................................................ 293 9.1.28 ma?message address........................................................................... 293 9.1.29 md?message data ............................................................................... 294 9.1.30 gdrst?graphics debug reset .............................................................. 294 9.1.31 pmcapid?power management capabilities id ........... ............ ......... .......... 295 9.1.32 pmcap?power management capabilities ..... .......... ...................... ............ 295 9.1.33 pmcs?power management control/status............................................... 296 9.1.34 swsmi?software smi .......................................................................... 296 9.2 integrated graphics registers (d2:f1) ............................................................... 297 9.2.1 vid2?vendor identification................................................................... 298 9.2.2 did2?device identification ................................................................... 298 9.2.3 pcicmd2?pci command ...................................................................... 299 9.2.4 pcists2?pci status ............................................................................ 300 9.2.5 rid2?revision identification ................. ................................................ 301 9.2.6 cc?class code register ....................................................................... 301 9.2.7 cls?cache line size............................................................................ 302 9.2.8 mlt2?master latency timer ................................................................. 302 9.2.9 hdr2?header type ............................................................................. 302 9.2.10 mmadr?memory mapped range address................................................ 303 9.2.11 svid2?subsystem vendor identification................................................. 303 9.2.12 sid2?subsystem identification ............................................................. 304 9.2.13 romadr?video bios rom base address................................................ 304 9.2.14 cappoint?capabilities pointe r ............ ............ ........... .......... ........... ...... 304 9.2.15 mingnt?minimum grant...................................................................... 305 9.2.16 maxlat?maximum latency .................................................................. 305 9.2.17 capid0?mirror of dev0 capability identifi er .......... ...................... ............ 305 10 datasheet 9.2.18 mggc?mirror of device 0 gmch graphics control register ........................ 306 9.2.19 deven?device enable .......................................................................... 308 9.2.20 ssrw?mirror of function 0 software scratch read write........................... 309 9.2.21 bsm?mirror of function 0 base of stolen memory..................................... 310 9.2.22 hsrw?mirror of device 2 function 0 hardware scratch read write ............ 310 9.2.23 gdrst?mirror of device 2 function 0 graphics reset ............................... 311 9.2.24 pmcapid?mirror of fun 0 power manageme nt capabilities id.... ........... ...... 312 9.2.25 pmcap?mirror of fun 0 power management capabilities ............................ 312 9.2.26 pmcs?power management control/status ............................................... 313 9.2.27 swsmi?mirror of func0 software smi .................................................... 313 10 intel ? manageability engine subsystem registers ................................................. 315 10.1 heci function in me subsystem registers ....... .................................................... 315 10.1.1 id? identifiers..................................................................................... 316 10.1.2 cmd? command.................................................................................. 316 10.1.3 sts? device status.............................................................................. 317 10.1.4 rid? revision id ................................................................................. 318 10.1.5 cc? class code ................................................................................... 318 10.1.6 cls? cache line size ........................................................................... 319 10.1.7 mlt? master latency timer................................................................... 319 10.1.8 htype? header type............................................................................ 319 10.1.9 bist? built in self test ........................................................................ 320 10.1.10heci_mbar? heci mmio base address .................................................. 320 10.1.11ss? sub system identifiers................................................................... 321 10.1.12cap? capabilities pointer ... ............ ........... ............ ........... ........ ............. 321 10.1.13intr? interrupt information ................................................................. 322 10.1.14mgnt? minimum grant ........................................................................ 322 10.1.15mlat? maximum latency...................................................................... 322 10.1.16hfs? host firmware status................................................................... 323 10.1.17pid? pci power management capability id .. ................ .......... ........... ...... 323 10.1.18pc? pci power management capabilities ..... ............ ........... ........ ............. 324 10.1.19pmcs? pci power management control and status .................................. 325 10.1.20mid? message signaled interrupt identifiers ........................................... 326 10.1.21mc? message signaled interrupt message control .................................... 326 10.1.22ma? message signaled interrupt message address ................................... 326 10.1.23mua? message signaled interrupt upper address (optional)...................... 327 10.1.24md? message signaled interrupt message data ....................................... 327 10.2 second heci function in me subsystem registers................................................ 328 10.2.1 id? identifiers..................................................................................... 329 10.2.2 cmd? command.................................................................................. 329 10.2.3 sts? device status.............................................................................. 330 10.2.4 rid?revision id .................................................................................. 331 10.2.5 cc? class code ................................................................................... 331 10.2.6 cls? cache line size ........................................................................... 332 10.2.7 mlt? master latency timer................................................................... 332 10.2.8 htype? header type............................................................................ 332 10.2.9 heci_mbar? heci mmio base address .................................................. 333 10.2.10ss? sub system identifiers................................................................... 333 10.2.11cap? capabilities pointer ... ............ ........... ............ ........... ........ ............. 334 10.2.12intr? interrupt information ................................................................. 334 10.2.13mgnt? minimum grant ........................................................................ 334 10.2.14mlat? maximum latency...................................................................... 335 10.2.15hfs? host firmware status................................................................... 335 10.2.16pid? pci power management capability id .. ................ .......... ........... ...... 335 10.2.17pc? pci power management capabilities ..... ............ ........... ........ ............. 336 datasheet 11 10.2.18pmcs? pci power management control and status .................................. 337 10.2.19mid? message signaled interrupt identifi ers ........................................... 338 10.2.20mc? message signaled interrupt message control.................................... 338 10.2.21ma? message signaled interrupt message address................................... 338 10.2.22mua? message signaled interrupt upper address (optional) ..................... 339 10.2.23md? message signaled interrupt message data ....................................... 339 10.2.24hidm?heci interrupt delivery mode ...................................................... 339 10.3 heci pci mmio space registers ........................................................................ 340 10.3.1 h_cb_ww? host circular buffer write wi ndow........................................ 340 10.3.2 h_csr? host control status ................... .............................................. 341 10.3.3 me_cb_rw? me circular buffer read wind ow ......................................... 342 10.3.4 me_csr_ha? me control status host access .......................................... 343 10.4 second heci function mmio space registers ...... ................................................ 344 10.4.1 h_cb_ww? host circular buffer write wi ndow........................................ 344 10.4.2 h_csr? host control status ................... .............................................. 345 10.4.3 me_cb_rw? me circular buffer read wind ow ......................................... 346 10.4.4 me_csr_ha? me control status host access .......................................... 347 10.5 ide function for remote boot and installations pt ider registers ......................... 348 10.5.1 id?identification ................................................................................. 349 10.5.2 cmd?command register ...................................................................... 349 10.5.3 sts?device status .............................................................................. 350 10.5.4 rid?revision id.................................................................................. 351 10.5.5 cc?class codes .................................................................................. 351 10.5.6 cls?cache line size............................................................................ 351 10.5.7 mlt?master latency timer ................................................................... 352 10.5.8 pcmdba?primary command block io bar ..... .......................................... 352 10.5.9 pctlba?primary control block base address .......................................... 353 10.5.10 scmdba?secondary command block base address ................................. 353 10.5.11sctlba?secondary control block base address....................................... 354 10.5.12lbar?legacy bus master base address .................................................. 354 10.5.13ss?sub system identifiers ................................................................... 355 10.5.14erom?expansion rom base address...................................................... 355 10.5.15cap?capabilities poin ter............. ................ ........... ............ ......... .......... 355 10.5.16intr?interrupt information .................................................................. 356 10.5.17mgnt?minimum grant ......................................................................... 356 10.5.18mlat?maximum latency ...................................................................... 356 10.5.19pid?pci power management capability id .. .......... ...................... ............ 357 10.5.20pc?pci power management capabilities ..... .......... ...................... ............ 357 10.5.21pmcs?pci power management control and status ................................... 358 10.5.22mid?message signaled interrupt capabilit y id ......... ............ ......... .......... 359 10.5.23mc?message signaled interrupt message control..................................... 359 10.5.24ma?message signaled interrupt message address.................................... 360 10.5.25mau?message signaled interrupt message upper address ........................ 360 10.5.26md?message signaled interrupt message data ........................................ 360 10.6 ide bar0 ....................................................................................................... 361 10.6.1 idedata?ide data register ................................................................. 362 10.6.2 ideerd1?ide error register device 1 .................................................... 362 10.6.3 ideerd0?ide error register dev0 ........................................................ 363 10.6.4 idefr?ide features register ................................................................ 363 10.6.5 idescir?ide sector count in register...... ............................................. 364 10.6.6 idescor1?ide sector count out register dev1...................................... 364 10.6.7 idescor0?ide sector count out register device 0 ................................. 365 10.6.8 idesnor0?ide sector number out register device 0 .............................. 365 10.6.9 idesnor1?ide sector number out register device 1 .............................. 366 10.6.10idesnir?ide sector number in register................................................ 366 12 datasheet 10.6.11ideclir?ide cylinder low in register.................................................... 367 10.6.12idclor1?ide cylinder low out register device 1.................................... 367 10.6.13idclor0?ide cylinder low out register device 0.................................... 368 10.6.14idchor0?ide cylinder high out register device 0 .................................. 368 10.6.15idchor1?ide cylinder high out register device 1 .................................. 369 10.6.16idechir?ide cylinder high in register .................................................. 369 10.6.17idedhir?ide drive/head in register ..................................................... 370 10.6.18iddhor1?ide drive head out register device 1 ..................................... 370 10.6.19iddhor0?ide drive head out register device 0 ..................................... 371 10.6.20idesd0r?ide status device 0 register .................................................. 372 10.6.21idesd1r?ide status device 1 register .................................................. 373 10.6.22idecr?ide command register .............................................................. 374 10.7 ide bar1 ....................................................................................................... 375 10.7.1 iddcr?ide device control register ....................................................... 375 10.7.2 idasr?ide alternate status register...................................................... 376 10.8 ide bar4 ....................................................................................................... 377 10.8.1 idepbmcr?ide primary bus master command register ............................ 378 10.8.2 idepbmds0r?ide primary bus master device specific 0 register ............... 378 10.8.3 idepbmsr?ide primary bus master status register ................................. 379 10.8.4 idepbmds1r?ide primary bus master device specific 1 register ............... 380 10.8.5 idepbmdtpr0?ide primary bus master descriptor table pointer register byte 0 .......................................................................... 380 10.8.6 idepbmdtpr1?ide primary bus master descriptor table pointer register byte 1 .......................................................................... 380 10.8.7 idepbmdtpr2?ide primary bus master descriptor table pointer register byte 2 .......................................................................... 381 10.8.8 idepbmdtpr3?ide primary bus master descriptor table pointer register byte 3 .......................................................................... 381 10.8.9 idesbmcr?ide secondary bus master co mmand register ........................ 382 10.8.10idesbmds0r?ide secondary bus master device specific 0 register ........... 382 10.8.11idesbmsr?ide secondary bus master status register ............................. 383 10.8.12idesbmds1r?ide secondary bus master device specific 1 register ........... 383 10.8.13idesbmdtpr0?ide secondary bus master descriptor table pointer register byte 0 ........................................................................................................ 384 10.8.14idesbmdtpr1?ide secondary bus master descriptor table pointer register byte 1 ........................................................................................................ 384 10.8.15idesbmdtpr2?ide secondary bus master descriptor table pointer register byte 2 ........................................................................................................ 384 10.8.16idesbmdtpr3?ide secondary bus master descriptor table pointer register byte 3 ........................................................................................................ 385 10.9 serial port for remote keyboard and text (kt) redirection ................................... 386 10.9.1 id?identification.................................................................................. 387 10.9.2 cmd?command register ...................................................................... 387 10.9.3 sts?device status............................................................................... 388 10.9.4 rid?revision id .................................................................................. 389 10.9.5 cc?class codes................................................................................... 389 10.9.6 cls?cache line size ............................................................................ 389 10.9.7 mlt?master latency timer.................................................................... 390 10.9.8 htype?header type............................................................................. 390 10.9.9 bist?built in self test ......................................................................... 390 10.9.10ktiba?kt io block base address........................................................... 391 10.9.11ktmba?kt memory block base address .................................................. 391 10.9.12rsvd?reserved .................................................................................. 392 10.9.13rsvd?reserved .................................................................................. 392 10.9.14rsvd?reserved .................................................................................. 392 datasheet 13 10.9.15rsvd?reserved .................................................................................. 392 10.9.16ss?sub system identifiers ................................................................... 393 10.9.17erom?expansion rom base address...................................................... 393 10.9.18cap?capabilities poin ter............. ................ ........... ............ ......... .......... 393 10.9.19intr?interrupt information .................................................................. 394 10.9.20mgnt?minimum grant ......................................................................... 394 10.9.21mlat?maximum latency ...................................................................... 394 10.9.22pid?pci power management capability id .. .......... ...................... ............ 395 10.9.23pc?pci power management capabilities ..... .......... ...................... ............ 395 10.9.24pmcs?pci power management control and status ................................... 396 10.9.25mid?message signaled interrupt capabilit y id ......... ............ ......... .......... 397 10.9.26mc?message signaled interrupt message control..................................... 397 10.9.27ma?message signaled interrupt message address.................................... 398 10.9.28mau?message signaled interrupt message upper address ........................ 398 10.9.29md?message signaled interrupt message data ........................................ 398 10.10 kt io/ memory mapped device registers............................................................ 399 10.10.1ktrxbr?kt receive buffer register ....................................................... 399 10.10.2ktthr?kt transmit holding register ..................................................... 400 10.10.3ktdllr?kt divisor latch lsb register ................................................... 400 10.10.4ktier?kt interrupt enable register....................................................... 401 10.10.5ktdlmr?kt divisor latch msb register ................................................. 401 10.10.6ktiir?kt interrupt identification register .............................................. 402 10.10.7ktfcr?kt fifo control register ........................................................... 403 10.10.8ktlcr?kt line control register ............................................................ 404 10.10.9ktmcr?kt modem control register ....................................................... 405 10.10.10ktlsr?kt line status register ............................................................ 406 10.10.11ktmsr?kt modem status register....................................................... 407 10.10.12ktscr?kt scratch register................................................................. 407 11 intel ? trusted execution te chnology registers (intel ? 82q45 and 82q43 gmch only) .................................................................. 409 11.1 intel trusted execution technology specific re gisters .......................................... 409 11.1.1 txt.sts?txt status register ............................................................... 411 11.1.2 txt.ests?txt error status register ...................................................... 412 11.1.3 txt.thread.exists?txt thread exists register..................................... 413 11.1.4 txt.threads.join?txt threads join register ....................................... 414 11.1.5 txt.errorcode (aka txt.crash)?txt error code register ................... 415 11.1.6 txt.cmd.reset?txt system reset command........................................ 415 11.1.7 txt.cmd.close-private?txt close private command ........................... 415 11.1.8 txt.did?txt device id register ........................................................... 416 11.1.9 txt.cmd.flush-wb?txt flush write buffer command ............................ 416 11.1.10txt.sinit.memory.base?txt sinit code base register ......................... 416 11.1.11txt.sinit.memory.size?txt sinit memory size register ...................... 417 11.1.12txt.mle.join?txt mle join base register ............................................. 417 11.1.13txt.heap.base?txt heap base register ............................................... 418 11.1.14txt.heap.size?txt heap size register ................................................. 418 11.1.15txt.mseg.base?txt mseg base register.............................................. 418 11.1.16txt.mseg.size?txt mseg size address register ................................... 419 11.1.17txt.scratchpad.0?txt scratch pad 0 register ..................................... 419 11.1.18txt.scratchpad.1?txt scratch pad 1 register ..................................... 419 11.1.19txt.dpr?dma protected range............................................................. 420 11.1.20txt.cmd.open.locality1?txt open locality 1 command ...................... 420 11.1.21txt.cmd.close.locality1?txt close locality 1 command..................... 421 11.1.22txt.cmd.open.locality2?txt open locality 2 command ...................... 421 11.1.23txt.cmd.close.locality2?txt close locality 2 command..................... 421 14 datasheet 11.1.24txt.public.key?txt chipset public key hash......................................... 421 11.1.25txt.cmd.secrets?txt secrets command ............................................. 422 11.1.26txt.cmd.no-secrets?txt secrets command........................................ 422 11.1.27txt.e2sts?txt extended error status register....................................... 422 11.2 intel ? txt memory map ................................................................................... 423 11.2.1 intel ? txt private space ....................................................................... 423 11.2.2 intel ? txt public space......................................................................... 423 11.2.3 tpm decode area.................................................................................. 423 12 intel ? virtualization technology for dire cted i/o registers (d0:f0) (intel ? 82q45 gmch only) ........................................................................................................... 425 12.1 dmi and peg vc0/vcp remap registers ............................................................. 425 12.1.1 ver_reg?version register ................................................................... 426 12.1.2 cap_reg?capability register .. ...................... ........... ............ ........... ...... 426 12.1.3 ecap_reg?extended capability register...... ................ .......... ........... ...... 430 12.1.4 gcmd_reg?global command register ................................................... 432 12.1.5 gsts_reg?global status register ........... .............................................. 437 12.1.6 rtaddr_reg?root-entry table address register .................................... 438 12.1.7 ccmd_reg?context command register ................................................. 439 12.1.8 fsts_reg?fault status register............................................................ 442 12.1.9 fectl_reg?fault event control register ................................................ 444 12.1.10fedata_reg?fault event data register ................................................. 445 12.1.11feaddr_reg?fault event address register ............................................ 445 12.1.12feuaddr_reg?fault event upper address register ................................. 446 12.1.13aflog_reg?advanced fault log register ............................................... 447 12.1.14pmen_reg?protected memory enable register ........................................ 448 12.1.15plmbase_reg?protected low-memory base register ............................... 449 12.1.16 plmlimit_reg?protected low-memory limit register .............................. 450 12.1.17phmbase_reg?protected high-memory base register.............................. 451 12.1.18phmlimit_reg?protected high-memory limit register ............................. 452 12.1.19iva_reg?invalidate address register..................................................... 453 12.2 dmi vc1 remap engine registers ...................................................................... 455 12.2.1 ver_reg?version register ................................................................... 456 12.2.2 cap_reg?capability register .. ...................... ........... ............ ........... ...... 456 12.2.3 ecap_reg?extended capability register...... ................ .......... ........... ...... 460 12.2.4 gcmd_reg?global command register ................................................... 462 12.2.5 gsts_reg?global status register ........... .............................................. 466 12.2.6 rtaddr_reg?root-entry table address register .................................... 468 12.2.7 ccmd_reg?context command register ................................................. 469 12.2.8 fsts_reg?fault status register............................................................ 471 12.2.9 fectl_reg?fault event control register ................................................ 473 12.2.10fedata_reg?fault event data register ................................................. 475 12.2.11feaddr_reg?fault event address register ............................................ 475 12.2.12feuaddr_reg?fault event upper address register ................................. 476 12.2.13aflog_reg?advanced fault log register ............................................... 477 12.2.14pmen_reg?protected memory enable register ........................................ 478 12.2.15plmbase_reg?protected low-memory base register ............................... 479 12.2.16 plmlimit_reg?protected low-memory limit register .............................. 480 12.2.17phmbase_reg?protected high-memory base register.............................. 481 12.2.18phmlimit_reg?protected high-memory limit register ............................. 482 12.2.19iva_reg?invalidate address register..................................................... 483 12.2.20iotlb_reg?iotlb invalidate register.................................................... 485 12.2.21frcd_reg?fault recording registers....... .............................................. 488 12.3 gfxvtbar ...................................................................................................... 489 12.3.1 ver_reg?version register ................................................................... 490 datasheet 15 12.3.2 cap_reg?capability register................................................................ 490 12.3.3 ecap_reg?extend ed capability register .. ............ ...................... ............ 495 12.3.4 gcmd_reg?global command register................................................... 497 12.3.5 gsts_reg?global status register........... .............................................. 502 12.3.6 rtaddr_reg?root-entry table address register .................................... 503 12.3.7 ccmd_reg?context command register................................................. 504 12.3.8 fsts_reg?fault status register ............. .............................................. 506 12.3.9 fectl_reg?fault event control register.... ............................................ 508 12.3.10fedata_reg?fault event data register ................................................. 509 12.3.11feaddr_reg?fault event address register ............................................ 509 12.3.12feuaddr_reg?fault event upper address register................................. 510 12.3.13aflog_reg?advanced fault log register .............................................. 510 12.3.14pmen_reg?protected memory enable register........................................ 511 12.3.15plmbase_reg?protected low memory base register............................... 512 12.3.16 plmlimit_reg?protected low memory limit register .............................. 513 12.3.17phmbase_reg?protected high memory base register ............................. 514 12.3.18phmlimit_reg?protected high memory limit register............................. 515 12.3.19iva_reg?invalidate address register .................................................... 516 12.3.20iotlb_reg?iotlb invalidate register ................................................... 518 12.3.21frcd_reg?fault recording registers .................................................... 522 13 functional description ........................................................................................... 525 13.1 host interface................................................................................................. 525 13.1.1 fsb ioq depth .................................................................................... 525 13.1.2 fsb ooq depth ......... ........... .......... ...................... ............ ......... .......... 525 13.1.3 fsb gtl+ termination .......................................................................... 525 13.1.4 fsb dynamic bus inversion ................................................................... 525 13.1.5 apic cluster mode support.................................................................... 526 13.2 system memory controller ............................................................................... 527 13.2.1 system memory organization modes....................................................... 527 13.2.1.1 single channel mode ............................................................... 527 13.2.1.2 dual channel modes................................................................ 527 13.2.2 system memory technology supported ................................................... 529 13.3 pci express* .................................................................................................. 530 13.3.1 pci express* architecture ..................................................................... 530 13.3.1.1 transaction layer ................................................................... 530 13.3.1.2 data link layer ...................................................................... 530 13.3.1.3 physical layer ........................................................................ 530 13.3.2 pci express* on (g)mch ....................................................................... 530 13.4 integrated graphics device (intel ? 82q45, 82q43, 82b43, 82g45, 82g43 gmch only) .................................. 532 13.4.1 3d and video engines for graphics processing.......................................... 532 13.4.1.1 3d engine execution units (eus)............................................... 533 13.4.1.2 3d pipeline ............................................................................ 533 13.4.2 video engine ....................................................................................... 534 13.4.3 2d engine ........................................................................................... 534 13.4.3.1 chipset vga registers ............................................................. 534 13.4.3.2 logical 128-bit fixed blt and 256 fill engine .... .......... ........... .... 534 13.5 display interfaces (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ....................... 535 13.5.1 analog display port characteristics ......... ................................................ 535 13.5.1.1 integrated ramdac ................................................................ 536 13.5.1.2 sync signals .......................................................................... 536 13.5.1.3 vesa/vga mode ..................................................................... 536 13.5.1.4 ddc (display data channel)..................................................... 536 13.5.2 digital display interface ........................................................................ 536 16 datasheet 13.5.2.1 high definition multimedia interface (intel ? 82g45, 82g43, 82g41, 82b43 gmch only).................................................................. 536 13.5.2.2 digital video interface (dvi) ..................................................... 537 13.5.2.3 ddpc_ctrldata and ddpc_ctrlclk ....................................... 537 13.5.2.4 display port............................................................................ 538 13.5.2.5 auxiliary channel (aux ch) .......... ............ ........... ........ ............. 538 13.5.2.6 peg mapping of digital display signals ........................................ 538 13.5.2.7 multiplexed digital display channels ? intel ? sdvob and intel ? sdvoc .............................................. 540 13.5.3 multiple display configurations ............... ................................................ 542 13.5.3.1 high bandwidth digital content protection (hdcp) ....................... 542 13.6 intel ? virtualization technology for i/o devices (intel ? 82q45 gmch only) ............ 543 13.6.1 overview ............................................................................................. 543 13.6.2 embedded it client usage model ............................................................ 543 13.6.2.1 intel virtualization technology for i/o devices enables................. 544 13.6.2.2 hardware versus software virtualizat ion .................................... 544 13.6.2.3 hardware virtualization advantages ........................................... 544 13.6.3 concept of dma address remapping ....................................................... 544 13.7 intel ? trusted execution technology (intel ? txt) (intel ? 82q45 and 82q43 gmch only)............................................................... 545 13.8 intel ? management engine (me) subsystem ....................................................... 546 13.8.1 me host visible functional blocks............ ................................................ 546 13.8.2 me power states................................................................................... 547 13.8.3 host/me state transitions ...................................................................... 547 13.9 thermal sensor ............................................................................................... 548 13.9.1 pci device 0, function 0........................................................................ 548 13.9.2 gmchbar thermal sensor registers ....................................................... 548 13.10 power management.......................................................................................... 549 13.10.1main memory power management........................................................... 549 13.10.2interface power states supported ........................................................... 550 13.10.3chipset state combinations ................................................................... 551 13.11 clocking ......................................................................................................... 553 14 electrical characteristics ........................................................................................ 555 14.1 absolute minimum and maximum ratings............................................................ 555 14.2 current consumption ....................................................................................... 556 14.3 (g)mch buffer supply and dc characteristics...................................................... 560 14.3.1 i/o buffer supply voltages..................................................................... 560 14.3.2 general dc characteristics..................................................................... 562 14.3.3 r, g, b / crt dac display dc characteristics (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only)......................................................... 566 14.3.4 di/dt characteristics........................... ................................................... 566 15 ballout and package specifications ........................................................................ 569 15.1 ballout ........................................................................................................... 569 15.2 package specifications...................................................................................... 597 16 testability .............................................................................................................. 599 16.1 jtag boundary scan ........................................................................................ 599 16.1.1 tap instructions and opcodes ................................................................ 600 16.1.2 tap interface and timings. ..................................................................... 600 16.2 xor test mode initialization.............................................................................. 602 16.2.1 xor chain definition ............................................................................. 603 datasheet 17 figures 1 intel? q45, q43, b43, g45, g43 chipset system block diagram example ....................... 24 2 intel? p45, p43 chipset system block diagram example .............................................. 25 3 intel? g41 express chipset system block diagram example ......................................... 26 4 system address ranges............................................................................................ 56 5 dos legacy address range....................................................................................... 57 6 main memory address range ..................................................................................... 61 7 pci memory address range ...................................................................................... 64 8 memory map to pci express device configuration space ............................................... 79 9 mch configuration cycle flow chart ........................................................................... 80 10 gmch graphics controller block diagram .................................................................. 532 11 hdmi overview...................................................................................................... 537 12 display port overview............................................................................................. 538 13 display configurations on atx platforms............. ....................................................... 540 14 display configurations on balanced technology extended (btx) platforms ..................... 541 15 example of eit usage model.................................................................................... 543 16 dma address translation ........................................................................................ 545 17 platform clocking diagram ...................................................................................... 554 18 gmch ballout diagram (top view left ? columns 45?31) ............................................ 570 19 gmch ballout diagram (top view left ? columns 30?16) ............................................ 571 20 gmch ballout diagram (top view left ? columns 15?1).............................................. 572 21 (g)mch package drawing ....................................................................................... 597 22 jtag boundary scan test mode initialization cycles ................................................... 599 23 jtag test mode initialization cycles .................. ....................................................... 601 24 xor test mode initialization cycles ................... ....................................................... 602 tables 1intel ? series 4 chipset high-level feature component differences................................. 22 2 intel specification .................................................................................................... 29 3 sdvo, display port, hdmi/dvi, pci express* signal mapping ........................................ 47 4 expansion area memory segments ............................................................................. 59 5 extended system bios area memory segments........................................................... 59 6 system bios area memory segments......................................................................... 60 7 pre-allocated memory example for 64 mb dram , 1 mb vga, 1 mb gtt stolen and 1 mb tseg 62 8 transaction address ranges ? compatible, high, an d tseg ........................................... 70 9 smm space table ..................................................................................................... 70 10 smm control table ................................................................................................... 71 11 dram controller register address map (d0:f0) ........................................................... 85 12 dram rank attribute register programming ......... ..................................................... 130 13 pci express* register address map (d1:f0) .............................................................. 173 14 host-secondary pci express* bridge register address map (d6:f0) ............................. 229 15 integrated graphics register address map (d2:f0)..................................................... 275 16 pci register address map (d2:f1)............................................................................ 297 17 heci function in me subsystem register address map ................................................ 315 18 second heci function in me subsystem register address map ..................................... 328 19 heci pci mmio space register address map .............................................................. 340 20 second heci function mmio space register address map ............................................ 344 21 ide function for remote boot and installations pt ider register address map................ 348 22 ide bar0 register address map............................................................................... 361 23 ide bar4 register address map............................................................................... 377 24 serial port for remote keyboard and text (kt) redirection register address map........... 386 25 kt io/ memory mapped device register address map ................................................. 399 26 intel ? virtualization technology for directed i/o re gister address map ........................ 425 18 datasheet 27 dmi vc1 remap engine register address map............................................................ 455 28 gfxvtbar register address map.............................................................................. 489 29 host interface 4x, 2x, and 1x signal groups.............................................................. 526 30 sample system memory dual channel symmetric organization mode ............................ 527 3 1 s a m p l e s y s t e m m e mo r y d u a l c h a n ne l a s y m me t r i c o r g a n i z a t i o n m o d e w i t h i n t e l ? flex memory mode enabled ........................................................................................................ 528 3 2 s a m p l e s y s t e m m e mo r y d u a l c h a n ne l a s y m me t r i c o r g a n i z a t i o n m o d e w i t h i n t e l ? flex memory mode disabled ....................................................................................................... 528 33 supported dimm module configurations..................................................................... 529 34 supported usage models ......................................................................................... 531 35 analog port characteristics ...................................................................................... 535 36 (g)mch pci express tx/rx mapping of supported display technologies ........................ 539 37 host/me state combinations .................................................................................... 547 38 targeted memory state conditions ........................................................................... 549 39 platform system states ........................................................................................... 549 40 processor power states ........................................................................................... 550 41 internal graphics display device control ................................................................... 550 42 pci express link states........................................................................................... 550 43 main memory states ............................................................................................... 550 44 g, s, and c state combinations................................................................................ 551 45 interface activity to state mapping .................... ....................................................... 551 46 absolute minimum and maximum ratings .................................................................. 555 47 current consumption in acpi s0 state for intel ? 82g45, 82g43, 82b43, 82g41 gmch, and 82p45, 82p43 mch components............................................................................... 557 48 current consumption in acpi s0 state for intel ? 82q45 and 82q43 components............ 558 49 current consumption in s3, s4, s5 with inte l? active management technology operation (intel ? 82q45 gmch only)...................................................................................... 559 50 i/o buffer supply voltage ........................................................................................ 560 51 dc characteristics .................................................................................................. 562 52 r, g, b / crt dac display dc charac teristics: functional operating range (vcca_dac = 3.3 v 5%)....................................................................................... 566 53 di/dt simulation data ............................................................................................. 567 54 gmch ballout arranged by signal name .................................................................... 573 55 supported tap instructions...................................................................................... 600 56 jtag pins .............................................................................................................. 601 57 jtag signal timings ............................................................................................... 601 datasheet 19 revision history revision number description revision date -001 ? initial release june 2008 -002 ? updated table 1. ? updated the electrical characteristics. june 2008 -003 ? added intel 82g41 gmch september 2008 -004 ? added 82q43 and 82q45 gmch september 2008 -005 ? updated the document title to include the 82b43 gmch ? added support for 82b43 gmch to intel? 4 series (g)mch features ?chapter 1 ? section 1 : added 82b43 gmch in the compon ent list and updated note for 82g41 gmch ? ta b l e 1 : updated intel? series 4 chipset hi gh-level feature component differences ? figure 1 :added support for 82b43 gmch ? figure 3 : added support for ich7r in g41 express chipset system block diagram ? section 1.2.4 , section 1.2.6 , section 1.2.4.2 , section 1.2.4.3 , section 1.2.5 : added support for 82b43 gmch ?chapter 2 ? section 2.5 , section 2.8 , section 2.10 , section 2.11 : added support for 82b43 gmch ? section 2.9 : added support for 82g41 and 82b43 gmch ?chapter 3 ? section 3 , section 3.3 , section 3.7 , section 3.8 : added support for 82b43 gmch ?chapter 4 ? section 4 , section 4.2.1 : added support for 82b43 gmch ?chapter 5 ? ta b l e 1 1 , section 5.1.14 , section 5.1.15 , section 5.1.25 , section 5.1.32 , section 5.1.33 : added support for 82b43 gmch ?chapter 9 ? section 9 : added support for 82b43 gmch ?chapter 13 ? section 13.2 : added support for 82b43 gmch and 2 dimms/channel support on 82g43 ? section 13.4 , section 13.5 : added support for 82b43 gmch ? section 13.5.2.1 : added hdmi support for 82g41 and 82b43 gmch ?c hapter 14 ? section 14.1 , section 14.3.3 , ta b l e 4 7 , ta b l e 5 0 : added support for 82b43 gmch ?chapter 15 ? section 15.1 : added support for 82b43 gmch may 2009 -006 ?chapter 13 ? section 13.2.2 : added clarification on system memory dram device technology supported for ddr2 and ddr3 september 2009 -007 ?chapter 13 ? section 13.2 : updated note for dimm support for 82b43 gmch ?chapter 14 ? ta b l e 4 6 and ta b l e 5 0 : updated vcc and vcc_exp requirements for 82b43 gmch ? ta b l e 5 1 : added min and max spec for cl_vref march 2010 20 datasheet intel ? 4 series (g)mch features ? processor/host interface (fsb) ?supports intel ? core?2 extreme processor qx9000 series ?supports intel ? core?2 quad processor q9000 series ?supports intel ? core?2 duo processor e8000 and e7000 series ? 800/1067/1333 mt/s (200/266/333 mhz) fsb ? hyper-threading technology (ht technology) ? fsb dynamic bus inversion (dbi) ? 36-bit host bus addressing ? 12-deep in-order queue ?1-deep defer queue ? gtl+ bus driver with integrated gtl termination resistors ? supports cache line size of 64 bytes ? system memory interface ? one or two channels (each channel consisting of 64 data lines) ? single or dual channel memory organization ? ddr2-800/667 frequencies ? ddr3-1066/800 frequencies ? unbuffered, non-ecc dimms only ? supports 2-gb, 1-gb, 512-mb ddr2 and 1-gb, 512-mb ddr3 technologies for x8 and x16 devices ? 16 gb maximum memory ? direct media interface (dmi) ? chip-to-chip connection interface to intel ich10/ich7 ? 2 gb/s point-to-point dmi to ich9 (1 gb/s each direction) ? 100 mhz reference clock (shared with pci express graphics attach) ? 32-bit downstream addressing ? messaging and error handling ? pci express* interface ? one x16 pci express port ? compatible with the pci express base specification, revision 2.0 ? raw bit rate on data pins of 2.5 gb/s resulting in a real bandwidth per pair of 250 mb/s ?intel ? trusted execution technology (intel ? txt) (82q45 and 82q43 gmch only) ?intel ? virtualization technology (82q45 gmch only) ?integrated graphics devi ce (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ? core frequency of 400 mhz ?1.6 gp/s pixel rate ? high-quality 3d setup and render engine ? high-quality texture engine ? 3d graphics rendering enhancements ?2d graphics ? video overlay ? multiple overlay functionality ? analog display (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ? 350 mhz integrated 24-bit ramdac ? up to 2048x1536 @ 75 hz refresh ? hardware color cursor support ? ddc2b compliant interface ? digital display (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ? sdvo ports in single mode supported ? 200 mhz dot clock on each 12-bit interface ? flat panels up to 2048x1536 @ 60 hz or digital crt/ hdtv at 1400x1050 @ 85 hz ? dual independent display options with digital display ? multiplexed digital display channels (supported with add2 card). ? supports tmds transmitters or tv-out encoders ? add2/mec card uses pci express graphics x16 connector ? two channels multiplexed with pci express* graphics port ? supports hot-plug and display ? thermal sensor ? catastrophic trip point support ? hot trip point support for smi generation ? power management ? pc99 suspend to dram support (?str?, mapped to acpi state s3) ? acpi revision 2.0 compatible power management ? supports processor states: c0, c1, c2 ? supports system states: s0, s1, s3, and s5 ? supports processor thermal management 2 ?package ? fc-bga. 34 mm 34 mm. the 1254 balls are located in a non-grid pattern datasheet 21 introduction 1 introduction the intel ? intel 4 series chipset family is desi gned for use in desktop platforms. the chipset contains two components: gmch (or mch) for the host bridge and i/o controller hub 10 (ich10) for the i/o subsys tem (g45, g43, p45, p43 express chipset only). the ich10 is the tenth generation i/ o controller hub and provides a multitude of i/o related functions. the intel g41 chipset uses the i/o controller hub 7 (ich7). figure 1 , figure 2 , and figure 3 show example system block diagrams for the intel ? 4 series chipset. this document is the datasheet for the following components: ?intel ? 82q45 graphics and memory controller hub (gmch), which is part of the intel ? q45 chipset. ?intel ? 82q43 graphics and memory controller hub (gmch), which is part of the intel ? q43 chipset. ?intel ? 82b43 graphics and memory controller hub (gmch), which is part of the intel ? b43 chipset. ?intel ? 82g45 graphics and memory controller hub (gmch), which is part of the intel ? g45 chipset. ?intel ? 82g43 graphics and memory controller hub (gmch), which is part of the intel ? g43 chipset. ?intel ? 82g41 graphics and memory controller hub (gmch), which is part of the intel ? g41 chipset. ?intel ? 82p45 memory controller hub (mch ), which is part of the intel ? p45 chipset. ?intel ? 82p43 memory controller hub (mch ), which is part of the intel ? p43 chipset. topics covered include; signal description, system memory map, pci register description, a description of the (g)mch interf aces and major functional units, electrical characteristics, ballout definitions, and package characteristics. note: unless otherwise specified, ich10 refers to the intel ? 82801jib ich10, intel ? 82801jir ich10r, intel ? 82801jd ich10d, intel ? 82801jdo ich10do i/o controller hub 10 components. note: for the 82g41 gmch, references to ich are references to ich7/ich7r. note: unless otherwise specified, the information in this document applies to the intel ? 82q45, 82q43, 82b43, 82g45, 83g43, 82g41 graphics and memory controller hub (gmch) and intel ? 82p45, 82p43 memory controller hub (mch). note: in this document the integrated graphics components are referred to as gmch. the intel ? 82p45 and 82p43 components do not contain integrated graphics and are referred to as mch. the term (g)mch is us ed when referring to both gmch and mch. ta b l e 1 provides a high-level component feature summary. introduction 22 datasheet table 1. intel ? series 4 chipset high-level feature component differences feature 82q45 gmch 82q43 gmch 82b43 gmch 82g45 gmch 82g43 gmch 82g41 gmch 82p45 mch 82p43 mch fsb support 1333 mhz yes yes yes yes yes yes yes yes 1067 mhz yes yes yes yes yes yes yes yes 800 mhz yes yes yes yes yes yes yes yes memory support dimms per channel 22221/2 2 122 ddr3 1067 yesyesyesyesyesyesyesyes 800 yesyesyesyesyesyesyesyes ddr2 800 yesyesyesyesyesyesyesyes 667 yesyesyesyesyesyesyesyes ich support ich10do yes??????? ich10d ?yesyes????? ich10 ? ? ? yes yes ? yes yes ich10r ? ? ? yes yes ? yes yes ich7 ?????yes?? ich7r ?? ???yes 3 ?? discrete gfx pci express* gen 2, 1x16 yesyesyesyesyes ? yesyes pci express* gen 2, 2x8 ??????yes? pci express* gen 1, 1x16 yesyesyesyesyesyesyesyes pci express* gen 1, 2x8 ??????yes? internal graphics support ? general features 5th generation core yes yes yes yes yes yes na directx 10 yesyesyesyesyesyes opengl 1.5 yes yes yes yes yes yes intel clear video technology ? ? ? yes yes yes dual independent display yes yes yes yes yes yes add2/mec yesyesyesyesyesyes hdmi* 1.3 ? ? upgrad e 4 yes yes yes 3 dvi* yesyesyesyesyesyes display port yesyesyesyesyesyes integrated hdcp yes yes yes yes yes yes pavp yesyesyesyesyesyes vga* yesyesyesyesyesyes full hardware decode acceleration of mpeg2, vc1, and avc ???yes?? datasheet 23 introduction note: 1. ?yes? indicates the feature is supported. ??? indicates the feature is not supported. 2. support for dimms per channel varies on g 43 parts. please refer to component marking information to identify feature support. 3. support of ich7r/hdmi varies on g41 pa rts. please refer to component marking information to identify feature support. 4. enabled via intel? upgrade service 5. enabled via intel? upgrade service offeri ng a "down the wire" manageability upgrade consisting of intel standard manageability + cira. 6. intel ? quiet system technology and asf functi onality requires a correctly configured system, including an approp riate (g)mch with me, me fi rmware, and system bios support. platform technologies intel ? amt yes??????? intel? upgrade service ??yes????? standard manageability ? yes upgrad e 5 ????? intel ? remote wake technology (intel ? rwt) ? ? ? yes yes ? yes yes asf 5 yes yes yes yes yes ? yes yes intel quite system technology 5 yes yes yes yes yes ? yes yes intel tpm 1.2 yesyes?????? intel vtd yes??????? intel txt yesyes?????? table 1. intel ? series 4 chipset high-level feature component differences feature 82q45 gmch 82q43 gmch 82b43 gmch 82g45 gmch 82g43 gmch 82g41 gmch 82p45 mch 82p43 mch introduction 24 datasheet figure 1. intel ? q45, q43, b43, g45, g43 chipset system block diagram example processor gmch ddr2/ddr3 ddr2/ddr3 channel a 800/1066/1333 mhz fsb hda channel b pci express* x16 graphics system memory add2 or mec intel ? ich10 usb 2.0 12 ports gpio 6 serial ata ports spi tpm intel ? high definition audio codec(s) lpc interface power management sst and peci sensor input fan speed control output smbus 2.0/i 2 c intel ? 82567 gigabit platform lan connect sio spi flash bios lci pci express* bus 5 w/lanor 6 pcie slots pci bus four pci masters glci 8 4 4 dp/hdmi/dvi 16 dmi interface controller link dp/hdmi/dvi datasheet 25 introduction figure 2. intel ? p45, p43 chipset system block diagram example processor mch ddr2/ddr3 ddr2/ddr3 channel a 800/1066/1333 mhz fsb hda channel b pci express* 1x16 or 2x8 (p45) graphics system memory intel ? ich10 usb 2.0 12 ports gpio 6 serial ata ports spi tpm intel ? high definition audio codec(s) lpc interface power management sst and peci sensor input fan speed control output smbus 2.0/i 2 c intel ? 82567 gigabit platform lan connect sio spi flash bios lci pci express* bus 5 w/lanor 6 pcie slots pci bus four pci masters glci dmi interface controller link introduction 26 datasheet figure 3. intel ? g41 express chipset syst em block diagram example processor gmch ddr2/ddr3 ddr2/ddr3 channel a 800/1066/1333 mhz fsb channel b pci express* x16 graphics system memory add2 or mec 8 4 4 dp/hdmi/dvi 16 dmi interface dp/hdmi/dvi intel pci express gigabit ethernet intel ? ich7 / intel ? ich7r usb 2.0 (supports 8 usb ports) system management (tco) ide gpio smbus 2.0/i 2 c power management pci bus ... clock generators s l o t s l o t lan connect ac ?97/intel? high definition audio codec(s) firmware hub other asics (optional) lpc i/f super i/o sata (4 ports) pci express* x1 tpm (optional) spi bios datasheet 27 introduction 1.1 terminology term description add card advanced digital display card. provides digital display op tions for an intel graphics controller that supports add cards (have dvos multiplexed with agp interface). keyed like an agp 4x card and plugs into an agp connector. will not work with an intel graphics controller that implements intel ? sdvo. add2 card advanced digital display card ? 2nd generation. provides digital display options for an intel graphics controller that supports add2 cards. plugs into a x16 pci express* connector but utilizes the multiplexed sdvo interface. will not work with an intel graphics controller that supports intel ? dvo and add cards. chipset / root ? complex used in this specification to refer to one or more hardware components that connect processor complexes to the i/o and memory subsystems. the chipset may include a variety of integrated devices. clink controller link is a proprietary chip-t o-chip connection between the (g)mch and ich10. the intel 4 series chipset fa mily requires that clink be connected in the platform. core the internal base logic in the (g)mch crt cathode ray tube dbi dynamic bus inversion ddr2 a second generation double da ta rate sdram memory technology ddr3 a third generation double da ta rate sdram me mory technology dmi direct media interface is a proprietary chip-to-chip connection between the (g)mch and ich. this interface is based on the standard pci express* specification. domain a collection of physical, logical or virt ual resources that are allocated to work together. domain is used as a generic term for virtual ma chines, partitions, etc. dvi digital video interface. specification th at defines the connector and interface for digital displays. dvmt dynamic video memory technology ep pci express egress port fsb front side bus. synonymous with host or processor bus full reset full reset is when pwrok is de-asserte d. warm reset is when both rstin# and pwrok are asserted. gmch graphics and memory controller hub co mponent that contains the processor interface, dram controller, and pci ex press port. the gmch contains an integrated graphics device (igd). the gmch communicates with the i/o controller hub (intel ? ich) over the dmi interconnect. mec media expansion card. provides digital display options for an intel graphics controller that supports mec cards. pl ugs into an x16 pci express connector but utilizes the multiplexed sdvo inte rface. adds video in capabilities to platform. will not work with an intel graphics controller that supports dvo and add cards. will functi on as an add2 card in an add2 suppo rted system, but video in capabili ties will not work. hdmi high definition multimedia interface ? hdmi supports standard, enhanced, or high-definition video, plus multi-channe l digital audio on a single cable. it transmits all atsc hdtv standards and supports 8-channel di gital audio, with bandwidth to spare for future requir ements and enhancements (additional details available throug h http://www.hdmi.org/) host this term is used sy nonymously with processor introduction 28 datasheet igd internal graphics device intx an interrupt request si gnal where x stands for interrupts a, b, c and d intel ? ich10 tenth generation i/o controller hub co mponent that contains the primary pci interface, lpc interface, usb2.0, sata, and other i/o functions. intel ? ich7 seventh generation i/o controller hub component that cont ains additional functionality compared to previous in tel ich components. ich7 contains the primary pci interface, lpc interface, usb2, sata, ata-100, and other i/o functions. it communicates with the (g)mch over a proprietary interconnect called dmi. for the 82g41 gmch, the term intel ich in this document refers to the ich7. ioq in order queue lcd liquid crystal display lvds low voltage differential signaling. a hi gh speed, low power data transmission standard used for display connections to lcd panels. mch memory controller hub component that contains the processor interface, dram controller, and pci express port . the mch communicates with the i/o controller hub over the dmi interconnect. msi message signaled interrupt. a transactio n conveying interrupt information to the receiving agent through the same pa th that normally carries read and write commands. ooq out of order queueing pavp protected audio-video path for supportin g secure playback of intel hd audio and video content pci express* a high-speed serial interface whose conf iguration is software compatible with the legacy pci specifications. primary pci the physical pci bus that is driven di rectly by the ich10/ich7 component. communication between primary pci and the (g)mch occurs over dmi. the primary pci bus is not pci bus 0 from a configuration standpoint. processor refers to the microprocessor that connects to chipset through the fsb interface on the (g)mch. rank a unit of dram corresponding to eight x8 sdram devices in parallel or four x16 sdram devices in parallel, ignoring ecc. these device s are usually, but not always, mounted on a single side of a dimm. sci system control interrupt. used in acpi protocol. sdvo serial digital video out (sdvo). digital display channel that serially transmits digital display data to an external sdvo device. the sdvo de vice accepts this serialized format and then translates the data into the appropriate display format (i.e., tmds, lvds, and tv-out). this interface is not electrically compatible with the previous digita l display channel - dvo. the sdvo interface is multiplexed on a portion of the x16 graphics pci express interface. sdvo device third party codec that uses sdvo as an input. the device may have a variety of output formats, including dvi, lvds, hdmi, tv-out, etc. serr system error. an indicati on that an unrecoverable error has occurred on an i/o bus. smi system management interrupt . smi is used to indicate any of several system conditions such as thermal sensor events, throttling activated, access to system management ram, chassis open, or other system state related activity. tmds transition minimized differential signal ing. signaling interface from silicon image that is used in dvi and hdmi. term description datasheet 29 introduction tpm trusted platform module uma unified memory architectu re. describes an igd usin g system memory for its frame buffers. vco voltage controlled oscillator term description table 2. intel specification document name location intel ? 4 series chipset family specification update http://www.intel.com/assets/pdf/ specupdate/319971.pdf intel ? 4 series chipset family thermal and mechanical design guide http://www.intel.com/assets/pdf/ designguide/319972.pdf intel ? i/o controller hub 10 (i ch10) family datasheet http://www.intel.com/assets/ pdf/datasheet/319973.pdf intel ? i/o controller hub 10 (ich10) family thermal mechanical design guide. http://www.intel.com/assets/pdf/ designguide/319975.pdf intel ? i/o controller hub 7 (ich7) family datasheet http://www.intel.com/assets/pdf/ datasheet/307013.pdf intel ? i/o controller hub 7 (ich7) family thermal mechanical design guide. http://www.intel.com/assets/pdf/ designguide/307015.pdf advanced configuration and power interface specification, version 2.0 http://www.acpi.info/ advanced configuration and power interface specification, version 1.0b http://www.acpi.info/ the pci local bus specification, version 2.3 http://www.pcisig.com/ specifications pci express* specification, version 1.1 http://www.pcisig.com/ specifications introduction 30 datasheet 1.2 (g)mch system overview the (g)mch was designed for use with the intel ? core?2 extreme processor qx9000 series, intel ? core?2 quad processor q9000 series, and intel ? core?2 duo processor e8000 and e7000 series in the lga775 land grid array package targeted for desktop platforms. the role of a (g)mch in a syst em is to manage the flow of information between its interfaces: the pr ocessor interface, the system memory interface, the external graphics or pci express interface, internal graphics interfaces, and the i/o controller through dmi interface. this includ es arbitrating between the interfaces when each initiates transactions. it supports one or two channels of dd r2 or ddr3 sdram. it also supports pci express based external graphics and devices. the intel 4 series chipset platform supports the tenth generation i/o controller hub 10 (ich10) to provide i/o related features. note that the intel g41 chipset supports the i/o controller hub 7 (ich7). 1.2.1 host interface the (g)mch supports a single lga775 sock et processor. the (g)mch supports a fsb frequency of 800, 1066, 1333 mhz. host-initiated i/o cycles are decoded to pci express, dmi, or the (g)mch configuration space. host-initiated memory cycles are decoded to pci express, dmi, or system memory. pci express device accesses to non- cacheable system memory are not snooped on the host bus. memory accesses initiated from pci express using pci semantics and fr om dmi to system sdram will be snooped on the host bus. processor/host interface (fsb) details ?supports intel ? core?2 extreme processor qx9000 series, intel ? core?2 quad processor q9000 series, and intel ? core?2 duo processor e8000 and e7000 series family processors ? supports front side bus (fsb) at the following frequency ranges: ? 800, 1066, 1333 mt/s. fsb speeds are processor dependent. ? supports fsb dynamic bus inversion (dbi) ? supports 36-bit host bus addressing, allowing the processor to access the entire 64 gb of the host address space. ? has a 12-deep in-order queue to suppor t up to twelve outstanding pipelined address requests on the host bus ? has a 1-deep defer queue ? uses gtl+ bus driver with inte grated gtl termination resistors ? supports a cache line size of 64 bytes datasheet 31 introduction 1.2.2 system memory interface the (g)mch integrates a system memory dd r2/ddr3 controller with two, 64-bit wide interfaces. the buffers support both sstl_1.8 (stub series terminated logic for 1.8 v) and sstl_1.5 (stub series terminated logic for 1.5v) signal interfaces. the memory controller interface is fully configurab le through a set of control registers. system memory interface details ? directly supports one or two channels of ddr2 or ddr3 memory with a maximum of two dimms per channel. ? supports single and dual channel memory organization modes. ? supports a data burst length of eight for all memory organization modes. ? supported memory data transfer rates: ? 667 mhz and 800 mhz for ddr2 ? 800 mhz and 1066 mhz for ddr3. ? i/o voltage of 1.8 v for ddr2 and 1.5 v for ddr3. ? supports both un-buffered non-ecc ddr2 or non-ecc ddr3 dimms. ? supports maximum memory bandwidth of 6.4 gb/s in single-channel mode or 12.8 gb/s in dual-channel mode assuming ddr2 800 mhz. ? supports 512-mb, 1-gb, 2-gb ddr2 and 512-mb, 1-gb ddr3 dram technologies for x8 and x16 devices. ? using 512 mb device technologies, the smallest memory capacity possible is 256 mb, assuming single channel mode with a single x16 single sided un-buffered non-ecc dimm memory configuration. ? using 2 gb device technologies, the largest memory capacity possible is 16 gb, assuming dual channel mode with four x8 double sided un-buffered non-ecc or ecc dimm memory configurations. note: the ability to support greater than the largest memory capacity is subject to availability of higher density memory devices. ? supports up to 32 simultaneous open pages per channel (assuming 4 ranks of 8 bank devices) ? supports opportunistic refresh scheme ? supports partial writes to memory using data mask (dm) signals ? supports a memory thermal management scheme to selectively manage reads and/or writes. memory thermal management can be triggered either by on-die thermal sensor, or by preset limits. mana gement limits are dete rmined by weighted sum of various commands that are scheduled on the memory interface. 1.2.3 direct media interface (dmi) direct media interface (dmi) is the chip-t o-chip connection between the (g)mch and ich10/ich7. this high-speed interface inte grates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. base functionality is completely software transpar ent permitting current and legacy software to operate normally. to provide for true isochronous transfers and configurable quality of service (qos) transactions, the ich10/ich7 supports two virtual channels on dmi: vc0 and vc1. these two channels provide a fixed arbitration scheme where vc1 is always the highest introduction 32 datasheet priority. vc0 is the default conduit of traffic for dmi and is always enabled. vc1 must be specifically enabled and configured at both ends of the dmi link (i.e., the ich10/ich7 and (g)mch). ? a chip-to-chip connection in terface to intel ich10/ich7 ? 2 gb/s point-to-point dmi to ich10 (1 gb/s each direction) ? 100 mhz reference clock (shared with pci express) ? 32-bit downstream addressing ? apic and msi interrupt messaging suppor t. will send intel-defined ?end of interrupt? broadcast message when initiated by the processor. ? message signaled interrupt (msi) messages ? smi, sci, and serr error indication 1.2.4 multiplexed pci express* graphics interface and intel ? sdvo/dvi/hdmi/dp interface for the 82q45, 82q43, 82b43, 82g45, 82g 43, and 82g41 gmchs, the pci express interface is multiplexed with the sdvo an d hdmi/dvi interfaces. for the 82p45 and 82p43 mchs, the pci express interface is not multiplexed. 1.2.4.1 pci express* interface the (g)mch supports either two pci express* 8-lane (x8) ports or one pci express 16- lane (x16) port. the (g)mch contains one 16-lane (x16) pci ex press port intended for supporting up to two external pci express graphics card in bifurcated mode, fully compliant to the pci express base specification, revision 2.0 . ? supports pci express gen1 frequency of 1.25 ghz resulting in 2.5 gb/s each direction (500 mb/s total). maximum theoretical bandwidth on interface of 4 gb/s in each direction simultaneously, for an ag gregate of 8 gb/s when operating in x16 mode. ? supports pci express gen2 frequency of 2.5 ghz resulting in 5.0 gb/s each direction (1000 mb/s total). maximum theoretical bandwidth on interface of 8 gb/s in each direction simultaneously, for an aggregate of 16 gb/s when operating in x16 mode. ? pci express port 0 is mapped to pci device 1 (peg). ? pci express port 1 is mapped to pci device 6 (peg2). ? peer to peer traffic is supported on virtual channel 0: ?from dmi to peg ?from dmi to peg2 ? from peg to peg2 ?from peg2 to peg ? supports pci express enhanced access mechanism. allowing accesses to the device configuration space in a flat memory mapped fashion. ? the port may negotiate down to narrower widths. for each of the ports: ? support for x16/x8/x4/x1 widths for a single peg mode. ? support for the x8/x4/x1 widths for a dual peg mode. ? x1 width support simultaneously with the sdvo functionality which is multiplexed onto the peg port. such shared use facilitates add2+/mec implementation. ? the x16 lanes can be configured to two ports in bifurcated mode. in this mode, maximum x8 width is supported. datasheet 33 introduction ? the two x8 pci express ports can operate in gen1 or gen2 mode independent of each other. ? supports ?static? lane numbering reversal. ? does not support ?dynamic? lane reversal, as defined (optional) by the pci express specification. ? supports l1 aspm power management capability. 1.2.4.2 sdvo multiplexed interface (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) the gmch supports two multiplexed sdvo ports that each drive pixel clocks up to 270 mhz. the gmch can make use of these di gital display channels via an advanced digital display card (add2) or media expansion card. 1.2.4.3 hdmi/dvi/dp multiplexed interface (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) the gmch supports two multiplexed digital display ports that each drive pixel clocks up to 165 mhz. the gmch supports combinations of dp/dp, dvi/dvi, hdmi/hdmi*, dp/ dvi, hdmi/dvi, and dp/hdmi multiplexed on the 2 digital display ports. note: only one channel can support embedded audio at a time. 1.2.5 graphics features (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) the gmch provides an integrated graphics de vice (igd) delivering cost competitive 3d, 2d and video capabilities. dx10 and opengl 2.1 are supported. the gmch contains an extensive set of instructions for 3d operations, 2d operations, motion compensation, overlay, and display control. hd-dvd and blu-ray are also natively supported with hardware based vc-1, mpeg2, and avc decode capabilities. the gmch also supports pavp (protected audio-video path), which allows for protected intel ? hd audio hd video playback. the gmch uses a uma configuration with dvmt for graphics memory. the gmch also has the capability to support external gr aphics accelerators via the pci express graphics (peg) port but cannot work concurre ntly with the integrated graphics device. high bandwidth access to data is provided through the system memory port. 1.2.6 (g)mch clocking ? differential host clock of 200/266/333 mhz. the (g)mch supports fsb transfer rates of 800/1066/1333 mt/s. ? differential memory clocks of 333/400/533/600 mhz. the (g)mch supports memory transfer rates of ddr2-667, ddr2-800, ddr3-800, and ddr3-1067. ? the pci express* pll of 100 mhz serial reference clock generates the pci express core clock of 250 mhz. ? display timings are generated from displa y plls that use a 96 mhz differential non- spread spectrum clock as a referenc e. display plls can also use the ssdvo_tvclkin[+/-] from an sdvo device as a reference. (82q45, 82q43, 82b43, 82g45, 82g43, and 82g41 gmch only) ? all of the above clocks are capable of tolerating spread spectrum clocking. ? host, memory, and pci express plls are disabled until pwrok is asserted. introduction 34 datasheet 1.2.7 power management (g)mch power management support includes: ? pc99 suspend to dram support (? str?, mapped to acpi state s3) ? smram space remapping to a0000h (128 kb) ? supports extended smram space above 256 mb, additional 1 mb tseg from the base of graphics stolen memory (bsm) wh en enabled, and cacheable (cacheability controlled by processor) ? acpi rev 3.0b compatible power management ? supports active state power management (aspm) ? supports processor states: c0, c1, c2, c3, and c4 ? supports system states: s0, s1, s3, and s5 ? supports processor thermal management 2 (tm2) ? supports manageability states m0, m1?s3, m1?s5, moff?s3, moff?s5, moff-m1 1.2.8 thermal sensor (g)mch thermal sensor support includes: ? catastrophic trip point support for emergency clock gating for the (g)mch ? hot trip point support for smi generation datasheet 35 signal description 2 signal description this chapter provides a detailed descripti on of (g)mch signals. the signals are arranged in functional groups according to their associated interface. the following notations are used to describe the signal type. signal type description pci express* pci express interface signals. these signals are compatible with pci express 2.0 signaling environment ac sp ecifications and are ac coupled. the buffers are not 3.3 v tolerant. differential voltage spec = (|d+ ? d-|) * 2 = 1.2 vmax. single-ended maximum = 1.25 v. single-ended minimum = 0 v. dmi direct media interface sign als. these signals are comp atible with pci express 2.0 signaling environment ac specificat ions, but are dc co upled. the buffers are not 3.3 v tolerant. differential voltage spec = (|d+ ? d-|) * 2 = 1.2 vmax. single-ended maximum = 1.25 v. single-ended minimum = 0 v. cmos cmos buffers. 1.5 v tolerant. cod cmos open drain buffers. 3.3 v tolerant. hvcmos high voltage cmos buffers. 3.3 v tolerant. hvin high voltage cmos input- only buffers. 3.3 v tolerant. sstl_1.8 stub series termination logic. these are 1.8 v output capable buffers. 1.8 v tolerant. sstl_1.5 stub series termination logic. these are 1.5 v output capable buffers. 1.5 v tolerant a analog reference or output. may be used as a threshold voltage or for buffer compensation. gtl+ gunning transceiver logic si gnaling technology. implements a voltage level as defined by v tt of 1.2 v and/or 1.1 v. signal description 36 datasheet 2.1 host interface signals note: unless otherwise noted, the voltage level for a ll signals in this interface is tied to the termination voltage of the host bus (v tt ). signal name type description fsb_adsb i/o gtl+ address strobe: the processor bus ow ner asserts fsb_adsb to indicate the first of two cy cles of a request phase. the (g)mch can assert this signal for snoop cycles and interrupt messages. fsb_bnrb i/o gtl+ block next request: used to block the current request bus owner from issuing new requests . this signal is used to dynamically control the proc essor bus pipeline depth. fsb_bprib o gtl+ priority agent bus request: the (g)mch is the only priority agent on the processor bus. it asserts this signal to obtain the ownership of the address bus. th is signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new tran sactions unless the fsb_lockb signal was asserted. fsb_breq0b o gtl+ bus request 0: the (g)mch pulls the processor bus? fsb_breq0b signal low during fsb_cpurstb. the processors sample this signal on the active-to-inactive transition of fsb_cpurstb. the minimum setup time for this signal is 4 hclks. the minimum hold time is 2 hclks and the maximum hold time is 20 hclks. fsb_breq 0b should be tr i-stated after the hold time requirement has been satisfied. fsb_cpurstb o gtl+ cpu reset: the fsb_cpurstb pin is an output from the (g)mch. the (g)mch asserts fsb_cpurstb while rstinb (pcirst# from the ich) is asserted and for approximately 1 ms after rstinb is de-asser ted. the fsb_cpurstb allows the processor to begin execution in a known state. fsb_dbsyb i/o gtl+ data bus busy: used by the data bus owner to hold the data bus for transfers requiring more than one cycle. fsb_deferb o gtl+ defer: signals that the (g)mch wi ll terminate the transaction currently being snooped with ei ther a deferred response or with a retry response. fsb_dinvb_[3:0] i/o gtl+ 4x dynamic bus inversion: driven along with the fsb_db_[63:0] signals. indicates if the associated signals are inverted or not. fsb_dinvb_[3:0 ] are asserted such that the number of data bits driven electr ically low (low voltage) within the corresponding 16 bit group never exceeds 8. fsb_dinvb_x data bits fsb_dinvb_3 fsb_db_[63:48] fsb_dinvb_2 fsb_db_[47:32] fsb_dinvb_1 fsb_db_[31:16] fsb_dinvb_0 fsb_db_[15:0] fsb_drdyb i/o gtl+ data ready: asserted for each cycle that data is transferred. datasheet 37 signal description fsb_ab_[35:3] i/o gtl+ 2x host address bus: fsb_ab_[35:3] connect to the processor address bus. during processor cycles the fsb_ab_[35:3] are inputs. the (g)mch drives fsb_ ab_[35:3] during snoop cycles on behalf of dmi and pci expr ess initiators. fsb_ab_[35:3] are transferred at 2x rate. note that the address is inverted on the processor bus. the values are driven by the (g)mch between pwrok assertion and fs b_cpurstinb deassertion to allow processor configuration. fsb_adstbb_[1:0] i/o gtl+ 2x host address strobe: the source synchronous strobes used to transfer fsb_ab_[31:3] an d fsb_reqb_[4:0] at the 2x transfer rate. strobe address bits fsb_adstbb_0 fsb_ab_[16:3], fsb_reqb_[4:0] fsb_adstbb_1 fsb_ab_[31:17] fsb_db_[63:0] i/o gtl+ 4x host data: these signals are connected to the processor data bus. data on fsb_db_[63:0] is transferred at a 4x rate. note that the data signals may be in verted on the processor bus, depending on the fsb_ dinvb_[3:0] signals. fsb_dstbpb_[3:0] fsb_dstbnb_[3:0] i/o gtl+ 4x differential host data strobes: the differential source synchronous strobes used to transfer fsb_db_[63:0] and fsb_dinvb_[3:0] at the 4x transfer rate. named this way because they are not level sensitive. data is captured on the falling edge of both strobes. he nce, they are pseudo-differential, an d not true differential. strobe data bits fsb_dstb[p,n]b_3 fsb_db_[63:48], hdinvb_3 fsb_dstb[p,n]b_2 fsb_db_[47:32], hdinvb_2 fsb_dstb[p,n]b_1 fsb_db_[31:16], hdinvb_1 fsb_dstb[p,n]b_0 fsb_db_[15:0], hdinvb_0 fsb_hitb i/o gtl+ hit: indicates that a caching agent holds an unmodified version of the requested line. al so, driven in conjunction with fsb_hitmb by the target to extend the snoop window. fsb_hitmb i/o gtl+ hit modified: indicates that a caching agent holds a modified version of the reques ted line and that this agent assumes responsibility for providing the line. also, driven in conjunction with fsb_hitb to extend the snoop window. fsb_lockb i gtl+ host lock: all processor bus cycles sampled with the assertion of fsb_lockb and fsb_ adsb, until the negation of fsb_lockb must be atomic, i.e. no dmi or pci express access to dram are allowed when fsb_ lockb is asserted by the processor. fsb_reqb_[4:0] i/o gtl+ 2x host request command: defines the attributes of the request. fsb_reqb_[4:0] are tran sferred at 2x rate. asserted by the requesting agent during both halves of request phase. in the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second half the signals carry a dditional informat ion to define the complete transaction type. the transactions supported by the (g)mch host bridge are defined in the host interface section of this document. signal name type description signal description 38 datasheet fsb_trdyb o gtl+ host target ready: indicates that the target of the processor transaction is able to enter the data transfer phase. fsb_rsb_[2:0] o gtl+ response signals: indicates type of response according to the table at left: encoding response type 000 idle state 001 retry response 010 deferred response 011 reserved (not driven by (g)mch ) 100 hard failure (not driven by (g)mch ) 101 no data response 110 implicit writeback 111 normal data response fsb_rcomp i/o a host rcomp: used to calibrate the host gtl+ i/o buffers. this signal is powered by the host interface te rmination rail (v tt ). connects to fsb_xrcomp1in in the package. fsb_scomp i/o a slew rate compensation: compensation for the host interface for rising edges. fsb_scompb i/o a slew rate compensation: compensation for the host interface for falling edges. fsb_swing i/o a host voltage swing: these signals provide reference voltages used by the fsb rc omp circuits. fsb_xswing is used for the signals handled by fsb_xrcomp. fsb_dvref i/o a host reference voltage: reference voltage input for the data signals of the host gtl interface. fsb_accvref i/o a host reference voltage: reference voltage input for the address signals of the host gtl interface. signal name type description datasheet 39 signal description 2.2 system memory (ddr2/d dr3) interface signals 2.2.1 system memory channel a interface signals signal name type description ddr_a_ck o sstl-1.8/1.5 sdram differential clocks: ? ddr2: three per dimm ? ddr3: two per dimm ddr_a_ckb o sstl-1.8/1.5 sdram inverted differential clocks: ? ddr2: three per dimm ? ddr3: two per dimm ddr_a_csb_[3:0] o sstl-1.8/1.5 ddr2/ddr3 device rank 3, 2, and 0 chip selects ddr_a_cke_[3:0] o sstl-1.8/1.5 ddr2/ddr3 clock enable: (1 per device rank) ddr_a_odt_[3:0] o sstl-1.8/1.5 ddr2/ddr3 on die termination: (1 per device rank) ddr_a_ma_[14:0] o sstl-1.8/1.5 ddr2 address signals [14:0] ddr_a_bs_[2:0] o sstl-1.8/1.5 ddr2/ddr3 bank select ddr_a_rasb o sstl-1.8/1.5 ddr2/ddr3 row address select signal ddr_a_casb o sstl-1.8/1.5 ddr2/ddr3 column address select signal ddr_a_web o sstl-1.8/1.5 ddr2/ddr3 write enable signal ddr_a_dq_[63:0] i/o sstl-1.8/1.5 ddr2/ddr3 data lines ddr_a_dm_[7:0] o sstl-1.8/1.5 ddr2/ddr3 data mask ddr_a_dqs_[7:0] i/o sstl-1.8/1.5 ddr2/ddr3 data strobes ddr_a_dqsb_[7:0] i/o sstl-1.8/1.5 ddr2/ddr3 data strobe complements signal description 40 datasheet 2.2.2 system memory chan nel b interface signals signal name type description ddr_b_ck o sstl-1.8/1.5 sdram differential clocks: ? ddr2: three per dimm ? ddr3: two per dimm ddr_b_ckb o sstl-1.8/1.5 sdram inverted differential clocks: ? ddr2: three per dimm ? ddr3: two per dimm ddr_b_csb_[3:0] o sstl-1.8/1.5 ddr2/ddr3 device rank 3, 2, 1, and 0 chip select ddr_b_cke_[3:0] o sstl-1.8/1.5 ddr2/ddr3 clock enable: (1 per device rank) ddr_b_odt_[3:0] o sstl-1.8/1.5 ddr2/ddr3 device rank 3, 2, 1, and 0 on die termination ddr_b_ma_[14:0] o sstl-1.8/1.5 ddr2/ddr3 address signals [14:0] ddr_b_bs_[2:0] o sstl-1.8/1.5 ddr2/ddr3 bank select ddr_b_rasb o sstl-1.8/1.5 ddr2/ddr3 row address select signal ddr_b_casb o sstl-1.8/1.5 ddr2/ddr3 column a ddress select signal ddr_b_web o sstl-1.8/1.5 ddr2/ddr3 write enable signal ddr_b_dq_[63:0] i/o sstl-1.8/1.5 ddr2/ddr3 data lines ddr_b_dm_[7:0] o sstl-1.8/1.5 ddr2/ddr3 data mask ddr_b_dqs_[7:0] i/o sstl-1.8/1.5 ddr2/ddr3 data strobes ddr_b_dqsb_[7:0] i/o sstl-1.8/1.5 ddr2/ddr3 data strobe complements datasheet 41 signal description 2.2.3 system memory miscellaneous signals 2.3 pci express* interface signals signal name type description ddr_rpd i/o a system memory pull-down rcomp ddr_rpu i/o a system memory pull-up rcomp ddr_spd i/o a system memory pull-down rcomp ddr_spu i/o a system memory pull-up rcomp ddr_vref i a system memory reference voltage ddr3_dram_pwrok i a ddr3 vcc_ddr power ok ddr3_dramrstb o sstl-1.5 ddr3 reset signal ddr3_a_csb1 o sstl-1.8/1.5 ddr3 csb1 signal ddr3_a_ma0 o sstl-1.8/1.5 ddr3 ma0 signal ddr3_a_web o sstl-1.8/1.5 ddr3 web signal ddr3_b_odt3 o sstl-1.8/1.5 ddr3 odt3 signal signal name type description peg_rxn_[15:0] peg_rxp_[15:0] i/o pcie primary pci express receive differential pair peg_txn_[15:0] peg_txp_[15:0] o pcie primary pci express tran smit differential pair exp_icompo i a primary pci express output current compensation exp_compi i a primary pci express input current compensation exp_rcompo i a primary pci express re sistive compensation exp_rbias i a primary pci express bias signal description 42 datasheet 2.4 controller link interface signals 2.5 analog display signals (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) signal name type description cl_data i/o cmos controller link data (bi-directional) cl_clk i/o cmos controller link clock (bi-directional) cl_vref i cmos controller link vref cl_rst# i cmos controller link reset (active low) signal name type description crt_red o a red analog video output: this signal is a crt analog video output from the internal color pa lette dac. the dac is designed for a 37.5 ohm routing impedance bu t the terminating resistor to ground will be 75 ohms. (e.g., 75 ohm resistor on the board, in parallel with a 75 ohm crt load). crt_green o a green analog video output: this signal is a crt analog video output from the internal color pa lette dac. the dac is designed for a 37.5 ohm routing impedance bu t the terminating resistor to ground will be 75 ohms. (e.g., 75 ohm resistor on the board, in parallel with a 75 ohm crt load). crt_blue o a blue analog video output: this signal is a crt analog video output from the internal color pa lette dac. the dac is designed for a 37.5 ohm routing impedance bu t the terminating resistor to ground will be 75 ohms. (e.g., 75 ohm resistor on the board, in parallel with a 75 ohm crt load). crt_iref i/o a resistor set: set point resistor for the internal color palette dac. a 255 ohm 1% resistor is required between crt_iref and motherboard ground. crt_hsync o hvcmos crt horizontal synchronization: this signal is used as the horizontal sync (polarity is programmable) or ?sync interval?. 2.5 v output. crt_vsync o hvcmos crt vertical synchronization: this signal is used as the vertical sync (polarity is programmable). 2.5 v output. crt_ddc_clk i/o cod monitor control clock crt_ddc_data i/o cod monitor control data crt_irtn i/o cod monitor interrupt return datasheet 43 signal description 2.6 clocks, reset, and miscellaneous signal name type description hpl_clkinp hpl_clkinn i cmos differential host clock in: these pins receive a differential host clock from the external clock synthesizer. this clock is used by all of the (g)mch logic that is in the host clock domain. exp_clkp exp_clkn i cmos differential primary pci express clock in: these pins receive a differential 100 mhz se rial reference clock from the external clock synthesizer. this clock is used to generate the clocks necessary for the support of primary pci express and dmi. dpl_refclkinn dpl_refclkinp i cmos display pll differential clock in: tie dpl_refclkinp to v cc and tie dpl_refclkinn to ground when not using dp. dpl_refssclkinp dpl_refssclkinn i cmos display pll differential clock in: tie dpl_refssclkinp to v cc and tie dpl_refssclkinn to ground when not using dp. rstinb i sstl reset in: when asserted, this sign al will asynchronously reset the (g)mch logic. this signal is connected to the pcirst# output of the ich. al l pci express output signals and dmi output signals will also tri-state compliant to pci express specification, revision 2.0 . this input should have a schmitt trigger to avoid spurious resets. this signal is required to be 3.3 v tolerant. cl_pwrok i/o sstl cl power ok: when asserted, cl_pwrok is an indication to the (g)mch that core power (vcc_cl) has been stable for at least 10 us. exp_slr i cmos pci express* static lane reversal/form factor selection: (g)mch?s pci express lane numbers are reversed to differentiate balanced tech nology extended (btx) and atx form factors. 0 = (g)mch pci express lane numbers are reversed (btx) 1 = normal operation (atx) bsel[2:0] i cmos bus speed select: at the de-assertion of pwrok, the value sampled on these pins determin es the expected frequency of the bus. exp_sm i gtl+ concurrent pci express port enable: concurrent sdvo and pci express 0 = only sdvo or pci express is operational. 1 = both sdvo and pci express are operating simultaneously via the pci express port. note: for the 82p45 and 82p42 mch, this signal should be pulled low. pwrok i/o sstl power ok: when asserted, pwrok is an indication to the (g)mch that core po wer has been stable for at least 10 us. dprstpb o hvcmos advanced power management signal signal description 44 datasheet 2.7 direct media interface slpb o hvcmos advanced power ma nagement signal ich_syncb o hvcmos ich sync signal allztest i gtl+ all z test: this signal is used for chipset bed of nails testing to execute all z test. it is used as output for xor chain testing. xortest i gtl+ xor chain test: this signal is used for chipset bed of nails testing to execute xor chain test. cen i gtl+ tls confidentiality enable: 0 = disable tls 1 = enable tls itpm_enb i gtl+ integrated tpm enable: 0 = enable intel tpm 1 = disable intel tpm note: this signal is not used on the 82g45, 82g43, 82g41 gmch and 82p45, 82p43 mch. dualx8_enable i gtl+ 2x8 peg port bifurcation: 0 = 2x8 pci express ports enabled 1 = 1x16 pci express port enabled bscantest i gtl+ boundary scan test enable: this signal is used to enter boundary scan mode jtag_tck i/o sstl jtag clock jtag_tdi i/o sstl jtag data in jtag_tdo i/o sstl jtag data out jtag_tms i/o sstl jtag test mode select signal name type description signal name type description dmi_rxp_[3:0] dmi_rxn_[3:0] i dmi direct media interface: receive differential pair (rx). (g)mch-ich serial interface input. dmi_txp_[3:0] dmi_txn_[3:0] o dmi direct media interface: transmit differential pair (tx). (g)mch-ich serial interface output. datasheet 45 signal description 2.8 serial dvo interface (intel ? 82q45, 82q43, 82b 43, 82g45, 82g43, 82g41 gmch only) most of these signals are multiplexed wi th pci express signals. sdvo_cttclk and sdvo_ctrldata are the only unmultiplexed si gnals on the sdvo interface. sdvo is mapped to lanes 0?7 or lanes 15?8 of the peg port depending on the pci express static lane reversal and sdvo/pci express coexistence straps. the lower 8 lanes are used when both straps are either asserted or not asserted. otherwise, the upper 8 lanes are used. signal name type description sdvob_clk- o pcie serial digital video channel b clock complement sdvob_clk+ o pcie serial digital video channel b clock sdvob_red- o pcie serial digital video channel c red complement sdvob_red+ o pcie serial digital video channel c red sdvob_green- o pcie serial digital video channel b green complement sdvobgreen+ o pcie serial digital video channel b green sdvob_blue- o pcie serial digital video ch annel b blue complement sdvob_blue+ o pcie serial digital video channel b blue sdvoc_red- o pcie serial digital video channel c red complement sdvoc_red+ o pcie serial digital video cha nnel c red channel b alpha sdvoc_green- o pcie serial digital video channel c green complement sdvoc_green+ o pcie serial digital video channel c green sdvoc_blue- o pcie serial digital video ch annel c blue complement sdvoc_blue+ o pcie serial digital video channel c blue sdvoc_clk- o pcie serial digital video channel c clock complement sdvoc_clk+ o pcie serial digital video channel c clock signal description 46 datasheet sdvo_tvclkin- i pcie serial digital video tvout synchronization clock complement sdvo_tvclkin i pcie serial digital video tvout synchronization clock sdvob_int- i pcie serial digital video input interrupt complement sdvob_int+ i pcie serial digital video input interrupt sdvoc_int- i pcie serial digital video input interrupt complement sdvoc_int+ i pcie serial digital video input interrupt sdvo_stall- i pcie serial digital video field stall complement sdvo_stall+ i pcie serial digital video field stall sdvo_ctrlclk i/o cod serial digital video device control clock sdvo_ctrldata i/o cod serial digital video device control data signal name type description datasheet 47 signal description table 3. sdvo, display port, hdmi/d vi, pci express* signal mapping configuration-wise mapping pcie ? normal pcie ? reversed sdvo signal display port hdmi/dvi peg_txp7 peg_txp8 sdvoc_clkp dpc_lane3 tmds_clk peg_txn7 peg_txn8 sdvoc_clkn dpc_lane3b tmds_clkb peg_txp6 peg_txp9 sdvoc_blue dpc_lane2 tmds_data0 peg_txn6 peg_txn9 sdvoc_blue# dpc_lane2b tmds_data0b peg_txp5 peg_txp10 sdvoc_green dpc_lane1 tmds_data1 peg_txn5 peg_txn10 sdvoc_green# dpc_lane1b tmds_data1b peg_txp4 peg_txp11 sdvoc_red dpc_lane0 tmds_data2 peg_txn4 peg_txn11 sdvoc_red# dpc_lane0b tmds_data2b peg_txp3 peg_txp12 sdvob_clkp dpb_lane3 tmds_clk peg_txn3 peg_txn12 sdvob_clkn dpb_lane3b tmds_clkb peg_txp2 peg_txp13 sdvob_blue dpb_lane2 tmds_data0 peg_txn2 peg_txn13 sdvob_blu e# dpb_lane2b tmds_data0b peg_txp1 peg_txp14 sdvob_green dpb_lane1 tmds_data1 peg_txn1 peg_txn14 sdvob_green# dpb_lane1b tmds_data1b peg_txp0 peg_txp15 sdvob_red dpb_lane0 tmds_data2 peg_txn0 peg_txn15 sdvob_red# dpb_lane0b tmds_data2b peg_rxp7 peg_rxp8 dpc_hpd port-c_hpd peg_rxn7 peg_rxn8 peg_rxp6 peg_rxp9 dpc_aux peg_rxn6 peg_rxn9 dpc_auxb peg_rxp5 peg_rxp10 sdvoc_int peg_rxn5 peg_rxn10 sdvoc_int# peg_rxp4 peg_rxp11 peg_rxn4 peg_rxn11 peg_rxp3 peg_rxp12 dpb_hpd port-b_hpd peg_rxn3 peg_rxn12 peg_rxp2 peg_rxp13 sdvo_fldstall dpb_aux peg_rxn2 peg_rxn13 sdvo_fldstall# dpb_auxb peg_rxp1 peg_rxp14 sdvob_int peg_rxn1 peg_rxn14 sdvob_int# peg_rxp0 peg_rxp15 sdvo_tvclkin signal description 48 datasheet 2.9 hdmi interface (intel ? 82g45, 82g43, 82g41, 82b43 gmch only) signal name type description hdmib_clk- o pcie serial digital video channel b clock complement: multiplexed with exp_txn_3/exp_txn_12. hdmib_clk+ o pcie serial digital video channel b clock: multiplexed with exp_txp_3/exp_ txp_12. hdmib_red- o pcie serial digital video channel b red complement: multiplexed with / exp_txn_0./exp_txn_15 hdmib_red+ o pcie serial digital video channel b red: multiplexed with exp_txp_0/exp__txp_15. hdmib_green- o pcie serial digital video channel b green complement: multiplexed with exp_txn_1/exp_txn_14. hdmibgreen+ o pcie serial digital video channel b green: multiplexed with exp_txp_1/exp_txp_14. hdmib_blue- o pcie serial digital video cha nnel b blue complement. multiplexed with exp_txn_2/exp_txn_13. hdmib_blue+ o pcie serial digital video channel b blue: multiplexed with exp_txp_2/exp_txp_13. hdmic_red- o pcie serial digital video channel c red complement: multiplexed with exp_txn_4/exp_txn_11. hdmic_red+ o pcie serial digital video channel c red: multiplexed with exp_txp_4/exp_txp_11. hdmic_green- o pcie serial digital video channel c green complement: multiplexed with exp_txn_5/exp_txn_10. hdmic_green+ o pcie serial digital video channel c green: multiplexed with exp_txp_5/exp_txp_10. hdmic_blue- o pcie serial digital video cha nnel c blue complement: multiplexed with exp_txn_6/exp_txn_9. hdmic_blue+ o pcie serial digital vide o channel c blue: multiplexed with exp_txp_6/exp_txp_9. hdmic_clk- o pcie serial digital video channel c clock complement: multiplexed with exp_txn_7/exp_txn_8. hdmic_clk+ o pcie serial digital video channel c clock: multiplexed with exp_txn_7/exp_txp_8. hdmi_tvclkin- i pci e serial digital video tvout synchronization clock complement: multiplexed with exp_rxn_0/exp_rxn_15 hdmi_tvclkin i pcie serial digital video tvout synchronization clock: multiplexed with exp_rxp_0/exp_rxp_15. hdmib_int- i pcie serial digital video input interrupt complement: multiplexed with exp_rxn_3/exp_rxn_12. datasheet 49 signal description note: hdmi support on 82b43 is enabled via intel? upgrade service 2.10 display port interface (intel ? 82q45, 82q43, 82b 43, 82g45, 82g43, 82g41 gmch only) hdmib_int+ i pcie serial digital video input interrupt: multiplexed with exp_rxp_3/exp_rxp_12 hdmic_int- i cie serial digital video input interrupt: multiplexed with exp_rxn_7/exp_rxn_8. hdmic_int+ i pcie serial digital video input interrupt: multiplexed with exp_rxp_7/exp_rxp_8. sdvo_ctrlclk i/o cod hdmi port b control clock: (this pin is shared with sdvo) sdvo_ctrldata i/o cod hdmi port b control data: (this pin is shared with sdvo) ddpc_ctrlclk i/o cod hdmi port c control clock: also used as the dp ctrlclk ddpc_ctrldata i/o cod hdmi port c control data: also used as the dp ctrldata signal name type description dpb_aux# o pcie display port baux channel: multiplexed with exp_rxn_02 dpb_aux o pcie display port baux channel: multiplexed with exp_rxp_02 dpb_hdp o pcie display port b hot plug detect: multiplexed with exp_rxp_03 dpc_aux# o pcie display port c aux channel: multiplexed with exp_rxn_06 dpc_aux o pcie display port c aux channel: multiplexed with exp_rxp_06 dpc_hdp o pcie display port c hot plug detect: multiplexed with exp_rxp_07 dpb_lane0# o pcie display port b data lane: multiplexed with exp_txn_00 dpb_lane0 o pcie display port b data lane: multiplexed with exp_txp_00 dpb_lane1# o pcie display port b data lane: multiplexed with exp_txn_01 dpb_lane1 o pcie display port b data lane: multiplexed with exp_txp_01 signal name type description signal description 50 datasheet 2.11 intel ? high definition audio intel ? 82q45, 82q43, 82b43,82g45, 82g 43, 82g41 gmch only) dpb_lane2# o pcie display port b data lane: multiplexed with exp_txn_02 dpb_lane2 o pcie display port b data lane: multiplexed with exp_txp_02 dpb_lane3# o pcie display port b data lane: multiplexed with exp_txn_03 dpb_lane3 o pcie display port b data lane: multiplexed with exp_txp_03 dpc_lane0# o pcie display port c data lane: multiplexed with exp_txn_04 dpc_lane0 o pcie display port c data lane: multiplexed with exp_txp_04 dpc_lane1# o pcie display port c data lane: multiplexed with exp_txn_05 dpc_lane1 o pcie display port c data lane: multiplexed with exp_txp_05 dpc_lane2# o pcie display port c data lane: multiplexed with exp_txn_06 dpc_lane2 o pcie display port c data lane: multiplexed with exp_txp_06 dpc_lane3# o pcie display port c data lane: multiplexed with exp_txn_07 dpc_lane3 o pcie display port c data lane: multiplexed with exp_txp_07 signal name type description name type description hda_bclk i cmos hda bus clock hda_rst i cmos hda reset hda_sdi o cmos hda serial data in: wrt ich10/ich7 hda_sdo i cmos hda serial data out: wrt ich10/ich7 hda_sync i cmos hda sync datasheet 51 signal description 2.12 power and grounds name voltage description vcc 1.1 v core power vtt_fsb 1.1 v processor system bus power vcc_exp 1.5 v pci express* and dmi power vcca_exp 1.5 v pci express* pll power vccavrm_exp 1.1v internal pcie gen2 pll filter vcc_sm 1.8 v/1.5v ddr2/ddr3 system memory power vcc_smclk 1.8v/1.5v ddr2/ddr3 system clock memory power vcccml_ddr 1.1 v ddr2/ddr3 analog power vcc3_3 3.3 v 3.3 v cmos power vcca_dplla 1.1 v display pll a analog power vcca_dpllb 1.1 v display pll b analog power vcca_hpll 1.1 v host pll analog power vccd_hpll 1.1v host pll analog power vcca_mpll 1.1 v system memory pll analog power vcca_dac 3.3 v display dac analog power vcc3_3 3.3 v vcc 3.3 v vccdq_crt 1.5/1.8 v display digital supply power vcc_cl 1.1 v controller link aux power vcc_hda 1.5 v intel integrated hda power vss 0 v ground signal description 52 datasheet datasheet 53 system address map 3 system address map the (g)mch supports 64 gb (36 bit) of host address space and 64 kb+3 of addressable i/o space. there is a programmable memory address space under the 1 mb region which is divided into regions which can be individually controlled with programmable attributes such as disable, read/write, write only, or read only. attribute programming is described in the register description section. this section focuses on how the memory space is partitioned and what the separate memory regions are used for. i/o address space has simpler mapping and is explained near the end of this section. note: references to the internal graphics device (igd) apply to the 82q45, 82q43, 82b43, 82g45, 82g43,and 82g41 gmch only. the (g)mch supports pci express* upper pr e-fetchable base/limit registers. this allows the pci express unit to claim io accesses above 36 bit, complying with the pci express specification . addressing of greater than 8 gb is allowed on either the dmi interface or pci express interface. the (g)m ch supports a maximum of 8 gb of dram. no dram memory will be accessible above 8 gb. when running in internal graphics mode, writes to gmadr range linear range are supported. write accesses to linear regions are supported from dmi only. write accesses to tilex and tiley regions (defined via fence registers) are not supported from dmi or the peg port. gmadr read accesses are not supported from either dmi or peg. in the following sections, it is assumed that all of the compatibility memory ranges reside on the dmi interface. the exception to this rule is vga ranges, which may be mapped to pci express or dmi, or to the in ternal graphics device (igd). in the absence of more specific references, cycle description s referencing pci should be interpreted as the dmi interface/pci, while cycle descrip tions referencing pci express or igd are related to the pci express bus or the internal graphics device respectively. the (g)mch does not remap apic or any other memory spaces above tolud (top of low usable dram). the tolud register is set to the appropriate value by bios. the reclaim base/ reclaim limit registers remap logical accesses bound for addresses above 4 gb onto physical addresses that fall within dram. the address map includes a number of programmable ranges: ? device 0 ? pxpepbar ? egress port registers. ne cessary for setting up vc1 as an isochronous channel using time based weighted round robin arbitration. (4 kb window) ? mchbar ? memory mapped range for inte rnal (g)mch regist ers. for example, memory buffer register controls. (16 kb window) ? pciexbar ? flat memory-mapped address spaced to access device configuration registers. this mechanism can be used to access pci configuration space (0?ffh) and extend ed configuration space (100h?fffh) for pci express devices. this enhanced configuration access mechanism is defined in the pci express specification. (64 mb, 128 mb, or 256 mb window). ? dmibar ?this window is used to access registers associated with the direct media interface (dmi) register memory range. (4 kb window) ? ggcgms ? gmch graphics control register, graphics mode select (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only). this register is used to select the amount of main memory that is pre-allocated to support the internal system address map 54 datasheet graphics device in vga (non-linear) and native (linear) modes. (0?256 mb options). ? ggcggms ? gmch graphics control register, gtt graphics memory size (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only). this register is used to select the amount of main memory that is pre-allocated to support the internal graphics translation table. (0?2 mb options). ? device 1 ? mbase1/mlimit1 ? pci express port no n-prefetchable memory access window. ? pmbase1/pmlimit1 ? pci express port prefetchable memory access window. ? pmubase/pmulimit ? pci express port upper prefetchable memory access window ? iobase1/iolimit1 ? pci express port i/o access window. ? device 2, function 0 (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ? mmadr ? igd registers and internal graphics instruction port. (512 kb window) ? iobar ? i/o access window for internal graphics. though this window address/ data register pair, using i/o semantics, the igd and internal graphics instruction port registers can be accessed. note that this allows accessing the same registers as mmadr. in addition, the iobar can be used to issue writes to the gttadr table. ? gmadr ? internal graphics translation window. (128 mb, 256 mb or 512 mb window). ? gttadr ? internal graphics translation table location. (1 mb window). note that the base of gtt stolen memory register (device 0 a8) indicates the physical address base which is 1 mb aligned. ? device 2, function 1 (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) ? mmadr ? function 1 igd registers and internal graphics instruction port. (512 kb window) ? device 3 ?me control ? device 6, function 0 (82p45 mch only) ? mbase1/mlimit1 ? pci express port no n-prefetchable memory access window. ? pmbase1/pmlimit1 ? pci express port prefetchable memory access window. ? pmubase/pmulimit ? pci express port upper prefetchable memory access window ? iobase1/iolimit1 ? pci express port io access window. the rules for the above programmable ranges are: 1. all of these ranges must be unique and non-overlapping. it is the bios or system designers' responsibility to limit me mory population so that adequate pci, pci express, high bios, and pci express memory mapped space, and apic memory space can be allocated. 2. in the case of overlapping ranges with memory, the memory decode will be given priority. this is an intel trusted execution technology requirement. it is necessary to get intel tet protection checks, avoiding potential attacks. 3. there are no hardware interlocks to prev ent problems in the case of overlapping ranges. 4. accesses to overlapped ranges may produce indeterminate results. datasheet 55 system address map 5. the only peer-to-peer cycles allowed belo w the top of low usable memory (register tolud) are dmi interface to pci express vga range writes. note that peer to peer cycles to the internal graphics vga range are not supported. figure 5 represents system memory address map in a simplified form. system address map 56 datasheet note: for non-amt system, do not fo llow the ep uma requirement. figure 4. system address ranges main memory a ddress range main memory a ddress range 4g main memory reclaim a ddress range 64 g reclaim base reclaim limit = reclaim base + x os visible < 4 gb pci memory a ddress range ( subtractively decoded to dmi ) os invisible reclaim os visible > 4 gb gfx stolen ( 0 - 256 mb ) ep - uma ( 1 - 64 mb ) tom host / system view physical memory ( dram controller view ) tseg tseg ( 0 - 8 mb ) x 0 0 pci memory a ddress range ( subtractivel y decoded to dmi ) tseg base gfx gtt stolen base ep stolen base 1 mb ali g ned 1 mb aligned 64 mb ali g ned 1 mb aligned 64 mb aligned 64 mb aligned 64 mb ali g ned for reclaim 0 mb - 63 mb wasted 64 mb ali g ned tolud base 64 mb ali g ned touud base legacy a ddress range 1 mb independentl y pro g rammable non - overlappin g windows device 0 bars ( pxpepbar , mchbar , pciexbar , dmibar ) device 1 bars ( mbase 1 / mlimit 1, pmbase 1 / pmlimit 1 ) device 0 ggc ( graphics stolen memor y , graphics gtt stolen memor y ) device 2 ( mmadr , gmadr , gttadr ) device 3 ( ephecibar , epheci 2 bar , epktbar ) independentl y pro g rammable non - overlappin g windows device 0 bars ( pxpepbar , mchbar , pciexbar , dmibar ) device 1 bars ( pmubase 1 / pmulimit 1 ) device 3 ( ephecibar , epheci 2 bar ) mc hbar ( gfxvtbar , dmivc 1 bar , vtmebar , vtdpvc 0 bar ) gfx - gtt ( 0 - 2 mb ) gfx stolen base 1 mb aligned datasheet 57 system address map 3.1 legacy address range this area is divided into the following address regions: ? 0 ? 640 kb ? dos area ? 640 ? 768 kb ? legacy video buffer area ? 768 ? 896 kb in 16 kb sections (total of 8 sections) ? expansion area ? 896 ? 960 kb in 16 kb sections (total of 4 sections) ? extended system bios area ? 960 kb - 1 mb memory ? system bios area 3.1.1 dos range (0h ? 9_ffffh) the dos area is 640 kb (0000_0000h ? 0009_ffffh) in size and is always mapped to the main memory controlled by the (g)mch. 3.1.2 legacy video area (a_0000h?b_ffffh) the legacy 128 kb vga memory range, frame buffer, (000a_0000h ? 000b_ffffh) can be mapped to igd (device 2), to pci express (device 1), and/or to the dmi interface. the appropriate mapping depends on which devices are enabled and the programming of the vga steering bits. based on the vga steering bits, priority for vga mapping is constant. the (g)mch always decodes internally mapped devices first. internal to the (g)mch, decode precedence is always given to igd. the (g)mch always positively decodes internally mapped devices, namely the igd and pci express. subsequent figure 5. dos legacy address range expansion area 128 kb (16kbx8) 000c_0000h 000d_ffffh 896 kb extended system bios (lower) 64 kb (16kbx4) 000e_0000h 000e_ffffh 960 kb legacy video area (smm memory) 128 kb 000a_0000h 000b_ffffh 768 kb dos area 0000_0000h 0009_ffffh 640 kb system bios (upper) 64 kb 000f_0000h 000f_ffffh 1 mb system address map 58 datasheet decoding of regions mapped to pci expr ess or the dmi interface depends on the legacy vga configuration bits (vga enable and mdap). this region is also the default for smm space. compatible smram address range (a_0000h?b_ffffh) when compatible smm space is enabled, smm-mode processor accesses to this range are routed to physical system dram at 000a 0000h ? 000b ffffh. non-smm-mode processor accesses to this range are considered to be to the video buffer area as described above. pci express and dmi origin ated cycles to enabled smm space are not allowed and are considered to be to the video buffer area if igd is not enabled as the vga device. pci express and dmi initiated cycles are attempted as peer cycles, and will master abort on pci if no external vga device claims them. monochrome adapter (mda) range (b_0000h?b_7fffh) legacy support requires the ability to have a second graphics controller (monochrome) in the system. accesses in the standard vga range are forwarded to igd, pci express, or the dmi interface (depending on configuration bits). since the monochrome adapter may be mapped to anyone of these devices, the (g)mch must decode cycles in the mda range (000b_0000h ? 000b_7fffh) and forw ard either to igd, pci express, or the dmi interface. this capability is contro lled by a vga steering bits and the legacy configuration bit (mdap bit). in addition to the memory range b0000h to b7fffh, the (g)mch decodes i/o cycles at 3b4h, 3b5h, 3b8h, 3b9h, 3bah and 3bfh and forwards them to the either igd, pci express, and/or the dmi interface. peg 16-bit vga decode the pci to pci bridge architecture specification, revision 1.2 , states that 16-bit vga decode be a feature. it is expected that once the official version of the pci to pci bridge architecture specification, revision 1.2 , has been released that microsoft will include a windows logo program requirement that devices are comp liant to this version of specification. a draft version of the windows logo program 3.0 document includes this requirement as a proposed requirement; also microsoft may potentially make this an out of band update to the existing wlp2.1a requirements. the vga 16-bit decode originally was described in an ecr to the pci to pci bridge architecture specification, revision 1.1 , this is now listed as a required feature in the updated 1.2 specification. datasheet 59 system address map 3.1.3 expansion area (c_0000h-d_ffffh) this 128 kb isa expansion region (000c _0000h ? 000d_ffffh) is divided into eight 16 kb segments. each segment can be assigned one of four read/write states: read- only, write-only, read/write, or disabled. typically, these blocks are mapped through the (g)mch and are subtractive decoded to is a space. memory that is disabled is not remapped. non-snooped accesses from pci express or dm i to this region are always sent to dram. 3.1.4 extended system bios area (e_0000h?e_ffffh) this 64 kb area (000e_0000h ? 000e_ffffh) is divided into four 16 kb segments. each segment can be assigned independent read and write attributes so it can be mapped either to main dram or to dmi interface. typically, this area is used for ram or rom. memory segments that are disabled are not remapped elsewhere. non-snooped accesses from pci express or dm i to this region are always sent to dram. table 4. expansion area memory segments memory segments attributes comments 0c0000h ? 0c3fffh we re add-on bios 0c4000h ? 0c7fffh we re add-on bios 0c8000h ? 0cbfffh we re add-on bios 0cc000h ? 0cffffh we re add-on bios 0d0000h ? 0d3fffh we re add-on bios 0d4000h ? 0d7fffh we re add-on bios 0d8000h ? 0dbfffh we re add-on bios 0dc000h ? 0dffffh we re add-on bios table 5. extended system bios area memory segments memory segments attributes comments 0e0000h ? 0e3fffh we re bios extension 0e4000h ? 0e7fffh we re bios extension 0e8000h ? 0ebfffh we re bios extension 0ec000h ? 0effffh we re bios extension system address map 60 datasheet 3.1.5 system bios area (f_0000h?f_ffffh) this area is a single 64 kb segment (000f_0000h ? 000f_ffffh). this segment can be assigned read and write attributes. it is, by default (after reset), read/write disabled and cycles are forwarded to the dmi interface. by manipulating the read/write attributes, the (g)mch can ?shadow? bios into the main dram. when disabled, this segment is not remapped. non-snooped accesses from pci express or dmi to this region are always sent to dram. 3.1.6 pam memory area details the 13 sections from 768 kb to 1 mb comprise what is also known as the pam memory area. the (g)mch does not handle iwb (implicit write-back) cycles targeting dmi. since all memory residing on dmi should be set as non-cacheable, there will normally not be iwb cycles targeting dmi. however, dmi be comes the default target for processor and dmi originated accesses to disabled segments of the pam region. if the mtrrs covering the pam regions are set to wb or rd, it is possible to get iwb cycles targeting dmi. this may occur for processor-originated cycl es (in a dp system) and for dmi-originated cycles to disabled pam regions. for example, say that a particular pam region is set for ?read disabled? and the mtrr associated with this region is set to wb. a dmi master generates a memory read targeting the pam region. a snoop is generate d on the fsb and the result is an iwb. since the pam region is ?read disabled? the default target for the memory read becomes dmi. the iwb associated with this cycle will cause the (g)mch to hang. non-snooped accesses from pci express or dmi to this region are always sent to dram. 3.2 main memory address range (1mb ? tolud) this address range extends from 1 mb to the top of low usable physical memory that is permitted to be accessible by the (g)mch (a s programmed in the tolud register). all accesses to addresses within this range will be forwarded by the (g)mch to the dram unless it falls into the optional tseg, or optional isa hole, or optional igd stolen vga memory. table 6. system bios area memory segments memory segments attributes comments 0f0000h ? 0fffffh we re bios area datasheet 61 system address map 3.2.1 isa hole (15 mb ?16 mb) a hole can be created at 15 mb?16 mb as cont rolled by the fixed hole enable in device 0 space. accesses within this hole are forw arded to the dmi interface. the range of physical dram memory disabled by opening th e hole is not remapped to the top of the memory ? that physical dram space is not accessible. this 15 mb?16 mb hole is an optionally enabled isa hole. video accelerators originally used this hole. it is also used by validation and customer sv teams for some of their test cards. that is why it is being supported. there is no inherent bios request for the 15 mb?16 mb window. figure 6. main memory address range dos compatibility memory main memory isa hole (optional) main memory main memory tseg (1mb/2mb/8mb, optional) pci memory range lt flash apic 4 gb 0h 0010_0000h 00f0_0000h 0100_0000h 8 gb ffff_ffffh . . . . . system address map 62 datasheet 3.2.2 tseg tseg is optionally 1 mb, 2 mb, or 8 mb in size. tseg is below igd stolen memory, which is at the top of low usable physic al memory (tolud). smm-mode processor accesses to enabled tseg access the physical dram at the same address. non- processor originated accesses are not allowe d to smm space. pci express, dmi, and internal graphics originated cycles to enab led smm space are handled as invalid cycle type with reads and writes to location 0 an d byte enables turned off for writes. when the extended smram space is enabled, proc essor accesses to the tseg range without smm attribute or without wb attribute ar e also forwarded to memory as invalid accesses. non-smm-mode write back cycles that target tseg space are completed to dram for cache coherency. when smm is enabled, the maximum amount of memory available to the system is equal to the amount of physical dram minus the value in the tseg register, which is fixed at 1 mb, 2 mb, or 8 mb. 3.2.3 pre-allocated memory voids of physical addresses that are not accessible as general system memory and reside within system memory address range (< tolud) are created for smm-mode, legacy vga graphics compatibility, and gfx gtt stolen memory. it is the responsibility of bios to prop erly initialize these regions. ta b l e 7 details the location and attributes of the regions. enab ling/disabling these ranges are described in the (g)mch control register device 0 (gcc). table 7. pre-allocated memory example for 64 mb dram, 1 mb vga, 1 mb gtt stolen and 1 mb tseg memory segments attributes comments 0000_0000h ? 03cf_ffffh r/w available system memory 61 mb 03d0_0000h ? 03df_ffffh smm mode only - processor reads tseg address range & pre-allocated memory 03e0_0000h ? 03ef_ffffh r/w pre-allocated graphics vga memory. 1 mb (or 4/8/16/32/64/128/256 mb) when igd is enabled. 03f0_0000h ? 03ff_ffffh r/w pre-allocated graphics gtt stolen memory. 1 mb (or 2 mb) when igd is enabled. datasheet 63 system address map 3.3 pci memory address range (tolud ? 4 gb) this address range, from the top of low usable dram (tolud) to 4 gb is normally mapped to the dmi interface. device 0 exceptions are: ? addresses decoded to the egress port registers (pxpepbar). ? addresses decoded to the memory mapped range for internal (g)mch registers (gmchbar). ? addresses decoded to the flat memory-m apped address spaced to access device configuration registers (pciexbar). ? addresses decoded to the registers associated with the direct media interface (dmi) register memory range (dmibar). with pci express port, there are two exceptions to this rule. ? addresses decoded to the pci express me mory window defined by the mbase1, mlimit1, registers are mapped to pci express. ? addresses decoded to the pci express pref etchable memory window defined by the pmbase1, pmlimit1, registers are mapped to pci express. in integrated graphics configurations, there are exceptions to this rule (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only): 1. addresses decoded to the igd registers and internal graphics instruction port (function 0 mmadr, function 1 mmadr). 2. addresses decode to the internal graphics translation window (gmadr) 3. addresses decode to the internal graphics translation table (gttadr) in an intel me configuration, there are exceptions to this rule: 1. addresses decoded to the me keyboard and text mmio range (epktbar) 2. addresses decoded to the me heci mmio range (ephecibar) 3. addresses decoded to the me heci2 mmio range (epheci2bar) in a virtualization technology (vt) enable co nfiguration, there are exceptions to this rule (82q45 gmch only): 1. addresses decoded to the memory mappe d window to graphics vt remap engine registers (gfxvtbar) 2. addresses decoded to the memory mapped window to dmi vc1 vt remap engine registers (dmivc1bar) 3. addresses decoded to the memory mapped window to me vt remap engine registers (vtmebar) addresses decoded to the memory mapped window to peg/dmi vc0 vt remap engine registers (vtdpvc0bar) some of the mmio bars may be mapped to this range or to the range above touud. there are sub-ranges within the pci memory address range defined as apic configuration space, fsb interrupt spac e, and high bios address range. the exceptions listed above for internal graphics and the pci express ports must not overlap with these ranges. system address map 64 datasheet figure 7. pci memory address range dmi interface (subtractive decode) fef0_0000h 4 gb ? 2 mb fsb interrupts fee0_0000h pci express configuration space e000_0000h high bios ffe0_0000h ffff_ffffh 4 gb 4 gb ? 17 mb dmi interface (subtractive decode) fed0_0000h 4 gb ? 18 mb local (cpu) apic fec8_0000h 4 gb ? 19 mb i/o apic fec0_0000h 4 gb ? 20 mb dmi interface (subtractive decode) f000_0000h 4 gb ? 256 mb possible address range/ size (not ensured) 4 gb ? 512 mb dmi interface (subtractive decode) tolud optional hseg feda_0000h to fedb_ffffh bars, internal graphics ranges, pci express port could be here. datasheet 65 system address map 3.3.1 apic configuration space (fec0_0000h?fecf_ffffh) this range is reserved for apic configuratio n space. the i/o apic(s) usually reside in the ich portion of the chip-set, but may also exist as stand-alone components like pxh. the ioapic spaces are used to communicate with ioapic interrupt controllers that may be populated in the system. since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. processor accesses to the default ioapic region (fec0_0000h to fec7_ffffh) are always forwarded to dmi. the (g)mch optionally supports additional i/o apics behind the pci express ?graphics? port. when enabled via the pci express config uration register (device 1 offset 200h), the pci express port will positively decode a subset of the apic configuration space ? specifically fec8_0000h through fecf_ffffh. memory request to this range would then be forwarded to the pci express port. this mode would be disabled in typical desktop systems. when disabled, any access within entire apic configuration space (fec0_0000h to fecf_ffffh) is forwarded to dmi. 3.3.2 hseg (feda_0000h?fedb_ffffh) this optional segment from feda_0000h to fedb_ffffh provides a remapping window to smm memory. it is sometimes called the high smm memory space. smm-mode processor accesses to the optionally enabled hseg are remapped to 000a_0000h?000b_ffffh. non-smm-mode proc essor accesses to enabled hseg are considered invalid and are term inated immediately on the fs b. the exceptions to this rule are non-smm-mode write back cycles which are remapped to smm space to maintain cache coherency. pci express an d dmi originated cycles to enabled smm space are not allowed. physical dram behi nd the hseg transaction address is not remapped and is not accessible. all cacheline wr ites with wb attribute or implicit write backs to the hseg range are completed to dram like an smm cycle. 3.3.3 fsb interrupt memo ry space (fee0_0000?feef_ffff) the fsb interrupt space is the address used to deliver interrupts to the fsb. any device on pci express or dmi may issue a memory write to 0feex_xxxxh. the (g)mch will forward this memory write along with the data to the fsb as an interrupt message transaction. the (g)mch terminates the fsb transaction by providing the response and asserting htrdyb. this memory write cycle does not go to dram. 3.3.4 high bios area the top 2 mb (ffe0_0000h?ffff_ffffh) of the pci memory address range is reserved for system bios (high bios), extended bios for pci devices, and the a20 alias of the system bios. the processor begins execution from the high bios after reset. this region is mapped to dmi interface so that the upper subset of this region aliases to 16 mb?256 kb range . the actual address space required for the bios is less than 2 mb but the minimum processor mtrr range for this region is 2 mb so that full 2 mb must be considered. system address map 66 datasheet 3.4 main memory address space (4 gb to touud) the (g)mch supports 36 bit addressing. the maximum main memory size supported is 8 gb total dram memory. a hole between tolud and 4 gb occurs when main memory size approaches 4 gb or larger. as a result, tom, and touud registers and reclaimbase/reclaimlimit registers become relevant. the new reclaim configuration registers exist to reclaim lost main memory space. the greater than 32 bit reclaim handling w ill be handled similar to other (g)mchs. upstream read and write accesses above 36-bi t addressing will be treated as invalid cycles by peg and dmi. top of memory the ?top of memory? (tom) register reflects the total amount of populated physical memory. this is not necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory mapped i/o above tom). tom is used to allocate the intel ma nagement engine's stolen memory. the intel me stolen size register reflects the total am ount of physical memory stolen by the intel me. the me stolen memory is located at th e top of physical memory. the me stolen memory base is calculated by subtracting th e amount of memory stolen by the intel me from tom. the top of upper usable dram (touud) register reflects the total amount of addressable dram. if reclaim is disabled, to uud will reflect tom minus intel me stolen size. if reclaim is enabled, then it will re flect the reclaim limit. also, the reclaim base will be the same as tom minus me stolen me mory size to the nearest 64 mb alignment. tolud register is restricted to 4 gb memo ry (a[31:20]), but the (g)mch can support up to 16 gb, limited by dram pins. for phys ical memory greater than 4 gb, the touud register helps identify the address range in between the 4 gb boundary and the top of physical memory. this identifies memory that can be directly accessed (including reclaim address calculation) which is useful for memory access indication, early path indication, and trusted read indication. wh en reclaim is enabled, tolud must be 64 mb aligned, but when reclaim is disabled, tolud can be 1 mb aligned. c1drb3 cannot be used directly to determ ine the effective size of memory as the values programmed in the drbs depend on the memory mode (stacked, interleaved). the reclaim base/limit registers also can not be used because reclaim can be disabled. the c0drb3 register is used for memory channel identification (channel 0 vs. channel 1) in the case of stacked memory. datasheet 67 system address map 3.4.1 memory re-claim background the following are examples of memory mapp ed io devices are typically located below 4gb: ?high bios ?hseg ?tseg ?gfx stolen ?gtt stolen ?xapic ?local apic ? fsb interrupts ? mbase/mlimit ? memory mapped i/o space that supports only 32-bit addressing the (g)mch provides the capability to re-cla im the physical memory overlapped by the memory mapped i/o logical address space. the (g)mch re-maps physical memory from the top of low memory (tolud) boundary up to the 4 gb boundary to an equivalent sized logical address range locate d just below the intel me's stolen memory. 3.4.2 memory reclaiming an incoming address (referred to as a logical ad dress) is checked to see if it falls in the memory re-map window. the bottom of the re -map window is defined by the value in the reclaimbase register. the top of the re-m ap window is defined by the value in the reclaimlimit register. an address that falls within this window is reclaimed to the physical memory starting at the address defined by the tolud register. the tolud register must be 64 mb aligned when recl aim is enabled, but can be 1 mb aligned when reclaim is disabled. 3.5 pci express* configuration address space there is a device 0 register, pciexbar, which defines the base address for the configuration space associated with all devices and functions that are potentially a part of the pci express root complex hierarchy. the size of this range will be programmable for the (g)mch. bios must assign this address range such that it will not conflict with any other address ranges. system address map 68 datasheet 3.6 pci express* address space the (g)mch can be programmed to direct memory accesses to the pci express interface when addresses are within either of two ranges specified via registers in (g)mch?s device 1 configuration space. ? the first range is controlled via the memory base register (mbase) and memory limit register (mlimit) registers. ? the second range is controlled via th e pre-fetchable memory base (pmbase) and pre-fetchable memory limit (pmlimit) registers. conceptually, address decoding for each range follows the same basic concept. the top 12 bits of the respective memory base and memory limit registers correspond to address bits a[31:20] of a memory address. for the purpose of address decoding, the (g)mch assumes that address bits a[19:0] of the memory base are zero and that address bits a[19:0] of the memory limit ad dress are fffffh. this forces each memory address range to be aligned to 1mb boundary and to have a size granularity of 1 mb. the (g)mch positively decodes memory accesses to pci express memory address space as defined by the following equations: memory_base_address address memory_limit_address prefetchable_memory_base_address address prefetchable_memory_limit_address the window size is programmed by the plug-and-play configuration software. the window size depends on the size of me mory claimed by the pci express device. normally, these ranges will reside above the top-of-low usable-dram and below high bios and apic address ranges. they must reside above the top of low memory (tolud) if they reside below 4 gb and must reside above top of upper memory (touud) if they reside above 4 gb or they will steal physical dram memory space. it is essential to support a separate pre-fetchable range in order to apply uswc attribute (from the processor point of view) to that range. the uswc attribute is used by the processor for write combining. note that the (g)mch device 1 memory range registers described above are used to allocate memory address space for any pci ex press devices sitting on pci express that require such a window. the pcicmd1 register can override the routin g of memory accesses to pci express. in other words, the memory access enable bi t must be set in th e device 1 pcicmd1 register to enable the memory base/limit and pre-fetchable base/limit windows. for the (g)mch, the upper pmubase1/pmulim it1 registers have been implemented for pci express spec compliance. the (g)mch locates mmio space above 4 gb using these registers. datasheet 69 system address map 3.7 graphics memory address ranges (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) the gmch can be programmed to direct memory accesses to igd when addresses are within any of five ranges specified via registers in gmch?s device 2 configuration space. 1. the memory map base register (mmadr) is used to access graphics control registers. 2. the graphics memory aperture base register (gmadr) is used to access graphics memory allocated via the graphics translation table. 3. the graphics translation table base register (gttadr) is used to access the translation table. these ranges can reside above the top-of-low-dram and below high bios and apic address ranges. they must reside above the top of memory (tolud) and below 4 gb so they do not steal any physical dram memory space. gmadr is a prefetchable range in order to apply uswc attribute (from the processor point of view) to that range. the uswc a ttribute is used by the processor for write combining. 3.8 system management mode (smm) system management mode uses main me mory for system management ram (smm ram). the (g)mch supports: compatible smram (c_smram), high segment (hseg), and top of memory segment (tseg). system management ram space provides a memory area that is available for the smi handlers and code and data storage. this memory resource is normally hidden fr om the system os so the processor has immediate access to this memory space up on entry to smm. the (g)mch provides three smram options: ? below 1 mb option that supports compatible smi handlers. ? above 1 mb option that allows new sm i handlers to execute with write-back cacheable smram. ? optional tseg area of 1 mb, 2 mb, or 8 mb in size. for the 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch, tseg area lies below igd stolen memory. the above 1 mb solutions require changes to compatible smram handlers code to properly execute above 1 mb. note: dmi interface and pci express masters ar e not allowed to access the smm space. 3.8.1 smm space definition smm space is defined by its addressed smm space and its dram smm space. the addressed smm space is defined as the range of bus addresses used by the processor to access smm space. dram smm space is defined as the range of physical dram memory locations containing the smm code. smm space can be accessed at one of three transaction address ranges: compatib le, high, and tseg. the compatible and tseg smm space is not remapped; therefore, the addressed and dram smm space is the same address range. since the high smm space is remapped the addressed and dram smm space is a different address range. note that the high dram space is the same as the compatible transaction address space. ta b l e 8 describes three unique address ranges: ? compatible transaction address ? high transaction address ? tseg transaction address system address map 70 datasheet 3.8.2 smm space restrictions if any of the following conditions are violated the results of smm accesses are unpredictable and may cause the system to hang: 1. the compatible smm space must not be set-up as cacheable. 2. high or tseg smm transaction address space must not overlap address space assigned to system dram, or to any ?pci? devices (including dmi interface, and pci-express, and graphics devices) . this is a bios responsibility. 3. both d_open and d_close must not be set to 1 at the same time. 4. when tseg smm space is enabled, the tseg space must not be reported to the os as available dram. this is a bios responsibility. 5. any address translated through the gmadr tlb must not target dram from a_0000-f_ffff. 3.8.3 smm space combinations when high smm is enabled (g_smrame= 1 and h_smram_en=1), the compatible smm space is effectively disabled. processor-originated accesses to the compatible smm space are forwarded to pci express if vgaen=1 (also depends on mdap), otherwise they are forwarded to the dmi interface. pci express and dmi interface originated accesses are never allowed to access smm space. 3.8.4 smm control combinations the g_smrame bit provides a global enable for all smm memory. the d_open bit allows software to write to the smm ranges without being in smm mode. bios software can use this bit to initialize smm code at powerup. the d_lck bit limits the smm range access to only smm mode accesses. the d_ cls bit causes smm (both cseg and tseg) data accesses to be forwarded to the dmi in terface or pci express. the smm software can use this bit to write to video memo ry while running smm code out of dram. table 8. transaction address rang es ? compatible, high, and tseg smm space enabled transaction address space dram space (dram) compatible 000a_0000h to 000b_ffffh 000a_0000h to 000b_ffffh high feda_0000h to fedb_ffffh 000a_0000h to 000b_ffffh tseg (tolud?stolen?tseg) to tolud?stolen (tolud?stolen?tseg) to tolud?stolen table 9. smm space table global enable g_smrame high enable h_smram_en tseg enable tseg_en compatible (c) range high (h) range tseg (t) range 0 x x disable disable disable 1 0 0 enable disable disable 1 0 1 enable disable enable 1 1 0 disabled enable disable 1 1 1 disabled enable enable datasheet 71 system address map 3.8.5 smm space decode and transaction handling only the processor is allowed to access smm space. pci express and dmi interface originated transactions are not allowed to smm space. 3.8.6 processor wb transactio n to an enabled smm address space processor writeback transactions (reqa[1]# = 0) to enabled smm address space must be written to the associated smm dram even though d_open=0 and the transaction is not performed in smm mode. this ensures smm space cache coherency when cacheable extended smm space is used. 3.8.7 smm access through gtt tlb (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) accesses through gtt tlb address translat ion to enabled smm dram space are not allowed. writes will be routed to memory address 000c_0000h with byte enables de- asserted and reads will be routed to memory address 000c_0000h. if a gtt tlb translated address hits enabled smm dram space, an error is recorded. pci express and dmi interface originated accesses are never allowed to access smm space directly or through the gtt tlb addr ess translation. if a gtt tlb translated address hits enabled smm dram space, an error is recorded. pci express and dmi interface write acce sses through gmadr range will be snooped. assesses to gmadr linear range (defined vi a fence registers) are supported. pci express and dmi interface tiley and tilex writ es to gmadr are not supported. if, when translated, the resulting physical address is to enabled smm dram space, the request will be remapped to address 000c_0000h with de-asserted byte enables. pci express and dmi interface read accesse s to the gmadr range are not supported therefore will have no address translatio n concerns. pci express and dmi interface reads to gmadr will be remapped to addre ss 000c_0000h. the read will complete with ur (unsupported request) completion status. table 10. smm control table g_smrame d_lck d_cls d_open processor in smm mode smm code access smm data access 0 x x x x disable disable 1 0 x 0 0 disable disable 1 0 0 0 1 enable enable 1 0 0 1 x enable enable 1 0 1 0 1 enable disable 1 0 1 1 x invalid invalid 1 1 x x 0 disable disable 1 1 0 x 1 enable enable 1 1 1 x 1 enable disable system address map 72 datasheet gtt fetches are always decoded (at fetch time) to ensure not in smm (actually, anything above base of tseg or 640 kb?1 mb). thus, they will be invalid and go to address 000c_0000h, but that is not specific to pci express or dmi; it applies to processor or internal graphics engines. also, since the gmadr snoop would not be directly to the smm space, there wouldn?t be a writeback to smm. in fact, the writeback would also be invalid (because it uses the same translation) and go to address 000c_0000h. 3.9 memory shadowing any block of memory that can be designat ed as read-only or write-only can be ?shadowed? into (g)mch dram memory. typica lly this is done to allow rom code to execute more rapidly out of main dram. rom is used as a read-only during the copy process while dram at the same time is designated write-only. after copying, the dram is designated read-only so that rom is shadowed. processor bus transactions are routed accordingly. 3.10 i/o address space the (g)mch does not support the existence of any other i/o devices beside itself on the processor bus. the (g)mch generates either dmi interface or pci express bus cycles for all processor i/o accesses that it does not claim. within the host bridge, the (g)mch contains two internal registers in the processor i/o space, configuration address register (config_address) and the configuration data register (config_data). these locations are used to implement configuration space access mechanism. the processor allows 64 k+3 bytes to be ad dressed within the i/o space. the (g)mch propagates the processor i/o address without any translation on to the destination bus and therefore provides addressability for 64k+3 byte locations. note that the upper 3 locations can be accessed only during i/o address wrap-around when processor bus hab_16 address signal is asserted. hab_16 is asserted on the processor bus whenever an i/o access is made to 4 bytes from ad dress 0fffdh, 0fffeh, or 0ffffh. hab_16 is also asserted when an i/o access is made to 2 bytes from address 0ffffh. a set of i/o accesses (other than ones used for configuration space access) are consumed by the internal graphics device if it is enabled. the mechanisms for internal graphics i/o decode and the associated control is explained later. the i/o accesses (other than ones used for configuration space access) are forwarded normally to the dmi interface bus unless they fall within the pci express i/o address range as defined by the mechanisms explained below. i/o writes are not posted. memory writes to ich or pci express are po sted. the pcicmd1 register can disable the routing of i/o cycles to the pci express. the (g)mch responds to i/o cycles initiated on pci express or dmi with an ur status. upstream i/o cycles and configuration cycles should never occur. if one does occur, the request will route as a read to memory address 000c_0000h so a completion is naturally generated (whether the original re quest was a read or write). the transaction will complete with an ur completion status. i/o reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from the processor as 1 transaction. the (g)mch will break this into 2 separate transactions. i/o writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed to be split into 2 transactions by the processor. datasheet 73 system address map 3.10.1 pci express* i/o address mapping the (g)mch can be programmed to direct non-memory (i/o) accesses to the pci express bus interface when processor initiated i/o cycle addresses are within the pci express i/o address range. this range is controlled via the i/o base address (iobase) and i/o limit address (iolimit) registers in (g)mch device 1 configuration space. address decoding for this range is based on the following concept. the top 4 bits of the respective i/o base and i/o limit registers correspond to address bits a[15:12] of an i/o address. for the purpose of address de coding, the (g)mch assumes that lower 12 address bits a[11:0] of the i/o base are zero and that address bits a[11:0] of the i/o limit address are fffh. this forces the i/o address range alignment to 4 kb boundary and produces a size granularity of 4 kb. the (g)mch positively decodes i/o accesse s to pci express i/o address space as defined by the following equation: i/o_base_address processor i/o cycle address i/o_limit_address the effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of i/o space claimed by the pci express device. the (g)mch also forwards accesses to the legacy vga i/o ranges according to the settings in the device #1 configuration registers bctrl (vga enable) and pcicmd1 (ioae1), unless a second adap ter (monochrome) is present on the dmi interface/pci (or isa). the presence of a second grap hics adapter is determined by the mdap configuration bit. when mdap is set, the (g)mch will decode legacy monochrome i/o ranges and forward them to the dmi interface. the io ranges decoded for the monochrome adapter are 3b4h, 3b 5h, 3b8h, 3b9h, 3bah, and 3bfh. note that the (g)mch device 1 and/or device 6 i/o address range registers defined above are used for all i/o space allocation for any devices requiring it (such a window on pci express). the pcicmd1 register can disable the ro uting of i/o cycles to pci express. 3.11 (g)mch decode rules and cross-bridge address mapping vgaa = 000a_0000 ? 000a_ffff mda = 000b_0000 ? 000b_7fff vgab = 000b_8000 ? 000b_ffff mainmem = 0100_0000 to tolud highmem = 4 gb to tom reclaimmem = reclaimbase to reclaimlimit 3.11.1 legacy vga and i/ o range decode rules the legacy 128 kb vga memory range 000a_0000h-000b_ffffh can be mapped to igd (device 2), to pci express (device 1), and/or to the dmi interface depending on the programming of the vga steering bits. priority for vga mapping is constant in that the (g)mch always decodes internally mapped devices first. inte rnal to the (g)mch, decode precedence is always given to igd. the (g)mch always positively decodes internally mapped devices, namely the igd and pci-express. subsequent decoding of regions mapped to pci express or the dm i interface depends on the legacy vga configurations bits (vga enable and mdap). system address map 74 datasheet datasheet 75 register description 4 register description the (g)mch contains two sets of software accessible registers, accessed via the host processor i/o address space: control registers and internal configuration registers. ? control registers are i/o mapped into the processor i/o space, which control access to pci and pci express configuration space (see section 4.5 ). ? internal configuration registers residing within the (g)mch are partitioned into logical device register sets (?logical? since they reside within a single physical device). one register set is dedicated to host bridge functionality (i.e., dram configuration, other chip-set operating parameters and optional features). another register set is dedicated to host-pci express bridge functions (controls pci express interface configurations and operating parameters). the 82p45 has a second register set devoted to host-pci express bridge functions. there is also a register sets devoted to management engine (me) control. for the 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch, a register set is for the internal graphics functions. the 82q45 gmch has register sets devoted to intel trusted execution technology and intel virtualization technology. the (g)mch internal registers (i/o mapped , configuration and pci express extended configuration registers) are accessible by the host processor. the registers that reside within the lower 256 bytes of each device can be accessed as byte, word (16 bit), or dword (32 bit) quantities, with the exception of config_address, which can only be accessed as a dword. all multi-byte numer ic fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field). registers which reside in bytes 256 through 4095 of each de vice may only be accessed using memory mapped transactions in dword (32 bit) quantities. some of the (g)mch registers described in this section contain reserved bits. these bits are labeled "reserved?. software must de al correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, and write operation for the configuration address register. in addition to reserved bits within a regist er, the (g)mch contains address locations in the configuration space of the host bridge en tity that are marked either "reserved" or ?intel reserved?. the (g)mch responds to a ccesses to ?reserved? address locations by completing the host cycle. when a ?reserved? register location is read, a zero value is returned. (?reserved? registers can be 8-, 16-, or 32 bits in size). writes to ?reserved? registers have no effect on the (g)mch. regi sters that are marked as ?intel reserved? must not be modified by system software. writes to ?intel reserved? registers may cause system failure. reads from ?intel reserved? registers may return a non-zero value. upon a full reset, the (g)mch sets its entire set of internal configuration registers to predetermined default states. some register values at reset are determined by external strapping options. the default state repres ents the minimum functionality feature set required to successfully bringing up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software (usually bios) to properly dete rmine the dram configurations, operating parameters and optional system features that are applicable, and to program the (g)mch registers accordingly. register description 76 datasheet 4.1 register terminology the following table shows the register -related terminology that is used. item definition ro read only bit(s). writes to these bits ha ve no effect. this may be a status bit or a static value. ro/s read only / sticky bit(s). writes to these bits have no effect. these are status bits only. bits are not returned to their default values by "warm" reset, but will be reset with a cold/complete reset (for pci express related bits a cold reset is ?power good reset? as defined in the pci express spec). rs/wc read set / write clear bit(s).the first time the bit is read with an enabled byte, it returns the value 0, but a side -effect of the read is that the value changes to 1. any subsequent reads with enabled bytes return a 1 until a 1 is written to the bit. when the bit is read, but the byte is not enabled, the state of the bit does not change, and the value returned is irreleva nt, but will match the state of the bit. when a 0 is written to the bit, there is no effect. when a 1 is written to the bit, its value becomes 0, until the next byte-enabled read. when the bit is written, but the byte is not enable d, there is no effect. r/w read / write bit(s). these bits can be read and written by software. hardware may only change the state of this bit by reset. r/wc read / write clear bit(s). these bits can be read. internal events may set this bit. a software write of ?1 ? clears (sets to ?0?) the corresponding bit(s) and a write of ?0? has no effect. r/wc/s read / write clear / sticky bit(s). these bits can be read. internal events may set this bit. a software write of ?1? clea rs (sets to ?0?) the corresponding bit(s) and a write of ?0? has no e ffect. bits are not cleared by "warm" reset, but will be reset with a cold/complete reset (for pci express related bits a cold reset is ?power good reset? as defined in the pci express spec). r/w/k read / write / key bit(s). these bits can be read and written by software. additionally this bit, wh en set, prohibits some ot her bit field(s) from being writeable (bit fields become read only). r/w/l read / write / lockable bit(s). these bits can be read and wr itten by software. additionally, there is a key bit (which is marked r/w/k or r/w/l/k) that, when set, prohibits this bit field from being writeable (bit field becomes read only). r/w/s read / write / sticky bit(s). these bits can be read and written by software. bits are not cleared by "w arm" reset, but will be reset with a cold/complete reset (for pci express related bits a co ld reset is ?power good reset? as defined in the pci express spec). r/w/sc read / write / self clear bit(s). thes e bits can be read and written by software. when the bit is 1, hardware may clear the bit to ?0? based upon internal events, possibly sooner than any subsequent so ftware read could retrieve a 1. datasheet 77 register description 4.2 configuration process and registers 4.2.1 platform configuration structure the dmi physically connects the (g)mch and the intel ich10/ich7; so, from a configuration standpoint, the dmi is logically pci bus 0. as a result, all devices internal to the (g)mch and the intel ich10/ich7 appear to be on pci bus 0. the ich10/ich7 internal lan controller does not appear on bus 0 ? it appears on the external pci bus (whose number is configurable). the system?s primary pci expansion bus is ph ysically attached to the intel ich10/ich7 and, from a configuration perspective, appe ars to be a hierarchical pci bus behind a pci-to-pci bridge and therefore has a prog rammable pci bus number. the pci express graphics attach appears to system software to be a real pci bus behind a pci-to-pci bridge that is a device resident on pci bus 0. a physical pci bus 0 does not exist and that dmi and the internal devices in the (g)mch and intel ich10/ich7 logically consti tute pci bus 0 to configuration software. this is shown in the following figure. the (g)mch contains the following pci device s within a single physical component. the configuration registers for the four devices are mapped as devices residing on pci bus 0. ? device 0: host brid ge/dram controller. logically this appears as a pci device residing on pci bus 0. device 0 contains the standard pci header registers, pci express base address register, dram contro l (including thermal/throttling control), configuration for the dmi, and other (g)mch specific registers. ? device 1: host-pci express bridge. logically this appears as a ?virtual? pci-to- pci bridge residing on pci bus 0 and is compliant with pci express specification revision 1.0. device 1 contains the standard pci-to-pci bridge registers and the standard pci express/pci configuration registers (including the pci express memory address mapping). it also contains isochronous and virtual channel controls in the pci express extended configuration space. ? device 2: internal graphics control (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only). logically, this appears as a pci device residing on pci bus #0. physically, device 2 contains the configuration registers for 3d, 2d, and display functions. ? device 3: management engine control . me control. r/w/sc/l read / write / self clear / lockable bit( s). these bits can be read and written by software. when the bit is ?1?, hardware may clear the bit to ?0? based upon internal events, possibly sooner than any subseque nt software read could retrieve a ?1?. additionally there is a bit (which is marked r/w/k or r/w/l/k) that, when set, prohibits this bit fiel d from being writeable (bit field becomes read only). r/wo write once bit(s). once written by software, bits with this attribute become read only. these bits can only be clea red by a reset. if there are multiple r/wo fields within a dword, they should be written all at once (atomically) to avoid capturing an incorrect value. w write only. these bits may be written by software, but will al ways return zeros when read. they are used for write si de-effects. any data written to these registers cannot be retrieved. item definition register description 78 datasheet ? device 6: secondary host-pci express bridge. (82p45 mch only). logically this appears as a ?virtual? pci-to-pci bridge residing on pci bus 0 and is compliant with pci express specification revision 1.0. device 6 contains the standard pci-to- pci bridge registers and the standard pci express/pci configuration registers (including the pci express memory address mapping). it also contains isochronous and virtual channel controls in the pc i express extended configuration space. 4.3 configuration mechanisms the processor is the originator of configuratio n cycles so the fsb is the only interface in the platform where these mechanisms are used. internal to the (g)mch transactions received through both configuration mechan isms are translated to the same format. 4.3.1 standard pci confi guration mechanism the following is the mechanism for translating processor i/o bus cycles to configuration cycles. the pci specification defines a slot based "con figuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechanism implemented within the (g)mch. the configuration access mechanism makes use of the config_address register (at i/o address 0cf8h though 0cfbh) and config_data register (at i/o address 0cfch though 0cffh). to reference a configuration register a dw i/o write cycle is used to place a value into config_address that specif ies the pci bus, the device on that bus, the function within the device and a specific configuration register of the device function being accessed. config_address[31] must be 1 to enable a configuration cycle. config_data then becomes a window into the four bytes of configuration space specified by the contents of config_address. any read or write to config_data will result in the (g)mch translating the config_address into the appropriate configuration cycle. the (g)mch is responsible for translating and routing the processor?s i/o accesses to the config_address and config_data regist ers to internal (g)mch configuration registers, dmi or pci express. 4.3.2 pci express* enhanced configuration mechanism pci express extends the configuration spac e to 4096 bytes per device/function as compared to 256 bytes allowed by the pci specification, revision 2.3. pci express configuration space is divided into a pci 2.3 compatible region, which consists of the first 256b of a logical device?s configuratio n space and a pci express extended region which consists of the remaining configuration space. the pci compatible region can be accessed using either the standard pci configuration mechanism or using the pci express enhanc ed configuration mechanism described in this section. the extended configuration re gisters may only be accessed using the pci express enhanced configuration mechanis m. to maintain compatibility with pci configuration addressing mechanisms, system software must access the extended configuration space using 32-bit operations (32-bit aligned) only. these 32-bit operations include byte enables allowing only appropriate bytes within the dword to be accessed. locked transactions to the pc i express memory mapped configuration address space are not supported. all change s made using either access mechanism are equivalent. datasheet 79 register description the pci express enhanced configuration mechanism utilizes a flat memory-mapped address space to access device configuration registers. this address space is reported by the system firmware to the operating system. there is a register, pciexbar, that defines the base address for the block of addresses below 4 gb for the configuration space associated with busses, devices and f unctions that are potentially a part of the pci express root complex hierarchy. in the pc iexbar register there exists controls to limit the size of this reserved memory mapp ed space. 256 mb is the amount of address space required to reserve space for every bu s, device, and function that could possibly exist. options for 128 mb and 64 mb exist in order to free up those addresses for other uses. in these cases the number of busses and all of their associated devices and functions are limited to 128 or 64 busses respectively. the pci express configuration transaction header includes an additional 4 bits (extendedregisteraddress[3:0]) between the function number and register address fields to provide indexing into the 4 kb of configuration space allocated to each potential device. for pci compatible configuration requests, the extended register address field must be all zeros. just the same as with pci devices, each device is selected based on decoded address information that is provided as a part of the address portion of configuration request packets. a pci express device will decode all address information fields (bus, device, function and extended address numbers) to provide access to the correct register. to access this space (steps 1, 2, 3 are done only once by bios), 1. use the pci compatible configuration mechanism to enable the pci express enhanced configuration mechanism by writing 1 to bit 0 of the pciexbar register. 2. use the pci compatible configuration mechanism to write an appropriate pci express base address into the pciexbar register 3. calculate the host address of the register you wish to set using (pci express base + (bus number * 1 mb) + (device number * 32kb) + (function number * 4 kb) + (1 b * offset within the function) = host address) 4. use a memory write or memory read cycle to the calculated host address to write or read that register. figure 8. memory map to pci express device configuration space bus 255 fffffffh bus 1 bus 0 1fffffh fffffh 0h device 31 fffffh device 1 device 0 ffffh 7fffh function 7 7fffh function 1 function 0 1fffh fffh fffh pci compatible config space pci compatible config header ffh 3fh pci express* extended configuration space located by pci express* base address register description 80 datasheet 4.4 routing configuration accesses the (g)mch supports two pci related interfaces: dmi and pci expres s. the (g)mch is responsible for routing pci and pci express configuration cycles to the appropriate device that is an integrated part of the (g)mch or to one of these two interfaces. configuration cycles to the ich10/ich7 in ternal devices and primary pci (including downstream devices) are routed to the ich10/ich7 via dmi. configuration cycles to both the pci express graphics pci compat ibility configuration space and the pci express graphics extended configuration spac e are routed to the pci express graphics port device or associated link. figure 9. mch configuration cycle flow chart dw i/o write to config_address with bit 31 = 1 i/o read/write to config_data mch generates t y pe 1 access to pci express mch allows c y cle to g o to dmi resultin g in master abort bus# > sec bus bus # sub bus in mch dev 1 bus# = 0 device# = 1 & dev # 1 enabled & function# = 0 device# = 0 & function# = 0 mch generates dmi type 1 configuration cycle bus# = secondarybus in mch dev 1 mch claims mch claims yes no yes yes no no yes yes no no device# = 0 mch generates t y pe 0 access to pci express yes mch generates dmi t y pe 0 confi g uration c y cle no datasheet 81 register description 4.4.1 internal device configuration accesses the (g)mch decodes the bus number (bits 23: 16) and the device number fields of the config_address register. if the bus number field of config_address is 0 the configuration cycle is targeting a pci bus 0 device. if the targeted pci bus 0 device exists in the (g)mch and is not disabled, the configuration cycle is claimed by the appropriate device. 4.4.2 bridge related configuration accesses configuration accesses on pci express or dmi are pci express configuration tlps. ? bus number [7:0] is header byte 8 [7:0] ? device number [4:0] is header byte 9 [7:3] ? function number [2:0] is header byte 9 [2:0] and special fields for this type of tlp: ? extended register number [3:0] is header byte 10 [3:0] ? register number [5:0] is header byte 11 [7:2] see the pci express specification for more in formation on both the pci 2.3 compatible and pci express enhanced configuration mechanism and transaction rules. 4.4.2.1 pci express* configuration accesses when the bus number of a type 1 standard pci configuration cy cle or pci express enhanced configuration access matches the device 1 secondary bus number a pci express type 0 configuration tlp is genera ted on the pci express link targeting the device directly on the opposite side of th e link. this should be device 0 on the bus number assigned to the pci express link (likely bus 1). the device on other side of link must be device 0. the (g)mch will master abort any type 0 configuration access to a non-zero device number. if there is to be more than one device on that side of the link there must be a bridge implemented in the downstream device. when the bus number of a type 1 standard pci configuration cy cle or pci express enhanced configuration access is within the claimed range (between the upper bound of the bridge device?s subordinate bus nu mber register and the lower bound of the bridge device?s secondary bus number register) but does not match the device 1 secondary bus number, a pci express type 1 configuration tlp is generated on the secondary side of the pci express link. pci express configuration writes: ? internally the host interface unit will tr anslate writes to pci express extended configuration space to configuration writes on the backbone. ? writes to extended space are posted on the fsb, but non-posted on the pci express or dmi (i.e., translated to config writes) register description 82 datasheet 4.4.2.2 dmi configuration accesses accesses to disabled (g)mch internal devi ces, bus numbers not claimed by the host- pci express bridge, or pci bus 0 devices no t part of the (g)mch will subtractively decode to the ich10/ich7 and consequent ly be forwarded over the dmi via a pci express configuration tlp. if the bus number is zero, the (g)mch will generate a type 0 configuration cycle tlp on dmi. if the bus number is non-zero, and falls outside the range claimed by the host-pci express bridge, the (g)mch will generate a type 1 configuration cycle tlp on dmi. the ich10/ich7 routes configurations acce sses in a manner similar to the (g)mch. the ich10/ich7 decodes the configuratio n tlp and generates a corresponding configuration access. accesses targeting a de vice on pci bus 0 may be claimed by an internal device. the ich10/ich7 compar es the non-zero bus number with the secondary bus number and subordinate bu s number registers of its pci-to-pci bridges to determine if the configuration access is meant for primary pci, or some other downstream pci bus or pci express link. configuration accesses that are forwarded to the ich10/ich7, but remain unclaimed by any device or bridge will result in a master abort. 4.5 i/o mapped registers the (g)mch contains two registers that reside in the processor i/o address space ? the configuration address (config_address) register and the configuration data (config_data) register. the configuration address register enables/disables the configuration space and determines what po rtion of configuration space is visible through the configuration data window. 4.5.1 config_address?configuration address register i/o address: 0cf8h accessed as a dword default value: 00000000h access: r/w size: 32 bits config_address is a 32-bit register that can be accessed only as a dword. a byte or word reference will "pass through" the configuration address register and dmi onto the primary pci bus as an i/o cycle. the config_address register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. datasheet 83 register description bit access & default description 31 r/w 0b configuration enable (cfge): 0 = disable 1 = enable 30:24 reserved 23:16 r/w 00h bus number: if the bus number is programmed to 00h, the target of the configuration cycle is a pci bus 0 agent. if this is the case and the (g)mch is not the target (i .e., the device number is 2), then a dmi type 0 configuration cycle is generated. if the bus number is non-zero, and does not fall within the ranges enumerated by device 1?s secondary bus number or subordinate bus number register, then a dmi type 1 configuration cycle is generated. if the bus number is non-zero and matches the value programmed into the secondary bus number register of device 1, a type 0 pci configuration cycle will be generated on pci express. if the bus number is non-zero, greater than the value in the secondary bus number register of device 1 an d less than or equal to the value programmed into the subordinate bus number register of device 1, a type 1 pci configuration cycle wi ll be generated on pci express. this field is mapped to byte 8 [7:0] of the request head er format during pci express configuration cycles an d a[23:16] during the dmi type 1 configuration cycles. 15:11 r/w 00h device number: this field selects one agent on the pci bus selected by the bus number. when the bus number field is ?00? the (g)mch decodes the device number field. th e (g)mch is always device number 0 for the host bridge entity, device number 1 for the host-pci express entity. therefore, when the bus number =0 and the device number equals 0, 1, or 2 the internal (g)mch devices are selected. this field is mapped to byte 6 [7:3] of the request header format during pci express configuration cycles and a [15:11] during the dmi configuration cycles. 10:8 r/w 000b function number: this field allows the conf iguration registers of a particular function in a multi-function device to be accessed. the (g)mch ignores configuration cycles to its internal devices if the function number is not equal to 0 or 1. this field is mapped to byte 6 [2:0] of the request header format during pci express configuration cycles and a[10:8] during the dmi configuration cycles. 7:2 r/w 00h register number: this field selects one regi ster within a particular bus, device, and function as spec ified by the other fields in the configuration address register. this field is mapped to byte 7 [7:2] of the request head er format during pci express configuration cycles and a[7:2] during the dmi configuration cycles. 1:0 reserved register description 84 datasheet 4.5.2 config_data?configuration data register i/o address: 0cfch default value: 00000000h access: r/w size: 32 bits config_data is a 32-bit read/write window into configuration space. the portion of configuration space that is referenced by config_data is determined by the contents of config_address. bit access & default description 31:0 r/w 0000 0000 h configuration data window (cdw): if bit 31 of config_address is 1, any i/o access to the config_data regi ster will produce a configuration transaction using the contents of config_address to determine the bus, device , function, and o ffset of the register to be accessed. datasheet 85 dram controller registers (d0:f0) 5 dram controller registers (d0:f0) 5.1 dram controller registers (d0:f0) the dram controller registers are in device 0 (d0), function 0 (f0). warning: address locations that are not listed are considered intel reserved registers locations. reads to reserved registers may return non-zero values. writes to reserved locations may cause system failures. all registers that are defined in the pci 2.3 specification, but are not necessary or implemented in this component are simply not included in this document. the reserved/unimplemented space in the pci configuration header space is not documented as such in this summary. table 11. dram controller register ad dress map (d0:f0) (sheet 1 of 2) address offset register symbol register name default value access 0?1h vid vendor identification 8086h ro 2?3h did device identification see register description ro 4?5h pcicmd pci command 0006h ro, r/w 6 pcists pci status 0090h ro, r/wc 8h rid revision identification see register description ro 9?bh cc class code 060000h ro dh mlt master latency timer 00h ro eh hdr header type 00h ro 2c?2ch svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h capptr capabiliti es pointer e0h ro 40?47h pxpepbar pci express egress port base address 000000000000 0000h ro, r/w/l 48?4fh mchbar (g)mch memory mapped register range base 000000000000 0000h r/w/l, ro 52?53h ggc gmch graphics control register (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 0030h r/w/l, ro 54?57h deven device enable 000023dbh ro, r/w/l 60?67h pciexbar pci express register range base address 00000000e000 0000h ro, r/w/l, r/w/l/k 68?6fh dmibar root complex register range base address 000000000000 0000h ro, r/w/l 90h pam0 programmable attribute map 0 00h ro, r/w/l dram controller registers (d0:f0) 86 datasheet 91h pam1 programmable attribute map 1 00h ro, r/w/l 92h pam2 programmable attribute map 2 00h ro, r/w/l 93h pam3 programmable attribute map 3 00h ro, r/w/l 94h pam4 programmable attribute map 4 00h ro, r/w/l 95h pam5 programmable attribute map 5 00h ro, r/w/l 96h pam6 programmable attribute map 6 00h ro, r/w/l 97h lac legacy access control 00h r/w, r/w/l, ro 98?99h remapbase remap base address register 03ffh ro, r/w/l 9a?9bh remaplimit remap limit address register 0000h ro, r/w/l 9dh smram system management ram control 02h ro, r/w/l, r/ w, r / w / l / k 9eh esmramc extended system management ram control 38h r/w/l, r/wc, ro a0?a1h tom top of memory 0001h ro, r/w/l a2?a3h touud top of upper usable dram 0000h r/w/l a4?a7h gbsm graphics base of stolen memory (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 00000000h r/w/l, ro a8?abh bgsm base of gtt stolen memory 00000000h r/w/l, ro ac?afh tsegmb tseg memory base 00000000h ro, r/w/l b0?b1h tolud top of low usable dram 0010h r/w/l, ro c8?c9h errsts error status 0000h ro, r/wc/s ca?cbh errcmd error command 0000h r/w, ro cc?cdh smicmd smi command 0000h ro, r/w dc?dfh skpd scratchpad data 00000000h r/w e0?ech capid0 capability identifier 000000000000 000000010c00 09h ro table 11. dram controller register a ddress map (d0:f0) (sheet 2 of 2) address offset register symbol register name default value access datasheet 87 dram controller registers (d0:f0) 5.1.1 vid?vendor identification b/d/f/type: 0/0/0/pci address offset: 0-1h default value: 8086h access: ro size: 16 bits this register combined with the device identification register uniquely identifies any pci device. 5.1.2 did?device identification b/d/f/type: 0/0/0/pci address offset: 2-3h default value: see table description access: ro size: 16 bits this register combined with the vendor identification register uniquely identifies any pci device. bit access default value rst/ pwr description 15:0 ro 8086h core vendor identification number (vid): pci standard identification for intel. bit access default value rst/ pwr description 15:0 ro see description core device identification number (did): identifier assigned to the (g)mch core/p rimary pci device. refer to the intel ? 4 series chipset family specification update for values in this register. dram controller registers (d0:f0) 88 datasheet 5.1.3 pcicmd?pci command b/d/f/type: 0/0/0/pci address offset: 4-5h default value: 0006h access: ro, r/w size: 16 bits since (g)mch device 0 does not physically reside on pci_a many of the bits are not implemented. bit access default value rst/ pwr description 15:10 ro 00h core reserved 9r o 0 b c o r e fast back-to-back enable (fb2b): this bit controls whether or not the master can do fast back-to-back write. since device 0 is strictly a target this bit is not implemented and is hardwired to 0. writes to this bit position have no effect. 8r/w 0b core serr enable (serre): this bit is a global enable bit for device 0 serr messaging. th e (g)mch does not have an serr signal. the (g)mch communicates the serr condition by sending an serr message over dmi to the ich. 1 = the (g)mch is enabled to generate serr messages over dmi for specific device 0 error conditions that are individually enabled in the errcmd and dmiuemsk registers. the erro r status is reported in the errsts, pcists, and dmiuest registers. 0 = the serr message is not generated by the (g)mch for device 0. note that this bit only cont rols serr messaging for the device 0. device 1 has its own serre bits to control error reporting for error conditions occurring in that device. the control bits are used in a lo gical or manner to enable the serr dmi message mechanism. 7r o 0 b c o r e address/data stepping enable (adstep): address/ data stepping is not implemen ted in the (g)mch, and this bit is hardwired to 0. writes to this bit position have no effect. 6r/w 0b core parity error enable (perre): controls whether or not the master data parity error bi t in the pci status register can bet set. 0 = master data parity error bi t in pci status register can not be set. 1 = master data parity error bi t in pci status register can be set. 5r o 0 b c o r e vga palette snoop enable (vgasnoop): the (g)mch does not implement this bit and it is hardwired to a 0. 4r o 0 b c o r e memory write and invalidate enable (mwie): the (g)mch will never issue memory write and invalidate commands. this bit is therefore hardwired to 0. 3r o 0 b c o r e special cycle enable (sce): the (g)mch does not implement this bit and it is hardwired to a 0. datasheet 89 dram controller registers (d0:f0) 5.1.4 pcists?pci status b/d/f/type: 0/0/0/pci address offset: 6-7h default value: 0090h access: ro, r/wc size: 16 bits this status register reports the occurrence of error events on device 0's pci interface. since the (g)mch device 0 does not physically reside on pci_a many of the bits are not implemented. 2r o 1 b c o r e bus master enable (bme): the (g)mch is always enabled as a master on the ba ckbone. this bit is hardwired to a 1. 1r o 1 b c o r e memory access enable (mae): the (g)mch always allows access to main memory. this bit is not implemented and is hardwired to 1. 0r o 0 b c o r e i/o access enable (ioae): this bit is not implemented in the (g)mch and is hardwired to a 0. bit access default value rst/ pwr description bit access default value rst/ pwr description 15 r/wc 0b core detected parity error (dpe): this bit is set when this device receives a poisoned tlp. 14 r/wc 0b core signaled system error (sse): this bit is set to 1 when the (g)mch device 0 generates an serr message over dmi for any enabled device 0 error condition. device 0 error conditions are enabled in the pcicmd, errcmd, and dmiuemsk registers. device 0 error flags are read/reset from the pcists, errsts, or dmiuest registers. software clears this bi t by writing a 1 to it. 13 r/wc 0b core received master abort status (rmas): this bit is set when the (g)mch generates a dmi request that receives an unsupported request comp letion packet . software clears this bit by writing a 1 to it. 12 r/wc 0b core received target abort status (rtas): this bit is set when the (g)mch generates a dmi request that receives a completer abort completion pa cket. software clears this bit by writing a 1 to it. 11 ro 0b core signaled target abort status (stas): the (g)mch will not generate a target abort dmi completion packet or special cycle. this bit is not implemented in the (g)mch and is hardwired to a 0. writes to this bit position have no effect. 10:9 ro 00b core devsel timing (devt): these bits are hardwired to "00". writes to these bit positions have no affect. device 0 does not physically connect to pci_a. these bits are set to "00" (fast decode) so that optimum devsel timing for pci_a is not limited by the (g)mch. dram controller registers (d0:f0) 90 datasheet 5.1.5 rid?revision identification b/d/f/type: 0/0/0/pci address offset: 8h default value: see description below access: ro size: 8 bits this register contains the revision number of the (g)mch device 0. these bits are read only and writes to this register have no effect. 8r/wc 0b core master data parity error detected (dpd): this bit is set when dmi received a pois oned completion from the ich. this bit can only be set when the parity error enable bit in the pci command re gister is set. 7ro 1b core fast back-to-back (fb2b): this bit is hardwired to 1. writes to these bit positions have no effect. device 0 does not physically connect to pci_a. this bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for pci_a is not limited by the (g)mch. 6 ro 0b core reserved 5ro 0b core 66 mhz capable: does not apply to pci express. must be hardwired to 0. 4ro 1b core capability list (clist): this bit is hardwired to 1 to indicate to the configuration software that this device/ function implements a list of new capabilities. a list of new capabilities is accessed via register capptr at configuration address offs et 34h. register capptr contains an offset pointing to the start address within configuration space of this device where the capability identification register resides. 3:0 ro 0000b core reserved bit access default value rst/ pwr description bit access default value rst/ pwr description 7:0 ro see description core revision identification number (rid): this is an 8-bit value that indicates the revisi on identification number for the (g)mch device 0. refer to the intel ? 4 series chipset family specification update for the value of this register. datasheet 91 dram controller registers (d0:f0) 5.1.6 cc?class code b/d/f/type: 0/0/0/pci address offset: 9-bh default value: 060000h access: ro size: 24 bits this register identifies the basic function of the device, a more specific sub-class, and a register-specific programming interface. 5.1.7 mlt?master latency timer b/d/f/type: 0/0/0/pci address offset: dh default value: 00h access: ro size: 8 bits device 0 in the (g)mch is not a pci master. therefore, this register is not implemented. bit access default value rst/pwr description 23:16 ro 06h core base class code (bcc): this is an 8-bit value that indicates the base clas s code for the (g)mch. 06h = bridge device. 15:8 ro 00h core sub-class code (subcc): this is an 8-bit value that indicates the category of bridge into which the (g)mch falls. 00h = host bridge. 7:0 ro 00h core programming interface (pi): this is an 8-bit value that indicates the programming inte rface of this device. this value does not specify a particular register set layout and provides no practical use for this device. bit access default value rst/pwr description 7:0 ro 00h core reserved dram controller registers (d0:f0) 92 datasheet 5.1.8 hdr?header type b/d/f/type: 0/0/0/pci address offset: eh default value: 00h access: ro size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. 5.1.9 svid?subsystem vendor identification b/d/f/type: 0/0/0/pci address offset: 2c-2dh default value: 0000h access: r/wo size: 16 bits this value is used to identify the vendor of the subsystem. 5.1.10 sid?subsystem identification b/d/f/type: 0/0/0/pci address offset: 2e-2fh default value: 0000h access: r/wo size: 16 bits this value is used to identify a particular subsystem. bit access default value rst/ pwr description 7:0 ro 00h core pci header (hdr): this field always returns 00h to indicate that the (g)mch is a single function device with standard header layout. reads and writes to this location have no effect. bit access default value rst/ pwr description 15:0 r/wo 0000h core subsystem vendor id (subvid): this field should be programmed during boot-up to indicate the vendor of the system board. after it has be en written once, it becomes read only. bit access default value rst/ pwr description 15:0 r/wo 0000h core subsystem id (subid): this field should be programmed during bios initialization. after it has been written once, it becomes read only. datasheet 93 dram controller registers (d0:f0) 5.1.11 capptr?capabilities pointer b/d/f/type: 0/0/0/pci address offset: 34h default value: e0h access: ro size: 8 bits the capptr provides the offset that is the po inter to the location of the first device capability in the capability list. 5.1.12 pxpepbar?pci express egress port base address b/d/f/type: 0/0/0/pci address offset: 40-47h default value: 0000000000000000h access: ro, r/w/l size: 64 bits this is the base address for the pci express egress port mmio configuration space. there is no physical memory within this 4 kb window that can be addressed. the 4 kb reserved by this register does not alias to any pci 2.3 compliant memory mapped space. on reset, the egress port mmio co nfiguration space is disabled and must be enabled by writing a 1 to pxpepbaren [dev 0, offset 40h, bit 0] note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/ pwr description 7:0 ro e0h core capabilities pointer (capptr): this field is a pointer to the offset of the first capability id register block. in this case the first capability is th e product-specific capability identifier (capid0). bit access default value rst/ pwr description 63:36 ro 0000000h core reserved 35:12 r/w/l 000000h core pci express egress port mmio base address (pxpepbar): this field corresponds to bits 35:12 of the base address pci express egress port mmio configuration space. bios will program this register resulting in a base address for a 4 kb block of contiguous memory address space. this register ensures that a naturally aligned 4 kb space is allocated within th e first 6 4gb of addressable memory space. system software uses this base address to program the (g)mch mmio register set. 11:1 ro 000h core reserved 0r/w/l 0b core pxpepbar enable (pxpepbaren): 0 = pxpepbar is disabled an d does not claim any memory 1 = pxpepbar memory mapped accesses are claimed and decoded appropriately dram controller registers (d0:f0) 94 datasheet 5.1.13 mchbar?(g)mch memory mapped register range base b/d/f/type: 0/0/0/pci address offset: 48-4fh default value: 0000000000000000h access: r/w/l, ro size: 64 bits this is the base address for the (g) mch memory mapped configuration space. there is no physical memory within this 16 kb window that can be addressed. the 16 kb reserved by this register does not alias to any pci 2.3 compliant memory mapped space. on reset, the (g)mch mmio memory mapped configuration space is disabled and must be enabled by writing a 1 to mchbaren [device 0, offset48h, bit 0]. all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 63:36 ro 0000000h core reserved 35:14 r/w/l 000000h core (g)mch memory mapped base address (mchbar): this field corresponds to bits 35:14 of the base address (g)mch memory mapped config uration space. bios will program this register resulting in a base address for a 16 kb block of contiguous me mory address space. this register ensures that a natu rally aligned 16 kb space is allocated within the first 64gb of addressable memory space. system software uses this base address to program the (g)mch memory mapped register set. 13:1 ro 0000h core reserved 0 r/w/l 0b core mchbar enable (mchbaren): 0 = mchbar is disabled and does not claim any memory 1 = mchbar memory mapped ac cesses are claimed and decoded appropriately datasheet 95 dram controller registers (d0:f0) 5.1.14 ggc?gmch graphics control register (intel ? 82q45, 82q43, 82b43, 82g45, 82g 43, 82g41 gmch only) b/d/f/type: 0/0/0/pci address offset: 52-53h default value: 0030h access: r/w/l, ro size: 16 bits note: all the bits in this register are inte l txt lockable (82q45/82q43 gmch only). bit access default value rst/ pwr description 15:12 ro 0h core reserved 11:8 r/w/l 0h core gtt graphics memory size (ggms): this field is used to select the amount of main memory that is pre-allocated to support the internal graphics translation table. the bios ensures that memory is pre-allocated only when internal graphics is enabled. gsm is assumed to be a contig uous physical dram space with dsm, and bios needs to allocate a contiguous memory chunk. hardware will drive the base of gsm from dsm only using the gsm size programmed in the register. 0000 = no memory pre-allocated. 0001 = no vt mode, 1 mb of memory pre-allocated for gtt. 0011 = no vt mode, 2 mb of memory pre-allocated for gtt 1001 = vt mode, 2 mb of memory pre-allocated for 1 mb of global gtt and 1 mb for shadow gtt 1010 = vt mode, 3 mb of memory pre-allocated for 1.5 mb of global gtt and 1.5 mb for shadow gtt (82q45 gmch only) 1011 = vt mode, 4 mb of memory pre-allocated for 2 mb of global gtt and 2 mb for shadow gtt. (82q45 gmch only) note: all unspecified encodings of this register field are reserved, hardware functionality is not as sured if used. this register is locked and becomes read only when the d_lck bit in the smram register is set. dram controller registers (d0:f0) 96 datasheet 7:4 r/w/l 0011b core graphics mode select (gms): this field is used to select the amount of main memory that is pre-allocated to support the internal graphics device in vga (non-linear) and native (linear) modes. the bios ensures that memo ry is pre-allocated only when internal graphics is enabled. 0000 = no memory pre-allocated. device 2 (igd) does not claim vga cycles (memory and i/o) , and the sub-class code field within device 2, function 0 class code register is 80h. 0001 = reserved 0010 = reserved 0011 = reserved 0100 = reserved 0101 = dvmt (uma) mode, 32 mb of memory pre-allocated for frame buffer. 0110 = dvmt (uma) mode, 48 mb of memory pre-allocated for frame buffer. 0111 = dvmt (uma) mode, 64 mb of memory pre-allocated for frame buffer. 1000 = dvmt (uma) mode, 128 mb of memory pre-allocated for frame buffer. 1001 = dvmt (uma) mode, 256 mb of memory pre-allocated for frame buffer. 1010 = dvmt (uma) mode, 96 mb of memory pre-allocated (0 + 96). 1011 = dvmt (uma) mode, 160 mb of memory pre-allocated (64 + 96). 1100 = dvmt (uma) mode, 224 mb of memory pre-allocated (128 + 96). 1101 = dvmt (uma) mode, 352 mb of memory pre-allocated (256 + 96). note: this register is locked and becomes read only when the d_lck bit in the smram register is set. hardware does not clear or set any of these bits automatically based on igd being disabled/enabled. ios requirement: bios must not set this field to 000 if ivd (bit 1 of this register) is 0. 3:2 ro 00b core reserved 1 r/w/l 0b core igd vga disable (ivd): 0 = enable. device 2 (igd) claims vga memory and io cycles, the sub-class code within device 2 class code register is 00h. 1 = disable. device 2 (igd) does not claim vga cycles (memory and i/o), and the sub- class co de field within device 2, function 0 class code register is 80h. bios requirement: bios must not set this bit to 0 if the gms field (bits 6:4 of this register) pre-allocates no memory. this bit must be set to 1 if device 2 is di sabled either via a fuse or fuse override (capid0[46] = 1) or via a register (deven[3] = 0). this register is locked by inte l txt (82q45/82q43 gmch only) or me stolen memory lock. 0 ro 0b core reserved bit access default value rst/ pwr description datasheet 97 dram controller registers (d0:f0) 5.1.15 deven?device enable b/d/f/type: 0/0/0/pci address offset: 54-57h default value: 000023dbh access: ro, r/w/l size: 32 bits allows for enabling/disabling of pci devices and functions that are within the (g)mch. the table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. note: all the bits in this register are inte l txt lockable (82q45/82q43 gmch only). bit access default value rst/ pwr description 31:15 ro 00000h core reserved 14 r/w/l 0b core reserved 13 (82p45 mch only) r/w/l 1b core peg1 enable (d6en): 0 = bus 0, device 6 is disabled and hidden. 1 = bus 0, device 6 is enabled and visible. 13 (82q45, 82q43, 82b43, 82g45, 82g43, 82g41, 82p43 (g)mch only) r/w/l 1b core reserved 12:10 ro 000b core reserved 9 r/w/l 1b core ep function 3 (d3f3en): 0 = bus 0, device 3, functi on 3 is disabled and hidden 1 = bus 0, device 3, function 3 is enabled and visible if device 3, function 0 is di sabled and hidden, then device 3, function 3 is also disabl ed and hidden independent of the state of this bit. if this (g)mch does not have me capability (capid0[57] = 1 or capid0[56] = 1), then device 3, function 3 is disabled and hidden independen t of the state of this bit. 8 r/w/l 1b core ep function 2 (d3f2en): 0 = bus 0, device 3, functi on 2 is disabled and hidden 1 = bus 0, device 3, function 2 is enabled and visible if device 3, function 0 is di sabled and hidden, then device 3, function 2 is also disabl ed and hidden independent of the state of this bit. if this (g)mch does not have me capability (capid0[57] = 1 or capid0[56] = 1) then device 3 function 2 is disabled and hidden independent of the state of this bit. 7 r/w/l 1b core ep function 1 (d3f1en): 0 = bus 0, device 3, functi on 1 is disabled and hidden 1 = bus 0, device 3, function 1 is enabled and visible. if device 3, function 0 is di sabled and hidden, then device 3, function 1 is also disabl ed and hidden independent of the state of this bit. dram controller registers (d0:f0) 98 datasheet 6r / w / l1 bc o r e ep function 0 (d3f0en): 0 = bus 0, device 3, functi on 0 is disabled and hidden 1 = bus 0, device 3, function 0 is enabled and visible. 5 ro 0b core reserved 4 (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) r/w/l 1b core internal graphics engine function 1 (d2f1en): 0 = bus 0, device 2, functi on 1 is disabled and hidden 1 = bus 0, device 2, function 1 is enabled and visible if device 2, function 0 is di sabled and hidden, then device 2, function 1 is also disabl ed and hidden independent of the state of this bit. if this component is not ca pable of dual independent display (capid0[78] = 1), then this bit is hardwired to 0b to hide device 2, function 1. 4 (82p45, 82p43 mch only) r/w/l 1b core reserved 3 (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) r/w/l 1b core internal graphics engine function 0 (d2f0en): 0 = bus 0, device 2, functi on 0 is disabled and hidden 1 = bus 0, device 2, function 0 is enabled and visible if this gmch does not have internal graphics capability (capid0[46] = 1), then device 2, function 0 is disabled and hidden independent of the state of this bit. 3 (82p45, 82p43 only) r/w/l 1b core reserved 2 ro 0b core reserved 1r / w / l1 bc o r e pci express port (d1en): 0 = bus 0, device 1, function 0 is disabled and hidden. 1 = bus 0, device 1, function 0 is enabled and visible. default value is determined by the device capa bilities (see capid0 [44]), sdvo presen ce hardware strap and the sdvo/pcie concurrent hardwa re strap. device 1 is disabled on reset if the sdvo presence strap was sampled high, and the sdvo/pcie concurrent strap was sampled low at the last assertion of pwrok, and is enabled by default otherwise. 0r o1 bc o r e host bridge (d0en): bus 0, device 0, function 0 may not be disabled and is therefore hardwired to 1. bit access default value rst/ pwr description datasheet 99 dram controller registers (d0:f0) 5.1.16 pciexbar?pci express re gister range base address b/d/f/type: 0/0/0/pci address offset: 60-67h default value: 00000000e0000000h access: ro, r/w/l, r/w/l/k size: 64 bits this is the base address for the pci expr ess configuration space. this window of addresses contains the 4 kb of configuration space for each pci express device that can potentially be part of th e pci express hierarchy associ ated with the (g)mch. there is not actual physical memory within this window of up to 256 mb that can be addressed. the actual length is determined by a field in this register. each pci express hierarchy requires a pci express base regi ster. the (g)mch supports one pci express hierarchy. the region reserved by this register does not alias to any pci 2.3 compliant memory mapped space. for example mchbar reserves a 16 kb space and chapadr reserves a 4 kb space both outside of pciexbar space. they cannot be overlayed on the space reserved by pciexbar for devices 0 and 7 respectively. on reset, this register is disabled and must be enabled by writing a 1 to the enable field in this register. this base address shall be assigned on a boundary consistent with the number of buses (defined by the length fi eld in this register), above tolud and still within 64 bit addressable memory space. all other bits not decoded are read only 0. the pci express base address cannot be less than the maximum address written to the top of physical memory register (tolud). software must ensure that these ranges do not overlap with known ranges located above tolud. software must ensure that the sum of length of enhanced configuratio n region + tolud + (other known ranges reserved above tolud) is not greater than the 64-bit addressable limit of 64 gb. in general system implementation and number of pci/pci express/pci-x buses supported in the hierarchy will dictate the length of the region. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/ pwr description 63:36 ro 0000000h core reserved 35:28 r/w/l 0eh core pci express base address (pciexbar): this field corresponds to bits 35:28 of the base address for pci express enhanced configuration space. bios will program this register resulting in a base address for a contiguous memory address space; size is defined by bits 2:1 of this register. this base address shall be assigned on a boundary consistent with the number of buses (defined by the length field in this register) above tolud and still within 64-bit addressable memory space. the address bits decoded depend on the length of the re gion defined by this register. the address used to access the pci express configuration space for a specific device ca n be determined as follows: pci express base address + bus number * 1mb + device number * 32kb + func tion number * 4kb the address used to access the pci express configuration space for device 1 in this component is: pci express base address + 0 * 1mb + 1 * 32kb + 0 * 4kb = pci express base address + 32kb. remember that this address is the beginning of the 4 kb space that contains both the pci compatible configuration space and the pci express extended configuration space. dram controller registers (d0:f0) 100 datasheet 27 r/w/l 0b core 128mb base address mask (128admsk): this bit is either part of the pci express base address (r/w) or part of the address mask (ro, read 0b), depending on the value of bits 2:1 in this register. 26 r/w/l 0b core 64mb base address mask (64admsk): this bit is either part of the pci express base address (r/w) or part of the address mask (ro, read 0b), de pending on the value of bits 2:1 in this register. 25:3 ro 000000h core reserved 2:1 r/w/l/k 00b core length (length): this field describes the length of this region. it provides the enhanced configuration space region/buses decoded 00 =256 mb (buses 0?255). bits 31:28 are decoded in the pci express base address field 01 = 128 mb (buses 0?127). bits 31:27 are decoded in the pci express base address field. 10 =64 mb (buses 0?63). bits 31:26 are decoded in the pci express base address field. 11 = reserved 0 r/w/l 0b core pciexbar enable (pciexbaren): 0 = the pciexbar register is disabled. memory read and write transactions proceed as if there were no pciexbar register. pciexbar bits 35:26 are r/w with no functionality behind them. 1 = the pciexbar register is enabled. memory read and write transactions whose address bits 35:26 match pciexbar will be translated to configuration reads and writes within the (g)mch. these translated cycles are routed as shown in the table above. bit access default value rst/ pwr description datasheet 101 dram controller registers (d0:f0) 5.1.17 dmibar?root complex re gister range base address b/d/f/type: 0/0/0/pci address offset: 68-6fh default value: 0000000000000000h access: ro, r/w/l size: 64 bits this is the base address for the root comp lex configuration spac e. this window of addresses contains the root complex register set for the pci express hierarchy associated with the (g)mch. there is no physical memory within this 4 kb window that can be addressed. the 4 kb reserved by this register does not alias to any pci 2.3 compliant memory mapped spac e. on reset, the root complex configuration space is disabled and must be enabled by writing a 1 to dmibaren [dev 0, offset 68h, bit 0]. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 63:36 ro 0000000h core reserved 35:12 r/w/l 000000h core dmi base address (dmibar): this field corresponds to bits 35:12 of the base addres s dmi configuration space. bios will program this register resulting in a base address for a 4 kb block of contiguous memory address space. this register ensures that a naturally aligned 4 kb space is allocated within the first 64 gb of addressable memory space. system software uses this base address to program the dmi register set. 11:1 ro 000h core reserved 0r/w/l 0b core dmibar enable (dmibaren): 0 = dmibar is disabled and does not claim any memory 1 = dmibar memory mapped accesses are claimed and decoded appropriately dram controller registers (d0:f0) 102 datasheet 5.1.18 pam0?programmable attribute map 0 b/d/f/type: 0/0/0/pci address offset: 90h default value: 00h access: ro, r/w/l size: 8 bits this register controls the read, write, and shadowing attributes of the bios area from 0f0000h?0fffffh. the (g)mch allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 kb to 1 mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlled vi a the mtrr registers in the processor. two bits are used to specify memory attributes for each memory segment. these bits apply to both host accesses and pci initiator accesses to the pam areas. these attributes are: re - read enable. when re = 1, the proce ssor read accesses to the corresponding memory segment are claimed by th e (g)mch and directed to main memory. conversely, when re = 0, the host read accesses are directed to pci_a. we - write enable. when we = 1, the host write accesses to the corresponding memory segment are claimed by th e (g)mch and directed to main memory. conversely, when we = 0, the host write accesses are directed to pci_a. the re and we attributes permit a memory segment to be read only, write only, read/write, or disabled. for example, if a memory segment has re = 1 and we = 0, the segment is read only. each pam register controls two regions, typically 16 kb in size. note that the (g)mch may hang if a pci express graphics attach or dmi originated access to read disabled or write disabled pam segments occur (due to a possible iwb to non-dram). for these reasons, the following critical rest riction is placed on the programming of the pam regions: at the time that a dmi or pci express graphics attach accesses to the pam region may occur, the targeted pam segment must be programmed to be both readable and writeable. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 7:6 ro 00b core reserved 5:4 r/w/l 00b core 0f0000h-0fffffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0f0000h to 0fffffh. 00 = dram disabled: all accesses are directed to dmi. 01 = read only: all reads are sent to dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:0 ro 0h core reserved datasheet 103 dram controller registers (d0:f0) 5.1.19 pam1?programmable attribute map 1 b/d/f/type: 0/0/0/pci address offset: 91h default value: 00h access: ro, r/w/l size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0c0000h?0c7fffh. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 7:6 ro 00b core reserved 5:4 r/w/l 00b core 0c4000h-0c7fffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0c4000h to 0c7fffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 ro 00b core reserved 1:0 r/w/l 00b core 0c0000h-0c3fffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0c0000h to 0c3fffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. dram controller registers (d0:f0) 104 datasheet 5.1.20 pam2?programmable attribute map 2 b/d/f/type: 0/0/0/pci address offset: 92h default value: 00h access: ro, r/w/l size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0c8000h?0cffffh. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/ pwr description 7:6 ro 00b core reserved 5:4 r/w/l 00b core 0cc000h-0cffffh attribute (hienable): 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 ro 00b core reserved 1:0 r/w/l 00b core 0c8000h-0cbfffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0c8000h to 0cbfffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operatio n: all reads and writes are serviced by dram. datasheet 105 dram controller registers (d0:f0) 5.1.21 pam3?programmable attribute map 3 b/d/f/type: 0/0/0/pci address offset: 93h default value: 00h access: ro, r/w/l size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0d0000h?0d7fffh. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 7:6 ro 00b core reserved 5:4 r/w/l 00b core 0d4000h-0d7fffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0d4000 to 0d7fff. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 ro 00b core reserved 1:0 r/w/l 00b core 0d0000h-0d3fffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0d0000h to 0d3fffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. dram controller registers (d0:f0) 106 datasheet 5.1.22 pam4?programmable attribute map 4 b/d/f/type: 0/0/0/pci address offset: 94h default value: 00h access: ro, r/w/l size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0d8000h?0dffffh. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 7:6 ro 00b core reserved 5:4 r/w/l 00b core 0dc000h-0dffffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0dc000h to 0dffffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 ro 00b core reserved 1:0 r/w/l 00b core 0d8000h-0dbfffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0d8000h to 0dbfffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. datasheet 107 dram controller registers (d0:f0) 5.1.23 pam5?programmable attribute map 5 b/d/f/type: 0/0/0/pci address offset: 95h default value: 00h access: ro, r/w/l size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0e0000h?0e7fffh. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 7:6 ro 00b core reserved 5:4 r/w/l 00b core 0e4000h-0e7fffh attribute (hienable): this field controls the steering of read and write cycles that address the bios area from 0e4000h to 0e7fffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 ro 00b core reserved 1:0 r/w/l 00b core 0e0000-0e3fff attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0e0000 to 0e3fff. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. dram controller registers (d0:f0) 108 datasheet 5.1.24 pam6?programmable attribute map 6 b/d/f/type: 0/0/0/pci address offset: 96h default value: 00h access: ro, r/w/l size: 8 bits this register controls the read, write, and shadowing attributes of the bios areas from 0e8000h?0effffh. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 7:6 ro 00b core reserved 5:4 r/w/l 00b core 0ec000h-0effffh attr ibute (hienable): this field controls the steering of read and write cycles that address the bios area from 0e4000h to 0e7fffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. 3:2 ro 00b core reserved 1:0 r/w/l 00b core 0e8000h-0ebfffh attribute (loenable): this field controls the steering of read and write cycles that address the bios area from 0e0000h to 0e3fffh. 00 = dram disabled: accesses are directed to dmi. 01 = read only: all reads are serviced by dram. all writes are forwarded to dmi. 10 = write only: all writes are sent to dram. reads are serviced by dmi. 11 = normal dram operation: all reads and writes are serviced by dram. datasheet 109 dram controller registers (d0:f0) 5.1.25 lac?legacy access control b/d/f/type: 0/0/0/pci address offset: 97h default value: 00h access: r/w, r/w/l, ro size: 8 bits this 8-bit register controls a fixed dram hole from 15?16 mb. bit access default value rst/ pwr description 7r/w/l0bcore hole enable (hen): this field enables a memory hole in dram space. the dram that lie s "behind" this space is not remapped. 0 = no memory hole. 1 = memory hole from 15 mb to 16 mb. this bit is intel txt lockable (82q45/82q43 gmch only). 6:2 ro 00h core reserved 1 (82p45 mch only) r/w 0b core peg1 mda present (mdap1): definition of this bit is the same as for the adjace nt peg0 mda present bit except for all references to device 1 are re placed with device 6. 1 (82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch and 82p43 mch only) r/w 0b core reserved dram controller registers (d0:f0) 110 datasheet 0r / w0 bc o r e peg0 mda present (mdap0): this bit works with the vga enable bits in the bctrl register of device 1 to control the routing of processor-initiated transactions targeting mda compatible i/o and memory address ranges. this bit should not be set if device 1's vga enable bit is not set. if device 1's vga enable bit is not set, then accesses to i/o address range x3bch?x3bfh are forwarded to dmi. if the vga enable bit is set and mda is not present, then accesses to io address range x3bch?x3bfh are forwarded to pci express if the address is within the corresponding iobase and iolimit, otherwise they are forwarded to dmi. mda resources are defined as the following: memory: 0b0000h?0b7fffh i/o: 3b4h, 3b5h, 3b8h , 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) any i/o reference that includ es the i/o locations listed above, or their aliases, will be forwarded to the dmi even if the reference includes i/o locations not listed above. the following table shows the behavior for all combinations of mda and vga: vgaen mdap description 0 0 all references to mda and vga space are routed to dmi 0 1 invalid combination 1 0 all vga and mda references are routed to pci express graphics attach. 1 1 all vga references are routed to pci express graphics attach. mda references are routed to dmi. vga and mda memory cycles can only be routed across the peg when mae (pcicmd1[1]) is set. vga and mda i/ o cycles can only be routed across the peg if ioae (pcicmd1[0]) is set. bit access default value rst/ pwr description datasheet 111 dram controller registers (d0:f0) 5.1.26 remapbase?remap base address register b/d/f/type: 0/0/0/pci address offset: 98-99h default value: 03ffh access: ro, r/w/l size: 16 bits 5.1.27 remaplimit?remap limit address register b/d/f/type: 0/0/0/pci address offset: 9a-9bh default value: 0000h access: ro, r/w/l size: 16 bits bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w/l 3ffh core remap base address [35:26] (remapbase): the value in this register define s the lower boundary of the remap window. the remap window is inclusive of this address. in the decoder a[ 25:0] of the remap base address are assumed to be 0s. thus the bottom of the defined memory range will be aligned to a 64 mb boundary. when the value in this regist er is greater than the value programmed into the remap limit register, the remap window is disabled. these bits are intel txt lockable (82q45/82q43 gmch only) or me stolen memory lockable. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w/l 000h core remap limit address [35:26] (remaplmt): the value in this register defines the upper boundary of the remap window. the remap window is inclusive of this address. in the decoder a[25:0] of the remap limit address are assumed to be fh. thus the top of the defined range will be one less than a 64 mb boundary. when the value in this register is less than the value programmed into the remap base register, the remap window is disabled. these bits are intel txt lockable (82q45/82q43 gmch only) or me stolen memory lockable. dram controller registers (d0:f0) 112 datasheet 5.1.28 smram?system ma nagement ram control b/d/f/type: 0/0/0/pci address offset: 9dh default value: 02h access: ro, r/w/l, r/w, r/w/l/k size: 8 bits the smramc register controls how acce sses to compatible and extended smram spaces are treated. the open, close, and lo ck bits function only when g_smrame bit is set to a 1. also, the open bit must be reset before the lock bit is set. bit access default value rst/pwr description 7 ro 0b core reserved 6 r/w/l 0b core smm space open (d_open): when d_open=1 and d_lck=0, the smm space dram is made visible even when smm decode is not active. this is intended to help bios initialize smm space. soft ware should ensure that d_open=1 and d_cls=1 are no t set at the same time. 5r/w 0b core smm space closed (d_cls): when d_cls = 1 smm space dram is not accessible to data references, even if smm decode is active. code references may still access smm space dram. this will allow smm software to reference through smm space to update the display even when smm is mapped over the vga range. software should ensure that d_open=1 and d_cls=1 are not set at the same time. 4 r/w/l/k 0b core smm space locked (d_lck): when d_lck is set to 1 then d_open is reset to 0 and d_lck, d_open, c_base_seg, h_smram_en, tseg_sz and tseg_en become read only. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a full reset. the combination of d_lck and d_open provide convenience with security. the bios can use the d_open function to initialize smm space and then use d_lck to "lock down" smm space in the fu ture so that no application software (or bios itself) can violate the integrity of smm space, even if the program has knowledge of the d_open function. 3 r/w/l 0b core global smram enable (g_smrame): if set to a 1, then compatible smram function s are enabled, providing 128 kb of dram accessible at the a0000h address while in smm (adsb with smm decode). to enable extended smram function this bit has be set to 1. refer to the section on smm for more detail s. once d_lck is set, this bit becomes read only. 2:0 ro 010b core compatible smm space base segment (c_base_seg): this field indicates the location of smm space. smm dram is not rema pped. it is simply made visible if the conditions are right to access smm space, otherwise the access is forwarded to dmi. since the (g)mch supports only the smm space between a0000h and bffffh, this field is hardwired to 010b. datasheet 113 dram controller registers (d0:f0) 5.1.29 esmramc?extended system management ram control b/d/f/type: 0/0/0/pci address offset: 9eh default value: 38h access: r/w/l, r/wc, ro size: 8 bits the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) memory provides a write-back cacheable smram memory space that is above 1 mb. bit access default value rst/pwr description 7r/w/l 0b core enable high smram (h_smrame): controls the smm memory space location (i.e., above 1 mb or below 1 mb) when g_smrame is 1 and h_smrame is set to 1, the high smram memory space is enabled. smram accesses within the range 0feda0000h to 0fedbffffh are remapped to dram addresses within the range 000a0000h to 000bffffh. once d_lck has be en set, this bit becomes read only. 6r/wc 0b core invalid smram access (e_smerr): this bit is set when the processor has accessed the defined memory ranges in extended smram (high memory and t-segment) while not in smm space and with the d-open bit = 0. it is software's responsibility to clear this bit. the software must write a 1 to this bit to clear it. 5r o 1 b c o r e smram cacheable (sm_cache): this bit is forced to 1 by the (g)mch. 4r o 1 b c o r e l1 cache enable for smram (sm_l1): this bit is forced to 1 by the (g)mch. 3r o 1 b c o r e l2 cache enable for smram (sm_l2): this bit is forced to 1 by the (g)mch. dram controller registers (d0:f0) 114 datasheet 5.1.30 tom?top of memory b/d/f/type: 0/0/0/pci address offset: a0-a1h default value: 0001h access: ro, r/w/l size: 16 bits this register contains the size of physical memory. bios determines the memory size reported to the os using this register. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). 2:1 r/w/l 00b core tseg size (tseg_sz): selects the size of the tseg memory block if enabled. memory from the top of dram space is partitioned away so th at it may only be accessed by the processor interface and only then when the smm bit is set in the request packet. non-smm accesses to this memory region are sent to dmi when the tseg memory block is enabled. 00 = 1 mb tseg. (tolud ? gtt graphics memory size ? graphics stolen memory size ? 1m) to (tolud ? gtt graphics memory size ? graphics stolen memory size). 01 = 2 mb tseg (tolud ? gtt graphics memory size ? graphics stolen memory size ? 2m) to (tolud ? gtt graphics memory size ? graphics stolen memory size). 10 = 8 mb tseg (tolud ? gtt graphics memory size ? graphics stolen memory size ? 8m) to (tolud ? gtt graphics memory size ? graphics stolen memory size). 11 = reserved. once d_lck has been set, these bits becomes read only. 0 r/w/l 0b core tseg enable (t_en): enabling of smram memory for extended smram space only. when g_smrame = 1 and tseg_en = 1, the tseg is enabled to appear in the appropriate physical address sp ace. note that once d_lck is set, this bit becomes read only. bit access default value rst/pwr description bit access default value rst/pwr description 15:10 ro 00h core reserved 9:0 r/w/l 001h core top of memory (tom): this register reflects the total amount of populated physic al memory. this is not necessarily the highest main memory address (holes may exist in main memory addr ess map due to addresses allocated for memory-mapped i/ o). these bits correspond to address bits 35:26 (64 mb granularity). bits 25:0 are assumed to be 0. the (g)mch determines the base of ep stolen memory by subtracting the ep stolen memory size from tom. datasheet 115 dram controller registers (d0:f0) 5.1.31 touud?top of upper usable dram b/d/f/type: 0/0/0/pci address offset: a2-a3h default value: 0000h access: r/w/l size: 16 bits this 16 bit register defines the top of upper usable dram. configuration software must set this value to tom minus all ep stolen memory if reclaim is disabled. if reclaim is enabled, th is value must be set to reclaim limit + 1byte 64 mb aligned since reclaim limit is 64m b aligned. address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. the host interface positively decodes an address towards dram if the incoming address is less than the value programmed in this register and greater than or equal to 4 b. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 15:0 r/w/l 0000h core touud (touud): this register contai ns bits 35:20 of an address one byte above the maximum dram memory above 4 gb that is usable by the operating system. configuration software must set this value to tom minus all ep stolen memory , if reclaim is disabled. if reclaim is enabled, this value must be set to reclaim limit 64 mb aligned since reclaim limit + 1byte is 64 mb aligned. address bits 19:0 are assumed to be 000_0000h for the purposes of address compar ison. the host interface positively decodes an address towards dram if the incoming address is less than the value programmed in this register and greater than 4 gb. dram controller registers (d0:f0) 116 datasheet 5.1.32 gbsm?graphics base of stolen memory (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) b/d/f/type: 0/0/0/pci address offset: a4-a7h default value: 00000000h access: r/w/l, ro size: 32 bits this register contains the base address of graph ics data stolen dram memory. bios determines the base of graphics data stolen memory by subtract ing the graphics data stolen memory size (pci device 0, offset 52h, bits 6:4) f rom tolud (pci device 0, offset b0h, bits 15:4). note: this register is locked and becomes read only w hen the d_lck bit in the smram register is set. 5.1.33 bgsm?base of gtt stolen memory (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) b/d/f/type: 0/0/0/pci address offset: a8-abh default value: 00000000h access: r/w/l, ro size: 32 bits this register contains the base address of stolen dram memory for the gtt. bios determines the base of gtt stolen memory by subtracting the gtt graphics stolen memory size (pci device 0, offset 52h, bits 9:8) from the graphics stolen memory base (pci device 0, offset a4h, bits 31:20). note: this register is locked and becomes read only when the d_lck bit in the smram register is set. bit access default value rst/pwr description 31:20 r/w/l 000h core graphics base of stolen memory (gbsm): this register contains bits 31:20 of the base address of stolen dram memory. bios determines the base of graphics stolen memory by subtracting the gr aphics stolen memory size (pci device 0, offset 52h, bits 6:4) from tolud (pci device 0, offset b0h, bits 15:4). note: this register is locked and becomes read only when the d_lck bit in the smram register is set. 19:0 ro 00000h core reserved bit access default value rst/pwr description 31:20 r/w/l 000h core graphics base of stolen memory (gbsm): this register contains bits 31:20 of the base address of stolen dram memory. bios determin es the base of graphics stolen memory by subtracting the graphics stolen memory size (pci device 0, offset 52h, bits 9:8) from the graphics stolen memory base (pci de vice 0, offset a4h, bits 31:20). note: this register is locked and becomes read only when the d_lck bit in the smram register is set. 19:0 ro 00000h core reserved datasheet 117 dram controller registers (d0:f0) 5.1.34 tsegmb?tseg memory base b/d/f/type: 0/0/0/pci address offset: ac-afh default value: 00000000h access: ro, r/w/l size: 32 bits this register contains the base address of t seg dram memory. bios determines the base of tseg memory by subtracting the tseg size (pci device 0, offset 9eh, bits 2:1) f rom graphics gtt stolen base (pci device 0, offset a8h, bits 31:20). once d_lck has been set, these bits becomes read only. 5.1.35 tolud?top of low usable dram b/d/f/type: 0/0/0/pci address offset: b0-b1h default value: 0010h access: r/w/l, ro size: 16 bits this 16 bit register defines the top of low usable dram. tseg, gtt graphics memory and graphics stolen memory are within the dram space defined. from the top, (g)mch optionally claims 1 to 64 mb of dram for internal graphics if enabled, 1, 2 mb of dram for gtt graphics stolen memory (if enabled) and 1, 2, or 8 mb of dram for tseg if enabled. programming example: c1drb3 is set to 4 gb tseg is enabled and tseg size is set to 1 mb internal graphics is enabled, and graphics mode select is set to 32 mb gtt graphics stolen memory size set to 2 mb bios knows the operating system requires 1 gb of pci space. bios also knows the range from fec0_00 00h to ffff_ffffh is not usable by the system. this 20 mb range at the very top of addressable memory space is lost to apic and intel txt (82q45/82q43 gmch only). according to the above equation, tolud is originally calculated to: 4 gb = 1_0000_0000h the system memory requirements are: 4 gb (max addressable space) ? 1 gb (pci space) ? 35 mb (lost memory) = 3 gb ? 35 mb (minimum granularity) = ecb0_0000h. bit access default value rst/pwr description 31:20 r/w/l 000h core tesg memory base (tsegmb): this register contains bits 31:20 of the base addr ess of tseg dram memory. bios determines the base of tseg memory by subtracting the tseg size (pci device 0, offset 9eh, bits 2:1) from graphics gtt stolen base (pci device 0, offset a8h, bits 31:20). once d_lck has been set, th ese bits becomes read only. 19:0 ro 00000h core reserved dram controller registers (d0:f0) 118 datasheet since ecb0_0000h (pci and other system requirements) is less than 1_0000_0000h, tolud should be programmed to ecbh. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). 5.1.36 errsts?error status b/d/f/type: 0/0/0/pci address offset: c8-c9h default value: 0000h access: ro, r/wc/s size: 16 bits this register is used to report various error conditions via the serr dmi messaging mechanism. an serr dmi message is generated on a zero to one transition of any of these flags (if enabled by the errcmd and pcicmd registers). these bits are set regardless of whether or not the serr is enabled and generated. after the error processing is complete, the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it. bit access default value rst/ pwr description 15:4 r/w/l 001h core top of low usable dram (tolud): this register contains bits 31:20 of an address one byte above the maximum dram memory below 4 gb that is usab le by the operating system. address bits 31:20 programmed to 01h implies a minimum memory size of 1 mb. configur ation software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus me stolen memory plus one byte or the minimum address allocated for pci memory. address bits 19:0 are assumed to be 0_0000h for the purposes of address compar ison. the host interface positively decodes an address towards dram if the incoming address is less than the value programmed in this register. note that the top of low usable dram is the lowest address above both graphics stolen memory and tseg. bios determines the base of gr aphics stolen memory by subtracting the graphics stolen memory size from tolud and further decrements by tseg size to determine base of tseg. this register must be 64 mb aligned when reclaim is enabled. 3:0 ro 0000b core reserved datasheet 119 dram controller registers (d0:f0) bit access default value rst/pwr description 15:13 ro 000b core reserved 12 r/wc/s 0b core (g)mch software generated event for smi (gsgesmi): this indicates the source of the smi was a device 2 software event. 11 r/wc/s 0b core (g)mch thermal sensor event for smi/sci/serr (gtse): this bit indicates that a (g)mch thermal sensor trip has occurred and an sm i, sci, or serr has been generated. the status bit is se t only if a message is sent based on thermal event enab les in error command, smi command and sci command registers. a trip point can generate one of smi, sci, or serr interrupts (two or more per event is invalid). multiple trip points can generate the same interrupt, if software chooses this mode, subsequent trips may be lost. if this bit is already set, then an interrupt message will not be sent on a new thermal sensor event. 10 ro 0b core reserved 9r/wc/s 0b core lock to non-dram memory flag (lckf): when this bit is set to 1, the (g)mch has detected a lock operation to memory space that did not map into dram. 8 ro 0b core received refresh timeout flag (rrtof): reserved 7r/wc/s 0b core dram throttle flag (dtf): 1 = indicates that a dram throttling condition occurred. 0 = software has cleared this flag since the most recent throttling event. 6:2 ro 00h core reserved 1r/wc/s 0b core multiple-bit dram ecc error flag (dmerr): if this bit is set to 1, a memory re ad data transfer had an uncorrectable multiple-bit error. when this bit is set the address, channel number, and device number that caused the error are logged in the deap register. once this bit is set, the deap, derrsyn, and derrdst fields are locked until the processor clears this bit by writing a 1. software uses bits [1:0] to detect whether the logged error address is for single or multiple-bit error. this bit is reset on pwrok. 0r/wc/s 0b core single-bit dram ecc error flag (dserr): if this bit is set to 1, a memory read data transfer had a single-bit correctable error an d the corrected data was sent for the access. when this bit is se t, the address and device number that caused the e rror are logged in the deap register. once this bit is set, the deap, derrsyn, and derrdst fields are locked to further single bit error updates until the processor clears this bit by writing a 1. a multiple bit error that occurs after this bit is set will overwrite the deap and derrsyn fields with the multiple- bit error signature and the dme rr bit will also be set. a single bit error that occurs af ter a multi-bit error will set this bit but will not overwrite the other fields. this bit is reset on pwrok. dram controller registers (d0:f0) 120 datasheet 5.1.37 errcmd?error command b/d/f/type: 0/0/0/pci address offset: ca-cbh default value: 0000h access: r/w, ro size: 16 bits this register controls the (g)mch responses to various system errors. since the (g)mch does not have an serrb signal, serr messages are passed from the (g)mch to the ich over dmi. when a bit in this register is set, a se rr message will be generated on dmi whenever the corresponding flag is set in the errsts register. the actual generation of the serr message is globally enabled for device 0 via the pci command register. bit access default value rst/ pwr description 15:12 ro 0h core reserved 11 r/w 0b core serr on (g)mch thermal sensor event (tseserr): 1 = the (g)mch generates a dmi serr special cycle when bit 11 of the errsts is set. the serr mu st not be enabled at the same time as the smi for the same thermal sensor event. 0 = reporting of this condition via serr messaging is disabled. 10 ro 0b core reserved 9r/w 0b core serr on lock to non-dram memory (lckerr): 1 = the (g)mch will generate a dmi serr special cycle whenever a processor lock cycle is detected that does not hit dram. 0 = reporting of this condition via serr messaging is disabled. 8r/w 0b core serr on dram refresh timeout (drtoerr): 1 = the (g)mch generates a dmi serr special cycle when a dram refresh timeout occurs. 0 = reporting of this condition via serr messaging is disabled. 7r/w 0b core serr on dram throttle condition (dtcerr): 1 = the (g)mch generates a dmi serr special cycle when a dram read or write throttle condition occurs. 0 = reporting of this condition via serr messaging is disabled. 6:2 ro 00h core reserved 1r/w 0b core serr multiple-bit dram ecc error (dmerr): 1 = the (g)mch generates a serr message over dmi when it detects a multiple-bit error re ported by the dram controller. 0 = reporting of this condition via serr messaging is disabled. for systems not supporting ecc, th is bit must be disabled. 0r/w 0b core serr on single-bit ecc error (dserr): 1 = the (g)mch generates a serr special cycle over dmi when the dram controller detects a single bit error. 0 = reporting of this condition via serr messaging is disabled. for systems that do not support e cc, this bit must be disabled. datasheet 121 dram controller registers (d0:f0) 5.1.38 smicmd?smi command b/d/f/type: 0/0/0/pci address offset: cc-cdh default value: 0000h access: ro, r/w size: 16 bits this register enables various errors to ge nerate an smi dmi special cycle. when an error flag is set in the errsts register, it can generate an serr, smi, or sci dmi special cycle when enabled in the e rrcmd, smicmd, or scicmd registers, respectively. note that one and only one message type can be enabled. bit access default value rst/pwr description 15:12 ro 0h core reserved 11 r/w 0b core smi on (g)mch thermal sensor trip (tstsmi): 1 = a smi dmi special cycle is generated by (g)mch when the thermal sensor trip requires an smi. a thermal sensor trip point cannot generate more than one special cycle. 0 = reporting of this condition via smi messaging is disabled. 10:2 ro 000h core reserved 1r/w 0b core smi on multiple-bit dram ecc error (dmesmi): 1 = the (g)mch generates an smi dmi message when it detects a multiple-bit erro r reported by the dram controller. 0 = reporting of this condition via smi messaging is disabled. for systems not supporting ecc this bit must be disabled. 0r/w 0b core smi on single-bit ecc error (dsesmi): 1 = the (g)mch generates an smi dmi special cycle when the dram controller detects a single bit error. 0 = reporting of this condition via smi messaging is disabled. for systems that do not support ecc this bit must be disabled. dram controller registers (d0:f0) 122 datasheet 5.1.39 skpd?scratchpad data b/d/f/type: 0/0/0/pci address offset: dc-dfh default value: 00000000h access: r/w size: 32 bits this register holds 32 writable bits with no functionality behind them. it is for the convenience of bios and graphics drivers. 5.1.40 capid0?capability identifier b/d/f/type: 0/0/0/pci address offset: e0-ech default value: 000000000000000000010c0009h access: ro size: 104 bits bios optimal default 0h bit access default value rst/pwr description 31:0 r/w 00000000h core scratchpad data (skpd): 1 dword of data storage. bit access default value rst/pwr description 103:28 ro 0000b core reserved 27:24 ro 1h core capid version (capidv): this field has the value 0001b to identify the first revision of the capid register definition. 23:16 ro 0ch core capid length (capidl): this field has the value 0ch to indicate the structure length (12 bytes). 15:8 ro 00h core next capability pointer (ncp): this field is hardwired to 00h indicating the end of th e capabilities linked list. 7:0 ro 09h core capability identifier (cap_id): this field has the value 1001b to identify the cap_id assigned by the pci sig for vendor dependent capability pointers. datasheet 123 dram controller registers (d0:f0) 5.2 mchbar address offset register symbol register name default value access 111h chdecmisc channel decode miscellaneous 00h r/w/l, r/w 200?201h c0drb0 channel 0 dram rank boundary address 0 0000h r/w/l, ro 202?203h c0drb1 channel 0 dram rank boundary address 1 0000h ro, r/w/l 204?205h c0drb2 channel 0 dram rank boundary address 2 0000h ro, r/w/l 206?207h c0drb3 channel 0 dram rank boundary address 3 0000h r/w, ro 208?209h c0dra01 channel 0 dram rank 0,1 attribute 0000h r/w/l 20a?20bh c0dra23 channel 0 dram rank 2,3 attribute 0000h r/w/l 250?251h c0cyctrkpchg channel 0 cyctrk pchg 0000h r/w, ro 252?255h c0cyctrkact channel 0 cyctrk act 00000000h r/w, ro 256?257h c0cyctrkwr channel 0 cyctrk wr 0000h r/w 258?25ah c0cyctrkrd channel 0 cyctrk read 000000h r/w, ro 25b?25ch c0cyctrkrefr channel 0 cyctrk refr 0000h ro, r/w 260?263h c0ckectrl channel 0 cke control 00000800h r/w, ro 269?26eh c0refrctrl channel 0 dram refresh control 241830000c 30h r/w, ro 29c?29fh c0odtctrl channel 0 odt control 00000000h ro, r/w 602?603h c1drb1 channel 1 dram rank boundary address 1 0000h r/w/l, ro 604?605h c1drb2 channel 1 dram rank boundary address 2 0000h r/w/l, ro 606?607h c1drb3 channel 1 dram rank boundary address 3 0000h r/w, ro 608?609h c1dra01 channel 1 dram rank 0,1 attributes 0000h r/w/l 60a?60bh c1dra23 channel 1 dram rank 2,3 attributes 0000h r/w/l 650?651h c1cyctrkpchg channel 1 cyctrk pchg 0000h r/w, ro 652?655h c1cyctrkact channel 1 cyctrk act 00000000h r/w, ro 656?657h c1cyctrkwr channel 1 cyctrk wr 0000h r/w 658?65ah c1cyctrkrd channel 1 cyctrk read 000000h r/w, ro 660?663h c1ckectrl channel 1 cke control 00000800h r/w, ro 669?66eh c1refrctrl channel 1 dram refresh control 241830000c 30h r/w, ro 69c?69fh c1odtctrl channel 1 odt control 00000000h r/w, ro a00?a01h epc0drb0 ep channel 0 dram rank boundary address 0 0000h r/w, ro a02?a03h epc0drb1 ep channel 0 dram rank boundary address 1 0000h ro, r/w a04?a05h epc0drb2 ep channel 0 dram rank boundary address 2 0000h ro, r/w a06? a07h epc0drb3 ep channel 0 dram rank boundary address 3 0000h r/w, ro dram controller registers (d0:f0) 124 datasheet a08?a09h epc0dra01 ep channel 0 dram rank 0,1 attribute 0000h r/w a0a?a0bh epc0dra23 ep channel 0 dram rank 2,3 attribute 0000h r/w a19?a1ah epdcyctrkwr tpre epd cyctrk wrt pre 0000h r/w, ro a1c?a1fh epdcyctrkwr tact epd cyctrk wrt act 00000000h ro, r/w a20?a21h epdcyctrkwr twr epd cyctrk wrt wr 0000h r/w, ro a22?a23h epdcyctrkwr tref epd cyctrk wrt ref 0000h ro, r/w a24?a26h epdcyctrkwr trd epd cyctrk wrt read 000000h r/w a28?a2ch epdckeconfig reg epd cke related configuration registers 00e0000000 h r/w a30?a33h epdrefconfig ep dram refresh configuration 40000c30h ro, r/w cd8h tsc1 thermal sensor control 1 00h r/w/l, r/w, rs/wc cd9h tsc2 thermal sensor control 2 00h r/w/l, ro cdah tss thermal sensor status 00h ro cdc?cdfh tsttp thermal sensor temperature trip point 00000000h ro, r/w, r/w/l ce2h tco thermal calibration offset 00h r/w/l/k, r/w/l ce4h therm1 hardware throttle control 00h ro, r/w/l, r/w/l/k cea?cebh tis thermal interrupt status 0000h r/wc, ro cf1h tsmicmd thermal smi command 00h ro, r/w f14?f17h pmsts power management status 00000000h r/wc/s, ro address offset register symbol register name default value access datasheet 125 dram controller registers (d0:f0) 5.2.1 chdecmisc?channel decode miscellaneous b/d/f/type: 0/0/0/mchbar address offset: 111h default value: 00h access: r/w/l, r/w size: 8 bits this register provides miscellaneous chdec/magen configuration bits. bit access default value rst/pwr description 7r/w/l 0b core enhanced address for dimm select (enhdimmsel): this bit can be set when enha nced mode of addressing for ranks are enabled and all four ranks are populated with equal amount of memory. this should be disabled when ep is present. 0 = use standard methods for dimm select. 1 = use enhanced address as dimm select. this field is locked by me stolen memory lock. 6:5 r/w/l 00b core enhanced mode select (enhmodesel): 00 = swap enabled for bank selects and rank selects 01 = xor enabled for bank selects and rank selects 10 = swap enabled for bank selects only 11 = xor enabled for bank select only this field is locked by me stolen memory lock. 4r/w/l 0b core l-shaped gfx tile cycle (lgfxtlcyc): this bit forces graphics tiled cycles in l-shaped memory configuration to modify bit 6 of the address. th is field should be set to 1 only when l-mode memory co nfiguration is enabled and should be set to 0 for all other memory configurations. this bit is locked by me stolen memory lock. 3r/w/l 0b core ch1 enhanced mode (ch1_enhmode): this bit indicates that enhanced addressing mode of operation is enabled for ch1. enhanced addressing mode of operation should be enabled only when both the channels are equally populated with same size and same type of dram memory. an added restriction is that the number of ranks/channel has to be 1, 2, or 4. note: if any of the channels is in enhanced mode, the other channel should also be in enhanced mode. this bit is locked by me stolen memory lock. dram controller registers (d0:f0) 126 datasheet 5.2.2 c0drb0?channel 0 dram rank boundary address 0 b/d/f/type: 0/0/0/mchbar address offset: 200-201h default value: 0000h access: r/w/l, ro size: 16 bits the dram rank boundary registers define th e upper boundary address of each dram rank with a granularity of 64 mb. each rank has its own single-word drb register. these registers are used to determine which chip select will be active for a given address. channel and rank map: ch0 rank0: 200h ch0 rank1: 202h ch0 rank2: 204h ch0 rank3: 206h ch1 rank0: 600h ch1 rank1: 602h ch1 rank2: 604h ch1 rank3: 606h 2 r/w/l 0b core ch0 enhanced mode (ch0_enhmode): this bit indicates that enhanced addressing mode of operation is enabled for ch0. enhanced addressing mode of operation should be enabled only when both the channels are equally populated with same size and same type of dram memory. an added restriction is that the number of ranks/channel has to be 1, 2, or 4. note: if any of the two channels is in enhanced mode, the other channel should also be in enhanced mode. this bit is locked by me stolen memory lock. 1 r/w/l 0b core stacked memory (stkmem): this bit disables the l shaped memory configuration. when this bit is set, all the three channel memory appear s as stacked, one above other. this bit is locked by me stolen memory lock. 0r/w 0b core ep present (epprsnt): this bit indicates whether ep uma is present in the system or not. this bit is locked by me stolen memory lock. bit access default value rst/pwr description datasheet 127 dram controller registers (d0:f0) programming guide non-stacked mode if channel 0 is empty, all of the c0drbs are programmed with 00h. c0drb0 = total memory in ch0 rank0 (in 64 mb increments) c0drb1 = total memory in ch0 rank 0 + ch0 rank1 (in 64 mb increments) and so on. if channel 1 is empty, all of the c1drbs are programmed with 00h. c1drb0 = total memory in ch1 rank0 (in 64 mb increments) c1drb1 = total memory in ch1 rank 0 + ch1 rank1 (in 64 mb increments) and so on. stacked mode: codrbs: similar to non-stacked mode. c1drb0, c1drb1 and c1drb2: they are also programmed similar to non-stacked mode. only exception is, the drbs corresponding to the topmost populated rank and the (unpopulated) higher ranks in channel 1 must be programmed with the value of the total channel 1 population plus the value of total channe l 0 population (c0drb3). example: if only ranks 0 and 1 are po pulated in ch1 in stacked mode, then c1drb0 = total memory in ch1 rank0 (in 64 mb increments) c1drb1 = c0drb3 + total memory in ch1 rank0 + ch1 rank1 (in 64 mb increments) (rank 1 is the topmost populated rank) c1drb2 = c1drb1 c1drb3 = c1drb1 c1drb3: c1drb3 = c0drb3 + total memory in channel 1. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w/l 000h core channel 0 dram rank boundary address 0 (c0drba0): this register defi nes the dram rank boundary for rank0 of cha nnel 0 (64 mb granularity) =r0 r0 = total rank0 memory size/64 mb r1 = total rank1 memory size/64 mb r2 = total rank2 memory size/64 mb r3 = total rank3 memory size/64 mb this register is locked by me stolen memory lock. dram controller registers (d0:f0) 128 datasheet 5.2.3 c0drb1?channel 0 dram rank boundary address 1 b/d/f/type: 0/0/0/mchbar address offset: 202-203h default value: 0000h access: ro, r/w/l size: 16 bits see the c0drb0 register for detailed descriptions. 5.2.4 c0drb2?channel 0 dram rank boundary address 2 b/d/f/type: 0/0/0/mchbar address offset: 204-205h default value: 0000h access: ro, r/w/l size: 16 bits see the c0drb0 register for detailed descriptions. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w/l 000h core channel 0 dram rank boundary address 1 (c0drba1): this register defines the dram rank boundary for rank1 of channel 0 (64 mb granularity) =(r1 + r0) r0 = total rank0 memory size/64 mb r1 = total rank1 memory size/64 mb r2 = total rank2 memory size/64 mb r3 = total rank3 memory size/64 mb this register is locked by me stolen memory lock. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w/l 000h core channel 0 dram rank boundary address 2 (c0drba2): this register defines the dram rank boundary for rank2 of channel 0 (64 mb granularity) =(r2 + r1 + r0) r0 = total rank0 memory size/64 mb r1 = total rank1 memory size/64 mb r2 = total rank2 memory size/64 mb r3 = total rank3 memory size/64 mb this register is locked by me stolen memory lock. datasheet 129 dram controller registers (d0:f0) 5.2.5 c0drb3?channel 0 dram rank boundary address 3 b/d/f/type: 0/0/0/mchbar address offset: 206-207h default value: 0000h access: r/w, ro size: 16 bits see the c0drb0 register for detailed descriptions. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w 000h core channel 0 dram rank boundary address 3 (c0drba3): this register defi nes the dram rank boundary for rank3 of cha nnel 0 (64 mb granularity) =(r3 + r2 + r1 + r0) r0 = total rank0 memory size/64mb r1 = total rank1 memory size/64mb r2 = total rank2 memory size/64mb r3 = total rank3 memory size/64mb this register is locked by me stolen memory lock. dram controller registers (d0:f0) 130 datasheet 5.2.6 c0dra01?channel 0 dr am rank 0,1 attribute b/d/f/type: 0/0/0/mchbar address offset: 208-209h default value: 0000h access: r/w/l size: 16 bits the dram rank attribute registers define the page sizes/number of banks to be used when accessing different ranks. these register s should be left with their default value (all zeros) for any rank that is unpopula ted, as determined by the corresponding cxdrb registers. each byte of information in the cxdra registers describes the page size of a pair of ranks. channel and rank map: ch0 rank0, 1: 208h-209h ch0 rank2, 3: 20ah-20bh ch1 rank0, 1: 608h - 609h ch1 rank2, 3: 60ah - 60bh dra[6:0] = "00" means cfg0, dra[6:0] ="01" means cfg1.... dra[6:0] = "09" means cfg9 and so on. dra[7] indicates whether it's an 8 bank config or not. dra[7] = 0 means 4 bank, dra[7] = 1 means 8 bank. table 12. dram rank attribute register programming cfg tech ddrx depth width row col bank size size 0 256mb 2 32m 8 13 10 2 256 mb 8k 1 256mb 2 16m 16 13 9 2 128 mb 4k 2 512mb 2 64m 8 14 10 2 512 mb 8k 3 512mb 2 32m 16 13 10 2 256 mb 8k 4 512mb 3 64m 8 13 10 3 512 mb 8k 5 512mb 3 32m 16 12 10 3 256 mb 8k 6 1 gb 2,3 128m 8 14 10 3 1 gb 8k 7 1 gb 2,3 64m 16 13 10 3 512 mb 8k 8 2 gb 2,3 256m 8 15 10 3 2 gb 8k 9 2 gb 2,3 128m 16 14 10 3 1 gb 8k bit access default value rst/pwr description 15:8 r/w/l 00h core channel 0 dram rank-1 attributes (c0dra1): this register defines dram page size/number-of-banks for rank1 for given channel . see ta b l e 1 2 . this register is locked by me stolen memory lock. 7:0 r/w/l 00h core channel 0 dram rank-0 attributes (c0dra0): this register defines dram page size/number-of-banks for rank0 for given channel. see ta b l e 1 2 . this register is locked by me stolen memory lock. datasheet 131 dram controller registers (d0:f0) 5.2.7 c0dra23?channel 0 dr am rank 2,3 attribute b/d/f/type: 0/0/0/mchbar address offset: 20a-20bh default value: 0000h access: r/w/l size: 16 bits see the c0dra01 register for detailed descriptions. 5.2.8 c0cyctrkpchg?ch annel 0 cyctrk pchg b/d/f/type: 0/0/0/mchbar address offset: 250-251h default value: 0000h access: r/w, ro size: 16 bits this register is for channel 0 cyctrk precharge control. bit access default value rst/pwr description 15:8 r/w/l 00h core channel 0 dram rank-3 attributes (c0dra3): this register defines dram page size/number-of-banks for rank3 for given channel. see ta b l e 1 2 . this register is locked by me stolen memory lock. 7:0 r/w/l 00h core channel 0 dram rank-2 attributes (c0dra2): this register defines dram page size/number-of-banks for rank2 for given channel. see ta b l e 1 2 . this register is locked by me stolen memory lock. bit access default value rst/pwr description 15:11 ro 00000b core reserved 10:6 r/w 00000b core write to pre delayed (c0sd_cr_wr_pchg): this configuration register indi cates the minimum allowed spacing (in dram clocks) between the write and pre commands to the same rank-bank.this field corresponds to twr in the ddr specification. 5:2 r/w 0000b core read to pre delayed (c0sd_cr_rd_pchg): this field indicates the minimum allowed spacing (in dram clocks) between the read and pre commands to the same rank- bank 1:0 r/w 00b core pre to pre delayed (c0sd_cr_pchg_pchg): this field indicates the minimum allowed spacing (in dram clocks) between two pre commands to the same rank. dram controller registers (d0:f0) 132 datasheet 5.2.9 c0cyctrkact?cha nnel 0 cyctrk act b/d/f/type: 0/0/0/mchbar address offset: 252-255h default value: 00000000h access: r/w, ro size: 32 bits this register is for channel 0 cyctrk activate. bit access default value rst/pwr description 31:30 ro 0h core reserved 29 r/w 0b core faw windowcnt bug fix disable (c0sd_cr_cyctrk_faw_wi ndowcnt_fix_disable): this configuration register disabl es the cyctrk faw windowcnt bug fix. 1 = disable cyctrk faw windowcnt bug fix 0 = enable cyctrk faw windowcnt bug fix 28 r/w 0b core faw phase bug fix disable (c0sd_cr_cyctrk_faw_phase_fix_disable): this configuration register disables the cyctrk faw phase indicator bug fix. 1 = disable cyctrk faw phase indicator bug fix 0 = enable cyctrk faw phase indicator bug fix 27:22 r/w 000000b core act window count (c0sd_cr_act_windowcnt): this configuration register indicates the window duration (in dram clocks) during which the controller counts the # of activate commands which are launched to a particular rank. if the number of activate commands launched within this window is greater than 4, then a check is implemented to block launch of further activa tes to this rank for the rest of the duration of this window. 21 r/w 0b core max act check (c0sd_cr_maxact_dischk): this configuration register enables the check which ensures that there are no more than fo ur activates to a particular rank in a given window. 20:17 r/w 0000b core act to act delayed (c0sd_cr_act_act[): this configuration register indicates the minimum allowed spacing (in dram clocks) betw een two act commands to the same rank. this field corre sponds to trrd in the ddr specification. 16:13 r/w 0000b core pre to act delayed (c0sd_cr_pre_act): this configuration register indicates the minimum allowed spacing (in dram clocks) between the pre and act commands to the same rank-bank:12:9r/w0000bpre-all to act delayed (c0sd_cr_preall_act):this configuration register indicates the minimu m allowed spacing (in dram clocks) between the pre-all and act commands to the same rank. this field corre sponds to trp in the ddr specification. datasheet 133 dram controller registers (d0:f0) 5.2.10 c0cyctrkwr?channel 0 cyctrk wr b/d/f/type: 0/0/0/mchbar address offset: 256-257h default value: 0000h access: r/w size: 16 bits 12:9 r/w 0h core allpre to act delay (c0sd0_cr_preall_act): from the launch of a prechargeall command wait for these many # of memory clocks before launching a activate command. this field corresponds to tpall_rp. in the ddr specification. 8:0 r/w 000000000b core ref to act delayed (c0sd_cr_rfsh_act): this configuration register indi cates the minimum allowed spacing (in dram clocks ) between ref and act commands to the same rank. this field corresponds to trfc in the ddr specification. bit access default value rst/pwr description bit access default value rst/pwr description 15:12 r/w 0h core act to write delay (c0sd_cr_act_wr): this configuration register indi cates the minimum allowed spacing (in dram clocks) between the act and write commands to the same rank-ban k. this field corresponds to trcd_wr in the ddr specification. 11:8 r/w 0h core same rank write to write delayed (c0sd_cr_wrsr_wr): this configuration register indicates the minimum allowed spacing (in dram clocks) between two write commands to the same rank. 7:4 r/w 0h core different rank write to write delay (c0sd_cr_wrdr_wr): this configuration register indicates the minimum allowed spacing (in dram clocks) between two write commands to different ranks. this field corresponds to twr_wr in the ddr specification. 3:0 r/w 0h core read to wrte delay (c0sd_cr_rd_wr): this configuration register indi cates the minimum allowed spacing (in dram clocks) be tween the read and write commands. this field corresponds to trd_wr in the ddr specification. dram controller registers (d0:f0) 134 datasheet 5.2.11 c0cyctrkrd?cha nnel 0 cyctrk read b/d/f/type: 0/0/0/mchbar address offset: 258-25ah default value: 000000h access: r/w, ro size: 24 bits bit access default value rst/pwr description 23:21 ro 000b core reserved 20:17 r/w 0h core min act to read delayed (c0sd_cr_act_rd): this configuration register indi cates the minimum allowed spacing (in dram clocks) between the act and read commands to the same rank-b ank. this field corresponds to trcd_rd in the ddr specification. 16:12 r/w 00000b core same rank write to read delayed (c0sd_cr_wrsr_rd): this configuration register indicates the minimum allowed spacing (in dram clocks) between the write and read commands to the same rank. this field corresponds to twtr in the ddr specification. 11:8 r/w 0000b core different ranks write to read delayed (c0sd_cr_wrdr_rd): this configuration register indicates the minimum allowed spacing (in dram clocks) between the write and read commands to different ranks. this field corresponds to twr_rd in the ddr specification. 7:4 r/w 0000b core same rank read to read delayed (c0sd_cr_rdsr_rd): this configuration register indicates the minimum allowed spacing (in dram clocks) between two read commands to the same rank. 3:0 r/w 0000b core different ranks read to read delayed (c0sd_cr_rddr_rd): this configuration register indicates the minimum allowed spacing (in dram clocks) between two read commands to diffe rent ranks. this field corresponds to trd_rd in the ddr specification. datasheet 135 dram controller registers (d0:f0) 5.2.12 c0cyctrkrefr?channel 0 cyctrk refr b/d/f/type: 0/0/0/mchbar address offset: 25b-25ch default value: 0000h access: ro, r/w size: 16 bits this register is for channel 0 cyctrk refresh. 5.2.13 c0ckectrl?chan nel 0 cke control b/d/f/type: 0/0/0/mchbar address offset: 260-263h default value: 00000800h access: r/w, ro size: 32 bits bit access default value rst/pwr description 15:13 ro 000b core reserved 12:9 r/w 0000b core same rank pall to ref delayed (c0sd_cr_pchgall_rfsh): this configuration register indicates the minimum allowed spacing (in dram clocks) between the pre-all and ref commands to the same rank. 8:0 r/w 000000000b core same rank ref to ref delayed (c0sd_cr_rfsh_rfsh): this configuration register indicates the minimum allowed spacing (in dram clocks) be tween two ref commands to same ranks. bit access default value rst/pwr description 31:28 ro 0000b core reserved 27 r/w 0b core start the self-refre sh exit sequence (sd0_cr_srcstart): this configuration register indicates the request to start the self-refresh exit sequence 26:24 r/w 000b core cke pulse width requirement in high phase (sd0_cr_cke_pw_hl_safe): this configuration register indicates cke pulse width requir ement in high phase. this field corresponds to tcke (high) in the ddr specification. 23 r/w 0b core rank 3 population (sd0_cr_rankpop3): 1 = rank 3 populated 0 = rank 3 not populated this register is locked by me stolen memory lock. 22 r/w 0b core rank 2 population (sd0_cr_rankpop2): 1 = rank 2 populated 0 = rank 2 not populated this register is locked by me stolen memory lock. dram controller registers (d0:f0) 136 datasheet 21 r/w 0b core rank 1 population (sd0_cr_rankpop1): 1 = rank 1 populated 0 = rank 1 not populated this register is locked by me stolen memory lock. 20 r/w 0b core rank 0 population (sd0_cr_rankpop0): 1 = rank 0 populated 0 = rank 0 not populated this register is locked by me stolen memory lock. 19:17 r/w 000b core cke pulse width requirement in low phase (sd0_cr_cke_pw_lh_safe): this configuration register indicates cke pulse width requ irement in low phase. this field corresponds to tcke (low) in the ddr specification. 16 r/w 0b core enable cke toggle for pdn entry/exit (sd0_cr_pdn_enable): this configuration bit indicates that the toggling of ckes (for pdn entry/exit) is enabled. 15:14 ro 00b core reserved 13:10 r/w 0010b core minimum powerdown exit to non-read command spacing (sd0_cr_txp): this configuration register indicates the minimum number of clocks to wait following assertion of cke before is suing a non-read command. 1010?1111=reserved. 0010?1001=2?9clocks. 0000?0001=reserved. 9:1 r/w 000000000 b core self refresh exit count (s d0_cr_slfrfsh_exit_cnt): this configuration register in dicates the self refresh exit count. (program to 255). this field corresponds to txsnr/ txsrd in the ddr specification. 0r/w 0b core indicates only 1 dimm populated (sd0_cr_singledimmpop): this configuration register indicates the that only 1 dimm is populated. bit access default value rst/pwr description datasheet 137 dram controller registers (d0:f0) 5.2.14 c0refrctrl?channel 0 dram refresh control b/d/f/type: 0/0/0/mchbar address offset: 269-26eh default value: 241830000c30h access: r/w, ro size: 48 bits this register provides settings to configure the dram refresh controller. bit access default value rst/pwr description 47 ro 0b core reserved 46:44 r/w 010b core initial refresh count (sd0_cr_init_refrcnt): this field specifies the initial refresh count value. 43:38 r/w 010000b core direct rcomp quiet window (dirquiet): this configuration setting indicate s the amount of refresh_tick events to wait before the service of rcomp request in non- default mode of independent rank refresh. 37:32 r/w 011000b core indirect rcomp quiet window (indirquiet): this configuration setting indicate s the amount of refresh_tick events to wait before the service of rcomp request in non- default mode of independent rank refresh. 31:27 r/w 00110b core rcomp wait (rcompwait): this configuration setting indicates the amount of refresh _tick events to wait before the service of rcomp reques t in non-default mode of independent rank refresh. 26 r/w 0b core zqcal enable (zqcalen): this bit enables the dram controller to issue zqcal s command periodically. 25 r/w 0b core refresh counter enable (refcnten): this bit is used to enable the refresh counter to count during times that dram is not in self-refresh, but refreshes are not enabled. such a condition may occur due to need to reprogram dimms following dram controller switch. this bit has no effect when refresh is enabled (i.e., there is no mode where refresh is en abled but the counter does not run). so, along with bit 23 refen, the modes are: refen:refcnten description 0:0 normal refresh disable 0:1 refresh disabled, but counter is accumulating refreshes. 1:x normal refresh enable 24 r/w 0b core all rank refresh (allrkref): this bit enables (by default) that all the ranks are refreshed in a staggered/ atomic fashion. if set, th e ranks are refreshed in an independent fashion. 23 r/w 0b core refresh enable (refen): 0 = disabled 1 = enabled 22 r/w 0b core ddr initialization done (initdone): this bit indicates that ddr initialization is complete. dram controller registers (d0:f0) 138 datasheet 21:20 r/w 00b core dram refresh hysterisis (refhysterisis): hysterisis level - useful for dref_high watermark cases. the dref_high flag is set when the dref_high watermark level is exceeded, and is cleared when the refresh count is less than the hysterisis level. this bit should be set to a value less than the high watermark level. 00 = 3 01 = 4 10 = 5 11 = 6 19:18 r/w 00b core dram refresh panic watermark (refpanicwm): when the refresh count exce eds this level, a refresh request is launched to the scheduler and the dref_panic flag is set. 00 = 5 01 = 6 10 = 7 11 = 8 17:16 r/w 00b core dram refresh high watermark (refhighwm): when the refresh count exce eds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 00 = 3 01 = 4 10 = 5 11 = 6 15:14 r/w 00b core dram refresh low wa termark (reflowwm): when the refresh count exce eds this level, a refresh request is launched to the scheduler and the dref_low flag is set. 00 = 1 01 = 2 10 = 3 11 = 4 13:0 r/w 001100001 10000b core refresh counter time out value (reftimeout): program this field with a value that will provide 7.8 us at the memory clock frequency. at various memory clock frequencies, this results in the following values: 266 mhz -> 820 hex 333 mhz -> a28 hex 400 mhz -> c30 hex 533 mhz -> 104b hex 666 mhz -> 1450 hex bit access default value rst/pwr description datasheet 139 dram controller registers (d0:f0) 5.2.15 c0odtctrl?channel 0 odt control b/d/f/type: 0/0/0/mchbar address offset: 29c-29fh default value: 00000000h access: ro, r/w size: 32 bits 5.2.16 c1drb1?channel 1 dram rank boundary address 1 b/d/f/type: 0/0/0/mchbar address offset: 602-603h default value: 0000h access: r/w/l, ro size: 16 bits the operation of this register is detailed in the description for the c0drb0 register. bit access default value rst/pwr description 31:12 ro 00000h core reserved 11:8 r/w 0000b core dram odt for read commands (sd0_cr_odt_duration_rd): this field specifies the duration in memory clocks to assert dram odt for read commands. the async value should be used when the dynamic powerdown bit is set; otherwise, use the sync value. 7:4 r/w 0000b core dram odt for write commands (sd0_cr_odt_duration_wr): this field specifies the duration in memory clocks to assert dram odt for write commands. the async value should be used when the dynamic powerdown bit is set; otherwise use the sync value. 3:0 r/w 0000b core mch odt for read commands (sd0_cr_mchodt_duration): this field specifies the duration in memory clocks to assert (g)mch odt for read commands. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w/l 000h core channel 1 dram rank boundary address 1 (c1drba1): see c0drb1. in stacked mode, if this is the topmost populated rank in ch annel 1, program this value to be cumulative of ch0 drb3. this register is locked by me stolen memory lock. dram controller registers (d0:f0) 140 datasheet 5.2.17 c1drb2?channel 1 dram rank boundary address 2 b/d/f/type: 0/0/0/mchbar address offset: 604-605h default value: 0000h access: r/w/l, ro size: 16 bits the operation of this register is detailed in the description for the c0drb0 register. 5.2.18 c1drb3?channel 1 dram rank boundary address 3 b/d/f/type: 0/0/0/mchbar address offset: 606-607h default value: 0000h access: r/w, ro size: 16 bits the operation of this register is detailed in the description for the c0drb0 register. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w/l 000h core channel 1 dram rank boundary address 2 (c1drba2): see c0drb2. in stacked mode, if this is the topmost populated rank in channel 1, program this value to be cumulative of ch0 drb3. this register is locked by me stolen memory lock. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w 000h core channel 1 dram rank boundary address 3 (c1drba3): see c0drb3. in stacked mode, this will be cumulative of ch0 drb3. this register is locked by me stolen memory lock. datasheet 141 dram controller registers (d0:f0) 5.2.19 c1dra01?channel 1 dr am rank 0,1 attributes b/d/f/type: 0/0/0/mchbar address offset: 608-609h default value: 0000h access: r/w/l size: 16 bits the operation of this register is detailed in the description for the c0dra01 register. 5.2.20 c1dra23?channel 1 dr am rank 2,3 attributes b/d/f/type: 0/0/0/mchbar address offset: 60a-60bh default value: 0000h access: r/w/l size: 16 bits the operation of this register is detailed in the description for the c0dra01 register. bit access default value rst/pwr description 15:8 r/w/l 00h core channel 1 dram rank-1 attributes (c1dra1): see c0dra1. this register is locked by me stolen memory lock. 7:0 r/w/l 00h core channel 1 dram rank-0 attributes (c1dra0): see c0dra0. this register is locked by me stolen memory lock. bit access default value rst/pwr description 15:8 r/w/l 00h core channel 1 dram rank-3 attributes (c1dra3): see c0dra3. this register is locked by me stolen memory lock. 7:0 r/w/l 00h core channel 1 dram rank-2 attributes (c1dra2): see c0dra2. this register is locked by me stolen memory lock. dram controller registers (d0:f0) 142 datasheet 5.2.21 c1cyctrkpchg?channel 1 cyctrk pchg b/d/f/type: 0/0/0/mchbar address offset: 650-651h default value: 0000h access: r/w, ro size: 16 bits bit access default value rst/pwr description 15:11 ro 00000b core reserved. 10:6 r/w 00000b core write to pre delayed (c1sd_cr_wr_pchg): this field indicates the minimum allowed spacing (in dram clocks) between the write and pre commands to the same rank- bank. this field corresponds to twr in the ddr specification. 5:2 r/w 0000b core read to pre delayed (c1sd_cr_rd_pchg): this field indicates the minimum allowed spacing (in dram clocks) between the read and pre commands to the same rank- bank 1:0 r/w 00b core pre to pre delayed (c1sd_cr_pchg_pchg): this field indicates the minimum allowed spacing (in dram clocks) between two pre commands to the same rank. datasheet 143 dram controller registers (d0:f0) 5.2.22 c1cyctrkact?channel 1 cyctrk act b/d/f/type: 0/0/0/mchbar address offset: 652-655h default value: 00000000h access: r/w, ro size: 32 bits bit access default value rst/pwr description 31:30 ro 0h core reserved 29 r/w 0b core faw windowcnt bug fix disable (c1sd_cr_cyctrk_faw_wi ndowcnt_fix_disable): this field disables the cyctrk faw windowcnt bug fix. 1 = disable cyctrk faw windowcnt bug fix 0 = enable cyctrk faw windowcnt bug fix 28 r/w 0b core faw phase bug fix disable (c1sd_cr_cyctrk_faw_phase_fix_disable): this field disables the cyctrk faw phase indicator bug fix. 1 = disable cyctrk faw phase indicator bug fix 0 = enable cyctrk faw phase indicator bug fix 27:22 r/w 000000b core act window count (c1sd_cr_act_windowcnt): this field indicates the window duration (in dram clocks) during which the controller counts the # of activate commands which are launched to a particular rank. if the number of activate commands launched within this window is greater than 4, then a check is implemented to block launch of further activates to this rank for the rest of the duration of this window. 21 r/w 0b core max act check (c1sd_cr_maxact_dischk): this field enables the check which ensures that there are no more than four activates to a particular rank in a given window. 20:17 r/w 0000b core act to act delayed (c1sd_cr_act_act[): this field indicates the minimum allowed spacing (in dram clocks) between two act commands to the same rank. this field corresponds to trrd in the ddr specification. 16:13 r/w 0000b core pre to act delayed (c1sd_cr_pre_act): this field indicates the minimum allowed spacing (in dram clocks) between the pre and act commands to the same rank- bank:12:9r/w0000bpre-all to act delayed (c1sd_cr_preall_act):. this configuration register indicates the minimum allowed spacing (in dram clocks) between the pre-all and act commands to the same rank. this field corresponds to trp in the ddr specification. 12:9 r/w 0h core allpre to act delay (c1sd_cr_preall_act): from the launch of a prechargeall command wait for this number of memory clocks before launchin g a activate command. this field corresponds to tpall_rp in the ddr specification. 8:0 r/w 000000000b core ref to act delayed (c1sd_cr_rfsh_act): this field indicates the minimum allowed spacing (in dram clocks) between ref and act commands to the same rank. this field corresponds to trfc in the ddr specification. dram controller registers (d0:f0) 144 datasheet 5.2.23 c1cyctrkwr?channel 1 cyctrk wr b/d/f/type: 0/0/0/mchbar address offset: 656-657h default value: 0000h access: r/w size: 16 bits bit access default value rst/pwr description 15:12 r/w 0h core act to write delay (c1sd_cr_act_wr): this field indicates the minimum allowed spacing (in dram clocks) between the act and write commands to the same rank- bank. this field corresponds to trcd_wr in the ddr specification. 11:8 r/w 0h core same rank write to write delayed (c1sd_cr_wrsr_wr): this field indica tes the minimum allowed spacing (in dram clocks) between two write commands to the same rank. 7:4 r/w 0h core different rank write to write delay (c1sd_cr_wrdr_wr): this field indicates the minimum allowed spacing (in dram clocks) between two write commands to different ranks. this field corresponds to twr_wr in the ddr specification. 3:0 r/w 0h core read to wrte delay (c1sd_cr_rd_wr): this field indicates the minimum allowed spacing (in dram clocks) between the read and writ e commands. this field corresponds to trd_wr in the ddr specification. datasheet 145 dram controller registers (d0:f0) 5.2.24 c1cyctrkrd?channel 1 cyctrk read b/d/f/type: 0/0/0/mchbar address offset: 658-65ah default value: 000000h access: r/w, ro size: 24 bits 5.2.25 c1ckectrl?chan nel 1 cke control b/d/f/type: 0/0/0/mchbar address offset: 660-663h default value: 00000800h access: r/w, ro size: 32 bits bit access default value rst/pwr description 23:21 ro 0h core reserved 20:17 r/w 0h core min act to read delayed (c1sd_cr_act_rd): this field indicates the minimum allowed spacing (in dram clocks) between the act and re ad commands to the same rank-bank. this field corresponds to trcd_rd in the ddr specification. 16:12 r/w 00000b core same rank write to read delayed (c1sd_cr_wrsr_rd): this field indicates the minimum allowed spacing (in dram cloc ks) between the write and read commands to the same rank. this field corresponds to twtr in the ddr specification. 11:8 r/w 0000b core different ranks write to read delayed (c1sd_cr_wrdr_rd): this field indicates the minimum allowed spacing (in dram cloc ks) between the write and read commands to different ra nks. this field corresponds to twr_rd in the ddr specification. 7:4 r/w 0000b core same rank read to read delayed (c1sd_cr_rdsr_rd): this field indicates the minimum allowed spacing (in dram cl ocks) between two read commands to the same rank. 3:0 r/w 0000b core different ranks read to read delayed (c1sd_cr_rddr_rd): this field indicates the minimum allowed spacing (in dram cl ocks) between two read commands to different ranks. this field corresponds to trd_rd in the ddr specification. bit access default value rst/pwr description 31:28 ro 0h core reserved 27 r/w 0b core start the self-refresh exit sequence (sd1_cr_srcstart): this field indicates the request to start the self-refresh exit sequence 26:24 r/w 000b core cke pulse width requirement in high phase (sd1_cr_cke_pw_hl_safe): this field indicates cke pulse width requirement in high phase. this field corresponds to tcke (high) in the ddr specification. dram controller registers (d0:f0) 146 datasheet 23 r/w 0b core rank 3 population (sd1_cr_rankpop3): 1 = rank 3 populated 0 = rank 3 not populated this register is locked by me stolen memory lock. 22 r/w 0b core rank 2 population (sd1_cr_rankpop2): 1 = rank 2 populated 0 = rank 2 not populated this register is locked by me stolen memory lock. 21 r/w 0b core rank 1 population (sd1_cr_rankpop1): 1 = rank 1 populated 0 = rank 1 not populated this register is locked by me stolen memory lock. 20 r/w 0b core rank 0 population (sd1_cr_rankpop0): 1 = rank 0 populated 0 = rank 0 not populated this register is locked by me stolen memory lock. 19:17 r/w 000b core cke pulse width requirement in low phase (sd1_cr_cke_pw_lh_safe): this field indicates cke pulse width requirement in low phase. this field corresponds to tcke (low) in the ddr specification. 16 r/w 0b core enable cke toggle for pdn entry/exit (sd1_cr_pdn_enable): this bit indicates that the toggling of ckes (for pdn entry/exit) is enabled. 15:14 ro 00b core reserved 13:10 r/w 0010b core minimum powerdown exit to non-read command spacing (sd1_cr_txp): this configuration register indicates the minimum number of clocks to wait following assertion of cke before is suing a non-read command. 1010?1111 = reserved. 0010?1001 = 2?9 clocks 0000?0001 = reserved. 9:1 r/w 000000000b core self refresh exit count (s d1_cr_slfrfsh_exit_cnt): this field indicates the self re fresh exit count. (program to 255). this field corresponds to txsnr/txsrd in the ddr specification. 0r/w 0b core indicates only 1 dimm populated (sd1_cr_singledimmpop): this field indicates the that only 1 dimm is populated. bit access default value rst/pwr description datasheet 147 dram controller registers (d0:f0) 5.2.26 c1refrctrl?channel 1 dram refresh control b/d/f/type: 0/0/0/mchbar address offset: 669-66eh default value: 241830000c30h access: r/w, ro size: 48 bits this register provides settings to configure the dram refresh controller. bit access default value rst/pwr description 47 ro 0b core reserved 46:44 r/w 010b core initial refresh count (sd1_cr_init_refrcnt): this field specifies the initial refresh count value. 43:38 r/w 010000b core direct rcomp quiet window (dirquiet): this configuration setting indicate s the amount of refresh_tick events to wait before the service of rcomp request in non- default mode of independent rank refresh. 37:32 r/w 011000b core indirect rcomp quiet window (indirquiet): this configuration setting indicate s the amount of refresh_tick events to wait before the service of rcomp request in non- default mode of inde pendent rank refresh. 31:27 r/w 00110b core rcomp wait (rcompwait): this configuration setting indicates the amount of refresh_tick events to wait before the service of rcomp reques t in non-default mode of independent rank refresh. 26 r/w 0b core zqcal enable (zqcalen): this bit enables the dram controller to issue zqcal s command periodically. 25 r/w 0b core refresh counter enable (refcnten): this bit is used to enable the refresh counter to count during times that dram is not in self-refresh, but refreshes are not enabled. such a condition may occur due to need to reprogram dimms following dram controller switch. this bit has no effect when re fresh is enabled (i.e. there is no mode where refresh is en abled but the counter does not run) so, in conjunction with bit 23 refen, the modes are: refen:refcnten description 0:0 normal refresh disable 0:1 refresh disabled, but counter is accumulating refreshes. 1:x normal refresh enable 24 r/w 0b core all rank refresh (allrkref): this configuration bit enables (by default) that all the ranks are refreshed in a staggered/atomic fash ion. if set, the ranks are refreshed in an independent fashion. 23 r/w 0b core refresh enable (refen): 0 = disabled 1 = enabled 22 r/w 0b core ddr initialization done (initdone): this bit indicates that ddr initialization is complete. dram controller registers (d0:f0) 148 datasheet 21:20 r/w 00b core dram refresh hysterisis (refhysterisis): hysterisis level - useful for dref_high watermark cases. the dref_high flag is set when the dref_high watermark level is exceeded, and is cleared when the refresh count is less than the hysterisis level. this bit should be set to a value less than the high watermark level. 00 = 3 01 = 4 10 = 5 11 = 6 19:18 r/w 00b core dram refresh panic watermark (refpanicwm): when the refresh count exce eds this level, a refresh request is launched to the scheduler and the dref_panic flag is set. 00 = 5 01 = 6 10 = 7 11 = 8 17:16 r/w 00b core dram refresh high watermark (refhighwm): when the refresh count exce eds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 00 = 3 01 = 4 10 = 5 11 = 6 15:14 r/w 00b core dram refresh low wa termark (reflowwm): when the refresh count exce eds this level, a refresh request is launched to the scheduler and the dref_low flag is set. 00 = 1 01 = 2 10 = 3 11 = 4 13:0 r/w 001100001 10000b core refresh counter time out value (reftimeout): program this field with a value that will provide 7.8 us at the memory clock frequency. at various memory frequencies this results in the following values: 266 mhz -> 820 hex 333 mhz -> a28 hex 400 mhz -> c30 hex 533 mhz -> 104b hex 666 mhz -> 1450 hex bit access default value rst/pwr description datasheet 149 dram controller registers (d0:f0) 5.2.27 c1odtctrl?channel 1 odt control b/d/f/type: 0/0/0/mchbar address offset: 69c-69fh default value: 00000000h access: r/w, ro size: 32 bits 5.2.28 epc0drb0?ep channel 0 dr am rank boundary address 0 b/d/f/type: 0/0/0/mchbar address offset: a00-a01h default value: 0000h access: r/w, ro size: 16 bits bit access default value rst/pwr description 31:12 ro 00000h core reserved 11:8 r/w 0h core dram odt for read commands (sd1_cr_odt_duration_rd): this field specifies the duration in memory clocks to assert dram odt for read commands. the async value should be used when the dynamic powerdown bit is set; otherwise use the sync value. 7:4 r/w 0h core dram odt for write commands (sd1_cr_odt_duration_wr): this field specifies the duration in memory clocks to assert dram odt for write commands. the async value should be used when the dynamic powerdown bit is set; otherwise, use the sync value. 3:0 r/w 0h core mch odt for read commands (sd1_cr_mchodt_duration): this field specifies the duration in memory clocks to assert (g)mch odt for read commands. bit access default value rst/ pwr description 15:10 ro 000000b core reserved 9:0 r/w 000h core channel 0 dram rank boundary address 0 (c0drba0): dram controller registers (d0:f0) 150 datasheet 5.2.29 epc0drb1?ep channel 0 dr am rank boundary address 1 b/d/f/type: 0/0/0/mchbar address offset: a02-a03h default value: 0000h access: ro, r/w size: 16 bits see c0drb0 register for description. 5.2.30 epc0drb2?ep channel 0 dr am rank boundary address 2 b/d/f/type: 0/0/0/mchbar address offset: a04-a05h default value: 0000h access: ro, r/w size: 16 bits see c0drb0 register for description. 5.2.31 epc0drb3?ep channel 0 dr am rank boundary address 3 b/d/f/type: 0/0/0/mchbar address offset: a06-a07h default value: 0000h access: r/w, ro size: 16 bits see c0drb0 register for description. bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w 000h core channel 0 dram rank boundary address 1 (c0drba1): bit access default value rst/pwr description 15:10 ro 000000b core reserved 9:0 r/w 000h core channel 0 dram rank boundary address 2 (c0drba2): bit access default value rst/ pwr description 15:10 ro 000000b core reserved 9:0 r/w 000h core channel 0 dram rank boundary address 3 (c0drba3): datasheet 151 dram controller registers (d0:f0) 5.2.32 epc0dra01?ep channel 0 dram rank 0,1 attribute b/d/f/type: 0/0/0/mchbar address offset: a08-a09h default value: 0000h access: r/w size: 16 bits the dram rank attribute registers define th e page sizes/number of banks to be used when accessing different ranks. these registers should be left with their default value (all zeros) for any rank that is unpopulated, as determined by the corresponding cxdrb registers. each byte of information in the cxdra registers describes the page size of a pair of ranks. channel and rank map: ch0 rank0, 1: 108h?109h ch0 rank2, 3: 10ah?10bh ch1 rank0, 1: 188h?189h ch1 rank2, 3: 18ah?18bh 5.2.33 epc0dra23?ep channel 0 dram rank 2,3 attribute b/d/f/type: 0/0/0/mchbar address offset: a0a-a0bh default value: 0000h access: r/w size: 16 bits see c0dra01 for detailed descriptions. bit access default value rst/pwr description 15:8 r/w 00h core channel 0 dram rank-1 attributes (c0dra1): this field defines dram pagesize/ number-of-banks for rank1 for given channel. 7:0 r/w 00h core channel 0 dram rank-0 attributes (c0dra0): this field defines dram pagesize/ number-of-banks for rank0 for given channel. bit access default value rst/pwr description 15:8 r/w 00h core channel 0 dram rank-3 attributes (c0dra3): this field defines dram pagesize/ number-of-banks for rank3 for given channel. 7:0 r/w 00h core channel 0 dram rank-2 attributes (c0dra2): this field defines dram pagesize/ number-of-banks for rank2 for given channel. dram controller registers (d0:f0) 152 datasheet 5.2.34 epdcyctrkwrtpre?epd cyctrk wrt pre b/d/f/type: 0/0/0/mchbar address offset: a19-a1ah default value: 0000h access: r/w, ro size: 16 bits 5.2.35 epdcyctrkwrtact?epd cyctrk wrt act b/d/f/type: 0/0/0/mchbar address offset: a1c-a1fh default value: 00000000h access: ro, r/w size: 32 bits bit access default value rst/pwr description 15:11 r/w 00000b core act to pre delayed (c0sd_cr_act_pchg): this field indicates the minimum allowed spacing (in dram clocks) between the act and pre commands to the same rank- bank. 10:6 r/w 00000b core write to pre delayed (c0sd_cr_wr_pchg): this field indicates the minimum allowed spacing (in dram clocks) between the write and pre commands to the same rank- bank. 5:2 r/w 0000b core read to pre delayed (c0sd_cr_rd_pchg): this field indicates the minimum allowed spacing (in dram clocks) between the read and pre commands to the same rank- bank. 1:0 ro 00b core reserved bit access default value rst/pwr description 31:21 ro 000h core reserved 20:17 r/w 0000b core act to act delayed (c0sd_cr_act_act[): this field indicates the minimum allowed spacing (in dram clocks) between two act commands to the same rank. 16:13 r/w 0000b core pre to act delayed (c0sd_cr_pre_act): this field indicates the minimum allowed spacing (in dram clocks) between the pre and act comm ands to the same rank- bank:12:9r/w0000bpre-all to act delayed (c0sd_cr_preall_act):. this configuration register indicates the minimum allowed spacing (in dram clocks) between the pre-all and act commands to the same rank. 12:9 ro 0h core reserved 8:0 r/w 000000000b core ref to act delayed (c0sd_cr_rfsh_act): this field indicates the minimum allowed spacing (in dram clocks) between ref and act commands to the same rank. datasheet 153 dram controller registers (d0:f0) 5.2.36 epdcyctrkwrtwr?epd cyctrk wrt wr b/d/f/type: 0/0/0/mchbar address offset: a20-a21h default value: 0000h access: r/w, ro size: 16 bits 5.2.37 epdcyctrkwrtref?epd cyctrk wrt ref b/d/f/type: 0/0/0/mchbar address offset: a22-a23h default value: 0000h access: ro, r/w size: 16 bits bios optimal default 0h epd cyctrk wrt act status register. bit access default value rst/pwr description 15:12 r/w 0h core act to write delay (c0sd_cr_act_wr): this field indicates the minimum allowed spacing (in dram clocks) between the act and write commands to the same rank- bank. 11:8 r/w 0h core same rank write to write delayed (c0sd_cr_wrsr_wr): this field indicates the minimum allowed spacing (in dram cl ocks) between two write commands to the same rank. 7:4 ro 0h core reserved 3:0 r/w 0h core same rank write to read delay (c0sd_cr_rd_wr): this field indicate s the minimum allowed spacing (in dram clocks) between the write and read commands to the same rank. bit access default value rst/pwr description 15:13 ro 000b core reserved 12:9 ro 0h reserved 8:0 r/w 000000000b core different rank ref to ref delayed (c0sd_cr_rfsh_rfsh): this field indicates the minimum allowed spacing (in dram clocks) between two ref commands to different ranks. dram controller registers (d0:f0) 154 datasheet 5.2.38 epdcyctrkwrtrd?e pd cyctrk wrt read b/d/f/type: 0/0/0/mchbar address offset: a24-a26h default value: 000000h access: r/w size: 24 bits bios optimal default 000h bit access default value rst/pwr description 23:23 ro 0h reserved 22:20 r/w 000b core epdunit dqs slave dll enable to read safe (epdsdll2rd): this field provides setting for read command safe from the point of enabling the slave dlls. 19:18 ro 0h reserved 17:14 r/w 0h core min act to read delayed (c0sd_cr_act_rd): this field indicates the minimu m allowed spacing (in dram clocks) between the act and read commands to the same rank-bank 13:9 r/w 00000b core same rank read to write delayed (c0sd_cr_wrsr_rd): this field indicates the minimum allowed spacing (in dram clocks) between the read and write commands. 8:6 ro 0h reserved 5:3 r/w 000b core same rank read to read delayed (c0sd_cr_rdsr_rd): this field indicates the minimum allowed spacing (in dram clocks) between two read commands to the same rank. 2:0 ro 0h reserved datasheet 155 dram controller registers (d0:f0) 5.2.39 epdckeconfigreg?epd cke related configuration registers b/d/f/type: 0/0/0/mchbar address offset: a28-a2ch default value: 00e0000000h access: r/w size: 40 bits bios optimal default 0h bit access default value rst/pwr description 39:35 r/w 00000b core epdunit txpdll count (epdtxpdll): this field specifies the delay from precharge power down exit to a command that requires the dram dll to be operational. the commands are read/write. 34:32 r/w 000b core epdunit txp count (epdcketxp): this field specifies the timing requirement for active power down exit or fast exit pre-charge power down exit to any command or slow exit pre-charge power down to no n-dll (rd/wr/odt). command. 31:29 r/w 111b core mode select (sd0_cr_sms): mode select register: this field setting indicates the mode in which the controller is operating in. 111 = indicates normal mode of operation, else special mode of operation. 28:27 r/w 00b core epdunit emrs command select. (epdemrssel): emrs mode to select bank address. 01 = emrs 10 = emrs2 11 = emrs3 26:24 r/w 000b core cke pulse width requirement in high phase (sd0_cr_cke_pw_hl_safe): this field indi cates cke pulse width requirement in high phase. 23:20 r/w 0h core one-hot active rank population (ep_scr_actrank): this field indicates the active rank in a one hot manner. 19:17 r/w 000b core cke pulse width requirement in low phase (sd0_cr_cke_pw_lh_safe): this field indi cates cke pulse width requirement in low phase. 16:15 ro 0h reserved 14 r/w 0b core epdunit mpr mode (epdmpr): 1 = mpr mode 0 = normal mode in mpr mode, only read cycles must be issued by firmware. page results are ignored by dcs and just issues the read chip select. 13 r/w 0b core epdunit power down enable for odt rank (epdoapden): this bit enables the odt ranks to dynamically enter power down. 1 = enable active power down. 0 = disable active power down. dram controller registers (d0:f0) 156 datasheet 5.2.40 epdrefconfig?ep dram refresh configuration b/d/f/type: 0/0/0/mchbar address offset: a30-a33h default value: 40000c30h access: ro, r/w size: 32 bits 12 r/w 0b core epdunit power down enab le for active rank (epdaapden): this bit enables the active rank to dynamically enter power down. 1 = enable active power down. 0 = disable active power down. 11:10 ro 0h reserved 9:1 r/w 0000000 00b core self refresh exit count (s d0_cr_slfrfsh_exit_cnt): this field indicates th e self refresh exit co unt. program to 255. 0r/w0bc o r e indicates only 1 rank enabled (sd0_cr_singledimmpop): this field indicates that only 1 rank is enabled. this bit needs to be set if there is one active rank and no odt ranks, or if there is one active rank and one odt rank and they are the same rank. bit access default value rst/pwr description bit access default value rst/pwr description 31 ro 0b core reserved 30:29 r/w 10b core epdunit refresh count additi on for self refresh exit. (epdref4sr): this field indicates the number of additional refreshes that need s to be added to the refresh request count after ex iting self refresh. typical value is to add 2 refreshes. 00 = add 0 refreshes 01 = add 1 refreshes 10 = add 2 refreshes 11 = add 3 refreshes 28 r/w 0b core refresh counter enable (refcnten): this bit is used to enable the refresh counter to count during times that dram is not in self-refresh, but refreshes are not enabled. such a condition may occur due to need to reprogram dimms following dram controller switch. this bit has no effect when re fresh is enabled (i.e. there is no mode where refresh is enabled but the counter does not run) so, in conjunction with bit 23 refen, the modes are: refen:refcnten description 0:0 normal refresh disable 0:1 refresh disabled, but counter is accumulating refreshes. 1:x normal refresh enable datasheet 157 dram controller registers (d0:f0) 27 r/w 0b core refresh enable (refen): 0 = disabled 1 = enabled 26 r/w 0b core ddr initialization done (initdone): this bit indicates that ddr initialization is complete. 25:22 r/w 0000b core dram refresh hysterisis (refhysterisis): hysterisis level - useful for dref_high watermark cases. the dref_high flag is set wh en the dref_high watermark level is exceeded, and is cleared when the refresh count is less than the hysterisis level. this bit should be set to a value less than the high watermark level. 0000 = 0 0001 = 1 ....... 1000 = 8 21:18 r/w 0000b core dram refresh high watermark (refhighwm): when the refresh count exce eds this level, a refresh request is launched to the scheduler and the dref_high flag is set. 0000 = 0 0001 = 1 ....... 1000 = 8 17:14 r/w 0000b core dram refresh low watermark (reflowwm): when the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_low flag is set. 0000 = 0 0001 = 1 ....... 1000 = 8 13:0 r/w 001100001 10000b core refresh counter time ou t value (reftimeout): program this field with a value that will provide 7.8 us at the memory clock frequency. at various memory clock frequ encies this results in the following values: 266 mhz -> 820 hex 333 mhz -> a28 hex 400 mhz -> c30 hex 533 mhz -> 104b hex 666 mhz -> 1450 hex bit access default value rst/pwr description dram controller registers (d0:f0) 158 datasheet 5.2.41 tsc1?thermal sensor control 1 b/d/f/type: 0/0/0/mchbar address offset: cd8h default value: 00h access: r/w/l, r/w, rs/wc size: 8 bits this register controls the operation of the thermal sensor. bits 7:1 of this register are reset to their defaults by mpwrok. bit 0 is reset to its default by pltrst#. bit access default value rst/pwr description 7 r/w/l 0b core thermal sensor enable (tse): this bit enables power to the thermal sensor. lockable via tco bit 7. 0 = disabled 1 = enabled 6r/w 0b core analog hysteresis control (ahc): this bit enables the analog hysteresis control to the thermal sensor. when enabled, about 1 degree of hyst eresis is applied. this bit should normally be off in thermometer mode since the thermometer mode of the th ermal sensor defeats the usefulness of analog hysteresis. 0 = hysteresis disabled 1= analog hysteresis enabled. 5:2 r/w 0000b core digital hysteresis amount (dha): this bit determines whether no offset, 1 lsb, 2... 15 is used for hysteresis for the trip points. 0000 = digital hysteresis disabled, no offset added to trip temperature 0001 = offset is 1 lsb added to each trip temperature when tripped ... 0110 = ~3.0 c (recommended setting) ... 1110 = added to each trip temperature when tripped 1111 = added to each trip temperature when tripped 1 r/w/l 0b core thermal sensor comparator select (tscs): this bit multiplexes between the two analog comparator outputs. normally catastrophic is used. lockable via tco bit 7. 0 = catastrophic 1 = hot datasheet 159 dram controller registers (d0:f0) 5.2.42 tsc2?thermal sensor control 2 b/d/f/type: 0/0/0/mchbar address offset: cd9h default value: 00h access: r/w/l, ro size: 8 bits this register controls the operation of the thermal sensor. all bits in this register are reset to their defaults by mpwrok. 0rs/wc 0b core in use (iu): software semaphore bit. after a full (g)mch reset, a read to this bit returns a 0. after the first read, subseque nt reads will return a 1. a write of a 1 to this bit will reset the next read value to 0. writing a 0 to this bit has no effect. software can poll this bit until it reads a 0, and will then own the usage of the thermal sensor. this bit has no other effect on the hardware, and is only used as a semaphore among va rious independent software threads that may need to use the thermal sensor. software that reads this regi ster but does not intend to claim exclusive access of the thermal sensor must write a one to this bit if it reads a 0, in order to allow other software threads to claim it. see also therm3 bit 7 and iub, which are independent additional se maphore bits. bit access default value rst/pwr description dram controller registers (d0:f0) 160 datasheet bit access default value rst/pwr description 7:4 ro 0h core reserved 3:0 r/w/l 0h core thermometer mode enab le and rate (te): if analog thermal sensor mode is not enab led by setting these bits to 0000b, these bits enable the thermometer mode functions and set the thermometer controller rate. when the thermometer mode is disabled and tsc1[tse] =enabled, the analog sensor mode should be fully functional. in the analog se nsor mode, the catastrophic trip is functional, and the hot trip is functional at the offset below the catastrophic programmed into tsc2[cho]. the other trip points are not functional in this mode. when thermometer mode is enabled, all the trip points (catastrophic, hot, aux0) will all operate using the programmed trip points an d thermometer mode rate. note: 1. when disabling the thermometer mode while thermometer running, the thermometer mode controller will finish the current cycle. 2. during boot, all other th ermometer mode registers (except lock bits) should be programmed appropriately before en abling the thermometer mode. clocks are memory clocks. note: since prior (g)mchs counted the thermometer rate in terms of host clocks rather than memory clocks, the clock count for each setting listed below has been doubled from what is was on those (g)mchs. this should make the actual thermometer rate approximately equivalent across products. lockable via tco bit 7. 0000 = thermometer mode disabled (i.e, analog sensor mode) 0001 = enabled, 512 clock mode 0010 = enabled, 1024 clock mode (normal thermometer mode operation), provides ~3.85 us settling time @ 266 mhz provides ~3.08 us settling time @ 333 mhz provides ~2.56 us settling time @ 400 mhz 0011 = enabled, 1536 clock mode 0100 = enabled, 2048 clock mode 0101 = enabled, 3072 clock mode 0110 = enabled, 4096 clock mode 0111 = enabled, 6144 clock mode provides ~23.1 us settling time @ 266 mhz provides ~18.5 us settling time @ 333 mhz provides ~15.4 us settling time @ 400 mhz all other permutations reserved 1111 = enabled, 4 clock mode (for testing digital logic) datasheet 161 dram controller registers (d0:f0) 5.2.43 tss?thermal sensor status b/d/f/type: 0/0/0/mchbar address offset: cdah default value: 00h access: ro size: 8 bits this read only register provides trip point and other status of the thermal sensor. all bits in this register are reset to their defaults by mpwrok. bit access default value rst/pwr description 7ro 0b core catastrophic trip indicator (cti): 1 = internal thermal sensor temperature is above the catastrophic setting. 6ro 0b core hot trip indicator (hti): 1 = internal thermal sensor temperature is above the hot setting. 5ro 0b core aux0 trip indicator (a0ti): 1 = a 1 indicates that the internal thermal sensor temperature is above the aux0 setting. 4ro 0b core thermometer mode output valid (tov): 1 = thermometer mode is able to converge to a temperature and that the tr register is reporting a reasonable estimate of the thermal sensor temperature. 0 = thermometer mode is off, or that temperature is out of range, or that the tr register is being looked at before a temperature conversion has had time to complete. 3:2 ro 00b core reserved 1ro 0b core direct catastrophic co mparator read (dccr): this bit reads the output of the catast rophic comparator directly, without latching via the thermometer mode circuit. used for testing. 0ro 0b core direct hot comparat or read (dhcr): this bit reads the output of the hot comparator directly, without latching via the thermometer mode circ uit. used for testing. dram controller registers (d0:f0) 162 datasheet 5.2.44 tsttp?thermal sensor temperature trip point b/d/f/type: 0/0/0/mchbar address offset: cdc-cdfh default value: 00000000h access: ro, r/w, r/w/l size: 32 bits this register: 1. sets the target values for the trip points in thermometer mode. see also tst [direct dac connect test enable]. 2. reports the relative thermal sensor temperature all bits in this register are reset to their defaults by mpwrok. bit access default value rst/pwr description 31:24 ro 00h core relative temperature (relt): in thermometer mode, the relt field of this register report the relative temperature of the thermal sensor. provides a two's complement value of the thermal sensor relative to the hot trip point. temperature above the hot trip point will be positive. tr and htps can both vary between 0 and 255. but relt will be clipped between 127 to keep it an 8 bit number. see also tss[thermomete r mode output valid] in the analog mode, the relt field reports htps value. 23:16 r/w 00h core aux0 trip point setting (a0tps): this field sets the target for the aux0 trip point. 15:8 r/w/l 00h core hot trip point setting (htps): this field sets the target value for the hot trip point. lockable via tco bit 7. 7:0 r/w/l 00h core catastrophic trip point setting (ctps): this field sets the target for the catastroph ic trip point. see also tst[direct dac connect test enable]. lockable via tco bit 7. datasheet 163 dram controller registers (d0:f0) 5.2.45 tco?thermal calibration offset b/d/f/type: 0/0/0/mchbar address offset: ce2h default value: 00h access: r/w/l/k, r/w/l size: 8 bits bit 7 reset to its default by pltrst# bits 6:0 reset to their defaults by mpwrok bit access default value rst/pwr description 7 r/w/l/k 0b core lock bit for catastrophic (lbc): this bit, when written to a 1, locks the catastrophic programming interface, including bits 7:0 of this regi ster and bits 15:0 of tsttp, bits 1,7 of tsc 1, bits 3:0 of tsc 2, bits 4:0 of tsc 3, and bits 0,7 of tst. this bit may only be set to a 0 by a hardware reset (pltrst#). writ ing a 0 to this bit has no effect. 6:0 r/w/l 00h core calibration offset (co): this field contains the current calibration offset for the th ermal sensor dac inputs. the calibration offset is a twos complement signed number which is added to the temperature counter value to help generate the final value going to the thermal sensor dac. this field is read/write and can be modified by software unless locked by setting bit 7 of this register. the fuses cannot be programmed via this register. once this register has been overwritten by software, the values of the tco fuses can be read using the therm3 register. note for tco operation: while this is a seven-bit field, the 7th bit is sign extended to 9 bits for tco operation. the range of 00h to 3fh corresponds to 0 0000 0000 to 0 0011 1111. the range of 41h to 7fh corresponds to 1 1100 001 (i.e, negative 3fh) to 1 1111 1111 (i.e, negative 1), respectively. dram controller registers (d0:f0) 164 datasheet 5.2.46 therm1?hardware throttle control b/d/f/type: 0/0/0/mchbar address offset: ce4h default value: 00h access: ro, r/w/l, r/w/l/k size: 8 bits all bits in this register are reset to their defaults by pltrst#. bit access default value rst/pwr description 7 r/w/l 0b core internal thermal hardware throttling enable (ithte): this bit is a master enable for internal thermal sensor-based hardware throttling. 0 = hardware actions via the in ternal thermal sensor are disabled. 1 = hardware actions via the in ternal thermal sensor are enabled. 6 r/w/l 0b core internal thermal hardware throttling type (ithtt): this policy bit determ ines what type of hardware throttling will be enacted by the internal thermal sensor when enabled by ithte: 0 = (g)mch throttling 1 = dram throttling 5 ro 0b core reserved 4 r/w/l 0b core throttling temperature ra nge selection (ttrs): this bit determines what temperature ranges will enable throttling. lockable by bit 0 of this register. see also the throttling registers in mchbar configuration space c0gtc and c1gtc [(g)mch thermal sensor trip enable] and pefc [thermal sensor trip enable] which are used to enable or disable throttling. 0 = catastrophic only. the catastrophic thermal temperature range will enable main memory thermal throttling. 1 = hot and catastrophic. 3 r/w/l 0b core halt on catastrophic (hoc): 0 = continue to toggle clocks when the catastrophic sensor trips. 1 = all clocks are disabled when the catastrophic sensor trips. a system reset is re quired to bring the system out of a halt from the thermal sensor. 2:1 ro 00b core reserved 0 r/w/l/k 0b core hardware throttling lock bit (htl): this bit locks bits 7:0 of this register. 0 = the register bits are unlocked. 1 = the register bits are locked. it may only be set to a 0 by a hardware reset. writing a 0 to this bit has no effect. datasheet 165 dram controller registers (d0:f0) 5.2.47 tis?thermal interrupt status b/d/f/type: 0/0/0/mchbar address offset: cea-cebh default value: 0000h access: r/wc, ro size: 16 bits this register is used to report which specific error condition resulted in the device 0 function 0 errsts[thermal sensor event for smi/sci/serr] or memory mapped iir thermal event. software can examine the current state of the thermal zones by examining the tss. software can distinguis h internal or external trip event by examining exttscs. software must write a 1 to clear the status bits in this register. the following scenario is possible: an interrupt is initiated on a rising temp erature trip, the appropriate dmi cycles are generated, and eventually the software se rvices the interrupt and sees a rising temperature trip as the cause in the status bits for the interrupts. assume that the software then goes and clears the local interrupt status bit in the tis register for that trip event. it is possible at this poin t that a falling temperature trip event occurs before the software has had the time to clear the global interrupts status bit. but since software has already looked at the status register before this event happened, software may not clear the local status flag for this event. therefore, after the global interrupt is cleared by software, software must look at the instantaneous status in the tss register. all bits in this register are reset to their defaults by pltrst#. bit access default value rst/pwr description 15:10 ro 00h core reserved 9r/wc 0b core was catastrophic thermal sensor interrupt event (wctsie): 1 = indicates a catastrophic th ermal sensor trip based on a higher to lower temperature transition through the trip point 0 = no trip for this event 8r/wc 0b core was hot thermal sensor interrupt event (whtsie): 1 = indicates a hot thermal sensor trip based on a higher to lower temperature transition through the trip point 0 = no trip for this event 7r/wc 0b core was aux0 thermal sensor interrupt event (wa0tsie): 1 = indicates an aux0 thermal sensor trip based on a higher to lower temperature transition through the trip point 0 = no trip for this event software must write a 1 to clear this status bit. 6:5 ro 00b core reserved dram controller registers (d0:f0) 166 datasheet 4r/wc 0b core catastrophic thermal sensor interrupt event (ctsie): 1 = indicates a catastrophic thermal sensor trip event occurred based on a lower to higher temperature transition through the trip point. 0 = no trip for this event software must write a 1 to clear this status bit. 3r/wc 0b core hot thermal sensor interrupt event (htsie): 1 = indicates a hot thermal sensor trip event occurred based on a lower to higher temperature transition through the trip point. 0 = no trip for this event software must write a 1 to clear this status bit. 2r/wc 0b core aux0 thermal sensor interrupt event (a0tsie): 1 = indicates an aux0 thermal sensor trip event occurred based on a lower to higher temperature transition through the trip point. 0 = no trip for this event software must write a 1 to clear this status bit. 1:0 ro 00b core reserved bit access default value rst/pwr description datasheet 167 dram controller registers (d0:f0) 5.2.48 tsmicmd?ther mal smi command b/d/f/type: 0/0/0/mchbar address offset: cf1h default value: 00h access: ro, r/w size: 8 bits this register selects specific errors to generate a smi dmi special cycle, as enabled by the device 0 smi error command register [smi on (g) mch thermal sensor trip]. the smi must not be enabled at the same time as the serr/sci for the thermal sensor event. all bits in this register are reset to their defaults by pltrst#. bit access default value rst/pwr description 7:3 ro 00h core reserved 2r/w 0b core smi on (g)mch catastrophic thermal sensor trip (smgctst): 1 = does not mask the generation of an smi dmi special cycle on a catastrophic thermal sensor trip. 0 = disable reporting of this condition via smi messaging. 1r/w 0b core smi on (g)mch hot th ermal sensor trip (smghtst): 1 = does not mask the generation of an smi dmi special cycle on a hot thermal sensor trip. 0 = disable reporting of this condition via smi messaging. 0r/w 0b core smi on (g)mch aux thermal sensor trip (smgatst): 1 = does not mask the generation of an smi dmi special cycle on an auxiliary thermal sensor trip. 0 = disable reporting of this condition via smi messaging. dram controller registers (d0:f0) 168 datasheet 5.2.49 pmsts?power management status b/d/f/type: 0/0/0/mchbar address offset: f14-f17h default value: 00000000h access: r/wc/s, ro size: 32 bits this register is reset by pwrok only. bit access default value rst/pwr description 31:9 ro 000000h core reserved 8r/wc/s 0b core warm reset occurred (wro): set by the pmunit whenever a warm reset is received, and cleared by pwrok=0. 0 = no warm reset occurred. 1 = warm reset occurred. bios requirement: bios can check and clear this bit whenever executing post code. this way bios knows that if the bit is set, then the pmsts bits [1:0] must also be set, and if not bios needs to power-cycle the platform. 7:2 ro 00h core reserved 1r/wc/s 0b core channel 1 in self-refresh (c1sr): set by power management hardware after ch annel 1 is placed in self refresh as a result of a po wer state or a reset warn sequence. cleared by power management hardware before starting channel 1 self refresh exit se quence initiated by a power management exit. cleared by the bios by wr iting a 1 in a warm reset (reset# asserted while pwrok is asserted) exit sequence. 0 = channel 1 not ensured to be in self refresh. 1 = channel 1 in self refresh. 0r/wc/s 0b core channel 0 in self-refresh (c0sr): set by power management hardware after ch annel 0 is placed in self refresh as a result of a po wer state or a reset warn sequence. cleared by power management hardware before starting channel 0 self refresh exit se quence initiated by a power management exit. cleared by the bios by wr iting a 1 in a warm reset (reset# asserted while pwrok is asserted) exit sequence. 0 = channel 0 not ensured to be in self refresh. 1 = channel 0 in self refresh. datasheet 169 dram controller registers (d0:f0) 5.3 epbar 5.3.1 epesd?ep elemen t self description b/d/f/type: 0/0/0/pxpepbar address offset: 44-47h default value: 00000301h access: ro, r/wo size: 32 bits this register provides information about the root complex element containing this link declaration capability. address offset register symbol register name default value access 44?47h epesd ep element self description 00000301h ro, r/wo 50?53h eple1d ep link entry 1 description 01000000h ro, r/wo 58?5fh eple1a ep link entry 1 address 0000000000 000000h ro, r/wo 60?63h eple2d ep link entry 2 description 02000002h ro, r/wo 68?6fh eple2a ep link entry 2 address 0000000000 008000h ro bit access default value rst/pwr description 31:24 ro 00h core port number (pn) : this field specifies the port number associated with this element with respect to the component that contains this element. a value of 00h indicates to configuration software that this is the default egress port. 23:16 r/wo 00h core component id (cid): this field identifies the physical component that contains this root complex element. 15:8 ro 03h core number of link entries (nle): this field indicates the number of link entries following the element self description. this field report s 3 (one each for peg0, peg1 and dmi). 7:4 ro 0h core reserved 3:0 ro 1h core element type (et): this field indicate s the type of the root complex element. value of 1h represents a port to system memory. dram controller registers (d0:f0) 170 datasheet 5.3.2 eple1d?ep link entry 1 description b/d/f/type: 0/0/0/pxpepbar address offset: 50-53h default value: 01000000h access: ro, r/wo size: 32 bits this register provides the first part of a link entry, which declares an internal link to another root complex element. 5.3.3 eple1a?ep link entry 1 address b/d/f/type: 0/0/0/pxpepbar address offset: 58-5fh default value: 0000000000000000h access: ro, r/wo size: 64 bits this register provides the second part of a li nk entry, which declares an internal link to another root complex element. bit access default value rst/pwr description 31:24 ro 01h core target port number (tpn): this field specifies the port number associated with the elem ent targeted by this link entry (dmi). the target port number is with respect to the component that contains this element as specified by the target component id. 23:16 r/wo 00h core target component id (tcid): this field identifies the physical or logical component th at is targeted by this link entry. 15:2 ro 0000h core reserved 1ro 0b core link type (ltyp): this bit indicates that the link points to memory-mapped space (for rcrb). the link address specifies the 64-bit base address of the target rcrb. 0r/wo 0b core link valid (lv): 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. bit access default value rst/pwr description 63:36 ro 0000000h core reserved: reserved for link address high order bits. 35:12 r/wo 000000h core link address (la): this field contains the memory mapped base address of the rcrb that is the target element (dmi) for this link entry. 11:0 ro 000h core reserved datasheet 171 dram controller registers (d0:f0) 5.3.4 eple2d?ep link entry 2 description b/d/f/type: 0/0/0/pxpepbar address offset: 60-63h default value: 02000002h access: ro, r/wo size: 32 bits this register provides the first part of a link entry, which declares an internal link to another root complex element. bit access default value rst/pwr description 31:24 ro 02h core target port number (tpn): this field specifies the port number associated with the element targeted by this link entry (peg0). the target port number is with respect to the component that contains this element as specified by the target component id. 23:16 r/wo 00h core target component id (tcid): this field identifies the physical or logical component that is targeted by this link entry. a value of 0 is reserv ed. component ids start at 1. this value is a mirror of the value in the component id field of all elements in this component. 15:2 ro 0000h core reserved 1ro 1b core link type (ltyp): this bit indicates that the link points to configuration space of the integrated device which controls the x16 root port for peg0. the link address specifies the configuration address (segment, bus, device, function ) of the target root port. 0r/wo 0b core link valid (lv): 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. dram controller registers (d0:f0) 172 datasheet 5.3.5 eple2a?ep link entry 2 address b/d/f/type: 0/0/0/pxpepbar address offset: 68-6fh default value: 0000000000008000h access: ro size: 64 bits this register provides the second part of a li nk entry, which declares an internal link to another root complex element. bit access default value rst/pwr description 63:28 ro 000000000h core reserved for configuration space base address: not required if root complex has only one config space. 27:20 ro 00h core bus number (busn): 19:15 ro 00001b core device number (devn): the target for this link is pci express x16 port peg0 (device 1). 14:12 ro 000b core function number (funn): 11:0 ro 000h core reserved datasheet 173 host-pci express* registers (d1:f0) 6 host-pci express* registers (d1:f0) device 1 contains the controls associated with the pci express x16 root port that is the intended to attach as the point for external graphics. it is typically referred to as pci express-g (pci express graphics) port. in addi tion, it also functions as the virtual pci- to-pci bridge. warning: when reading the pci express "conceptual" registers such as this, you may not get a valid value unless the register value is stable. the pci express* specification defines two types of reserved bits. reserved and preserved: 1. reserved for future r/w implementations; software must preserve value read for writes to bits. 2. reserved and zero: reserved for future r/wc/s implementations; software must use 0 for writes to bits. unless explicitly documented as reserved an d zero, all bits mark ed as reserved are part of the reserved and preserved type, which have historically been the typical definition for reserved. note: most (if not all) control bits in this device cannot be modified unless the link is down. software is required to first disable the lin k, then program the registers, and then re- enable the link (which will cause a full-retrain with the new settings). table 13. pci express* regi ster address map (d1:f0) address offset register symbol register name default value access 0?1h vid1 vendor identification 8086h ro 2?3h did1 device identification see register description ro 4?5h pcicmd1 pci command 0000h ro, r/w 6?7h pcists1 pci status 0010h ro, r/wc 8h rid1 revision identification see register description ro 9?bh cc1 class code 060400h ro ch cl1 cache line size 00h r/w eh hdr1 header type 01h ro 18h pbusn1 primary bus number 00h ro 19h sbusn1 secondary bus number 00h r/w 1ah subusn1 subordinate bus number 00h r/w 1ch iobase1 i/o base address f0h ro, r/w 1dh iolimit1 i/o limit address 00h r/w, ro 1e?1fh ssts1 secondary status 0000h r/wc, ro 20?21h mbase1 memory base address fff0h r/w, ro host-pci express* registers (d1:f0) 174 datasheet 22?23h mlimit1 memory limit address 0000h ro, r/w 24?25h pmbase1 prefetchable memory base address fff1h r/w, ro 26?27h pmlimit1 prefetchable memo ry limit address 0001h ro, r/w 28?2bh pmbaseu1 prefetchable memory base address upper 00000000h r/w 2c?2fh pmlimitu1 prefetchable memory limit address upper 00000000h r/w 34h capptr1 capabilities pointer 88h ro 3ch intrline1 interrupt line 00h r/w 3dh intrpin1 interrupt pin 01h ro 3e?3fh bctrl1 bridge control 0000h ro, r/w 80?83h pm_capid1 power management capabilities c8039001h ro 84?87h pm_cs1 power management control/status 00000008h ro, r/w/p, r/w 88?8bh ss_capid subsystem id and vendor id capabilities 0000800dh ro 8c?8fh ss subsystem id and subsystem vendor id 00008086h r/wo 90?91h msi_capid message signaled interrupts capability id a005h ro 92?93h mc message control 0000h ro, r/w 94?97h ma message address 00000000h r/w, ro 98?99h md message data 0000h r/w a0?a1h peg_capl pci express-g capability list 0010h ro a2?a3h peg_cap pci express- g capabilities 0142h ro, r/wo a4?a7h dcap device capabilities 00008000h ro a8?a9h dctl device control 0000h ro, r/w aa?abh dsts device status 0000h ro, r/wc ac?afh lcap link capabilities 02214d02h ro, r/wo b0?b1h lctl link control 0000h r/w, ro, r/w/sc b2?b3h lsts link status 1000h r/wc, ro b4?b7h slotcap slot capabilities 00040000h r/wo, ro b8?b9h slotctl slot control 0000h ro, r/w ba?bbh slotsts slot status 0000h ro, r/wc bc?bdh rctl root control 0000h ro, r/w c0?c3h rsts root status 00000000h ro, r/wc ec?efh peglc pci express-g legacy control 00000000h ro, r/w table 13. pci express* register address map (d1:f0) address offset register symbol register name default value access datasheet 175 host-pci express* registers (d1:f0) 6.1 host-pci express* regi ster description (d1:f0) 6.1.1 vid1?vendor identification b/d/f/type: 0/1/0/pci address offset: 0-1h default value: 8086h access: ro size: 16 bits this register, combined with the device identification register, uniquely identifies any pci device. 6.1.2 did1?device identification b/d/f/type: 0/1/0/pci address offset: 2-3h default value: 2e01h access: ro size: 16 bits this register, combined with the vendor identification register, uniquely identifies any pci device. bit access default value rst/pwr description 15:0 ro 8086h core vendor identification (vid1): pci standard identification for intel. bit access default value rst/pwr description 15:8 ro 2eh core device identification number (did1(ub)): identifier assigned to the (g)mch device 1 (virtual pci-to-pci bridge, pci expres s graphics port). 7:4 ro 0h core device identification number (did1(hw)): identifier assigned to the (g)mch device 1 (virtual pci-to-pci bridge, pci expres s graphics port). 3:0 ro 1h core device identification number (did1(lb)): identifier assigned to the (g)mch device 1 (virtual pci-to-pci bridge, pci expres s graphics port). host-pci express* registers (d1:f0) 176 datasheet 6.1.3 pcicmd1?pci command b/d/f/type: 0/1/0/pci address offset: 4-5h default value: 0000h access: ro, r/w size: 16 bits bit access default value rst/pwr description 15:11 ro 00h core reserved 10 r/w 0b core inta assertion disable (intaad): 0 = this device is permitted to generate inta interrupt messages. 1 = this device is prevente d from generating interrupt messages. any inta emul ation interrupts already asserted must be de-asser ted when this bit is set. only affects interrupts genera ted by the device (pci inta from a pme or hot plug event) controlled by this command register. it does not affect upstream msis, upstream pci inta?intd assert and de-assert messages. 9ro 0b core fast back-to-back enable (fb2b): not applicable or implemented. hardwired to 0. 8r/w 0b core serr# message enable (serre1): this bit controls device 1 serr# messaging. the (g)mch communicates the serr# condition by sending a serr message to the ich. this bit, when set, enab les reporting of non-fatal and fatal errors detected by the device to the root complex. note that errors are reported if enabled either through this bit or through the pci-express specific bits in the device control register. in addition, for type 1 config uration space header devices, this bit, when set, enables transmission by the primary interface of err_nonfatal and err_fatal error messages forwarded from the secondary in terface. this bit does not affect the transmission of forwarded err_cor messages. 0 = the serr message is ge nerated by the (g)mch for device 1 only under conditions enabled individually through the device control register. 1 = the (g)mch is enabled to generate serr messages, which will be sent to the ich for specific device 1 error conditions generated/ detected on the primary side of the virtual pci to pci bridge (not those received by the secondary si de). the status of serrs generated is reported in the pcists1 register. 7 ro 0b core reserved: not applicable or implemented. hardwired to 0. 6r/w 0b core parity error response enable (perre): this bit controls whether or not the mast er data parity error bit in the pci status register can bet set. 0 = master data parity error bit in pci status register can not be set. 1 = master data parity error bit in pci status register can be set. datasheet 177 host-pci express* registers (d1:f0) 5r o 0 b c o r e vga palette snoop (vgaps): not applicable or implemented. hardwired to 0. 4r o 0 b c o r e memory write and invalidate enable (mwie): not applicable or implemented. hardwired to 0. 3r o 0 b c o r e special cycle enable (sce): not applicable or implemented. hardwired to 0. 2r/w 0b core bus master enable (bme): this bit controls the ability of the peg port to forward memory and io read/write requests in the up stream direction. 0 = this device is prevented from making memory or i/o requests to its prim ary bus. note that according to pci specification, as msi inte rrupt messages are in-band memory writes, di sabling the bus ma ster enable bit prevents this device from generating msi interrupt messages or passing them from its secondary bus to its primary bus. upstream memory writes/reads, i/o writes/reads, peer writes/rea ds, and msis will all be treated as invalid cycles. writes are forwarded to memory address c0000h with byte enables de- asserted. reads are forwar ded to memory address c0000h and will return unsupported request status (or master abort) in its completion packet. 1 = this device is allowed to issue requests to its primary bus. completions for previously issued memory read requests on the primary bus will be issued when the data is available. this bit do es not affect forwarding of completions from the primary interface to the secondary interface. 1r/w 0b core memory access enable (mae): 0 = all of device 1's memory space is disabled. 1 = enable the memory and pre-fetchable memory address ranges defined in the mbase1, mlimit1, pmbase1, and pmlimit1 registers. 0r/w 0b core io access enable (ioae): 0 = all of device 1's i/o space is disabled. 1 = enable the i/o address rang e defined in the iobase1, and iolimit1 registers. bit access default value rst/pwr description host-pci express* registers (d1:f0) 178 datasheet 6.1.4 pcists1?pci status b/d/f/type: 0/1/0/pci address offset: 6-7h default value: 0010h access: ro, r/wc size: 16 bits this register reports the occurrence of error conditions associated with primary side of the "virtual" host-pci express brid ge embedded within the (g)mch. bit access default value rst/pwr description 15 ro 0b core detected parity error (dpe): not applicable or implemented. hardwired to 0. parity (generating poisoned tlps) is not supported on the primary side of this device. error forwarding is not performed. 14 r/wc 0b core signaled system error (sse): this bit is set when this device sends an serr due to detecting an err_fatal or err_nonfatal condition and the serr enable bit in the command register is 1. both received (if enabled by bctrl1[1]) and internally dete cted error messages do not affect this field. 13 ro 0b core received master abort status (rmas): not applicable or implemented. hardwired to 0. the concept of a master abort does not exist on prim ary side of this device. 12 ro 0b core received target abort status (rtas): not applicable or implemented. hardwired to 0. the concept of a target abort does not exist on prim ary side of this device. 11 ro 0b core signaled target abort status (stas): not applicable or implemented. hardwired to 0. the concept of a target abort does not exist on prim ary side of this device. 10:9 ro 00b core devselb timing (devt): this device is not the subtractive decode device on bus 0. this bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode. 8ro 0b core master data parity error (pmdpe): because the primary side of the peg's vi rtual pci-to-pci bridge is integrated with the mch functionality there is no scenario where this bit will get set. because hardware will never set this bit, it is impossible for software to have an opportunity to clear this bit or otherwise test that it is implemented. the pci specification defines it as a r/wc, but for our implementation an ro defini tion behaves the same way and will meet all micros oft testing requirements. this bit can only be set when the parity error enable bit in the pci command re gister is set. 7ro 0b core fast back-to-back (fb2b): not applicable or implemented. hardwired to 0. 6 ro 0b core reserved 5ro 0b core 66/60mhz capabi lity (cap66): not applicable or implemented. hardwired to 0. datasheet 179 host-pci express* registers (d1:f0) 6.1.5 rid1?revision identification b/d/f/type: 0/1/0/pci address offset: 8h default value: see description below access: ro size: 8 bits this register contains the revision number of the (g)mch device 1. these bits are read only and writes to this register have no effect. 4r o 1 b c o r e capabilities list (capl): this bit indicates that a capabilities list is pr esent. hardwired to 1. 3r o 0 b c o r e inta status (intas): this bit indicates that an interrupt message is pending internally to the device. only pme and hot plug sources feed into th is status bit (not pci inta- intd assert and de-assert me ssages). the inta assertion disable bit, pcicmd1[10], has no effect on this bit. note that inta emulation in terrupts received across the link are not reflected in this bit. 2:0 ro 000b core reserved bit access default value rst/pwr description bit access default value rst/pwr description 7:0 ro see description core revision identification number (rid1): this is an 8- bit value that indicates the revision identification number for the (g)mch device 0. refer to the intel ? 4 series chipset family specification update for the value of this register. host-pci express* registers (d1:f0) 180 datasheet 6.1.6 cc1?class code b/d/f/type: 0/1/0/pci address offset: 9-bh default value: 060400h access: ro size: 24 bits this register identifies the basic function of the device, a more specific sub-class, and a register- specific programming interface. 6.1.7 cl1?cache line size b/d/f/type: 0/1/0/pci address offset: ch default value: 00h access: r/w size: 8 bits bit access default value rst/pwr description 23:16 ro 06h core base class code (bcc): this field indi cates the base class code for this device. 06h = bridge device. 15:8 ro 04h core sub-class code (subcc): this field indi cates the sub- class code for this device. 04h = pci-to-pci bridge. 7:0 ro 00h core programming interface (pi): this field indicates the programming interface of this device. this value does not specify a particular register set layout and provides no practical use for this device. bit access default value rst/pwr description 7:0 r/w 00h core cache line size (scratch pad): this field is implemented by pci express de vices as a read-write field for legacy compatibility purpos es but has no impact on any pci express device functionality. datasheet 181 host-pci express* registers (d1:f0) 6.1.8 hdr1?header type b/d/f/type: 0/1/0/pci address offset: eh default value: 01h access: ro size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. 6.1.9 pbusn1?primary bus number b/d/f/type: 0/1/0/pci address offset: 18h default value: 00h access: ro size: 8 bits this register identifies that this "virtual" host-pci express bridge is connected to pci bus 0. 6.1.10 sbusn1?secondary bus number b/d/f/type: 0/1/0/pci address offset: 19h default value: 00h access: r/w size: 8 bits this register identifies the bus number assigned to the second bus side of the "virtual" bridge (i.e., to pci express). this numbe r is programmed by the pci configuration software to allow mapping of configuration cycles to pci express. bit access default value rst/pwr description 7:0 ro 01h core header type register (hdr): this field returns 01h to indicate that this is a single function device with bridge header layout. bit access default value rst/pwr description 7:0 ro 00h core primary bus number (busn): configuration software typically programs this field wi th the number of the bus on the primary side of the bridge. since device 1 is an internal device and its primary bus is al ways 0, these bits are read only and are hardwired to 0. bit access default value rst/pwr description 7:0 r/w 00h core secondary bus number (busn): this field is programmed by configuration software with the bus number assigned to pci express. host-pci express* registers (d1:f0) 182 datasheet 6.1.11 subusn1?subordinate bus number b/d/f/type: 0/1/0/pci address offset: 1ah default value: 00h access: r/w size: 8 bits this register identifies the subordinate bus (if any) that resides at the level below pci express. this number is programmed by the pci configuration software to allow mapping of configuration cycles to pci express. 6.1.12 iobase1?i/o base address b/d/f/type: 0/1/0/pci address offset: 1ch default value: f0h access: ro, r/w size: 8 bits this register controls the processor to pci express i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are treated as 0. thus, the bottom of the defined i/o address range will be aligned to a 4 kb boundary. bit access default value rst/pwr description 7:0 r/w 00h core subordinate bus number (busn): this register is programmed by configuration software with the number of the highest subordinate bus that lies behind the device 1 bridge. when only a single pc i device resides on the pci express segment, this register will contain the same value as the sbusn1 register. bit access default value rst/ pwr description 7:4 r/w fh core i/o address base (iobase): this field corresponds to a[15:12] of the i/o addresses passed by bridge 1 to pci express. bios must not set this regist er to 00h; ot herwise, 0cf8h/ 0cfch accesses will be fo rwarded to the pci express hierarchy associated with this device. 3:0 ro 0h core reserved datasheet 183 host-pci express* registers (d1:f0) 6.1.13 iolimit1?i/o limit address b/d/f/type: 0/1/0/pci address offset: 1dh default value: 00h access: r/w, ro size: 8 bits this register controls the processor-to-pci express i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for th e purpose of address decode, address bits a[11:0] are assumed to be fffh. thus, the to p of the defined i/o address range will be at the top of a 4 kb aligned address block. 6.1.14 ssts1?secondary status b/d/f/type: 0/1/0/pci address offset: 1e-1fh default value: 0000h access: r/wc, ro size: 16 bits ssts1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., pci ex press-g side) of the "virtual" pci-pci bridge in the (g)mch. bit access default value rst/pwr description 7:4 r/w 0h core i/o address limit (iolimit): this field corresponds to a[15:12] of the i/o address limit of device 1. devices between this upper limit and io base1 will be passed to the pci express hierarchy associated with this device. 3:0 ro 0h core reserved bit access default value rst/pwr description 15 r/wc 0b core detected parity error (dpe): this bit is set by the secondary side for a type 1 configuration space header device whenever it receives a poisoned tlp, regardless of the state of the parity error response enable bit in the bridge control register. 14 r/wc 0b core received system error (rse): this bit is set when the secondary side for a type 1 configuration space header device receives an err_fatal or err_nonfatal. 13 r/wc 0b core received master abort (rma): this bit is set when the secondary side for type 1 configuration space header device (for requests initiated by the type 1 header device itself) receives a completion with unsupported request completion status. host-pci express* registers (d1:f0) 184 datasheet 6.1.15 mbase1?memor y base address b/d/f/type: 0/1/0/pci address offset: 20-21h default value: fff0h access: r/w, ro size: 16 bits this register controls the processor to pci express non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are re ad/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read- only and return zeroes when read. this regist er must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. 12 r/wc 0b core received target abort (rta): this bit is set when the secondary side for type 1 configuration space header device (for requests initiated by the type 1 header device itself) receives a completion with completer abort completion status. 11 ro 0b core signaled target abort (sta): not applicable or implemented. hardwired to 0. the (g)mch does not generate target aborts (the (g)mch will never complete a request using the completer abort completion status. 10:9 ro 00b core devselb timing (devt): not applicable or implemented. hardwired to 0. 8r/wc 0b core master data parity error (smdpe): when set, this bit indicates that the mch received across the link (upstream) a read data completion poisoned tlp (ep=1). this bit can only be set when the parity error enable bit in the bridge control register is set. 7r o 0 b c o r e fast back-to-back (fb2b): not applicable or implemented. hardwired to 0. 6 ro 0b core reserved 5r o 0 b c o r e 66/60 mhz capability (cap66): not applicable or implemented. hardwired to 0. 4:0 ro 00h core reserved bit access default value rst/pwr description bit access default value rst/pwr description 15:4 r/w fffh core memory address base (mbase): this field corresponds to a[31:20] of the lower limit of the memory range that will be passed to pci express. 3:0 ro 0h core reserved datasheet 185 host-pci express* registers (d1:f0) 6.1.16 mlimit1?memory limit address b/d/f/type: 0/1/0/pci address offset: 22-23h default value: 0000h access: ro, r/w size: 16 bits this register controls the processor to pci express non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read- only and return zeroes when read. this regist er must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note: memory range covered by mbase and mlimit registers are used to map non- prefetchable pci express address ranges (typically where control/status memory- mapped i/o data structures of the graphics controller will reside) and pmbase and pmlimit are used to map prefetchable a ddress ranges (typically graphics local memory). this segregation allows applicatio n of uswc space attribute to be performed in a true plug-and-play manner to the pr efetchable address range for improved processor- pci express memory access performance. note: configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the va lues that provide exclusive address ranges i.e. prevent overlap with each other and/or with the ranges covered with the main memory. there is no provision in the (g)mch hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured. bit access default value rst/pwr description 15:4 r/w 000h core memory address limit (mlimit): this field corresponds to a[31:20] of th e upper limit of the address range passed to pci express. 3:0 ro 0h core reserved host-pci express* registers (d1:f0) 186 datasheet 6.1.17 pmbase1?prefetchable memory base address b/d/f/type: 0/1/0/pci address offset: 24-25h default value: fff1h access: r/w, ro size: 16 bits this register in conjunction with the corresponding upper base address register controls the processor to pci express prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are re ad/write and correspond to address bits a[31:20] of the 40-bit address. the lower 8 bits of the upper base address register are read/write and correspond to address bits a[39:32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. bit access default value rst/pwr description 15:4 r/w fffh core prefetchable memory ba se address (mbase): this field corresponds to a[31:20] of the lower limit of the memory range that will be passed to pci express. 3:0 ro 1h core 64-bit address support (64-bit address support): this field indicates that the upper 32 bits of the prefetchable memory region ba se address are contained in the prefetchable memory base upper address register at 28h. datasheet 187 host-pci express* registers (d1:f0) 6.1.18 pmlimit1?prefetchabl e memory limit address b/d/f/type: 0/1/0/pci address offset: 26-27h default value: 0001h access: ro, r/w size: 16 bits this register in conjunction with the corresponding upper limit address register controls the processor to pci express prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and corresp ond to address bits a[31:20] of the 40-bit address. the lower 8 bi ts of the upper limit address register are read/write and correspond to address bits a[39 :32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be f ffffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that mu st be defined as uc and the ones that can be designated as a uswc (i.e., prefetchable) from the processor perspective. bit access default value rst/ pwr description 15:4 r/w 000h core prefetchable memory address limit (pmlimit): this field corresponds to a[31:20] of the upper limit of the address range passed to pci express. 3:0 ro 1h core 64-bit address support (64-bit address support): this field indicates that the upper 32 bits of the prefetchable memory region li mit address are contained in the prefetchable memory base limit address register at 2ch. host-pci express* registers (d1:f0) 188 datasheet 6.1.19 pmbaseu1?prefetchable memory base address upper b/d/f/type: 0/1/0/pci address offset: 28-2bh default value: 00000000h access: r/w size: 32 bits the functionality associated with this register is present in the peg design implementation. this register in conjunction with the corresponding upper base address register controls the processor to pci express prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are re ad/write and correspond to address bits a[31:20] of the 40-bit address. the lower 8 bits of the upper base address register are read/write and correspond to address bits a[39:32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. bit access default value rst/pwr description 31:0 r/w 00000000h core prefetchable memory ba se address (mbaseu): this field corresponds to a[63:32] of the lower limit of the prefetchable memory range th at will be passed to pci express. datasheet 189 host-pci express* registers (d1:f0) 6.1.20 pmlimitu1?prefetchable memory limit address upper b/d/f/type: 0/1/0/pci address offset: 2c-2fh default value: 00000000h access: r/w size: 32 bits the functionality associated with this register is present in the peg design implementation. this register in conjunction with the corresponding upper limit address register controls the processor to pci express prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and corresp ond to address bits a[31:20] of the 40- bit address. the lower 8 bits of the upper limit address register are read/write and correspond to address bits a[39:32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as uc and the ones that can be designated as a uswc (i.e., prefetchable) from the processor perspective. 6.1.21 capptr1?capabilities pointer b/d/f/type: 0/1/0/pci address offset: 34h default value: 88h access: ro size: 8 bits the capabilities pointer provides the address o ffset to the location of the first entry in this device's linked list of capabilities. bit access default value rst/pwr description 31:0 r/w 00000000h core prefetchable memory address limit (mlimitu): this field corresponds to a[63:32] of the upper limit of the prefetchable memory range th at will be passed to pci express. bit access default value rst/pwr description 7:0 ro 88h core first capability (capptr1): the first capability in the list is the subsystem id and subsystem vendor id capability. host-pci express* registers (d1:f0) 190 datasheet 6.1.22 intrline1?interrupt line b/d/f/type: 0/1/0/pci address offset: 3ch default value: 00h access: r/w size: 8 bits this register contains interrupt line routing information. the device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information. 6.1.23 intrpin1?interrupt pin b/d/f/type: 0/1/0/pci address offset: 3dh default value: 01h access: ro size: 8 bits this register specifies which interrupt pin this device uses. bit access default value rst/pwr description 7:0 r/w 00h core interrupt connection (intcon): this field is used to communicate interrupt li ne routing information. bios requirement : post software writes the routing information into this register as it initializes and configures the system. the value indicates to which input of the system interrupt controller th is device's in terrupt pin is connected. bit access default value rst/pwr description 7:0 ro 01h core interrupt pin (intpin): as a single function device, the pci express device specifies inta as its interrupt pin. 01h=inta. datasheet 191 host-pci express* registers (d1:f0) 6.1.24 bctrl1?bridge control b/d/f/type: 0/1/0/pci address offset: 3e-3fh default value: 0000h access: ro, r/w size: 16 bits this register provides extensions to the pc icmd1 register that are specific to pci-pci bridges. the bctrl provides additional cont rol for the secondary interface (i.e., pci express) as well as some bits that affect the overall behavior of the "virtual" host-pci express bridge in the (g)mch (e.g., vga compatible address ranges mapping). bit access default value rst/pwr description 15:12 ro 0h core reserved 11 ro 0b core discard timer serr# enable (dtserre): not applicable or implemented. hardwired to 0. 10 ro 0b core discard timer status (dtsts): not applicable or implemented. hardwired to 0. 9ro 0b core secondary discard timer (sdt): not applicable or implemented. hardwired to 0. 8ro 0b core primary discard timer (pdt): not applicable or implemented. hardwired to 0. 7ro 0b core fast back-to-back enable (fb2ben): not applicable or implemented. hardwired to 0. 6r/w 0b core secondary bus reset (sreset): setting this bit triggers a hot reset on the co rresponding pci express port. this will force the ltssm to transition to the hot reset state (via recovery) from l0 or l1 states. 5ro 0b core master abort mode (mamode): does not apply to pci express. hardwired to 0. 4r/w 0b core vga 16-bit decode (vga16d): enables the pci-to-pci bridge to provide 16-bit decoding of vga i/o address precluding the decoding of alias addresses every 1 kb. this bit only has meaning if bit 3 (vga enable) of this register is also set to 1, enabling vga i/o decoding and forwarding by the bridge. 0 = execute 10-bit address decodes on vga i/o accesses. 1 = execute 16-bit address decodes on vga i/o accesses. 3r/w 0b core vga enable (vgaen): this bit controls the routing of processor-initiated transactions targeting vga compatible i/o and memory address ranges. see the vgaen/mdap table in device 0, offset 97h[0]. host-pci express* registers (d1:f0) 192 datasheet 2r/w 0b core isa enable (isaen): this bit is needed to exclude legacy resource decode to route isa resources to legacy decode path. modifies the response by the (g)mch to an i/o access issued by the proc essor that target isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and iolimit registers. 0 = all addresses defined by the iobase and iolimit for processor i/o transactions will be mapped to pci express. 1 = (g)mch will not forward to pci express any i/o transactions addressing the last 768 bytes in each 1 kb block even if the addresses are within the range defined by the iobase and iolimit registers. 1r/w 0b core serr enable (serren): 0 = no forwarding of error messages from secondary side to primary side that co uld result in an serr. 1 = err_cor, err_nonfatal, and err_fatal messages result in serr me ssage when individually enabled by the root control register. 0r/w 0b core parity error response enable (peren): this bit controls whether or not the mast er data parity error bit in the secondary status regist er is set when the mch receives across the link (upstream) a read data completion poisoned tlp. 0 = master data parity error bit in secondary status register can not be set. 1 = master data parity error bit in secondary status register can be set. bit access default value rst/pwr description datasheet 193 host-pci express* registers (d1:f0) 6.1.25 pm_capid1?power ma nagement capabilities b/d/f/type: 0/1/0/pci address offset: 80-83h default value: c8039001h access: ro size: 32 bits bit access default value rst/pwr description 31:27 ro 19h core pme support (pmes): this field indicates the power states in which this device may indicate pme wake via pci express messaging. d0, d3hot & d3cold. this device is not required to do anything to support d3hot & d3cold, it simply must report that thos e states are supported. refer to the pci power management 1.1 specification for encoding explanation and other power management details. 26 ro 0b core d2 power state support (d2pss): hardwired to 0 to indicate that the d2 powe r management state is not supported. 25 ro 0b core d1 power state support (d1pss): hardwired to 0 to indicate that the d1 powe r management state is not supported. 24:22 ro 000b core auxiliary current (auxc): hardwired to 0 to indicate that there are no 3.3vaux au xiliary current requirements. 21 ro 0b core device specific initialization (dsi): hardwired to 0 to indicate that special initialization of this device is not required before generic class device driver is to use it. 20 ro 0b core auxiliary power source (aps): hardwired to 0. 19 ro 0b core pme clock (pmeclk): hardwired to 0 to indicate this device does not support pmeb generation. 18:16 ro 011b core pci pm cap version (pcipmcv): a value of 011b indicates that this function co mplies with revision 1.2 of the pci power management interface specification . 15:8 ro 90h core pointer to next capability (pnc): this field contains a pointer to the next item in the capabilities list. if msich (capl[0] @ 7fh) is 0, th en the next item in the capabilities list is the mess age signaled interrupts (msi) capability at 90h. if msich (capl[0] @ 7fh) is 1, then the next item in the capabilities list is the pci express capability at a0h. 7:0 ro 01h core capability id (cid): value of 01h identifies this linked list item (capability struct ure) as being for pci power management registers. host-pci express* registers (d1:f0) 194 datasheet 6.1.26 pm_cs1?power management control/status b/d/f/type: 0/1/0/pci address offset: 84-87h default value: 00000008h access: ro, r/w/p, r/w size: 32 bits bit access default value rst/pwr description 31:16 ro 0000h core reserved: not applicable or implemented. hardwired to 0. 15 ro 0b core pme status (pmests): this bit indicates that this device does not support pmeb generation from d3cold. 14:13 ro 00b core data scale (dscale): this bit indicates that this device does not support the power management data register. 12:9 ro 0h core data select (dsel): this bit indicates that this device does not support the power management data register. 8 r/w/p 0b core pme enable (pmee): this bit indicates that this device does not generate pmeb assertion from any d-state. 0 = pmeb generation not possible from any d state 1 = pmeb generation enabled from any d state the setting of this bit ha s no effect on hardware. see pm_cap[15:11] 7:4 ro 0000b core reserved 3ro 1b core no soft reset (nsr): when set to 1 this bit indicates that the device is transitioning from d3hot to d0 because the power state commands do not perform a internal reset. configuration context is preserved. upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits. when clear the devices do no t perform an internal reset upon transitioning from d3hot to d0 via software control of the power state bits. regardless of this bit the devices that transition from a d3hot-to-d0 by a system or bus segment reset will return to the device state d0 unintialized with only pme context preserved if pme is supported and enabled. 2 ro 0b core reserved datasheet 195 host-pci express* registers (d1:f0) 6.1.27 ss_capid?subsystem id and vendor id capabilities b/d/f/type: 0/1/0/pci address offset: 88-8bh default value: 0000800dh access: ro size: 32 bits this capability is used to uniquely identify the subsystem where the pci device resides. because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. however, it is necessary because microsoft will test for its presence. 1:0 r/w 00b core power state (ps): this field indicates the current power state of this device and can be used to set the device into a new power state. if softwa re attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. 00 = d0 01 = d1 (not supported) 10 = d2 (not supported) 11 = d3 support of d3cold does not require any special action. while in the d3hot state, this device can only act as the target of pci configuration transactions (for power management control). this device also cannot generate interrupts or respond to mmr cy cles in the d3 state. the device must re turn to the d0 state in order to be fully- functional. when the power state is othe r than d0, the bridge will master abort (i.e. not claim) any downstream cycles (with exception of type 0 config cycles). consequently, these unclaimed cycles will go down dmi and come back up as unsupported requests, which the mch logs as master aborts in device 0 pcists[13] there is no additional hardwa re functionality required to support these power states. bit access default value rst/pwr description bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:8 ro 80h core pointer to next capability (pnc): this field contains a pointer to the next item in the capabilities list which is the pci power management capability. 7:0 ro 0dh core capability id (cid): value of 0dh identifies this linked list item (capability struct ure) as being for ssid/ssvid registers in a pci-to-pci bridge. host-pci express* registers (d1:f0) 196 datasheet 6.1.28 ss?subsystem id and subsystem vendor id b/d/f/type: 0/1/0/pci address offset: 8c-8fh default value: 00008086h access: r/wo size: 32 bits system bios can be used as the mechanism for loading the ssid/svid values. these values must be preserved through power management transitions and a hardware reset. 6.1.29 msi_capid?message signal ed interrupts capability id b/d/f/type: 0/1/0/pci address offset: 90-91h default value: a005h access: ro size: 16 bits when a device supports msi, it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. the reporting of the existence of this ca pability can be disabled by setting msich (capl[0] @ 7fh). in that case walking th is linked list will skip this capability and instead go directly from the pci pm capability to the pci express capability. bit access default value rst/pwr description 31:16 r/wo 0000h core subsystem id (ssid): this field identifies the particular subsystem and is assigned by the vendor. 15:0 r/wo 8086h core subsystem vendor id (ssvid): this field identifies the manufacturer of th e subsystem and is the same as the vendor id which is assigned by the pci special interest group. bit access default value rst/pwr description 15:8 ro a0h core pointer to next capability (pnc): this field contains a pointer to the next item in the capabilities list which is the pci express capability. 7:0 ro 05h core capability id (cid): value of 05h identifies this linked list item (capability structur e) as being for msi registers. datasheet 197 host-pci express* registers (d1:f0) 6.1.30 mc?message control b/d/f/type: 0/1/0/pci address offset: 92-93h default value: 0000h access: ro, r/w size: 16 bits system software can modify bits in this register, but the device is prohibited from modifying bits. if the device writes the same message mult iple times, only one of those messages is ensured to be serviced. if all of them must be serviced, the device must not generate the same message again until the driver services the earlier one. bit access default value rst/pwr description 15:8 ro 00h core reserved 7ro 0b core 64-bit address capable (64ac): hardwired to 0 to indicate that the function does not implement the upper 32 bits of the message address register and is incapable of generating a 64-bit memory address. this may need to change in future implementations when addressable system memory exceeds the 32b/4 gb limit. 6:4 r/w 000b core multiple message enable (mme): system software programs this field to indi cate the actual number of messages allocated to this device. this number will be equal to or less than the number actually requested. the encoding is the same as for the mmc field below. 3:1 ro 000b core multiple message capable (mmc): system software reads this field to determin e the number of messages being requested by this device. 000 = 1 all other encodings are reserved. 0r/w 0b core msi enable (msien): this bit controls the ability of this device to generate msis. 0 = msi will not be generated. 1 = msi will be generated when we receive pme or hotplug messages. inta wi ll not be generated and inta status (pcists1[3]) will not be set. host-pci express* registers (d1:f0) 198 datasheet 6.1.31 ma?message address b/d/f/type: 0/1/0/pci address offset: 94-97h default value: 00000000h access: r/w, ro size: 32 bits 6.1.32 md?message data b/d/f/type: 0/1/0/pci address offset: 98-99h default value: 0000h access: r/w size: 16 bits 6.1.33 peg_capl?pci expr ess-g capability list b/d/f/type: 0/1/0/pci address offset: a0-a1h default value: 0010h access: ro size: 16 bits this register enumerates the pci express capability structure. bit access default value rst/pwr description 31:2 r/w 00000000h core message address (ma): this field is used by system software to assign an msi address to the device. the device handles an msi by wr iting the padded contents of the md register to this address. 1:0 ro 00b core force dword align (fdwa): hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary. bit access default value rst/pwr description 15:0 r/w 0000h core message data (md): this field is the base message data pattern assigned by system so ftware and used to handle an msi from the device. when the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the ma register. the upper 16 bits are always set to 0. the lower 16 bits are supplie d by this register. bit access default value rst/pwr description 15:8 ro 00h core pointer to next capability (pnc): this value terminates the capabilities list . the virtual channel capability and any other pci express specific capabi lities that are reported via this mechanism are in a separate capabilities list located entirely within pci express extended configuration space. 7:0 ro 10h core capability id (cid): this field identifies this linked list item (capability structure) as being for pci express registers. datasheet 199 host-pci express* registers (d1:f0) 6.1.34 peg_cap?pci express-g capabilities b/d/f/type: 0/1/0/pci address offset: a2-a3h default value: 0142h access: ro, r/wo size: 16 bits this register indicates pci express device capabilities. 6.1.35 dcap?device capabilities b/d/f/type: 0/1/0/pci address offset: a4-a7h default value: 00008000h access: ro size: 32 bits this register indicates pci express device capabilities. bit access default value rst/pwr description 15:14 ro 0b core reserved 13:9 ro 00h core interrupt message number (imn): not applicable or implemented. hardwired to 0. 8r/wo 1b core slot implemented (si): 0 = the pci express link associated with this port is connected to an integrated component or is disabled. 1 = the pci express link associated with this port is connected to a slot. bios requirement: this field must be initialized appropriately if a slot conne ction is not implemented. 7:4 ro 4h core device/port type (dpt): hardwired to 4h to indicate root port of pci express root complex. 3:0 ro 2h core pci express capability version (pciecv): hardwired to 2h to indicate compliance to the pci express capabilities register expansion ecn. bit access default value rst/pwr description 31:16 ro 0000h core reserved: not applicable or implemented. hardwired to 0. 15 ro 1b core role based error reporting (rber): this bit indicates that this device implements th e functionality defined in the error reporting ecn as required by the pci express 1.1 specification . 14:6 ro 000h core reserved: not applicable or implemented. hardwired to 0. 5ro 0b core extended tag field supported (etfs): hardwired to indicate support for 5-bit tags as a requestor. 4:3 ro 00b core phantom functions supported (pfs): not applicable or implemented. hardwired to 0. 2:0 ro 000b core max payload size (mps): hardwired to indicate 128b max supported payload for transaction layer packets (tlp). host-pci express* registers (d1:f0) 200 datasheet 6.1.36 dctl?device control b/d/f/type: 0/1/0/pci address offset: a8-a9h default value: 0000h access: ro, r/w size: 16 bits this register provides control for pci express device specific capabilities. the error reporting enable bits are in refere nce to errors detected by this device, not error messages received across the link. th e reporting of error messages (err_corr, err_nonfatal, err_fatal) received by root port is controlled exclusively by root port command register. bit access default value rst/pwr description 15:8 ro 0s core reserved 7:5 r/w 000b core max payload size (mps): 000 = 128b max supported payload for transaction layer packets (tlp). as a receiver, the device must handle tlps as large as the set value, as transmitter, the device must not generate tlps exceeding the set value. all other encodings are reserved. hardware will actually ignore th is field. it is writeable only to support comp liance testing. 4 ro 0b core reserved for enable relaxed ordering 3r/w 0b core unsupported request reporting enable (urre): unsupported request reporting enable (urre): when set, this bit allows signaling er r_nonfatal, err_fatal, or err_corr to the root control register when detecting an unmasked unsupported reques t (ur). an err_corr is signaled when an unmasked advisory non-fatal ur is received. an err_fatal or e rr_nonfatal is sent to the root control register when an uncorrectable non-advisory ur is received with the severity bit set in the uncorrectable error severity register. 2r/w 0b core fatal error reporting enable (fere): fatal error reporting enable (fere): when set, enables signaling of err_fatal to the root control register due to internally detected errors or error messag es received across the link. other bits also control the full scope of related error reporting. 1r/w 0b core non-fatal error reporting enable (nere): non-fatal error reporting enable (n ere): when set, enables signaling of err_nonfatal to the rool control register due to internally detected errors or error messages received across the link. othe r bits also control the full scope of related error reporting. 0r/w 0b core correctable error reporting enable (cere): correctable error reporting enab le (cere): when set, this bit enables signaling of err_corr to the root control register due to internally dete cted errors or error messages received across the link. othe r bits also control the full scope of related error reporting. datasheet 201 host-pci express* registers (d1:f0) 6.1.37 dsts?device status b/d/f/type: 0/1/0/pci address offset: aa-abh default value: 0000h access: ro, r/wc size: 16 bits this register reflects status corresponding to controls in the device control register. the error reporting bits are in reference to errors detected by this device, not errors messages received across the link. bit access default value rst/pwr description 15:6 ro 000h core reserved and zero: for future r/wc/s implementations; software must use 0 for writes to bits. 5ro 0b core transactions pending (tp): 0 = all pending transactions (including completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1 = indicates that the device has transaction(s) pending (including completions for any outstanding non-posted requests for all used traffic classes). 4ro 0b core reserved 3r/wc 0b core unsupported request detected (urd): when set, this bit indicates that the device received an unsupported request. errors are logged in this regist er regardless of whether error report ing is enabled or not in the device control register. additionally, the non-fatal error detected bit or the fatal error detected bit is set according to the setting of the unsupported request error seve rity bit. in production systems setting the fatal error detected bit is not an option as support for ae r will not be reported. 2r/wc 0b core fatal error detected (fed): when set, this bit indicates that fatal error(s) were detect ed. errors are logged in this register regardless of whethe r error reporting is enabled or not in the device control register. when advanced error handling is enabled, errors are logged in this register regardless of the settings of the uncorrectable error mask register. 1r/wc 0b core non-fatal error detected (nfed): when set, this bit indicates that non-fatal error( s) were detect ed. errors are logged in this register re gardless of whether error reporting is enabled or not in the device control register. when advanced error handling is enabled, errors are logged in this register regard less of the settings of the uncorrectable error mask register. 0r/wc 0b core correctable error detected (ced): when set, this bit indicates that correctable error(s) were detected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. when advanced error handling is enabled, errors are logged in this register regard less of the settings of the correctable error mask register. host-pci express* registers (d1:f0) 202 datasheet 6.1.38 lcap?link capabilities b/d/f/type: 0/1/0/pci address offset: ac-afh default value: 02214d02h access: ro, r/wo size: 32 bits this register indicates pci express device specific capabilities. bit access default value rst/pwr description 31:24 ro 02h core port number (pn): this field indicates the pci express port number for the given pci express link. this field matches the value in element self description[31:24]. 23:22 ro 00b core reserved 21 ro 1b core link bandwidth notificati on capability (lbnc): a value of 1b indicates support for the link bandwidth notification status and in terrupt mechanisms. this capability is required for all root ports and switch downstream ports supporting li nks wider than x1 and/or multiple link speeds. this field is not applicable and is reserved for endpoint devices, pci express to pci/ pci-x bridges, and upstream ports of switches. devices that do not impl ement the link bandwidth notification capability must hardwire this bit to 0b. 20 ro 0b core data link layer link active reporting capable (dlllarc): for a downstream port, this bit must be set to 1b if the component supports the optional capability of reporting the dl_active state of the data link control and management state machine. for a hot-plug capable downstream port (as indicate d by the hot-plug capable field of the slot capabilities re gister), this bi t must be set to 1b. for upstream ports and compon ents that do not support this optional capability, this bit must be hardwired to 0b. 19 ro 0b core surprise down error reporting capable (sderc): for a downstream port, this bit must be set to 1b if the component supports the optional capability of detecting and reporting a surprise down error condition. for upstream ports and compon ents that do not support this optional capability, this bit must be hardwired to 0b. datasheet 203 host-pci express* registers (d1:f0) 18 ro 0b core clock power management (cpm): a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) when the link is in the l1 and l2/3 ready link states. a value of 0b indicates the component does not have this capability and that refe rence clock(s) must not be removed in these link states. this capability is applicable only in form factors that support "clock request" (clkreq#) capability. for a multi-function device, each function indicates its capability independently. po wer management configuration software must only permit re ference clock removal if all functions of the multifunction device indicate a 1b in this bit. 17:15 r/wo 010b core l1 exit latency (l1elat): this field indicates the length of time this port requires to complete the transition from l1 to l0. the value 010 b indicates the range of 2 us to less than 4 us. bios requirement: if this field is required to be any value other than the default, bios must initialize it accordingly. both bytes of this register th at contain a portion of this field must be wr itten simultaneously in order to prevent an intermediate (and undesired) value from ever existing. 14:12 ro 100b core reserved 11:10 r/wo 11b core active state link pm support (aslpms): the (g)mch supports aspm l1. 9:4 r/wo 10h core max link width (mlw): this field indicates the maximum number of lanes supported for this link. 3:0 r/wo 2h core max link speed (mls): supported link speed ? this field indicates the supported link speed(s) of the associated port. defined encodings are: 0001b = 2.5 gt/s link speed supported 0010b = 5.0 gt/s and 2.5gt/s link speeds supported all other encodings are reserved. bit access default value rst/pwr description host-pci express* registers (d1:f0) 204 datasheet 6.1.39 lctl?link control b/d/f/type: 0/1/0/pci address offset: b0-b1h default value: 0000h access: r/w, ro, r/w/sc size: 16 bits this register allows control of pci express link. bit access default value rst/pwr description 15:12 ro 0000b core reserved 11 r/w 0b core link autonomous bandwidth interrupt enable (labie): when set, this bit enables the generation of an interrupt to indicate that the link autonomous bandwidth status bit has been set. this bit is not applicable and is reserved for endpoint devices, pci express to pci/ pci-x bridges, and upstream ports of switches. devices that do not impl ement the link bandwidth notification capability must hardwire this bit to 0b. 10 r/w 0b core link bandwidth management interrupt enable (lbmie): when set, this bit enables the generation of an interrupt to indicate that the link bandwidth management status bit has been set. this bit is not applicable and is reserved for endpoint devices, pci express to pci/ pci-x bridges, and upstream ports of switches. 9ro 0b core hardware autonomous width disable (hawd): when set, this bit disables hardwa re from changi ng the link width for reasons other than attempting to correct unreliable link operation by reducing link width. devices that do not implement the ability autonomously to change link width are permitted to hardwire this bit to 0b. 8r o 0 b c o r e enable clock power management (ecpm): applicable only for form factors that support a "clock request" (clkreq#) mechanism, this en able functions as follows: 0 = clock power management is disabled and device must hold clkreq# signal low 1 = when this bit is set to 1, the device is permitted to use clkreq# signal to power ma nage link clock according to protocol defined in appropriate form factor specification. components that do not suppo rt clock power management (as indicated by a 0b value in the clock power management bit of the link capabilities register) must hardwire this bit to 0b. 7 r/w 0b core reserved datasheet 205 host-pci express* registers (d1:f0) 6r/w 0b core common clock configuration (ccc): 0 = indicates that this component and the component at the opposite end of this link are operating with asynchronous reference clock. 1 = indicates that this component and the component at the opposite end of this link are operating with a distributed common reference clock. the state of this bit affects the n_fts value advertised during link training. see pegl0slat at offset 22ch. 5 r/w/sc 0b core retrain link (rl): 0 = normal operation. 1 = full link retraining is init iated by directing the physical layer ltssm from l0 or l1 states to the recovery state. this bit always returns 0 when read. this bit is cleared automatically (no need to write a 0). 4r/w 0b core link disable (ld): 0 = normal operation 1 = link is disabled. forces the ltssm to transition to the disabled state (via recove ry) from l0 or l1 states. link retraining happens automatically on 0 to 1 transition, just like wh en coming out of reset. writes to this bit are immediately reflected in the value read from the bit, regardless of actual link state. 3ro 0b core read completion boundary (rcb): hardwired to 0 to indicate 64 byte. 2 ro 0b core reserved 1:0 r/w 00b core active state pm (aspm): this field controls the level of active state power manageme nt supported on the given link. 00 = disabled 01 = reserved 10 = l1 entry enabled 11 = l1 entry enabled bit access default value rst/pwr description host-pci express* registers (d1:f0) 206 datasheet 6.1.40 lsts?link status b/d/f/type: 0/1/0/pci address offset: b2-b3h default value: 1000h access: r/wc, ro size: 16 bits this register indicates pci express link status. bit access default value rst/pwr description 15 r/wc 0b core link autonomous bandwi dth status (labws): this bit is set to 1b by hardware to indicate that hardware has autonomously changed link sp eed or width, without the port transitioning through dl_down status, for reasons other than to attempt to corre ct unreliable link operation. this bit must be set if the physical layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change. this bit must be set when the upstream component receives eight consecutive ts1 or ts2 ordered sets with the autonomous change bit set. 14 r/wc 0b core link bandwidth management status (lbwms): this bit is set to 1b by hardware to indicate that either of the following has occurred withou t the port transitioning through dl_down status: ? a link retraining initiated by a write of 1b to the retrain link bit has completed. note: this bit is set following any write of 1b to the retrain link bit, including when the link is in the process of retraining for some other reason. ? hardware has autonomously changed link speed or width to attempt to correct unreliable link operation, either through an ltssm timeout or a higher level process this bit must be set if the physical layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change. 13 ro 0b core data link layer link ac tive (optional) (dllla): this bit indicates the status of the data link control and management state machine. it returns a 1b to indicate the dl_active state, 0b otherwise. this bit must be implemente d if the corresponding data link layer active capability bi t is implemented. otherwise, this bit must be hardwired to 0b. 12 ro 1b core slot clock configuration (scc): 0 = the device uses an indepe ndent clock irrespective of the presence of a reference on the connector. 1 = the device uses the same physical refere nce clock that the platform provides on the connector. datasheet 207 host-pci express* registers (d1:f0) 11 ro 0b core link training (ltrn): this bit indicates that the physical layer ltssm is in the configuration or recovery state, or that 1b was written to the retrain link bit but link training has not yet begun. hardware clears this bit when the ltssm exits the configuration/recovery state once link training is complete. 10 ro 0b core undefined (undefined): the value read from this bit is undefined. in previous versions of this specification, this bit was used to indicate a link training error. system software must ignore the valu e read from this bit. system software is permitted to write any value to this bit. 9:4 ro 00h core negotiated link width (nlw): this field indicates negotiated link width. this fiel d is valid only when the link is in the l0 or l1 states (after link width negotiation is successfully completed). 00h = reserved 01h = x1 02h = x2 04h = x4 08h = x8 10h = x16 all other encodings are reserved. 3:0 ro 0h core current link speed (cls): this field indicates the negotiated link speed of the given pci express link. 0001b = 2.5 gt/s pci express link 0010b = 5 gt/s pci express link all other encodings are reserved . the value in this field is undefined when the link is not up. bit access default value rst/pwr description host-pci express* registers (d1:f0) 208 datasheet 6.1.41 slotcap?slot capabilities b/d/f/type: 0/1/0/pci address offset: b4-b7h default value: 00040000h access: r/wo, ro size: 32 bits pci express slot related registers allow for the support of hot plug. bit access default value rst/pwr description 31:19 r/wo 0000h core physical slot number (psn): this field indicates the physical slot number attached to this port. bios requirement: this field must be initialized by bios to a value that assigns a slot number that is globally unique within the chassis. 18 r/wo 1b core no command completed support (nccs): when set to 1b, this bit indicates that th is slot does not generate software notification when an issued command is completed by the hot-plug co ntroller. this bit is only permitted to be set to 1b if th e hotplug capable port is able to accept writes to all fields of the slot control register without delay between successive writes. 17 ro 0b core reserved 16:15 r/wo 00b core slot power limit scale (spls): this field specifies the scale used for the slot power limit value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x if this field is written, the link sends a set_slot_power_limit message. 14:7 r/wo 00h core slot power limit value (splv): in combination with the slot power limit scale value, this field specifies the upper limit on power supplied by slot . power limit (in watts) is calculated by multiplying the va lue in this field by the value in the slot power limit scale field. if this field is written, the link sends a set_slot_power_limit message. 6:0 ro 0b core reserved datasheet 209 host-pci express* registers (d1:f0) 6.1.42 slotctl?slot control b/d/f/type: 0/1/0/pci address offset: b8-b9h default value: 0000h access: ro, r/w size: 16 bits pci express slot related registers allow for the support of hot plug. bit access default value rst/pwr description 15:4 ro 0s core reserved 3r/w 0b core presence detect chan ged enable (pdce): when set to 1b, this bit enables software notification on a presence detect changed event. 2:0 ro 000b core reserved host-pci express* registers (d1:f0) 210 datasheet 6.1.43 slotsts?slot status b/d/f/type: 0/1/0/pci address offset: ba-bbh default value: 0000h access: ro, r/wc size: 16 bits pci express slot related registers allow for the support of hot plug. bit access default value rst/ pwr description 15:9 ro 0000000b core reserved and zero: for future r/wc/s implementations; software must use 0 for writes to bits. 8:7 ro 00b core reserved 6ro 0b core presence detect state (pds): in band presence detect state: 0 = slot empty 1 = card present in slot this bit indicates the presence of an adapter in the slot, reflected by the logical "or" of the physical layer in-band presence detect mechanism and, if present, any out-of- band presence dete ct mechanism define d for the slot's corresponding form factor. note that the in-band presence detect mechanism requires th at power be applied to an adapter for its presence to be detected. consequently, form factors that require a po wer controller for hot-plug must implement a physical pin presen ce detect mechanism. this bit must be implemente d on all downstream ports that implement slots. for downstream ports not connected to slots (where the slot implemented bit of the pci express capabiliti es register is 0b), this bit must return 1b. 5:4 ro 00b core reserved 3r/wc 0b core presence detect changed (pdc): a pulse indication that the inband presence detect state has changed. this bit is set when the value reported in pr esence detect state is changed. 2:0 ro 000b core reserved datasheet 211 host-pci express* registers (d1:f0) 6.1.44 rctl?root control b/d/f/type: 0/1/0/pci address offset: bc-bdh default value: 0000h access: ro, r/w size: 16 bits this register allows control of pci express root complex specific parameters. the system error control bits in this regist er determine if corresponding serrs are generated when our device detects an error (reported in this device's device status register) or when an error message is received across the link. reporting of serr as controlled by these bits takes precedence over the serr enable in the pci command register. bit access default value rst/pwr description 15:4 ro 0s core reserved 3r/w 0b core pme interrupt enable (pmeie): 0 = no interrupts are generate d as a result of receiving pme messages. 1 = enables interrupt generati on upon receipt of a pme message as refl ected in the pme status bit of the root status register. a pme interru pt is also generated if the pme status bit of the ro ot status register is set when this bit is set from a cleared state. 2r/w 0b core system error on fatal error enable (sefee): this bit controls the root complex's response to fatal errors. 0 = no serr generated on receipt of fatal error. 1 = indicates that an serr sh ould be generated if a fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 1r/w 0b core system error on non-fatal uncorrectable error enable (senfuee): this bit controls the root complex's response to non-fatal errors. 0 = no serr generated on re ceipt of non-fatal error. 1 = indicates that an serr sh ould be generated if a non- fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 0r/w 0b core system error on correctable error enable (secee): this bit controls the root complex's response to correctable errors. 0 = no serr generated on re ceipt of correctable error. 1 = indicates that an serr should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. host-pci express* registers (d1:f0) 212 datasheet 6.1.45 rsts?root status b/d/f/type: 0/1/0/pci address offset: c0-c3h default value: 00000000h access: ro, r/wc size: 32 bits this register provides information about pci express root complex specific parameters. 6.1.46 dcap2?device capabilities 2 b/d/f/type: 0/1/0/pci address offset: c4-c7h default value: 00000000h access: ro size: 32 bits 6.1.47 dctl2?device control 2 b/d/f/type: 0/1/0/pci address offset: c8-c9h default value: 0000h access: ro size: 16 bits bit access default value rst/pwr description 31:18 ro 0000h core reserved and zero: for future r/wc/s implementations; software must use 0 for writes to bits. 17 ro 0b core pme pending (pmep): this bit indicates that another pme is pending when the pme st atus bit is set. when the pme status bit is cleared by software; the pme is delivered by hardware by setting the pme status bit again and updating the requestor id a ppropriately. the pme pending bit is cleared by hardware if no more pmes are pending. 16 r/wc 0b core pme status (pmes): this bit indicates that pme was asserted by the requestor id indicated in the pme requestor id field. subseque nt pmes are kept pending until the status register is cl eared by writing a 1 to this field. 15:0 ro 0000h core pme requestor id (pmerid): this field indicates the pci requestor id of the last pme requestor. bit access default value rst/pwr description 31:0 ro 00000000h core reserved bit access default value rst/pwr description 15:0 ro 0000h core reserved datasheet 213 host-pci express* registers (d1:f0) 6.1.48 dsts2?device status 2 b/d/f/type: 0/1/0/pci address offset: ca-cbh default value: 0000h access: ro size: 16 bits 6.1.49 lcap2?link capabilities 2 b/d/f/type: 0/1/0/pci address offset: cc-cfh default value: 00000000h access: ro size: 32 bits bit access default value rst/pwr description 15:0 ro 0000h core reserved bit access default value rst/pwr description 31:0 ro 00000000h core reserved host-pci express* registers (d1:f0) 214 datasheet 6.1.50 lctl2?link control 2 b/d/f/type: 0/1/0/pci address offset: d0-d1h default value: 0002h access: r/w/p, r/w, ro size: 16 bits bit access default value rst/pwr description 15:13 ro 000b core reserved 12 r/w/p 0b core compliance de -emphasis: this bit sets the de-emphasis level in polling.compliance state if the entry occurred due to the enter compliance bit being 1b. 1 = 3.5 db 0 = 6 db when the link is operating at 2.5 gt/s, the setting of this bit has no effect. components that support only 2.5 gt/s speed are permitted to hardwire this bit to 0b. for a multi-function device as sociated with an upstream port, the bit in function 0 is of type r/ws, and only function 0 controls the component's link behavior. in all other functions of that device , this bit is of type rsvd. this bit is intended for debug, compli ance testing purposes. system firmware and software is allowed to modify this bit only during debug or compliance testing. 11 r/w/p 0b core compliance sos (compsos): when set to 1b, the ltssm is required to send skp ordered sets pe riodically in between the (modified) compliance patterns. for a multi-function device as sociated with an upstream port, the bit in function 0 is of type r/ws, and only function 0 controls the component's link behavior. in all other functions of that device , this bit is of type rsvd. components that support on ly the 2.5 gt/s speed are permitted to hardwire this field to 0b. 10 r/w/p 0b core enter modified compliance (entermodcompliance): when this bit is set to 1b, the device transmits modified compliance pattern if the ltssm enters polling.compliance state. components that support only the 2.5gt/s speed are permitted to hardwire this bit to 0b. datasheet 215 host-pci express* registers (d1:f0) 9:7 r/w/p 000b core transmit margin (txmargin): this field controls the value of the non-deemphasized voltage level at the transmitter pins. this field is reset to 000b on entry to the ltssm polling.configuration substates. 000 = normal operating range 001 = 800?1200 mv for full swing and 400?700 mv for half-swing 010 ? (n-1) = values must be monotonic with a non- zero slope. the value of n must be greater than 3 and less than 7. at least two of these must be below the normal operating range n = 200?400 mv for full-swing and 100?200 mv for half-swing n ? 111 = reserved components that support only the 2.5 gt/s speed are permitted to hardwire this bit to 0b. when operating in 5 gt/s mo de with full swing, the deemphasis ratio must be maintained within 1 db from the specification defined operational value (either -3.5 or -6 db). 6r/w/p 0b core selectable de-emphasis (selectabledeemphasis): when the link is operating at 5 gt/s speed, selects the level of de-emphasis. 1 = 3.5 db 0 = 6 db default value is implementation specific, unless a specific value is required fo r a selected form factor or platform. when the link is operating at 2.5 gt/s speed, the setting of this bit has no effect. comp onents that support only the 2.5 gt/s speed are permitted to hardwire this bit to 0b. 5r/w 0b core hardware autonomous speed disable (hasd): when set to 1, this bit disables ha rdware from changing the link speed for reasons other than attempting to correct unreliable link operation by reducing link speed. 4r/w/p 0b core enter compliance (ec): software is permitted to force a link to enter compliance mode at the speed indicated in the target link speed field by setting this bit to 1 in both components on a link and then initiating a hot reset on the link. bit access default value rst/pwr description host-pci express* registers (d1:f0) 216 datasheet 6.1.51 lsts2?link status 2 b/d/f/type: 0/1/0/pci address offset: d2-d3h default value: 0000h access: ro size: 16 bits 3:0 r/w 2h core target link speed (tls): for downstream ports, this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001 = 2.5 gb/s target link speed 0010 = 5 gb/s target link speed all other encodings are reserved. if a value is written to this field that does not correspond to a speed included in the suppo rted link speeds field, the result is undefined. the default value of this field is the highest link speed supported by the componen t (as reported in the supported link speeds field of the link capabilities register) unless the correspond ing platform / form factor requires a different default value. for both upstream and downst ream ports, this field is used to set the target compliance mode speed when software is using the enter co mpliance bit to force a link into compliance mode. bit access default value rst/pwr description bit access default value rst/pwr description 15:1 ro 0000h core reserved 0ro 0b core current de-emphasis level (curdelvl): when the link is operating at 5 gt/s spee d, this reflects the level of de-emphasis. 1 = 3.5 db 0 = 6 db when the link is operating at 2.5 gt/s speed, this bit is 0b. datasheet 217 host-pci express* registers (d1:f0) 6.1.52 scap2?slot capabilities 2 b/d/f/type: 0/1/0/pci address offset: d4-d7h default value: 00000000h access: ro size: 32 bits 6.1.53 sctl2?slot control 2 b/d/f/type: 0/1/0/pci address offset: d8-d9h default value: 0000h access: ro size: 16 bits 6.1.54 ssts2?slot status 2 b/d/f/type: 0/1/0/pci address offset: da-dbh default value: 0000h access: ro size: 16 bits bit access default value rst/pwr description 31:0 ro 00000000h core reserved bit access default value rst/pwr description 15:0 ro 0000h core reserved bit access default value rst/pwr description 15:0 ro 0000h core reserved host-pci express* registers (d1:f0) 218 datasheet 6.1.55 peglc?pci express-g legacy control b/d/f/type: 0/1/0/pci address offset: ec-efh default value: 00000000h access: ro, r/w size: 32 bits this register controls functionality that is needed by legacy (non-pci express aware) operating systems during run time. bit access default value rst/pwr description 31:3 ro 00000000h core reserved 2r/w 0b core pme gpe enable (pmegpe): 0 = do not generate gpe pme message when pme is received. 1 = generate a gpe pme message when pme is received (assert_pmegpe and deassert_pmegpe messages on dmi). this enables the mch to support pmes on the peg port under legacy oss. 1r/w 0b core hot-plug gpe enable (hpgpe): 0 = do not generate gpe hot-plug message when hot-plug event is received. 1 = generate a gpe hot-plug message when hot-plug event is received (assert_hpgpe and deassert_hpgpe messages on dmi). this en ables the mch to support hot-plug on the peg port under legacy oss. 0r/w 0b core general message gpe enable (gengpe): 0 = do not forward receiv ed gpe assert/deassert messages. 1 = forward received gpe assert/deassert messages. these general gpe message can be received via the peg port from an ex ternal intel device (i.e., pxh) and will be subsequently forwarded to the ich (via assert_gpe and deassert_gpe messages on dmi). for example, pxh might send this message if a pci express device is hot plugged into a pxh downstream port. datasheet 219 direct memory interface registers (dmibar) 7 direct memory interface registers (dmibar) address offset register symbol register name default value access 0?3h dmivcech dmi virtual channel enhanced capability 04010002h ro 4?7h dmipvccap1 dmi port vc capability register 1 00000001h ro, r/wo 8?bh dmipvccap2 dmi port vc capability register 2 00000000h ro c?dh dmipvcctl dmi port vc control 0000h ro, r/w 10?13h dmivc0rcap dmi vc0 resource capability 00000001h ro 14?17h dmivc0rctl0 dmi vc0 resource control 800000ffh ro, r/w 1a?1bh dmivc0rsts dmi vc0 resource status 0002h ro 1c?1fh dmivc1rcap dmi vc1 resource capability 00008001h ro 20?23h dmivc1rctl1 dmi vc1 resource control 01000000h r/w, ro 26?27h dmivc1rsts dmi vc1 resource status 0002h ro 84?87h dmilcap dmi link capabilities 00012c41h ro, r/wo 88?89h dmilctl dmi link control 0000h ro, r/w 8a?8bh dmilsts dmi link status 0001h ro direct memory interface registers (dmibar) 220 datasheet 7.1 dmivcech?dmi virtual channel enhanced capability b/d/f/type: 0/0/0/dmibar address offset: 0-3h default value: 04010002h access: ro size: 32 bits this register indicates dmi virtual channel capabilities. 7.2 dmipvccap1?dmi port vc capability register 1 b/d/f/type: 0/0/0/dmibar address offset: 4-7h default value: 00000001h access: ro, r/wo size: 32 bits this register describes the configuration of pci express virtual channels associated with this port. bit access default value rst/pwr description 31:20 ro 040h core pointer to next capability (pnc): this field contains the offset to the next pci ex press capability structure in the linked list of capabilities (link declaration capability). 19:16 ro 1h core pci express virtual channel capability version (pcievccv): hardwired to 1 to indicate compliances with the 1.1 version of the pci express specification. note: this version does not change for 2.0 compliance. 15:0 ro 0002h core extended capability id (ecid): value of 0002h identifies this linked list item (capability structure) as being for pci express vi rtual channel registers. bit access default value rst/pwr description 31:7 ro 0000000h core reserved 6:4 ro 000b core low priority extended vc count (lpevcc): this field indicates the number of (extended) virtual channels in addition to the default vc belo nging to the low-priority vc (lpvc) group that has the lowest priority with respect to other vc resources in a strict-priority vc arbitration. the value of 0 in this field implies strict vc arbitration. 3 ro 0b core reserved 2:0 r/wo 001b core extended vc count (evcc): this field indicates the number of (extended) virtual ch annels in addition to the default vc supported by the device. the private virtual channel is not included in this count. datasheet 221 direct memory interface registers (dmibar) 7.3 dmipvccap2?dmi port vc capability register 2 b/d/f/type: 0/0/0/dmibar address offset: 8-bh default value: 00000000h access: ro size: 32 bits this register describes the configuration of pci express virtual channels associated with this port. 7.4 dmipvcctl?dmi port vc control b/d/f/type: 0/0/0/dmibar address offset: c-dh default value: 0000h access: ro, r/w size: 16 bits bit access default value rst/pwr description 31:24 ro 00h core reserved for vc arbitration table offset: 23:8 ro 0000h core reserved 7:0 ro 00h core reserved for vc ar bitration capabi lity (vcac): bit access default value rst/pwr description 15:4 ro 000h core reserved 3:1 r/w 000b core vc arbitration select (vcas): this field will be programmed by software to the only possible value as indicated in the vc arbitration capability field. the value 000b when written to this field will indicate the vc arbitration sche me is hardware fixed (in the root complex). this field cannot be modified when more than one vc in the lpvc group is enabled. 000 = hardware fixed arbitr ation scheme (e.g, round robin) others = reserved see the pci express specif ication for more details direct memory interface registers (dmibar) 222 datasheet 7.5 dmivc0rcap?dmi vc0 resource capability b/d/f/type: 0/0/0/dmibar address offset: 10-13h default value: 00000001h access: ro size: 32 bits 7.6 dmivc0rctl0?dmi vc0 resource control b/d/f/type: 0/0/0/dmibar address offset: 14-17h default value: 800000ffh access: ro, r/w size: 32 bits this register controls the resources associated with pci express virtual channel 0. bit access default value rst/pwr description 31:16 ro 0s core reserved 15 ro 0b core reject snoop transactions (rejsnpt): 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = when set, any transaction for which the no snoop attribute is applicable but is not set within the tlp header will be rejected as an unsupported request. 14:8 ro 00h core reserved 7:0 ro 01h core port arbitration ca pability (pac): having only bit 0 set indicates that the only suppo rted arbitration scheme for this vc is non-configurable hardware-fixed. bit access default value rst/pwr description 31 ro 1b core virtual channel 0 enable (vc0e): for vc0, this bit is hardwired to 1 and read only as vc0 can never be disabled. 30:27 ro 0h core reserved 26:24 ro 000b core virtual channel 0 id (vc0id): assigns a vc id to the vc resource. for vc0 this is hardwired to 0 and read only. 23:20 ro 0h core reserved 19:17 r/w 000b core port arbitration select (pas): this field configures the vc resource to provide a partic ular port arbitration service. valid value for this field is a number corresponding to one of the asserted bits in the port arbitration capability field of the vc resource. because only bit 0 of that field is asserted. this field will always be programmed to 1. datasheet 223 direct memory interface registers (dmibar) 7.7 dmivc0rsts?dmi vc0 resource status b/d/f/type: 0/0/0/dmibar address offset: 1a-1bh default value: 0002h access: ro size: 16 bits this register reports the virtual channel specific status. 16:8 ro 000h core reserved 7:1 r/w 7fh core traffic class / virtual channel 0 map (tcvc0m): this field indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. to remove one or more tcs from the tc/vc map of an enabled vc, software mu st ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 0r o 1 b c o r e traffic class 0 / virtual channel 0 map (tc0vc0m): traffic class 0 is always routed to vc0. bit access default value rst/pwr description bit access default value rst/pwr description 15:2 ro 0000h core reserved: reserved and zero for future r/wc/s implementations. software must use 0 for writes to these bits. 1ro 1b core virtual channel 0 negotiation pending (vc0np): 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). this bit indicates the status of the process of flow control initialization. it is set by default on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link su ccessfully exits the fc_init2 state. bios requirement: before using a virtual channel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0 ro 0b core reserved direct memory interface registers (dmibar) 224 datasheet 7.8 dmivc1rcap?dmi vc1 resource capability b/d/f/type: 0/0/0/dmibar address offset: 1c-1fh default value: 00008001h access: ro size: 32 bits 7.9 dmivc1rctl1?dmi vc1 resource control b/d/f/type: 0/0/0/dmibar address offset: 20-23h default value: 01000000h access: r/w, ro size: 32 bits this register controls the resources associated with pci express virtual channel 1. bit access default value rst/pwr description 31:16 ro 0s core reserved 15 ro 1b core reject snoop transactions (rejsnpt): 0 = transactions with or without the no snoop bit set within the tlp header are allowed on this vc. 1 = when set, any transaction for which the no snoop attribute is applicable but is not set within the tlp header will be rejected as an unsupported request. 14:8 ro 00h core reserved 7:0 ro 01h core port arbitration capability (pac): having only bit 0 set indicates that the only suppo rted arbitration scheme for this vc is non-configurable hardware-fixed. datasheet 225 direct memory interface registers (dmibar) bit access default value rst/pwr description 31 r/w 0b core virtual channel 1 enable (vc1e): 0 = virtual channel is disabled. 1 = virtual channel is enabled. see exceptions below. software must use the vc nego tiation pending bit to check whether the vc negotiation is complete. when vc negotiation pending bit is clea red, a 1 read from this vc enable bit indicates that the vc is enabled (flow control initialization is completed for the pci express port). a 0 read from this bit indicates that the virtual channel is currently disabled. bios requirement: 1. to enable a virtual channe l, the vc enable bits for that virtual channel must be set in both components on a link. 2. to disable a virtual channel, the vc enable bits for that virtual channel must be cleared in both components on a link. 3. software must en sure that no traffic is using a virtual channel at the time it is disabled. 4. software must fully disa ble a virtual channel in both components on a link before re-enabling the virtual channel. 30:27 ro 0h core reserved 26:24 r/w 001b core virtual channel 1 id (vc1id): assigns a vc id to the vc resource. assigned value mu st be non-zero. this field can not be modified when the vc is already enabled. 23:20 ro 0h core reserved 19:17 r/w 000b core port arbitration select (pas): this field configures the vc resource to provide a particular port arbitration service. valid value for this field is a number corresponding to one of the asserted bits in the port arbitration capability field of the vc resource. 16:8 ro 000h core reserved 7:1 r/w 00h core traffic class / virtual channel 1 map (tcvc1m): this field indicates the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for example, when bit 7 is set in this field, tc7 is mapped to this vc resource. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. in order to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 0r o 0 b c o r e traffic class 0 / virtual channel 1 map (tc0vc1m): traffic class 0 is always routed to vc0. direct memory interface registers (dmibar) 226 datasheet 7.10 dmivc1rsts?dmi vc1 resource status b/d/f/type: 0/0/0/dmibar address offset: 26-27h default value: 0002h access: ro size: 16 bits this register reports the virtual channel specific status. bit access default value rst/pwr description 15:2 ro 0000h core reserved 1ro 1b core virtual channel 1 negotiation pending (vc1np): 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). software may use this bit when enabling or disabling the vc. this bit indicates the status of the process of flow control initialization. it is set by default on reset, as well as whenever the corresponding virtual channel is disabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. before using a virtual cha nnel, software must check whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0 ro 0b core reserved datasheet 227 direct memory interface registers (dmibar) 7.11 dmilcap?dmi link capabilities b/d/f/type: 0/0/0/dmibar address offset: 84-87h default value: 00012c41h access: ro, r/wo size: 32 bits this register indicates dmi specific capabilities. bit access default value rst/pwr description 31:18 ro 0000h core reserved 17:15 r/wo 010b core l1 exit latency (l1selat): this field indicates the length of time this port requires to complete the transition from l1 to l0. the value 010 b indicates the range of 2 us to less than 4 us. 000 = less than 1s 001 = 1 s to less than 2 s 010 = 2 s to less than 4 s 011 = 4 s to less than 8 s 100 = 8 s to less than 16 s 101 = 16 s to less than 32 s 110 = 32 s?64 s 111 = more than 64 s both bytes of this register th at contain a portion of this field must be wr itten simultaneously in order to prevent an intermediate (and undesired) value from ever existing. 14:12 r/wo 010b core reserved 11:10 ro 11b core active state link pm support (aslpms): l1 entry supported. 9:4 ro 04h core max link width (mlw): this field indicates the maximum number of lanes supported for this link. 3:0 ro 1h core max link speed (mls): hardwired to indicate 2.5 gb/s. direct memory interface registers (dmibar) 228 datasheet 7.12 dmilctl?dmi link control b/d/f/type: 0/0/0/dmibar address offset: 88-89h default value: 0000h access: ro, r/w size: 16 bits this register allows control of dmi. 7.13 dmilsts?dmi link status b/d/f/type: 0/0/0/dmibar address offset: 8a-8bh default value: 0001h access: ro size: 16 bits this register indicates dmi status. bit access default value rst/pwr description 15:2 ro 00h core reserved 7 r/w 0b core reserved 6:2 ro 0h core reserved 1:0 r/w 00b core active state power management support (aspms): this register controls the level of active state power management supported on the given link. 00 = disabled 01 = reserved 10 = l1 entry enabled 11 = l1 entry enabled bit access default value rst/pwr description 15:10 ro 00h core reserved 9:4 ro 00h core negotiated width (nwid): this register indicates negotiated link width. this fiel d is valid only when the link is in the l0 or l1 states (a fter link width negotiation is successfully completed). 00h = reserved 01h = x1 02h = x2 04h = x4 all other encodings are reserved. 3:0 ro 1h core negotiated speed (nspd): this field indicates negotiated link speed. 1h = 2.5 gb/s all other encodings are reserved. datasheet 229 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) device 6 contains the controls associated with the pci express root port that is the intended attach point for external devices. in addition, it also functions as the virtual pci-to-pci bridge. ta b l e 1 4 provides an address map of the d1:f0 registers listed by address offset in ascending order. this chapter provides a detailed bit description of the registers. warning: when reading the pci express "conceptual" registers such as this, you may not get a valid value unless the register value is stable. the pci express* specification defines two types of reserved bits: reserved and preserved: ? reserved for future rw implementations; software must preserve value read for writes to bits. ? reserved and zero: reserved for future r/wc/s implementations; software must use 0 for writes to bits. unless explicitly documented as reserved an d zero, all bits marked as reserved are part of the reserved and preserved type, which have historically been the typical definition for reserved. note: most (if not all) control bits in this device cannot be modified unless the link is down. software is required to first disable the lin k, then program the registers, and then re- enable the link (which will cause a full-retrain with the new settings). table 14. host-secondary pci ex press* bridge regi ster address map (d6:f0) (sheet 1 of 3) address offset register symbol register name default value access 0?1h vid1 vendor identification 8086h ro 2?3h did1 device identification 29e9h ro 4?5h pcicmd1 pci command 0000h ro, rw 6?7h pcists1 pci status 0010h ro, rwc 8h rid1 revision identification see register description ro 9?bh cc1 class code 060400h ro ch cl1 cache line size 00h rw eh hdr1 header type 01h ro 18h pbusn1 primary bus number 00h ro 19h sbusn1 secondary bus number 00h rw 1ah subusn1 subordinate bus number 00h rw 1ch iobase1 i/o base address f0h ro, rw host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 230 datasheet 1dh iolimit1 i/o limit address 00h rw, ro 1e?1fh ssts1 secondary status 0000h ro, rwc 20?21h mbase1 memory base address fff0h rw, ro 22?23h mlimit1 memory limit address 0000h rw, ro 24?25h pmbase1 prefetchable memory base address fff1h rw, ro 26?27h pmlimit1 prefetchable memory limit address 0001h ro, rw 28?2bh pmbaseu1 prefetchable memory base address upper 00000000h rw 2c?2fh pmlimitu1 prefetchable memory limit address upper 00000000h rw 34h capptr1 capabilities pointer 88h ro 3ch intrline1 interrupt line 00h rw 3dh intrpin1 interrupt pin 01h ro 3e?3fh bctrl1 bridge control 0000h ro, rw 80?83h pm_capid1 power management capabilities c8039001h ro 84?87h pm_cs1 power management control/status 00000008h ro, rw, rw/p 88?8bh ss_capid subsystem id and vendor id capabilities 0000800dh ro 8c?8fh ss subsystem id and subsystem vendor id 00008086h rwo 90?91h msi_capid message signaled interrupts capability id a005h ro 92?93h mc message control 0000h rw, ro 94?97h ma message address 00000000h ro, rw 98?99h md message data 0000h rw a0?a1h pe_capl pci express capability list 0010h ro a2?a3h pe_cap pci express ca pabilities 0142h ro, rwo a4?a7h dcap device capabilities 00008000h ro a8?a9h dctl device control 0000h rw, ro aa?abh dsts device status 0000h ro, rwc ac?afh lcap link capabilities 03214d02h ro, rwo b0?b1h lctl link control 0000h ro, rw, rw/sc b2?hb3 lsts link status 1000h rwc, ro b4?b7h slotcap slot capabilities 00040000h rwo, ro b8?b9h slotctl slot control 0000h ro, rw ba?bbh slotsts slot status 0000h ro, rwc bc?bdh rctl root control 0000h ro, rw c0?c3h rsts root status 00000000h ro, rwc ec?efh pelc pci express legacy control 00000000h ro, rw table 14. host-secondary pci ex press* bridge regi ster address map (d6:f0) (sheet 2 of 3) address offset register symbol register name default value access datasheet 231 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.1 vid1?vendor identification b/d/f/type: 0/6/0/pci address offset: 0?1h default value: 8086h access: ro size: 16 bits this register combined with the device identification regi ster uniquely identify any pci device. 100?103h vcech virtual channel enhanced capability header 14010002h ro 104?107h pvccap1 port vc capability register 1 00000000h ro 108?10bh pvccap2 port vc capability register 2 00000000h ro 10c?10dh pvcctl port vc control 0000h ro, rw 110?113h vc0rcap vc0 resource capability 00000000h ro 114?117h vc0rctl vc0 resource control 800000ffh ro, rw 11a?11bh vc0rsts vc0 resource status 0002h ro 140?143h rcldech root complex link declaration enhanced 00010005h ro 144?147h esd element self description 03000100h ro, rwo 150?153h le1d link entry 1 description 00000000h ro, rwo 158?15fh le1a link entry 1 address 0000000000 000000h ro, rwo table 14. host-secondary pci ex press* bridge regi ster address map (d6:f0) (sheet 3 of 3) address offset register symbol register name default value access bit access default value rst/ pwr description 15:0 ro 8086h core vendor identification (vid1): pci standard identification for intel. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 232 datasheet 8.2 did1?device identification b/d/f/type: 0/6/0/pci address offset: 2?3h default value: 29e9h access: ro size: 16 bits this register combined with the vendor iden tification register uniquely identifies any pci device. 8.3 pcicmd1?pci command b/d/f/type: 0/6/0/pci address offset: 4?5h default value: 0000h access: ro, rw size: 16 bits bit access default value rst/ pwr description 15:8 ro 29h core device identification number (did1(ub)): identifier assigned to the mch device #6 (virtual pci-to -pci bridge, pci express port). 7:4 ro eh core device identification number (did1(hw)): identifier assigned to the mch device #6 (virtual pci- to-pci bridge, pci express port). 3:0 ro 9h core device identification number (did1(lb)): identifier assigned to the mch device #6 (virtual pci-to -pci bridge, pci express port). bit access default value rst/ pwr description 15:11 ro 00h core reserved 10 rw 0b core inta assertion di sable (intaad): 0 = this device is perm itted to generate inta interrupt messages. 1 = this device is prevented from ge nerating interrupt messages. any inta emulation interrupts already asserted must be de-asserted when this bit is set. this bit only affects interrupts ge nerated by the device (pci inta from a pme event) controlled by th is command regist er. it does not affect upstream msis, upstream pc i inta-intd assert and de-assert messages. 9ro0bcore fast back-to-back enable (fb2b): not applicable or implemented. hardwired to 0. datasheet 233 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8rw0bcore serr# message enable (serre1): this bit controls device 6 serr# messaging. the mch communicates the serr# condition by sending a serr message to the ich. this bit, when set, enables reporting of non-fatal and fatal erro rs detected by the device to the root complex. note that errors are reported if enabled either through this bit or through the pci-express sp ecific bits in the device control register. 0 = the serr message is generated by the mch for device 6 only under conditions enabled individually through the device control register. 1 = the mch is enabled to generate serr messages which will be sent to the ich for specific devi ce 6 error conditions generated/ detected on the primary side of the virtual pci to pci bridge (not those received by the secondary side). the status of serrs generated is reported in the pcists1 register. 7 ro 0b core reserved 6rw0bcore parity error response enable (perre): controls whether or not the master data parity error bit in the pci status register can bet set. 0 = master data parity error bit in pci status register can not be set. 1 = master data parity error bit in pci status register can be set. 5:3 ro 0b core reserved 2rw0bcore bus master enable (bme): controls the ability of the pci express port to forward memory and i/o read /write requests in the upstream direction. 0 = this device is prevented from making memory or io requests to its primary bus. note that accord ing to pci specification, as msi interrupt messages are in-band me mory writes, disabling the bus master enable bit prevents th is device from generating msi interrupt messages or passing them from its secondary bus to its primary bus. upstream memory writes/reads, io writes/reads, peer writes/reads, and msis will all be treated as illegal cycles. writes are forwarded to memory address c0000h with byte enables de-asserted. reads will be forwarded to memory address c0000h and will return unsupported request status (or master abort) in its completion packet. 1 = this device is allowed to issu e requests to its primary bus. completions for previously issued memory read re quests on the primary bus will be issued when the data is available. this bit does not affect forwardi ng of completions from the primary interface to the se condary interface. 1rw0bcore memory access enable (mae): 0 = all of device #6's me mory space is disabled. 1 = enable the memory and pre-fetchable memory address ranges defined in the mbase1, mlimit1, pmbase1, and pmlimit1 registers. 0rw0bcore io access enable (ioae): 0 = all of device #6's i/o space is disabled. 1 = enable the i/o address range defined in the iobase1, and iolimit1 registers. bit access default value rst/ pwr description host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 234 datasheet 8.4 pcists1?pci status b/d/f/type: 0/6/0/pci address offset: 6?7h default value: 0010h access: ro, rwc size: 16 bits this register reports the occurrence of error conditions associated with primary side of the "virtual" host-pci express br idge embedded within the mch. bit access default value rst/ pwr description 15 ro 0b core detected parity error (dpe): not applicable or implemented. hardwired to 0. parity (generating poisoned transaction layer packets) is not supported on th e primary side of this device. 14 rwc 0b core signaled system error (sse): this bit is set when this device sends a serr due to detecting an err_ fatal or err_nonfatal condition and the serr enable bit in the comm and register is 1. both received (if enabled by bctrl1[1]) and intern ally detected error messages do not affect this field). 13 ro 0b core received master abort status (rmas): not applicable or implemented. hardwired to 0. the concept of a master abort does not exist on primary side of this device. 12 ro 0b core received target abort status (rtas): not applicable or implemented. hardwired to 0. the concept of a target abort does not exist on primary side of this device. 11 ro 0b core signaled target abort status (stas): not applicable or implemented. hardwired to 0. the concept of a target abort does not exist on primary side of this device. 10:9 ro 00b core devselb timing (devt): this device is not the subtractively decoded device on bus 0. this bit fi eld is therefore hardwired to 00 to indicate that the device uses the fastest possible decode. 8ro0bcore master data parity error (pmdpe): because the primary side of the pci express's virtual peer-to-peer bridge is inte grated with the mch functionality, there is no scenario where this bit will get set. because hardware will never set this bit, it is impossible for software to have an opportunity to clear this bit or otherwise test that it is implemented. the pci specification defines it as a r/wc, but for our implementation an ro de finition behaves the same way and will meet all microsoft test ing requirements. this bit can only be set when the parity error enable bit in the pci command register is set. 7ro0bcore fast back-to-back (fb2b): not applicable or implemented. hardwired to 0. 6 ro 0b core reserved 5ro0bcore 66/60mhz capabi lity (cap66): not applicable or implemented. hardwired to 0. 4ro1bcore capabilities list (capl): indicates that a capabili ties list is present. hardwired to 1. datasheet 235 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.5 rid1?revision identification b/d/f/type: 0/6/0/pci address offset: 8h default value: see description below access: ro size: 8 bits this register contains the revision number of the mch device 6. these bits are read only and writes to this register have no effect. 8.6 cc1?class code b/d/f/type: 0/6/0/pci address offset: 9?bh default value: 060400h access: ro size: 24 bits this register identifies the basic function of the device, a more specific sub-class, and a register-specific programming interface. 3ro0bcore inta status (intas): indicates that an interrupt message is pending internally to the device. only pme sources feed into this status bit (not pci inta-intd asse rt and de-assert messages). the inta assertion disable bit, pcicmd1[ 10], has no effect on this bit. 2:0 ro 000b core reserved bit access default value rst/ pwr description bit access default value rst/ pwr description 7:0 ro see description core revision identification number (rid1): this is an 8-bit value that indicates the revision identifi cation number for the mch device 0. refer to the intel ? 4 series chipset specification update for the value of this register. bit access default value rst/ pwr description 23:16 ro 06h core base class code (bcc): indicates the base class code for this device. this code has the value 06 h, indicating a bridge device. 15:8 ro 04h core sub-class code (subcc): indicates the sub-class code for this device. the code is 04h indi cating a pci to pci bridge. 7:0 ro 00h core programming interface (pi): indicates the programming interface of this device. this value does no t specify a particular register set layout and provides no practical use for this device. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 236 datasheet 8.7 cl1?cache line size b/d/f/type: 0/6/0/pci address offset: ch default value: 00h access: rw size: 8 bits 8.8 hdr1?header type b/d/f/type: 0/6/0/pci address offset: eh default value: 01h access: ro size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. 8.9 pbusn1?primary bus number b/d/f/type: 0/6/0/pci address offset: 18h default value: 00h access: ro size: 8 bits this register identifies that this "virtual" host-pci express bridge is connected to pci bus #0. bit access default value rst/ pwr description 7:0 rw 00h core cache line size (scratch pad): implemented by pci express devices as a read-write field for le gacy compatibility purposes but has no impact on any pci expr ess device functionality. bit access default value description 7:0 ro 01h core header type register (hdr): returns 01h to indicate that this is a single function device wi th bridge header layout. bit access default value rst/ pwr description 7:0 ro 00h core primary bus number (busn): configuration software typically programs this field with the number of the bus on the primary side of the bridge. since de vice #6 is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0. datasheet 237 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.10 sbusn1?secondary bus number b/d/f/type: 0/6/0/pci address offset: 19h default value: 00h access: rw size: 8 bits this register identifies the bus number assigned to the second bus side of the "virtual" bridge. this number is programmed by the pc i configuration software to allow mapping of configuration cycles to pci express. 8.11 subusn1?subordinate bus number b/d/f/type: 0/6/0/pci address offset: 1ah default value: 00h access: rw size: 8 bits this register identifies the subordinate bus (if any) that resides at the level below pci express. this number is programmed by the pci configuration software to allow mapping of configuration cycles to pci express. bit access default value rst/ pwr description 7:0 rw 00h core secondary bus number (busn): this field is programmed by configuration software with the bus number assigned to pci express. bit access default value rst/ pwr description 7:0 rw 00h core subordinate bus number (busn): this register is programmed by configuration software with the number of the highest subordinate bus that lies behind the device #6 bri dge. when only a single pci device resides on the pci express segment, this register will contain the same value as the sbusn1 register. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 238 datasheet 8.12 iobase1?i/o base address b/d/f/type: 0/6/0/pci address offset: 1ch default value: f0h access: ro, rw size: 8 bits this register controls the processor to pci express i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for the purpose of address decode address bits a[11:0] are treated as 0. thus the bottom of the defined i/o address range will be aligned to a 4 kb boundary. 8.13 iolimit1?i/o limit address b/d/f/type: 0/6/0/pci address offset: 1dh default value: 00h access: rw, ro size: 8 bits this register controls the processor to pci express i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for the purpose of address decode address bits a[11:0] are assumed to be fffh. thus, the to p of the defined i/o address range will be at the top of a 4 kb aligned address block. bit access default value rst/ pwr description 7:4 rw fh core i/o address base (iobase): this field corresponds to a[15:12] of the i/o addresses passed by bridge 1 to pci express. 3:0 ro 0h core reserved bit access default value rst/ pwr description 7:4 rw 0h core i/o address limit (iolimit): corresponds to a[15:12] of the i/o address limit of device #6. devi ces between this upper limit and iobase1 will be passed to the pci express hierarchy associated with this device. 3:0 ro 0h core reserved datasheet 239 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.14 ssts1?secondary status b/d/f/type: 0/6/0/pci address offset: 1e?1fh default value: 0000h access: ro, rwc size: 16 bits ssts1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side of the "virtual" pci-pci bridge embedded within mch. bit access default value rst/ pwr description 15 rwc 0b core detected parity error (dpe): this bit is set by the secondary side for a type 1 configuration space head er device whenever it receives a poisoned transaction layer packet, regardless of the state of the parity error response enable bit in the bridge control register. 14 rwc 0b core received system error (rse): this bit is set when the secondary side for a type 1 configuration sp ace header device receives an err_fatal or err_nonfatal. 13 rwc 0b core received master abort (rma): this bit is set when the secondary side for type 1 configuration spac e header device (for requests initiated by the type 1 header device itself) receives a completion with unsupported reques t completion status. 12 rwc 0b core received target abort (rta): this bit is set when the secondary side for type 1 configuration spac e header device (for requests initiated by the type 1 header device itself) receives a completion with completer abort completion status. 11 ro 0b core signaled target abort (sta): not applicable or implemented. hardwired to 0. the mch does not generate target aborts (the mch will never complete a request using the completer abort completion status). 10:9 ro 00b core devselb timing (devt): not applicable or implemented. hardwired to 0. 8rwc0bcore master data parity error (smdpe): when set, indicates that the mch received across the link (ups tream) a read data completion poisoned transaction layer packet (ep=1). this bit can only be set when the parity error enable bit in the bridge control register is set. 7ro0bcore fast back-to-back (fb2b): not applicable or implemented. hardwired to 0. 6 ro 0b core reserved 5ro0bcore 66/60 mhz capability (cap66): not applicable or implemented. hardwired to 0. 4:0 ro 00h core reserved host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 240 datasheet 8.15 mbase1?memory base address b/d/f/type: 0/6/0/pci address offset: 20?21h default value: fff0h access: rw, ro size: 16 bits this register controls the processor to pci express non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are re ad/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read- only and return zeroes when read. this regist er must be initialized by the configuration software. for the purpose of address decode address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. bit access default value rst/ pwr description 15:4 rw fffh core memory address base (mbase): corresponds to a[31:20] of the lower limit of the memory range that will be passed to pci express. 3:0 ro 0h core reserved datasheet 241 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.16 mlimit1?memory limit address b/d/f/type: 0/6/0/pci address offset: 22?23h default value: 0000h access: rw, ro size: 16 bits this register controls the processor to pci express non-prefetchable memory access routing based on the following formula: memory_base address memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read- only and return zeroes when read. this regist er must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note: memory range covered by mbase and mlimit registers are used to map non- prefetchable pci express address ranges (typically where control/status memory- mapped i/o data structures of the controll er will reside) and pmbase and pmlimit are used to map prefetchable address ranges (typically device local memory). this segregation allows application of uswc space attribute to be performed in a true plug- and-play manner to the prefetchable address range for improved processor- pci express memory access performance. note: configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the va lues that provide exclusive address ranges (i.e., prevent overlap with each other and/ or with the ranges covered with the main memory). there is no provision in the mch hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured. bit access default value rst/ pwr description 15:4 rw 000h core memory address limit (mlimit): corresponds to a[ 31:20] of the upper limit of the address range passed to pci express. 3:0 ro 0h core reserved host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 242 datasheet 8.17 pmbase1?prefetchable memory base address upper b/d/f/type: 0/6/0/pci address offset: 24?25h default value: fff1h access: rw, ro size: 16 bits this register in conjunction with the corresponding upper base address register controls the processor to pci express prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are re ad/write and correspond to address bits a[31:20] of the 40-bit address. the lower 8 bits of the upper base address register are read/write and correspond to address bits a[39:32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. bit access default value rst/ pwr description 15:4 rw fffh core prefetchable memory ba se address (mbase): corresponds to a[31:20] of the lower limit of the memory range that will be passed to pci express. 3:0 ro 1h core 64-bit address support: indicates that the upper 32 bits of the prefetchable memory region base address are contained in the prefetchable memory base u pper address register at 28h. datasheet 243 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.18 pmlimit1?prefetchable memory limit address b/d/f/type: 0/6/0/pci address offset: 26?27h default value: 0001h access: ro, rw size: 16 bits this register in conjunction with the corresponding upper limit address register controls the processor to pci express prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and corresp ond to address bits a[31:20] of the 40-bit address. the lower 8 bi ts of the upper limit address register are read/write and correspond to address bits a[39 :32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be f ffffh. thus, the top of the defined memory address range will be at the top of a 1 mb aligned memory block. note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that mu st be defined as uc and the ones that can be designated as a uswc (i.e., prefetchable) from the processor perspective. bit access default value rst/ pwr description 15:4 rw 000h core prefetchable memory address limit (pmlimit): this field corresponds to a[31:20] of the upper limit of th e address range passed to pci express. 3:0 ro 1h core 64-bit address support: this field indicates that the upper 32 bits of the prefetchable memory region limit address are contained in the prefetchable memory base limit address register at 2ch host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 244 datasheet 8.19 pmbaseu1?prefetchable memory base address upper b/d/f/type: 0/6/0/pci address offset: 28?2bh default value: 00000000h access: rw size: 32 bits the functionality associated with this register is present in the pci express design implementation. this register in conjunction with the corresponding upper base address register controls the processor to pci express prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are re ad/write and correspond to address bits a[31:20] of the 40-bit address. the lower 8 bits of the upper base address register are read/write and correspond to address bits a[39:32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1 mb boundary. bit access default value rst/ pwr description 31:0 rw 0000000 0h core prefetchable memory ba se address (mbaseu): this field corresponds to a[63:32] of the lo wer limit of the prefetchable memory range that will be passed to pci express. datasheet 245 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.20 pmlimitu1?prefetchable memory limit address upper b/d/f/type: 0/6/0/pci address offset: 2c?2fh default value: 00000000h access: rw size: 32 bits the functionality associated with this regi ster is present in the pci express design implementation. this register in conjunction with the corresponding upper limit address register controls the processor to pci express prefetchable memory access routing based on the following formula: prefetchable_memory_base address prefetchable_memory_limit the upper 12 bits of this register are read/write and corresp ond to address bits a[31:20] of the 40- bit address. the lower 8 bits of the upper limit address register are read/write and correspond to address bits a[39:32] of the 40-bit address. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1mb aligned memory block. note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as uc and the ones that can be designated as a uswc (i.e., prefetchable) from the processor perspective. bit access default value rst/ pwr description 31:0 rw 0000000 0h core prefetchable memory address limit (mlimitu): this field corresponds to a[63:32] of the uppe r limit of the prefetchable memory range that will be passed to pci express. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 246 datasheet 8.21 capptr1?capabilities pointer b/d/f/type: 0/6/0/pci address offset: 34h default value: 88h access: ro size: 8 bits the capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. 8.22 intrline1?interrupt line b/d/f/type: 0/6/0/pci address offset: 3ch default value: 00h access: rw size: 8 bits this register contains interrupt line routing information. the device itself does not use this value, rather it is used by device drivers and operating systems to determine priority and vector information. 8.23 intrpin1?interrupt pin b/d/f/type: 0/6/0/pci address offset: 3dh default value: 01h access: ro size: 8 bits this register specifies which interrupt pin this device uses. bit access default value rst/ pwr description 7:0 ro 88h core first capability (capptr1): the first capability in the list is the subsystem id and subsyste m vendor id capability. bit access default value rst/ pwr description 7:0 rw 00h core interrupt connect ion (intcon): used to communicate interrupt line routing information. bit access default value rst/ pwr description 7:0 ro 01h core interrupt pin (intpin): as a single function device, the pci express device specifies inta as its interrupt pin. 01h=inta. datasheet 247 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.24 bctrl1?bridge control b/d/f/type: 0/6/0/pci address offset: 3e?3fh default value: 0000h access: ro, rw size: 16 bits this register provides extensions to the pc icmd1 register that are specific to pci-pci bridges. the bctrl provides additional cont rol for the secondary interface as well as some bits that affect the overall behavior of the "virtual" host-pci express bridge embedded in the mch. bit access default value rst/ pwr description 15:12 ro 0h core reserved 11 ro 0b core discard timer serr# enable (dtserre): not applicable or implemented. hardwired to 0. 10 ro 0b core discard timer status (dtsts): not applicable or implemented. hardwired to 0. 9ro 0b core secondary discard timer (sdt): not applicable or implemented. hardwired to 0. 8ro 0b core primary discard timer (pdt): not applicable or implemented. hardwired to 0. 7ro 0b core fast back-to-back enable (fb2ben): not applicable or implemented. hardwired to 0. 6rw 0b core secondary bus reset (sreset): setting this bit triggers a hot reset on the corresponding pci expres s port. this will force the ltssm to transition to the hot reset state (via recovery) from l0 or l1 states. 5ro 0b core master abort mode (mamode): does not apply to pci express. hardwired to 0. 4rw 0b core vga 16-bit decode (vga16d): enables the pci-to-pci bridge to provide 16-bit decoding of vga i/o a ddress precluding the decoding of alias addresses every 1 kb. this bit on ly has meaning if bit 3 (vga enable) of this register is also set to 1, en abling vga i/o decoding and forwarding by the bridge. 0 = execute 10-bit address decodes on vga i/o accesses. 1 = execute 16-bit address decodes on vga i/o accesses. 3rw 0b core vga enable (vgaen): controls the routing of processor initiated transactions targeting vga compatib le i/o and memory address ranges. see the vgaen/mdap table in device 0, offset 97h[0]. 2rw 0b core isa enable (isaen): needed to exclude legacy resource decode to route isa resources to legacy decode path. modifies the response by the mch to an i/o access issued by the processor that target isa i/o addresses. this applies only to i/o addresses that ar e enabled by the iobase and iolimit registers. 0 = all addresses defined by the io base and iolimit for processor i/o transactions will be mapped to pci express. 1 = mch will not forward to pci expr ess any i/o transactions addressing the last 768 bytes in each 1 kb bloc k even if the addresses are within the range defined by the io base and iolimit registers. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 248 datasheet 8.25 pm_capid1?power management capabilities b/d/f/type: 0/6/0/pci address offset: 80?83h default value: c8039001h access: ro size: 32 bits 1rw 0b core serr enable (serren): 0 = no forwarding of error messages from secondary side to primary side that could result in an serr. 1 = err_cor, err_nonfatal, and err_fatal messages result in serr message when individually enable d by the root control register. 0rw 0b core parity error response enable (peren): controls whether or not the master data parity error bit in the se condary status regi ster is set when the mch receives across the link (upstream) a read data completion poisoned transaction layer packet. 0 = master data parity error bit in se condary status register can not be set. 1 = master data parity error bit in se condary status register can be set. bit access default value rst/ pwr description bit access default value rst/ pwr description 31:27 ro 19h core pme support (pmes): this field indicate s the power states in which this device may indicate pme wake via pci express messaging. d0, d3hot & d3cold. this device is not required to do anything to support d3hot and d3cold, it simply must report that those states are supported. refer to the pci power management 1.1 specificat ion for encoding explanation and other power management details. 26 ro 0b core d2 power state support (d2pss): hardwired to 0 to indicate that the d2 power management st ate is not supported. 25 ro 0b core d1 power state support (d1pss): hardwired to 0 to indicate that the d1 power management st ate is not supported. 24:22 ro 000b core auxiliary current (auxc): hardwired to 0 to indicate that there are no 3.3vaux auxiliary cu rrent requirements. 21 ro 0b core device specific initialization (dsi): hardwired to 0 to indicate that special initialization of this device is not required before generic class device driver is to use it. 20 ro 0b core auxiliary power source (aps): hardwired to 0. 19 ro 0b core pme clock (pmeclk): hardwired to 0 to indicate this device does not support pmeb generation. 18:16 ro 011b core pci pm cap version (pcipmcv): a value of 011b indicates that this function complies with pci power management in terface specification, revision 1.2 . 15:8 ro 90h core pointer to next capability (pnc): this contains a pointer to the next item in the capabilities list. if msich (capl[0] @ 7fh) is 0, then the next item in the capabilities list is the message signaled interrupts (msi) capability at 90h. 7:0 ro 01h core capability id (cid): value of 01h identifies this linked list item (capability structure) as being fo r pci power management registers. datasheet 249 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.26 pm_cs1?power management control/status b/d/f/type: 0/6/0/pci address offset: 84?87h default value: 00000008h access: ro, rw, rw/p size: 32 bits bit access default value rst/ pwr description 31:16 ro 0000h core reserved 15 ro 0b core pme status (pmests): this bit indicates that this device does not support pmeb generation from d3cold. 14:13 ro 00b core data scale (dscale): this field indicates that this device does not support the power management data register. 12:9 ro 0h core data select (dsel): this field indicates that this device does not support the power management data register. 8rw/p0bcore pme enable (pmee): this bit indicates that this device does not generate pmeb assert ion from any d-state. 0 = pmeb generation not possible from any d state 1 = pmeb generation enabled from any d state the setting of this bit ha s no effect on hardware. see pm_cap[15:11] 7:2 ro 0000b core reserved 1:0 rw 00b core power state (ps): this field indicates the cu rrent power state of this device and can be used to set the device into a new power state. if software attempts to wr ite an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no st ate change occurs. 00 = d0 01 = d1 (not supported in this device.) 10 = d2 (not supported in this device.) 11 = d3 support of d3cold does not require any special action. while in the d3hot state, this device can only act as the target of pci configuration transactions (for power management control). this device also cannot generate interru pts or respond to mmr cycles in the d3 state. the device must return to the d0 state in order to be fully-functional. when the power state is other than d0, the bri dge will master abort (i.e. not claim) any downstream cycles (with exception of type 0 config cycles). consequently, these unclaimed cycles will go down dmi and come back up as unsupported requests, which the mch logs as master aborts in device 0 pcists[13] there is no additional hardware func tionality required to support these power states. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 250 datasheet 8.27 ss_capid?subsystem id and vendor id capabilities b/d/f/type: 0/6/0/pci address offset: 88?8bh default value: 0000800dh access: ro size: 32 bits this capability is used to uniquely identify the subsystem where the pci device resides. because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. however, it is necessary because microsoft will test for its presence. 8.28 ss?subsystem id an d subsystem vendor id b/d/f/type: 0/6/0/pci address offset: 8c?8fh default value: 00008086h access: rwo size: 32 bits system bios can be used as the mechanism for loading the ssid/svid values. these values must be preserved through power management transitions and a hardware reset. bit access default value rst/ pwr description 31:16 ro 0000h core reserved 15:8 ro 80h core pointer to next capability (pnc): this field contains a pointer to the next item in the capabiliti es list which is the pci power management capability. 7:0 ro 0dh core capability id (cid): value of 0dh identifies this linked list item (capability structure) as being for ssid/ssvid registers in a pci-to- pci bridge. bit access default value rst/ pwr description 31:16 rwo 0000h core subsystem id (ssid): this bit identifies the particular subsystem and is assigned by the vendor. 15:0 rwo 8086h core subsystem vendor id (ssvid): this field identifies the manufacturer of the subsystem and is the same as the vendor id which is assigned by the pci special interest group. datasheet 251 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.29 msi_capid?message signaled interrupts capability id b/d/f/type: 0/6/0/pci address offset: 90?91h default value: a005h access: ro size: 16 bits when a device supports msi, it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. 8.30 mc?message control b/d/f/type: 0/6/0/pci address offset: 92?93h default value: 0000h access: rw, ro size: 16 bits system software can modify bits in this register, but the device is prohibited from doing so. if the device writes the same message mult iple times, only one of those messages is guaranteed to be serviced. if all of them must be serviced, the device must not generate the same message again until the driver services the earlier one. bit access default value rst/ pwr description 15:8 ro a0h core pointer to next ca pability (pnc): this field contains a pointer to the next item in the capabilities list which is the pci express capability. 7:0 ro 05h core capability id (cid): value of 05h identifies this linked list item (capability structure) as being for msi registers. bit access default value rst/ pwr description 15:8 ro 00h core reserved 7ro0bcore 64-bit address capable (64ac): hardwired to 0 to indicate that the function does not implement the upper 32 bits of the message address register and is incapable of generating a 64-bit memory address. 6:4 rw 000b core multiple message enable (mme): system software programs this field to indicate the actual number of messages allocated to this device. this number will be equal to or less than the number actually requested. the encoding is the same as for the mmc field below. 3:1 ro 000b core multiple message capable (mmc): system software reads this field to determine the number of messages being re quested by this device. the value of 000b equates to 1 message requested. 000 = 1 message requested all other encodings are reserved. 0rw0bcore msi enable (msien): controls the ability of this device to generate msis. 0 = msi will not be generated. 1 = msi will be generated when we receive pme messages. inta will not be generated and inta status (pcists1[3]) will not be set. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 252 datasheet 8.31 ma?message address b/d/f/type: 0/6/0/pci address offset: 94?97h default value: 00000000h access: ro, rw size: 32 bits 8.32 md?message data b/d/f/type: 0/6/0/pci address offset: 98?99h default value: 0000h access: rw size: 16 bits 8.33 pe_capl?pci express* capability list b/d/f/type: 0/6/0/pci address offset: a0?a1h default value: 0010h access: ro size: 16 bits this register enumerates the pci express capability structure. bit access default value rst/ pwr description 31:2 rw 0000000 0h core message address (ma): used by system software to assign an msi address to the device. the device handles an msi by writing the padded contents of the md register to this address. 1:0 ro 00b core force dword align (fdwa): hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary. bit access default value rst/ pwr description 15:0 rw 0000h core message data (md): base message data pattern assigned by system software and used to handle an msi from the device. when the device must generate an in terrupt request, it writes a 32-bit value to the memory address specif ied in the ma register. the upper 16-bits are always set to 0. the lower 16-bits are supplied by this register. bit access default value rst/ pwr description 15:8 ro 00h core pointer to next capability (pnc): this value terminates the capabilities list . the virtual channel capability and any other pci express specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within pci express extended configuration space. 7:0 ro 10h core capability id (cid): identifies this linked list item (capability structure) as being fo r pci express registers. datasheet 253 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.34 pe_cap?pci express* capabilities b/d/f/type: 0/6/0/pci address offset: a2?a3h default value: 0142h access: ro, rwo size: 16 bits this register indicates pci express device capabilities. 8.35 dcap?device capabilities b/d/f/type: 0/6/0/pci address offset: a4?a7h default value: 00008000h access: ro size: 32 bits this register indicates pci express device capabilities. bit access default value rst/ pwr description 15:14 ro 00b core reserved 13:9 ro 00h core interrupt message number (imn): not applicable or implemented. ha rdwired to 0. 8rwo1bcore slot implemented (si): 0 = the pci express link associated with this port is connected to an integrated component or is disabled. 1 = the pci express link associated with this port is connected to a slot. 7:4 ro 4h core device/port type (dpt): hardwired to 4h to indicate root port of pci express root complex. 3:0 ro 2h core pci express capability version (pciecv): hardwired to 2h to indicate compliance to the pci express capabili ties register expansion ecn. bit access default value rst/ pwr description 31:16 ro 0000h core reserved 15 ro 1b core role based error reporting (rber): this bit indicates that this device implements the functionalit y defined in the error reporting ecn as required by the pci express 1.1 specification. 14:6 ro 000h core reserved 5ro0bcore extended tag field supported (etfs): hardwired to indicate support for 5-bit tags as a requestor. 4:3 ro 00b core phantom functions supported (pfs): not applicable or implemented. ha rdwired to 0. 2:0 ro 000b core max payload size (mps): hardwired to indicate 128b max supported payload for transaction layer packets (tlp). host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 254 datasheet 8.36 dctl?device control b/d/f/type: 0/6/0/pci address offset: a8?a9h default value: 0000h access: rw, ro size: 16 bits this register provides control for pci express device specific capabilities. the error reporting enable bits are in refere nce to errors detected by this device, not error messages received across the link. th e reporting of error messages (err_corr, err_nonfatal, err_fatal) received by root port is controlled exclusively by root port command register. bit access default value rst/ pwr description 15:8 ro 0h core reserved 7:5 rw 000b core max payload size (mps): 000 = 128b max supported payload for transaction layer packets (tlp). as a receiver, the device must handle tlps as large as the set value; as transmitter, the device must not generate tlps exceeding the set value. all other encodings are reserved. hardware will actually ignore this fi eld. it is writeabl e only to support compliance testing. 4 ro 0b core reserved 3rw0bcore unsupported request reporting enable (urre): when set, this bit allows signaling err_nonfatal, err_fatal, or err_corr to the root control register when dete cting an unmasked unsupported request (ur). an err_corr is signaled when an unmasked advisory non-fatal ur is received. an err_fatal or err_nonfatal is sent to the root control register when an uncorrectable non-advisory ur is received with the severity bit set in the uncorrectable error severity register. 2rw0bcore fatal error reporting enable (fere): when set, this bit enables signaling of err_fatal to the root control register du e to internally detected errors or erro r messages received across the link. other bits also control the full scope of related error reporting. 1rw0bcore non-fatal error reporting enable (nere): when set, this bit enables signaling of err_nonfatal to the rool control register due to internally detected errors or error messages re ceived across the link. other bits also control the fu ll scope of related error reporting. 0rw0bcore correctable error reporting enable (cere): when set, this bit enables signaling of err_corr to th e root control register due to internally detected errors or error messages re ceived across the link. other bits also control the full scope of related error reporting. datasheet 255 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.37 dsts?device status b/d/f/type: 0/6/0/pci address offset: aa?abh default value: 0000h access: ro, rwc size: 16 bits this register reflects status corresponding to controls in the device control register. the error reporting bits are in reference to errors detected by this device, not errors messages received across the link. bit access default value rst/ pwr description 15:6 ro 000h core reserved 5ro0bcore transactions pending (tp): 0 = all pending transactions (including completions for any outstanding non-posted requests on any used virtual channel) have been completed. 1 = indicates that the device has transaction(s) pending (including completions for any outstanding non-posted requests for all used traffic classes). 4 ro 0b core reserved 3rwc0bcore unsupported request detected (urd): when set, this bit indicates that the device received an unsupported request. errors are logged in this register regardle ss of whether e rror reporting is enabled or not in the de vice control register. additionally, the non-fatal error detected bit or the fatal error detected bit is set according to the setting of the unsupported request error severity bit. in pr oduction systems setting the fatal error detected bit is not an option as support for aer will not be reported. 2rwc0bcore fatal error detected (fed): when set, this bit indicates that fatal error(s) were de tected. errors are logged in this register regardless of whether error repo rting is enabled or not in the device control register. when advanced error handli ng is enabled, errors are logged in this register regardless of the settings of the un correctable error mask register. 1rwc0bcore non-fatal error detected (nfed): when set, this bit indicates that non-fatal error(s) were detected. errors are lo gged in this register regardless of whether e rror reporting is enabled or not in the device control register. when advanced error handling is en abled, errors are logged in this register regardless of the settings of the un correctable error mask register. 0rwc0bcore correctable error detected (ced): when set, this bit indicates that correctable error( s) were detected. erro rs are logged in this register regardless of whether error reporting is enabled or not in the device control register. when advanced error handling is en abled, errors are logged in this register regardless of the settings of the correctable error mask register. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 256 datasheet 8.38 lcap?link capabilities b/d/f/type: 0/6/0/pci address offset: ac?afh default value: 03214d02h access: ro, rwo size: 32 bits this register indicates pci express device specific capabilities. bit access default value rst/ pwr description 31:24 ro 03h core port number (pn): this field indicates the pci express port number for the given pci express link. matches the value in element self description[31:24]. 23:22 ro 000b core reserved 21 ro 1b core link bandwidth notifi cation capability: a value of 1b indicates support for the link bandwidth no tification status and interrupt mechanisms. this capability is requ ired for all root ports and switch downstream ports supporting links wider than x1 and/or multiple link speeds. this field is not applicable and is reserved for endpoint devices, pci express to pci/pci-x bridges, an d upstream ports of switches. devices that do not implement the link bandwidth notification capability must hardwire this bit to 0b. 20 ro 0b core data link layer link active reporting capable (dlllarc): for a downstream port, this bit must be set to 1b if the component supports the optional capability of reporting the dl _active state of the data link control and management state machine. for upstream ports and components th at do not support this optional capability, this bit must be hardwired to 0b. 19 ro 0b core surprise down error reporting capable (sderc): for a downstream port, this bit must be set to 1b if the component supports the optional capability of detecting and reporting a surprise down error condition. for upstream ports and components th at do not support this optional capability, this bit must be hardwired to 0b. 18 ro 0b core clock power mana gement (cpm): a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) when the link is in the l1 and l2/3 ready link states. a value of 0b indicates the component does not have this capability and that reference clock(s) must not be removed in these link states. this capability is applicable only in form factors that support "clock request" (clkreq#) capability. for a multi-function de vice, each function indicates its capability independently. power management configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1b in this bit. 17:15 rwo 010b core l1 exit latency (l1elat): indicates the length of time this port requires to complete the transition from l1 to l0. the value 010 b indicates the range of 2 us to less than 4 us. both bytes of this register that cont ain a portion of this field must be written simultaneously in order to prevent an intermediate (and undesired) value from ever existing. datasheet 257 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.39 lctl?link control b/d/f/type: 0/6/0/pci address offset: b0?b1h default value: 0000h access: ro, rw, rw/sc size: 16 bits this register allows control of pci express link. 14:12 ro 100b core reserved 11:10 rwo 11b core active state link pm support (aslpms): the mch supports aspm l1. 9:4 ro 10h core max link width (mlw): indicates the maximum number of lanes supported for this link. 10h = x16 3:0 ro 2h core max link speed (mls): supported link speed - this field indicates the supported link speed(s) of the associated port. 0001b = 2.5gt/s link speed supported 0010b = 5.0gt/s and 2.5gt/s link speeds supported all other encodings are reserved. bit access default value rst/ pwr description bit access default value rst/ pwr description 15:12 ro 0000000b core reserved 11 rw 0b core link autonomous bandwidth interrupt enable: when set, this bit enables the generation of an interrupt to indicate that the link autonomous bandwidth status bit has been set. this bit is not applicable and is reserved for endpoint devices, pci express to pci/pci-x bridges, an d upstream ports of switches. devices that do not implement the link bandwidth notification capability must hardwi re this bit to 0b. 10 rw 0b core link bandwidth manageme nt interrupt enable: when set, this bit enables the generation of an interrupt to indicate that the link bandwidth management status bit has been set. this bit is not applicable and is reserved for endpoint devices, pci express to pci/pci-x bridges, an d upstream ports of switches. 9r0 0bcore hardware autonomous width disable: when set, this bit disables hardware from changing the link width for reasons other than attempting to correct unreliable link operation by reducing link width. devices that do not implement the ability autonomously to change link width are permitted to hardwire this bit to 0b. the mch does not support autonomo us width change. so, this bit is "ro". host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 258 datasheet 8ro 0bcore enable clock power management (ecpm): applicable only for form factors that support a "clock request" (clkreq#) mechanism, this enable functions as follows: 0 = clock power management is di sabled and device must hold clkreq# signal low 1 = the device is pe rmitted to use clkreq # signal to power manage link clock according to protocol defined in appropriate form factor specification. default value of this field is 0b. components that do not support clock power management (as indicated by a 0b value in the cl ock power management bit of the link capabilities register) mu st hardwire this bit to 0b. 7 rw 0b core reserved 6rw 0bcore common clock configuration (ccc): 0 = indicates that this component and the component at the opposite end of this link ar e operating with asynchronous reference clock. 1 = indicates that this component and the component at the opposite end of this link ar e operating with a distributed common reference clock. the state of this bit affects the n_fts value advertised during link training. 5rw/sc 0b core retrain link (rl): 0 = normal operation. 1 = full link retraining is initiated by directing the physical layer ltssm from l0 or l1 states to the recovery state. this bit always returns 0 when read. this bit is cleared automatically (no need to write a 0). it is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. if the ltssm is not already in recovery or configuration, the resulting link training must use the modified values. if the ltssm is already in recovery or configuration, the modified values are not required to affect the link training that's already in progress. 4rw 0bcore link disable (ld): 0 = normal operation. 1 = link is disabled. forces the ltssm to transition to the disabled state (via recovery) from l0 or l1 states. link retraining happens automatically on 0 to 1 transition, just like when coming out of reset. writes to this bit are immediatel y reflected in the value read from the bit, regardless of actual link state. 3ro 0bcore read completion boundary (rcb): hardwired to 0 to indicate 64 byte. 2 rw 0b core reserved 1:0 rw 00b core active state pm (aspm): controls the level of active state power management supported on the given link. 00 = disabled 01 = reserved 10 = reserved 11 = l1 entry supported bit access default value rst/ pwr description datasheet 259 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.40 lsts?link status b/d/f/type: 0/6/0/pci address offset: b2?b3h default value: 1000h access: rwc, ro size: 16 bits this register indicates pci express link status. bit access default value rst/ pwr description 15 rwc 0b core link autonomous bandwidth status (labws): this bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width, without the port transitioning through dl_down status, for reasons othe r than to attempt to correct unreliable link operation. this bit must be set if the physic al layer reports a speed or width change was initiated by the do wnstream component that was indicated as an autonomous change. 14 rwc 0b core link bandwidth management status (lbwms): this bit is set to 1b by hardware to indicate that either of the foll owing has occurred without the port transitioning through dl_down status: a link retraining initiated by a writ e of 1b to the retrain link bit has completed. note: this bit is set following any write of 1b to the retrain link bit, including when the link is in the process of retraining for some other reason. hardware has autonomously changed link speed or width to attempt to correct unreliable link operation, either through an ltssm timeout or a higher level process this bit must be set if the physic al layer reports a speed or width change was initiated by the down stream component that was not indicated as an autonomous change. 13 ro 0b core data link layer link active (optional) (dllla): this bit indicates the status of the data link control and management state machine. it returns a 1b to indicate the dl_active state, 0b otherwise. this bit must be impl emented if the correspon ding data link layer active capability bit is implemented. otherwis e, this bit must be hardwired to 0b. 12 ro 1b core slot clock configuration (scc): 0 = the device uses an independ ent clock irrespective of the presence of a refere nce on the connector. 1 = the device uses the same ph ysical reference clock that the platform provides on the connector. 11 ro 0b core link training (ltrn): this bit indicates that the physical layer ltssm is in the configuration or recovery state, or that 1b was written to the retrain link bit but link training has not yet begun. hardware clears this bit when the ltssm exits the configuration/ recovery state once link training is complete. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 260 datasheet 10 ro 0b core undefined: the value read from this bit is undefined. in previous versions of this specification, this bit was used to indicate a link training error. system software mu st ignore the value read from this bit. system software is permitte d to write any value to this bit. 9:4 ro 00h core negotiated link width (nlw): indicates negotiated link width. this field is valid only when the link is in the l0 or l1 states (after link width negotiation is successfully completed). 01h = x1 04h = ?x4 ? this is not a supporte d pcie gen2.0 link width. link width x4 is only valid when pcie gen1.1 i/o card is used in the secondary port. 08h = x8 ? this is not a supported pcie gen2.0 link width. link width x8 is only valid when pcie gen1.1 i/o card is used in the secondary port. 10h = x16 all other encodings are reserved. 3:0 ro 0h core current link speed (cls): this field indicates the negotiated link speed of the given pci express link. defined encodings are: 0001b = 5.0 gt/s pci express link 0010b = 5 gt/s pci express link all other encodings are reserved. the value in this field is undefined when the link is not up. bit access default value rst/ pwr description datasheet 261 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.41 slotcap?slot capabilities b/d/f/type: 0/6/0/pci address offset: b4?b7h default value: 00040000h access: rwo, ro size: 32 bits pci express slot related registers. bit access default value rst/ pwr description 31:19 rwo 0000h core physical slot number (psn): indicates the physical slot number attached to this port. 18 ro 1b core reserved 17 ro 0b core electromechanical interlock present (eip): when set to 1b, this bit indicates that an electromecha nical interlock is implemented on the chassis for this slot. 16:15 rwo 00b core slot power limit scale (spls): specifies the scale used for the slot power limit value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x if this field is written, the link sends a set_slot_power_limit message. 14:7 rwo 00h core slot power limit value (splv): in combination with the slot power limit scale value, specifies the uppe r limit on power supplied by slot. power limit (in watts) is calculated by multiplying the value in this field by the value in the slot power limit scale field. if this field is written, the link sends a set_slot_power_limit message. 6:5 ro 00b core reserved 4ro0bcore power indicator present (pip): when set to 1b, this bit indicates that a power indicator is electrically controlled by the chassis for this slot. 3ro0bcore attention indicator present (aip): when set to 1b, this bit indicates that an attention indicator is electrically controlled by the chassis. 2ro0bcore mrl sensor present (msp): when set to 1b, this bit indicates that an mrl sensor is implemented on the chassis for this slot. 1ro0bcore power controller present (pcp): when set to 1b, this bit indicates that a software programmable powe r controller is implemented for this slot/adapter (depending on form factor). 0ro0bcore attention button present (abp): when set to 1b, this bit indicates that an attention button for this slot is electrically controlled by the chassis. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 262 datasheet 8.42 slotctl?slot control b/d/f/type: 0/6/0/pci address offset: b8?b9h default value: 0000h access: ro, rw size: 16 bits pci express slot related registers. bit access default value rst/ pwr description 15:13 ro 000b core reserved 12 ro 0b core data link layer state changed enable (dllsce): if the data link layer link active capability is implemented, when set to 1b, this field enables software notification when data link layer link active field is changed. if the data link layer link active capability is not implemented, this bit is permitted to be read only with a value of 0b. 11 ro 0b core electromechanical inte rlock control (eic): if an electromechanical interlock is implemented, a write of 1b to this field causes the state of the interlock to toggle. a write of 0b to this field has no effect. a read to this register always returns a 0. 10 ro 0b core power controller control (pcc): if a power controller is implemented, this field when written sets the power state of the slot per the defined encodings. reads of this field must reflect the value from the latest write, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. depending on the form factor, the po wer is turned on/off either to the slot or within the adapter. note that in some cases the power controller may autonomously remove slot power or not respond to a power-up request based on a detected fault condition, independent of the power controller control setting. 0 = power on 1 = power off if the power controller implemente d field in the slot capabilities register is set to 0b, then writes to this field have no effect and the read value of this field is undefined. 9:8 ro 00b core power indicator control (pic): if a power indicator is implemented, writes to this field set the power indicator to the written state. reads of this field mu st reflect the value from the latest write, unless software issues a wr ite without waiting for the previous command to complete in which ca se the read valu e is undefined. 00 = reserved 01 = on 10 = blink 11 = off if the power indicator present bit in the slot capabilities register is 0b, this field is perm itted to be read-only with a value of 00b. datasheet 263 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 7:6 ro 00b core attention indicator control (aic): if an attention indicator is implemented, writes to this field set the attention indicator to the written state. reads of this field must reflect the value from the latest write, unless software issues a write without wa iting for the previous command to complete in which case the read value is undefined. if the indicator is electrically controlled by chassis, th e indicator is controlled directly by the downstream port through impl ementation specific mechanisms. 00 = reserved 01 = on 10 = blink 11 = off if the attention indicator present bit in the slot capabili ties register is 0b, this field is perm itted to be read only with a value of 00b. 5:4 ro 00b core reserved 3rw0bcore presence detect changed enable (pdce): when set to 1b, this bit enables software notification on a presence detect changed event. 2ro0bcore mrl sensor changed enable (msce): when set to 1b, this bit enables software notification on a mrl sensor changed event. default value of this field is 0b. if the mrl sensor present field in the slot capabilities register is set to 0b, this bit is perm itted to be read- only with a value of 0b. 1ro0bcore power fault detected enable (pfde): when set to 1b, this bit enables software notificati on on a power fault event. default value of this field is 0b . if power fault detection is not supported, this bit is permitted to be read-only with a value of 0b 0ro0bcore button pressed enable (abpe): when set to 1b, this bit enables software notification on an attention button pressed event. bit access default value rst/ pwr description host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 264 datasheet 8.43 slotsts?slot status b/d/f/type: 0/6/0/pci address offset: ba?bbh default value: 0000h access: ro, rwc size: 16 bits pci express slot related registers. bit access default value rst/ pwr description 15:7 ro 0000000b core reserved 6ro 0bcore presence detect state (pds): this bit indicates the presence of an adapter in the slot, reflected by the logical "or" of the physical layer in-band presence detect mech anism and, if present, any out- of-band presence de tect mechanism defi ned for the slot's corresponding form factor. note th at the in-band presence detect mechanism requires that power be applied to an adapter for its presence to be detected. 0 = slot empty 1 = card present in slot this register must be implemented on all do wnstream ports that implement slots. for downstream ports not connected to slots (where the slot implemented bit of the pci express capabilities register is 0b), this bit must return 1b. 5:4 ro 00b core reserved 3rwc 0b core detect changed (pdc): this bit is set when the value reported in presence detect state is changed. 2ro 0bcore mrl sensor changed (msc): if an mrl sensor is implemented, this bit is set when a mrl sensor state change is detected. if an mrl sensor is not implemented, this bit must not be set. 1ro 0bcore power fault detected (pfd): if a power controller that supports power fault detection is implemented, this bit is set when the power controller detects a power fault at this slot. note that, depending on hardware capability, it is possible that a power fault can be detected at any time, inde pendent of the power controller control setting or the occupanc y of the slot. if power fault detection is not supported, this bit must not be set. 0ro 0bcore attention button pressed (abp): if an attention button is implemented, this bit is set when the attent ion button is pressed. if an attention button is not su pported, this bit must not be set. datasheet 265 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.44 rctl?root control b/d/f/type: 0/6/0/pci address offset: bc?bdh default value: 0000h access: ro, rw size: 16 bits this register allows control of pci express root complex specific parameters. the system error control bits in this regist er determine if corresponding serrs are generated when our device detects an error (reported in this device's device status register) or when an error message is received across the link. reporting of serr as controlled by these bits takes precedence over the serr enable in the pci command register. bit access default value rst/ pwr description 15:4 ro 000h core reserved 3rw0bcore pme interrupt enable (pmeie): 0 = no interrupts are generated as a result of receiving pme messages. 1 = enables interrupt ge neration upon receipt of a pme message as reflected in the pme status bit of the root status register. a pme interrupt is also generated if the pme status bit of the root status register is set when this bit is set from a cleared state. 2rw0bcore system error on fatal error enable (sefee): this bit controls the root complex's response to fatal errors. 0 = no serr generated on receipt of fatal error. 1 = indicates that an serr should be generate d if a fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 1rw0bcore system error on non-fatal uncorrectable error enable (senfuee): this bit controls the root complex's response to non- fatal errors. 0 = no serr generated on re ceipt of non-fatal error. 1 = indicates that an serr should be generated if a non-fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. 0rw0bcore system error on correctable error enable (secee): this bit controls the root complex's re sponse to corr ectable errors. 0 = no serr generated on receipt of correctable error. 1 = indicates that an serr should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 266 datasheet 8.45 rsts?root status b/d/f/type: 0/6/0/pci address offset: c0?c3h default value: 00000000h access: ro, rwc size: 32 bits this register provides information about pci express root complex specific parameters. 8.46 pelc?pci express legacy control b/d/f/type: 0/6/0/pci address offset: ec?efh default value: 00000000h access: ro, rw size: 32 bits this register controls functionality that is needed by legacy (non-pci express aware) oss during run time. bit access default value rst/ pwr description 31:18 ro 0000h core reserved 17 ro 0b core pme pending (pmep): this bit indicates that another pme is pending when the pme status bit is set. when the pme status bit is cleared by software; the pme is deli vered by hardware by setting the pme status bit again and updating the requestor id appropriately. the pme pending bit is cleared by hardware if no more pmes are pending. 16 rwc 0b core pme status (pmes): this bit indicates that pme was asserted by the requestor id indicated in the pme requestor id field. subsequent pmes are kept pending unt il the status register is cleared by writing a 1 to this field. 15:0 ro 0000h core pme requestor id (pmerid): this field indicate s the pci requestor id of the last pme requestor. bit access default value rst/ pwr description 31:3 ro 0000000 0h core reserved 2rw0bcore pme gpe enable (pmegpe): 0 = do not generate gpe pme message when pme is received. 1 = generate a gpe pme message when pme is received (assert_pmegpe and deassert_pmegpe messages on dmi). this enables the mch to support pmes on the pci express port under legacy oss. 1 ro 0b core reserved 0rw0bcore general message gpe enable (gengpe): 0 = do not forward received gp e assert/de-asse rt messages. 1 = forward received gpe assert/d e-assert messages. these general gpe message can be received via the pci express port from an external intel device and will be subsequently forwarded to the ich (via assert_gpe and deas sert_gpe messages on dmi). datasheet 267 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.47 vcech?virtual channel enhanced capability header b/d/f/type: 0/6/0/mmr address offset: 100?103h default value: 14010002h access: ro size: 32 bits this register indicates pci express device virtual channel capabilities. extended capability structures for pci express devices are located in pci express extended configuration space and have different field definitions than standard pci capability structures. 8.48 pvccap1?port vc capability register 1 b/d/f/type: 0/6/0/mmr address offset: 104?107h default value: 00000000h access: ro size: 32 bits this register describes the configuration of pci express virtual channels associated with this port. bit access default value rst/ pwr description 31:20 ro 140h core pointer to next ca pability (pnc): the link declaration capability is the next in the pci express extended capabilities list. 19:16 ro 1h core pci express virtual channel ca pability version (pcievccv): hardwired to 1 to indicate compliances with the 1.1 version of the pci express specification. note: this version does not change for 2.0 compliance. 15:0 ro 0002h core extended capability id (ecid): value of 0002h identifies this linked list item (capability structur e) as being for pci express virtual channel registers. bit access default value rst/ pwr description 31:7 ro 00000h core reserved 6:4 ro 000b core low priority extended vc count (lpevcc): this field indicates the number of (extended) virtual channels in addition to the default vc belonging to the low-priority vc (lpvc) group that has the lowest priority with respect to other vc resources in a strict-priority vc arbitration. the value of 0 in this field implies strict vc arbitration. 3 ro 0b core reserved 2:0 ro 000b core extended vc count (evcc): this field indicates the number of (extended) virtual channels in addi tion to the default vc supported by the device. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 268 datasheet 8.49 pvccap2?port vc capability register 2 b/d/f/type: 0/6/0/mmr address offset: 108?10bh default value: 00000000h access: ro size: 32 bits this register describes the configuration of pci express virtual channels associated with this port. 8.50 pvcctl?port vc control b/d/f/type: 0/6/0/mmr address offset: 10c?10dh default value: 0000h access: ro, rw size: 16 bits bit access default value rst/ pwr description 31:24 ro 00h core vc arbitration tabl e offset (vcato): this field indicates the location of the vc arbitration table. this field contains the zero-based offset of the table in dqwords (16 bytes) from the base address of the virtual channel capability struct ure. a value of 0 indicates that the table is not present (due to fixed vc priority). 23:0 ro 0000h core reserved bit access default value rst/ pwr description 15:4 ro 000h core reserved 3:1 rw 000b core vc arbitration select (vcas): this field will be programmed by software to the only possible value as indicated in the vc arbitration capability field. since there is no other vc supported than the default, this field is reserved. 0 ro 0b core reserved datasheet 269 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.51 vc0rcap?vc0 resource capability b/d/f/type: 0/6/0/mmr address offset: 110?113h default value: 00000001h access: ro size: 32 bits bit access default value rst/ pwr description 31:16 ro 0000h core reserved 15 ro 0b core reject snoop transactions (rsnpt): 0 = transactions with or without the no snoop bit set within the transaction layer packet header are allowed on this vc. 1 = when set, any transaction for which the no snoop attribute is applicable but is not set within the tlp header will be rejected as an unsupported request. 14:8 ro 0000h core reserved 7:0 ro 01h core port arbitration capability: indicates types of port arbitration supported by the vc resource. this fi eld is valid for all switch ports, root ports that support peer-to-peer traffic, and rcrbs, but not for pci express endpoint devices or root ports that do not support peer to peer traffic. each bit location within this fiel d corresponds to a port arbitration capability defined below. when more th an one bit in this field is set, it indicates that the vc resource can be configured to provide different arbitration services. software selects among these capabi lities by writing to the port arbitration select field (see below). bit[0] = default = 01b; non-configurable hardware-fixed arbitration scheme, e.g., round robin (rr) bit[1] = weighted round robin (wrr) arbitration with 32 phases bit[2] = wrr arbitration with 64 phases bit[3] = wrr arbitration with 128 phases bit[4] = time-based wrr with 128 phases bit[5] = wrr arbitration with 256 phases bits[6:7] = reserved mch default indicates "non-configu rable hardware-fixed arbitration scheme". host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 270 datasheet 8.52 vc0rctl?vc0 resource control b/d/f/type: 0/6/0/mmr address offset: 114?117h default value: 800000ffh access: ro, rw size: 32 bits this register controls the resources associated with pci express virtual channel 0. bit access default value rst/ pwr description 31 ro 1b core vc0 enable (vc0e): for vc0, this is hardwired to 1 and read only as vc0 can never be disabled. 30:27 ro 0h core reserved 26:24 ro 000b core vc0 id (vc0id): this field assigns a vc id to the vc resource. for vc0 this is hardwired to 0 and read only. 23:20 ro 0000h core reserved 19:17 rw 000b core port arbitration select: this field configures the vc resource to provide a particular port arbitration service. this field is valid for rcrbs, root ports that support peer to peer traffic, and switch ports, but not for pci express endpoint devices or root ports that do not support peer to peer traffic. the permissible value of this field is a number corresponding to one of the asserted bits in the port arbi tration capability field of the vc resource. 16:8 ro 00h core reserved 7:1 rw 7fh core tc/vc0 map (tcvc0m): this field indicate s the tcs (traffic classes) that are mapped to the vc resource. bit locations within this field correspond to tc values. for ex ample, when bit 7 is set in this field, tc7 is mapped to this vc re source. when more than one bit in this field is set, it indicates that multiple tcs are mapped to the vc resource. to remove one or more tcs from the tc/vc map of an enabled vc, software must ensure that no new or outstanding transactions with the tc labels are targeted at the given link. 0ro1bcore tc0/vc0 map (tc0vc0m): traffic class 0 is always routed to vc0. datasheet 271 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.53 vc0rsts?vc0 resource status b/d/f/type: 0/6/0/mmr address offset: 11a?11bh default value: 0002h access: ro size: 16 bits this register reports the virtual channel specific status. 8.54 rcldech?root complex link declaration enhanced b/d/f/type: 0/6/0/mmr address offset: 140?143h default value: 00010005h access: ro size: 32 bits this capability declares links from this element (pci express) to other elements of the root complex component to which it belong s. see pci express specification for link/ topology declaration requirements. bit access default value rst/ pwr description 15:2 ro 0000h core reserved 1ro1bcore vc0 negotiation pending (vc0np): 0 = the vc negotiation is complete. 1 = the vc resource is still in the process of negotiation (initialization or disabling). this bit indicates the status of the process of flow control initialization. it is set by default on reset, as well as whenever the corresponding virtual channel is di sabled or the link is in the dl_down state. it is cleared when the link successfully exits the fc_init2 state. before using a virtual channel, so ftware must chec k whether the vc negotiation pending fields for that virtual channel are cleared in both components on a link. 0 ro 0b core reserved bit access default value rst/ pwr description 31:20 ro 000h core pointer to next ca pability (pnc): this is the last capability in the pci express extended capabiliti es list. 19:16 ro 1h core link declaration capa bility version (ldcv): hardwired to 1 to indicate compliances with the 1.1 version of the pci express specification. note: this version does not change for 2.0 compliance. 15:0 ro 0005h core extended capability id (ecid): value of 0005h identifies this linked list item (capability struct ure) as being for pci express link declaration capability. host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 272 datasheet 8.55 esd?element self description b/d/f/type: 0/6/0/mmr address offset: 144?147h default value: 03000100h access: ro, rwo size: 32 bits this register provides information about the root complex element containing this link declaration capability. 8.56 le1d?link entr y 1 description b/d/f/type: 0/6/0/mmr address offset: 150?153h default value: 00000000h access: ro, rwo size: 32 bits this register provides the first part of a link entry that declares an internal link to another root complex element. bit access default value rst/ pwr description 31:24 ro 03h core port number (pn): this field specifies the port number associated with this element with respect to the component that contains this element. this port number value is used by the egress port of the component to provide arbitration to this root complex element. 23:16 rwo 00h core component id (cid): this field indicates th e physical component that contains this root complex element. 15:8 ro 01h core number of link entries (nle): this field indica tes the number of link entries following the element self description. this field reports 1 (to egress port only as we don't repo rt any peer-to-peer capabilities in our topology). 7:4 ro 0h core reserved 3:0 ro 0h core element type (et): this field indicates configuration space element. bit access default value rst/ pwr description 31:24 ro 00h core target port number (tpn): this field specifie s the port number associated with the element targeted by this link entry (egress port). the target port number is with resp ect to the component that contains this element as specified by the target component id. 23:16 rwo 00h core target component id (tcid): this field identifies the physical or logical component that is targeted by this link entry. 15:2 ro 0000h core reserved 1ro0bcore link type (ltyp): this bit indicates that the link points to memory?mapped space (for rcrb). the link address specifies the 64- bit base address of the target rcrb. 0rwo0bcore link valid (lv): 0 = link entry is not valid and will be ignored. 1 = link entry specifies a valid link. datasheet 273 host-secondary pci express* bridge registers (d6:f0) (intel ? 82p45 mch only) 8.57 le1a?link entry 1 address b/d/f/type: 0/6/0/mmr address offset: 158?15fh default value: 0000000000000000h access: ro, rwo size: 64 bits this register provides the second part of a link entry that declares an internal link to another root complex element. bit access default value rst/ pwr description 63:32 ro 0000000 0h core reserved 31:12 rwo 00000h core link address (la): this field provides th e memory mapped base address of the rcrb that is the ta rget element (egress port) for this link entry. 11:0 ro 000h core reserved host-secondary pci express* br idge registers (d6:f0) (intel ? 82p45 mch only) 274 datasheet datasheet 275 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1 integrated graphics registers (d2:f0) device 2 contains registers for the internal graphics functions. table 15 lists the pci configuration registers in order of ascending offset address. function 0 can be vga compatible or not. this is selected through bit 1 of ggc register (device 0, offset 52h). note: the following sections describe device 2 pci configuration registers only. table 15. integrated graphics register address map (d2:f0) address offset register symbol register name default value access 0?1h vid2 vendor identification 8086h ro 2?3h did2 device identification see register description ro 4?5h pcicmd2 pci command 0000h ro, r/w 6?7h pcists2 pci status 0090h ro 8h rid2 revision identification see register description ro 9?bh cc class code 030000h ro ch cls cache line size 00h ro dh mlt2 master latency timer 00h ro eh hdr2 header type 80h ro 10?17h gttmmadr graphics translation table, memory mapped range address 000000000 0000004h r/w, ro 18?1fh gmadr graphics memory range address 000000000 000000ch r/w, ro, |r/w/l 20?23h iobar i/o base address 00000001h ro, r/w 2c?2dh svid2 subsystem vendor identification 0000h r/wo 2e?2fh sid2 subsystem identification 0000h r/wo 30?33h romadr video bios rom base address 00000000h ro 34h cappoint capabilities pointer 90h ro 3ch intrline interrupt line 00h r/w 3dh intrpin interrupt pin 01h ro 3eh mingnt minimum grant 00h ro integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 276 datasheet 3fh maxlat maximum latency 00h ro 40?4ch capid0 capability identifier 000000000 000000000 010c0009h ro 52?53h mggc gmch graphics control register 0030h ro 54?57h deven device enable 000023dbh ro 58?5bh ssrw software scratch read write 00000000h r/w 5c?5fh bsm base of stolen memory 07800000h ro 60?61h hsrw hardware scratch read write 0000h r/w 92?93h mc message control 0000h ro, r/w 94?97h ma message address 00000000h r/w, ro 98?99h md message data 0000h r/w c0h gdrst graphics debug reset 00h ro, r/w/sc, r/w d0?d1h pmcapid power management capabilities id 0001h r/wo, ro d2?d3h pmcap power management capabilities 0022h ro d4?d5h pmcs power management control/status 0000h ro, r/w e0?e1h swsmi software smi 0000h r/w table 15. integrated graphics register address map (d2:f0) address offset register symbol register name default value access datasheet 277 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1.1 vid2?vendor identification b/d/f/type: 0/2/0/pci address offset: 0-1h default value: 8086h access: ro size: 16 bits this register combined with the device identification register uniquely identifies any pci device. 9.1.2 did2?device identification b/d/f/type: 0/2/0/pci address offset: 2-3h default value: see description below access: ro size: 16 bits this register combined with the vendor identification register uniquely identifies any pci device. bit access default value rst/pwr description 15:0 ro 8086h core vendor identification number (vid): this field provides the pci standard identification for intel. bit access default value rst/pwr description 15:0 ro see description core device identification number (did): this field is an identifier assigned to the gm ch core/primary pci device. refer to the intel ? 4 series chipset family specification update for values in this register. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 278 datasheet 9.1.3 pcicmd2?pci command b/d/f/type: 0/2/0/pci address offset: 4-5h default value: 0000h access: ro, r/w size: 16 bits this 16-bit register provides basic control over the igd's ability to respond to pci cycles. the pcicmd register in the igd disables the igd pci compliant master accesses to main memory. bit access default value rst/pwr description 15:11 ro 00h core reserved 10 r/w 0b flr, core interrupt disable (intdis): this bit disabl es the device from asserting intx#. 0 = enable the assertion of this device's intx# signal. 1 = disable the assertion of this device's intx# signal. do_intx messages will not be sent to dmi. 9ro 0b core fast back-to-back (fb2b): not implemented. hardwired to 0. 8ro 0b core serr enable (serre): not implemented. hardwired to 0. 7ro 0b core address/data stepping enable (adstep): not implemented. hardwired to 0. 6ro 0b core parity error enable (perre): not implemented. hardwired to 0. since the igd belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the igd ignores any parity error that it detects and conti nues with normal operation. 5r o 0 b c o r e video palette snooping (vps): this bit is hardwired to 0 to disable snooping. 4r o 0 b c o r e memory write and invalidate enable (mwie): hardwired to 0. the igd does not support memory write and invalidate commands. 3r o 0 b c o r e special cycle enable (sce): this bit is hardwired to 0. the igd ignores special cycles. 2 r/w 0b flr, core bus master enable (bme): 0 = disable igd bus mastering. 1 = enable the igd to function as a pci compliant master. 1 r/w 0b flr, core memory access enable (mae): this bit controls the igd's response to memory space accesses. 0 = disable. 1 = enable. 0 r/w 0b flr, core i/o access enable (ioae): this bit controls the igd's response to i/o space accesses. 0 = disable. 1 = enable. datasheet 279 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1.4 pcists2?pci status b/d/f/type: 0/2/0/pci address offset: 6-7h default value: 0090h access: ro size: 16 bits pcists is a 16-bit status register that reports the occurrence of a pci compliant master abort and pci compliant target abort. pcists also indicates the devsel# ti ming that has been set by the igd. bit access default value rst/pwr description 15 ro 0b core detected parity error (dpe): since the igd does not detect parity, this bit is always hardwired to 0. 14 ro 0b core signaled system error (sse): the igd never asserts serr#, therefore this bit is hardwired to 0. 13 ro 0b core received master abort status (rmas): the igd never gets a master abort, therefor e this bit is hardwired to 0. 12 ro 0b core received target abort status (rtas): the igd never gets a target abort, therefore this bit is hardwired to 0. 11 ro 0b core signaled target ab ort status (stas): hardwired to 0. the igd does not use target abort semantics. 10:9 ro 00b core devsel timing (devt): n/a. these bits are hardwired to 00. 8r o 0 b c o r e master data parity error detected (dpd): since parity error response is hardwired to disabled (and the igd does not do any parity detection), this bit is hardwired to 0. 7r o 1 b c o r e fast back-to-back (fb2b): hardwired to 1. the igd accepts fast back-to-back when the transactions are not to the same agent. 6r o 0 b c o r e user defined format (udf): hardwired to 0. 5r o 0 b c o r e 66 mhz pci capable (66c): n/a - hardwired to 0. 4r o 1 b c o r e capability list (clist): this bit is set to 1 to indicate that the register at 34h pr ovides an offs et into the function's pci configuration space containing a pointer to the location of the fi rst item in the list. 3r o 0 b c o r e interrupt status (intsts): this bit reflects the state of the interrupt in the device . only when the interrupt disable bit in the command register is a 0 and this interrupt status bit is a 1, will the devices intx# signal be asserted. 2:0 ro 000b core reserved integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 280 datasheet 9.1.5 rid2?revision identification b/d/f/type: 0/2/0/pci address offset: 8h default value: see description below access: ro size: 8 bits this register contains the revision number for device 2, functions 0 and 1. 9.1.6 cc?class code b/d/f/type: 0/2/0/pci address offset: 9-bh default value: 030000h access: ro size: 24 bits this register contains the device programming interface information related to the sub- class code and base class code definition for the igd. this register also contains the base class code and the function sub-class in relation to the base class code. bit access default value rst/pwr description 7:0 ro see description core revision identification number (rid): this is an 8-bit value that indicates the revisi on identification number for the gmch device 0. refer to the intel ? 4 series chipset family specification update for the value of this register. bit access default value rst/ pwr description 23:16 ro 03h core base class code (bcc): this is an 8-bit value that indicates the base class code for the gmch. this code has the value 03h, indicating a display controller. when mchbar offset 44h, bit 31 is 0 this code has the value 03h, indicating a display controller. when mchbar offset 44, bit 31 is 1 this code has the value 04h, indicating a multimedia device. 15:8 ro 00h core sub-class code (subcc): when mchbar offset 44 bit 31 is 0 this value will be determined base d on device 0 ggc register, gms and ivd fields. 00h = vga compatible 80h = non vga (gms = "0000" or ivd = "1") when mchbar offset 44 bit 31 is 1 this value is 80h, indicating other multimedia device. 7:0 ro 00h core programming interface (pi): when mchbar offset 44, bit 31 is 0 this value is 00h, indicating a display controller. when mchbar offset 44, bit 31 is 1 this value is 00h, indicating a nop. datasheet 281 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1.7 cls?cache line size b/d/f/type: 0/2/0/pci address offset: ch default value: 00h access: ro size: 8 bits the igd does not support this register as a pci slave. 9.1.8 mlt2?master latency timer b/d/f/type: 0/2/0/pci address offset: dh default value: 00h access: ro size: 8 bits the igd does not support the programmability of the master latency timer because it does not perform bursts. 9.1.9 hdr2?header type b/d/f/type: 0/2/0/pci address offset: eh default value: 80h access: ro size: 8 bits this register contains the header type of the igd. bit access default value rst/pwr description 7:0 ro 00h core cache line size (cls): this field is hardwired to 0s. the igd as a pci compliant master does not use the memory write and invalidate command and, in general, does not perform operations based on cache line size. bit access default value rst/pwr description 7:0 ro 00h core master latency timer count value (mltcv): hardwired to 0s. bit access default value rst/pwr description 7ro 1b core multi function status (mfunc): this bit indicates if the device is a multi-function device. the value of this register is determined by device #0, offset 54h, deven[4]. if device 0 deven[4] is set, the mfunc bit is also set. 6:0 ro 00h core header code (h): this is a 7-bit value that indicates the header code for the igd. this code has the value 00h, indicating a type 0 configuration space format. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 282 datasheet 9.1.10 gttmmadr?graphics transl ation table, memory mapped range address b/d/f/type: 0/2/0/pci address offset: 10-17h default value: 0000000000000004h access: r/w, ro size: 64 bits this register requests allocation for combined graphics translation table modification range and memory mapped range. the space is 4 mb combined for mmio and global gtt table aperture (512 kb for mmio and 2 mb for gtt). gttadr will be at (gttmmadr + 2 mb) while the mmio base address will be the same as gttmmadr. for the global gtt, this range is defined as a memory bar in graphics device configuration space is an alias with which software is required to write values (ptes) into and may also read values from the global graphics translation table (gtt). ptes cannot be written directly into the global gtt memory area. the device snoops writes to this region in order to invalidate any cached translations within the various tlbs implemented on-chip. there are some exceptions to this. the allocation is for 4 mb and the base address is defined by bits [35:22]. bit access default value rst/pwr description 63:36 r/w 0000000h flr, core (mba): this field must be set to 0 since addressing above 64 gb is not supported. 35:22 r/w 0000h flr, core memory base a ddress (mba): this field is set by the os, these bits correspond to address signals [35:22]. 4 mb combined for mmio and global gtt table aperture (512 kb for mmio and 2 mb for gtt). 21:4 ro 00000h core reserved: hardwired to 0s to indicate at least 4 mb address range. 3ro 0b core prefetchable memory (prefmem): hardwired to 0 to prevent prefetching. 2:1 ro 10b core memory type (memtyp) : 00 = indicates 32 bit base address 01 = reserved 10 = indicates 64 bit base address 11 = reserved 0ro 0b core memory/io space (mios): hardwired to 0 to indicate memory space. datasheet 283 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1.11 gmadr?graphics memory range address b/d/f/type: 0/2/0/pci address offset: 18-1fh default value: 000000000000000ch access: r/w, ro, r/w/l size: 64 bits igd graphics memory base address is specified in this register. bit access default value rst/pwr description 63:36 r/w 0000000h flr, core memory base address (mba2): this field is set by the os, these bits correspond to address signals 63:36. 35:29 r/w 0000000b flr, core memory base address (mba): this field is set by the os, these bits correspond to address signals 35:29. 28 r/w/l 0b flr, core 512mb address ma sk (512admsk): this bit is either part of the memory base address (r/w) or part of the address mask (ro), depending on the value of msac[2:1]. see msac (device 2, function 0, offset 62h) for details. 27 r/w/l 0b flr, core 256 mb address mask (256admsk): this bit is either part of the memory base address (r/w) or part of the address mask (ro), depending on the value of msac[2:1]. see msac (device 2, function 0, offset 62h) for details. 26:4 ro 000000h core address mask (adm): hardwired to 0s to indicate at least 128 mb address range. 3r o 1 b c o r e prefetchable memory (prefmem): hardwired to 1 to enable prefetching. 2:1 ro 10b core memory type (memtyp): 00 = indicates 32-bit address. 10 = indicates 64-bit address 0r o 0 b c o r e memory/io space (mios): hardwired to 0 to indicate memory space. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 284 datasheet 9.1.12 iobar?i/o base address b/d/f/type: 0/2/0/pci address offset: 20-23h default value: 00000001h access: ro, r/w size: 32 bits this register provides the base offset of the i/o registers within device 2. bits 15:3 are programmable allowing the i/o base to be located anywhere in 16 bit i/o address space. bits 2:1 are fixed and return zero, bit 0 is hardwired to a 1 indicating that 8 bytes of i/o space are decoded. access to th e 8bs of i/o space is allowed in pm state d0 when io enable (pcicmd bit 0) set. access is disallowed in pm states d1?d3 or if io enable is clear or if device 2 is turned off or if internal graphics is disabled through the fuse or fuse override mechanisms. note that access to this io bar is independent of vga functionality within device 2. also, note that this mechanism is available only through function 0 of device 2 and is not duplicated in function 1. if accesses to this io bar is allowed then the gmch claims all 8, 16, or 32 bit i/o cycles from the processor that falls within the 8b claimed. 9.1.13 svid2?subsystem vendor identification b/d/f/type: 0/2/0/pci address offset: 2c-2dh default value: 0000h access: r/wo size: 16 bits bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:3 r/w 0000h flr, core io base address (iobase): this field is set by the os, these bits correspond to address signals 15:3. 2:1 ro 00b core memory type (memtype): hardwired to 0s to indicate 32-bit address. 0ro 1b core memory/io space (mios): hardwired to 1 to indicate i/o space. bit access default value rst/pwr description 15:0 r/wo 0000h core subsystem vendor id (subvid): this value is used to identify the vendor of the subsystem. this register should be programmed by bios during boot-up. once written, this register becomes read only. this register can only be cleared by a reset. datasheet 285 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1.14 sid2?subsystem identification b/d/f/type: 0/2/0/pci address offset: 2e-2fh default value: 0000h access: r/wo size: 16 bits 9.1.15 romadr?video bi os rom base address b/d/f/type: 0/2/0/pci address offset: 30-33h default value: 00000000h access: ro size: 32 bits the igd does not use a separate bios rom, therefore this register is hardwired to 0s. 9.1.16 cappoint?capabilities pointer b/d/f/type: 0/2/0/pci address offset: 34h default value: 90h access: ro size: 8 bits bit access default value rst/pwr description 15:0 r/wo 0000h core subsystem identification (subid): this value is used to identify a particular subs ystem. this field should be programmed by bios during boot-up. once written, this register becomes read only. this register can only be cleared by a reset. bit access default value rst/pwr description 31:18 ro 0000h core rom base address (rba): hardwired to 0s. 17:11 ro 00h core address mask (admsk): hardwired to 0s to indicate 256 kb address range. 10:1 ro 000h core reserved: hardwired to 0s. 0r o 0 b c o r e rom bios enable (rbe): 0 = rom not accessible. bit access default value rst/pwr description 7:0 ro 90h core capabilities pointer value (cpv): this field contains an offset into the function's pc i configuration space for the first item in the new capabi lities linked list, the msi capabilities id registers at address 90h, or the power management capability at d0h. this value is determined by the configuration in capl[0]. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 286 datasheet 9.1.17 intrline?interrupt line b/d/f/type: 0/2/0/pci address offset: 3ch default value: 00h access: r/w size: 8 bits 9.1.18 intrpin?interrupt pin b/d/f/type: 0/2/0/pci address offset: 3dh default value: 01h access: ro size: 8 bits 9.1.19 mingnt?minimum grant b/d/f/type: 0/2/0/pci address offset: 3eh default value: 00h access: ro size: 8 bits bit access default value rst/pwr description 7:0 r/w 00h core interrupt connection (intcon): this field is used to communicate interrupt line routing information. post software writes the routing information into this register as it initializes and configures the system. the value in this register indicates to which in put of the system interrupt controller the device's in terrupt pin is connected. bit access default value rst/pwr description 7:0 ro 01h core interrupt pin (intpin): as a single func tion device, the igd specifies inta# as its interrupt pin. 01h = inta#. bit access default value rst/pwr description 7:0 ro 00h core minimum grant value (mgv): the igd does not burst as a pci compliant master. datasheet 287 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1.20 maxlat?maximum latency b/d/f/type: 0/2/0/pci address offset: 3fh default value: 00h access: ro size: 8 bits 9.1.21 capid0?capability identifier b/d/f/type: 0/2/0/pci address offset: 40-4ch default value: 000000000000000000010c0009h access: ro size: 104 bits bios optimal default 0h this register control of bits in this register are only required for customer visible component differentiation. bit access default value rst/pwr description 7:0 ro 00h core maximum latency value (mlv): the igd has no specific requirements for how often it needs to access the pci bus. bit access default value rst/pwr description 103:28 ro 0000b core reserved 27:24 ro 1h core capid version (capidv): this field has the value 0001b to identify the first re vision of the capid register definition. 23:16 ro 0ch core capid length (capidl): this field has the value 0ch to indicate the structure length (12 bytes). 15:8 ro 00h core next capability pointer (ncp): this field is hardwired to 00h indicating the end of the capabilities linked list. 7:0 ro 09h core capability identifier (cap_id): this field has the value 1001b to identify the cap_id assigned by the pci sig for vendor dependent capability pointers. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 288 datasheet 9.1.22 mggc?gmch graphics control register b/d/f/type: 0/2/0/pci address offset: 52-53h default value: 0030h access: ro size: 16 bits note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/ pwr description 15:12 ro 0h core reserved 11:8 ro 0h core gtt graphics memo ry size (ggms): this field is used to select the amount of main memory that is pr e-allocated to support the internal graphics translation table. the bi os ensures that memory is pre- allocated only when intern al graphics is enabled. gsm is assumed to be a contiguous physical dram space with dsm, and bios needs to allocate a contiguous memory chunk. hardware will drive the base of gsm from dsm only using the gsm size programmed in the register. 0000 = no memory pre-allocated. 0001 = no vt mode, 1 mb of memory pre-allocated for gtt. 0011 = no vt mode, 2 mb of memory pre-allocated for gtt 1001 = vt mode, 2 mb of memory pre-allocated for 1 mb of global gtt and 1 mb for shadow gtt (82q45, 82q43 gmch only) 1010 = vt mode, 3 mb of memory pre-allocated for 1.5 mb of global gtt and 1.5 mb for shadow gtt (82q45 gmch only) 1011 vt mode, 4 mb of memory pre-allocated for 2 mb of global gtt and 2 mb for shadow gtt (82q45 gmch only) note: all unspecified encodings of this register field are reserved, hardware functionality is not assured if used . this register is locked and becomes read only when the d_lck bit in the smram register is set. datasheet 289 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 7:4 ro 0011b core graphics mode select (gms): this field is used to select the amount of main memory that is pr e-allocated to support the internal graphics device in vga (non-linear) and native (lin ear) modes. the bios ensures that memo ry is pre-allocated only when internal graphics is enabled. 0000 = no memory pre-allocated. device 2 (igd) does not claim vga cycles (memory and i/o), and the su b-class code fiel d within device 2, function 0 class co de register is 80h. 0001 = reserved 0010 =reserved 0011 =reserved 0100 =reserved 0101 =dvmt (uma) mode, 32 mb of memory pre-allocated for frame buffer. 0110 =dvmt (uma) mode, 48 mb of memory pre-allocated for frame buffer. 0111 =dvmt (uma) mode, 64 mb of memory pre-allocated for frame buffer. 1000 =dvmt (uma) mode, 128 mb of memory pre-allocated for frame buffer. 1001 =dvmt (uma) mode, 256 mb of memory pre-allocated for frame buffer. 1010 =dvmt (uma) mode, 96 mb of memory pre-allocated (0 + 96). 1011 =dvmt (uma) mode, 160 mb of memory pre-allocated (64 + 96). 1100 =dvmt (uma) mode, 224 mb of memory pre-allocated (128 + 96). 1101 =dvmt (uma) mode, 352 mb of memory pre-allocated (256 + 96). note: this register is locked and becomes read only when the d_lck bit in the smram register is set. hardware does not clear or set any of these bits automatically based on igd being disabled/enabled. bios requirement: bios must not set this field to 000 if ivd (bit 1 of this register) is 0. 3:2 ro 00b core reserved 1ro0bcore igd vga disable (ivd): 0 = enable. device 2 (igd) claims vga memory and i/o cycles, the sub-class code within device 2 class code register is 00h. 1 = disable. device 2 (igd) does not claim vga cycles (memory and i/o), and the sub- class code fi eld within device 2 function 0 class code register is 80h. bios requirement: bios must not set this bit to 0 if the gms field (bits 6:4 of this register) pre-allocates no memory. this bit must be set to 1 if device 2 is disabled ei ther via a fuse or fuse override (capid0[38] = 1) or via a register (deven[3] = 0). 0 ro 0b core reserved bit access default value rst/ pwr description integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 290 datasheet 9.1.23 deven?device enable b/d/f/type: 0/2/0/pci address offset: 54-57h default value: 000023dbh access: ro size: 32 bits this register allows for enabling/disabling of pci devices and functions that are within the gmch. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/ pwr description 31:15 ro 00000h core reserved 14 ro 0b core reserved 13 ro 1b core reserved 12:11 ro 00b core reserved (deven): 10 ro 0b core reserved (d3f4en): 9ro1bcore ep function 3 (d3f3en): 0 = bus 0, device 3, function 3 is disabled and hidden 1 = bus 0, device 3, function 3 is enabled and visible if device 3, function 0 is disa bled and hidden, then device 3, function 3 is also disabled an d hidden independent of the state of this bit. 8ro1bcore ep function 2 (d3f2en) : 0 = bus 0, device 3, function 2 is disabled and hidden 1 = bus 0, device 3, function 2 is enabled and visible if device 3, function 0 is disa bled and hidden, then device 3, function 2 is also disabled an d hidden independent of the state of this bit. 7ro1bcore ep function 1 (d3f1en): 0 = bus 0, device 3, functi on 1 is disabled and hidden 1 = bus 0, device 3, function 1 is enabled and visible. if this gmch does not have me capability (capid0[??] = 1), then device 3, function 1 is disabl ed and hidden independent of the state of this bit. 6ro1bcore ep function 0 (d3f0en): 0 = bus 0, device 3, function 0 is disabled and hidden 1 = bus 0, device 3, function 0 is enabled and visible. if this gmch does not have me capability (capid0[??] = 1) then device 3, function 0 is disabl ed and hidden independent of the state of this bit. 5 ro 0b core reserved datasheet 291 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 4ro1bcore internal graphics engine function 1 (d2f1en): 0 = bus 0, device 2, functi on 1 is disabled and hidden 1 = bus 0, device 2, function 1 is enabled and visible if device 2, function 0 is disabled and hi dden, then device 2, function 1 is also disabled and hidden independen t of the state of this bit. if this component is not capabl e of dual independent display (capid0[78] = 1), then this bit is hardwired to 0b to hide device 2, function 1. 3ro1bcore internal graphics engine function 0 (d2f0en): 0 = bus 0, device 2, functi on 0 is disabled and hidden 1 = bus 0, device 2, function 0 is enabled and visible if this gmch does not have internal graphics capability (capid0[46] = 1), then device 2, function 0 is disabled and hidden independent of th e state of this bit. 2 ro 0b core reserved 1ro1bcore pci express port (d1en): 0 = bus 0, device 1, function 0 is disabled and hidden. 1 = bus 0, device 1, function 0 is enabled and visible. default value is determined by the device capabilities (see capid0[44]), sdvo presence hardware strap and the sdvo/ pcie concurrent hardware strap. de vice 1 is disabled on reset if the sdvo presence strap was sa mpled high, and the sdvo/pcie concurrent strap was sampled low at the last assertion of pwrok, and is enabled by default otherwise. 0ro1bcore host bridge (d0en): bus 0, device 0, function 0 may not be disabled and is therefore hardwired to 1. bit access default value rst/ pwr description integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 292 datasheet 9.1.24 ssrw?software scratch read write b/d/f/type: 0/2/0/pci address offset: 58-5bh default value: 00000000h access: r/w size: 32 bits 9.1.25 bsm?base of stolen memory b/d/f/type: 0/2/0/pci address offset: 5c-5fh default value: 07800000h access: ro size: 32 bits graphics stolen memory and tseg are within dram space defined under tolud. from the top of low used dram, gmch claims 1 to 64 mb of dram for internal graphics if enabled. the base of stolen memory will always be below 4 gb. this is required to prevent aliasing between stolen range and the reclaim region. 9.1.26 hsrw?hardware scratch read write b/d/f/type: 0/2/0/pci address offset: 60-61h default value: 0000h access: r/w size: 16 bits bit access default value rst/pwr description 31:0 r/w 00000000h flr, core reserved bit access default value rst/pwr description 31:20 ro 078h core base of stolen memory (bsm): this register contains bits 31:20 of the base addr ess of stolen dram memory. the host interface determines the base of graphics stolen memory by subtracting the gr aphics stolen memory size from tolud. see device 0 tolud for more explanation. 19:0 ro 00000h core reserved bit access default value rst/pwr description 15:0 r/w 0000h flr, core reserved datasheet 293 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1.27 mc?message control b/d/f/type: 0/2/0/pci address offset: 92-93h default value: 0000h access: ro, r/w size: 16 bits system software can modify bits in this register, but the device is prohibited from doing so. if the device writes the same message multiple times, only one of those messages is assured to be serviced. if all of them mu st be serviced, the device must not generate the same message again until the driver services the earlier one. 9.1.28 ma?message address b/d/f/type: 0/2/0/pci address offset: 94-97h default value: 00000000h access: r/w, ro size: 32 bits bit access default value rst/pwr description 15:8 ro 00h core reserved 7ro 0b core 64 bit capable (64bcap): hardwired to 0 to indicate that the function does not implement the upper 32 bits of the message address regist er and is incapable of generating a 64-bit memory address. this may need to change in future implementations when addressable system memory exceeds the 32b/4 gb limit. 6:4 r/w 000b flr, core multiple message enable (mme): system software programs this field to indi cate the actual number of messages allocated to this device. this number will be equal to or less than the number actually requested. the encoding is the same as for the mmc field below. 3:1 ro 000b core multiple message capable (mmc): system software reads this field to determin e the number of messages being requested by this device. 000 = 1 all other encodings are reserved. 0r/w 0bflr, core msi enable (msien): this bit controls the ability of this device to generate msis. bit access default value rst/pwr description 31:2 r/w 00000000h flr, core message address (messadd): this field is used by system software to assign an msi address to the device. the device handles an msi by writing the padded contents of the md register to this address. 1:0 ro 00b core force dword align (fdword): hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 294 datasheet 9.1.29 md?message data b/d/f/type: 0/2/0/pci address offset: 98-99h default value: 0000h access: r/w size: 16 bits 9.1.30 gdrst?graphi cs debug reset b/d/f/type: 0/2/0/pci address offset: c0h default value: 00h access: ro, r/w/sc, r/w size: 8 bits bit access default value rst/pwr description 15:0 r/w 0000h flr, core message data (messdata): this is the base message data pattern assigned by sy stem software and used to handle an msi from the device. when the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the ma register. the upper 16 bits are always set to 0. the lower 16 bits are supplie d by this register. bit access default value rst/pwr description 7:4 ro 0h flr, core reserved 3:2 r/w 00b flr, core graphics reset domain (grdom): 00 = full graphics reset will be performed (both render and display clock doma in resets asserted) 01 = render only reset (r ender clock domain reset asserted) 10 = reserved (invalid programming) 11 = media only reset (media domain reset get asserted) 1 ro 0b flr, core reserved 0 r/w/sc 0b flr, core graphics reset enable (gr): setting this bit asserts graphics-only reset. the clock domains to be reset are determined by grdom. hardware resets this bit when the reset is complete. setting this bit without waiting for it to clear, is undefined behavior. once this bit is set to a 1, all gfx core mmio registers are returned to power on default st ate. all ring buffer pointers are reset, command stream fetches are dropped and ongoing render pipeline pr ocessing is halted, state machines and state variables re turned to power on default state. if the display is reset, all display engines are halted (garbage on screen). vga memo ry is not available, store dwords and interrupts are no t ensured to be completed. device 2 i/o registers are not available. device 2 configuration register s continue to be available while graphics re set is asserted. this bit is hardwired auto-clear. datasheet 295 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.1.31 pmcapid?power mana gement capabilities id b/d/f/type: 0/2/0/pci address offset: d0-d1h default value: 0001h access: r/wo, ro size: 16 bits 9.1.32 pmcap?power management capabilities b/d/f/type: 0/2/0/pci address offset: d2-d3h default value: 0022h access: ro size: 16 bits this register is a mirror of function 0 with the same read/write attributes. the hardware implements a single physical register common to both functions 0 and 1. bit access default value rst/pwr description 15:8 r/wo 00h core next capability pointer (next_ptr): this field contains a pointer to the next item in the capabilities list. bios is responsible for writin g this to the flr capability when applicable. 7:0 ro 01h core capability identifier (cap_id): sig defines this id is 01h for power management. bit access default value rst/pwr description 15:11 ro 00h core pme support (pmes): this field indicates the power states in which the igd may assert pme#. hardwired to 0 to indicate that the igd does not assert th e pme# signal. 10 ro 0b core d2 support (d2): the d2 power management state is not supported. this bit is hardwired to 0. 9ro 0b core d1 support (d1): hardwired to 0 to indicate that the d1 power management state is not supported. 8:6 ro 000b core reserved 5ro 1b core device specific initialization (dsi): hardwired to 1 to indicate that special initialization of the igd is required before generic class device driver is to use it. 4 ro 0b core reserved 3ro 0b core pme clock (pmeclk): hardwired to 0 to indicate igd does not support pme# generation. 2:0 ro 010b core version (ver): hardwired to 010b to indicate that there are 4 bytes of power manage ment register s implemented and that this device complies with the pci power management interfa ce specification, revision 1.1 . integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 296 datasheet 9.1.33 pmcs?power management control/status b/d/f/type: 0/2/0/pci address offset: d4-d5h default value: 0000h access: ro, r/w size: 16 bits 9.1.34 swsmi?software smi b/d/f/type: 0/2/0/pci address offset: e0-e1h default value: 0000h access: r/w size: 16 bits as long as there is the potential that dvo port legacy drivers exist which expect this register at this address, device 2, functi on 0 address e0h?e1h must be reserved for this register. bit access default value rst/ pwr description 15 ro 0b core pme status (pmests): this bit is 0 to indicate that igd does not support pme# generation from d3 (cold). 14:13 ro 00b core data scale (dscale): the igd does not support data register. this bit always returns 00 when read, write operations have no effect. 12:9 ro 0h core data select (dsel): the igd does not support data register. this bit always returns 0h when read, write operat ions have no effect. 8ro 0b core pme enable (pme_en): this bit is 0 to indicate that pme# assertion from d3 (cold) is disabled. 7:2 ro 00h core reserved 1:0 r/w 00b flr, core power state (pwrstat): this field indicate s the current power state of the igd and can be used to set the igd into a new power state. if software attempts to write an unsupported state to this field, write operation must comple te normally on the bus, but the data is discarded and no state ch ange occurs. on a transition from d3 to d0 the graphics controller is optionally reset to initial values. 00 = d0 (default) 01 = d1 (not supported) 10 = d2 (not supported) 11 = d3 bit access default value rst/pwr description 15:8 r/w 00h core software scratch bits (swsb): 7:1 r/w 00h core software flag (swf): this field is used to indicate caller and smi function desired, as well as return result. 0r/w 0b core gmch software smi event (gssmie): when set, this bit will trigger an smi. soft ware must write a 0 to clear this bit. datasheet 297 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.2 integrated graphics registers (d2:f1) table 16. pci register address map (d2:f1) address offset register symbol register name default value access 0?1h vid2 vendor identification 8086h ro 2?3h did2 device identification see register description ro 4?5h pcicmd2 pci command 0000h ro, r/w 6?7h pcists2 pci status 0090h ro 8h rid2 revision identification see register description ro 9?bh cc class code register 038000h ro ch cls cache line size 00h ro dh mlt2 master latency timer 00h ro eh hdr2 header type 80h ro 10?17h mmadr memory mapped range address 0000000000 000004h r/w, ro 2c?2dh svid2 subsystem vendor identification 0000h ro 2e?2fh sid2 subsystem identification 0000h ro 30?33h romadr video bios rom base address 00000000h ro 34h cappoint capabilities pointer d0h ro 3eh mingnt minimum grant 00h ro 3fh maxlat maximum latency 00h ro 40?4ch capid0 mirror of dev0 capability identifier 0000000000 0000000001 0c0009h ro 52?53h mggc mirror of device 0 gmch graphics control register 0030h ro 54?57h deven device enable 000023dbh ro 58?5bh ssrw mirror of function 0 software scratch read write 00000000h ro 5c?5fh bsm mirror of function 0 base of stolen memory 07800000h ro 60?61h hsrw mirror of device 2 function 0 hardware scratch read write 0000h ro c0h gdrst mirror of device 2 function 0 graphics reset 00h ro d0?d1h pmcapid mirror of function 0 power management capabilities id 0001h r/wo, ro d2?d3h pmcap mirror of function 0 power management capabilities 0022h ro d4?d5h pmcs power management control/status 0000h ro, r/w d8?dbh ? reserved 00000000h ro e0?e1h swsmi mirror of func0 software smi 0000h ro integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 298 datasheet 9.2.1 vid2?vendor identification b/d/f/type: 0/2/1/pci address offset: 0-1h default value: 8086h access: ro size: 16 bits this register combined with the device identification register uniquely identifies any pci device. 9.2.2 did2?device identification b/d/f/type: 0/2/1/pci address offset: 2-3h default value: see description below access: ro size: 16 bits this register is unique in function 1 (the function 0 did is separate). this difference in device id is necessary for allowing distinct plug and play enumeration of function 1 when both function 0 and function 1 have the same class code. bit access default value rst/pwr description 15:0 ro 8086h core vendor identification number (vid): pci standard identification for intel. bit access default value rst/pwr description 15:0 ro see description core device identification number (did): identifier assigned to the gmch core/primary pci device. refer to the intel ? 4 series chipset family specification update for values in this register. datasheet 299 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.2.3 pcicmd2?pci command b/d/f/type: 0/2/1/pci address offset: 4-5h default value: 0000h access: ro, r/w size: 16 bits this 16-bit register provides basic control over the igd's ability to respond to pci cycles. the pcicmd register in the igd disables the igd pci compliant master accesses to main memory. bit access default value rst/pwr description 15:10 ro 00h core reserved 9ro 0b core fast back-to-back (fb2b): not implemented. hardwired to 0. 8ro 0b core serr enable (serre): not implemented. hardwired to 0. 7ro 0b core address/data stepping enable (adstep): not implemented. hardwired to 0. 6ro 0b core parity error enable (perre): not implemented. hardwired to 0. since the igd belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the igd ignores any parity error that it detects and contin ues with normal operation. 5ro 0b core vga palette snoop enable (vgasnoop): this bit is hardwired to 0 to disable snooping. 4ro 0b core memory write and invalidate enable (mwie): hardwired to 0. the igd does not support memory write and invalidate commands. 3ro 0b core special cycle enable (sce): this bit is hardwired to 0. the igd ignores special cycles. 2r/w 0bflr, core bus master enable (bme): 0 = disable igd bus mastering. 1 = enable the igd to function as a pci compliant master. 1r/w 0bflr, core memory access enable (mae): this bit controls the igd's response to memory space accesses. 0 = disable. 1 = enable. 0r/w 0bflr, core i/o access enable (ioae): this bit controls the igd's response to i/o space accesses. 0 = disable. 1 = enable. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 300 datasheet 9.2.4 pcists2?pci status b/d/f/type: 0/2/1/pci address offset: 6-7h default value: 0090h access: ro size: 16 bits pcists is a 16-bit status register that reports the occurrence of a pci compliant master abort and pci compliant target abort. pcists also indicates the devsel# timing that has been set by the igd. bit access default value rst/pwr description 15 ro 0b core detected parity error (dpe): since the igd does not detect parity, this bit is always hardwired to 0. 14 ro 0b core signaled system error (sse): the igd never asserts serr#, therefore this bit is hardwired to 0. 13 ro 0b core received master abort status (rmas): the igd never gets a master abort, therefore this bit is hardwired to 0. 12 ro 0b core received target abort status (rtas): the igd never gets a target abort, therefor e this bit is hardwired to 0. 11 ro 0b core signaled target ab ort status (stas): hardwired to 0. the igd does not use target abort semantics. 10:9 ro 00b core devsel timing (devt): n/a. these bits are hardwired to "00". 8r o 0 b c o r e master data parity error detected (dpd): since parity error response is hardwired to disabled (and the igd does not do any parity de tection), this bit is hardwired to 0. 7r o 1 b c o r e fast back-to-back (fb2b): hardwired to 1. the igd accepts fast back-to-back when the transactions are not to the same agent. 6r o 0 b c o r e user defined format (udf): hardwired to 0. 5r o 0 b c o r e 66 mhz pci capable (66c): n/a - hardwired to 0. 4r o 1 b c o r e capability list (clist): this bit is set to 1 to indicate that the register at 34h pr ovides an offset into the function's pci configuration space containing a pointer to the location of the first item in the list. 3r o 0 b c o r e interrupt status (intsts): hardwired to 0. 2:0 ro 000b core reserved datasheet 301 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.2.5 rid2?revision identification b/d/f/type: 0/2/1/pci address offset: 8h default value: see description below access: ro size: 8 bits this register contains the revision number for device #2 functions 0 and 1 9.2.6 cc?class code register b/d/f/type: 0/2/1/pci address offset: 9-bh default value: 038000h access: ro size: 24 bits this register contains the device programming interface information related to the sub- class code and base class code definition for the igd. this register also contains the base class code and the function sub-class in relation to the base class code. bit access default value rst/pwr description 7:0 ro see description core revision identification number (rid): this is an 8-bit value that indicates the revisi on identification number for the gmch device 0. refer to the intel ? 4 series chipset family specification update for the value of this register. bit access default value rst/pwr description 23:16 ro 03h core base class code (bcc): this is an 8-bit value that indicates the base class code for the gmch. this code has the value 03h, indicating a display controller. when mchbar offset 44h, bit 31 is 0 this code has the value 03h, indicating a display controller. when mchbar offset 44h, bit 31 is 1 this code has the value 04h, indicating a multimedia device. 15:8 ro 80h core sub-class code (subcc): when mchbar offset 44, bit 31 is 0 this value 80h, indicating non vga. when mchbar offset 44h, bit 31 is 1 this value is 80h, indicating other multimedia device. 7:0 ro 00h core programming interface (pi): when mchbar offset 44h, bit 31 is 0 this value is 00h, indicating a display controller. when mchbar offset 44h, bit 31 is 1 this value is 00h, indicating a nop. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 302 datasheet 9.2.7 cls?cache line size b/d/f/type: 0/2/1/pci address offset: ch default value: 00h access: ro size: 8 bits the igd does not support this register as a pci slave. 9.2.8 mlt2?master latency timer b/d/f/type: 0/2/1/pci address offset: dh default value: 00h access: ro size: 8 bits the igd does not support the programmability of the master latency timer because it does not perform bursts. 9.2.9 hdr2?header type b/d/f/type: 0/2/1/pci address offset: eh default value: 80h access: ro size: 8 bits this register contains the header type of the igd. bit access default value rst/pwr description 7:0 ro 00h core cache line size (cls): this field is hardwired to 0s. the igd as a pci compliant master does not use the memory write and invalidate command and, in general, does not perform operations base d on cache line size. bit access default value rst/pwr description 7:0 ro 00h core master latency timer count value (mltcv): hardwired to 0s. bit access default value rst/pwr description 7ro 1b core multi function status (mfunc): this bit indicates if the device is a multi-function device. the value of this register is determined by device 0, offset 54h, deven[4]. if device 0 deven[4] is set, the mfunc bit is also set. 6:0 ro 00h core header code (h): this is an 7-bit value that indicates the header code for the igd. th is code has the value 00h, indicating a type 0 configuration space format. datasheet 303 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.2.10 mmadr?memory mapped range address b/d/f/type: 0/2/1/pci address offset: 10-17h default value: 0000000000000004h access: r/w, ro size: 64 bits this register requests allocation for the igd registers and instruction ports. the allocation is for 512 kb and the base address is defined by bits [31:19]. 9.2.11 svid2?subsystem vendor identification b/d/f/type: 0/2/1/pci address offset: 2c-2dh default value: 0000h access: ro size: 16 bits bit access default value rst/pwr description 63:36 r/w 0000000h flr, core reserved 35:20 r/w 0000h flr, core memory base address (mba): set by the os, these bits correspond to address signals 35:20. 19:4 ro 0000h core address mask (admsk): hardwired to 0s to indicate 512 kb address range (aligned to 1 mb boundary). 3ro 0b core prefetchable memory (prefmem): hardwired to 0 to prevent prefetching. 2:1 ro 10b core memory type (memtyp): hardwired to 10b to indicate 64-bit address. 0ro 0b core memory / io space (mios): hardwired to 0 to indicate memory space. bit access default value rst/pwr description 15:0 ro 0000h core subsystem vendor id (subvid): this value is used to identify the vendor of the subsystem. this register should be programmed by bios during boot-up. once written, this register becomes read only. this register can only be cleared by a reset. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 304 datasheet 9.2.12 sid2?subsystem identification b/d/f/type: 0/2/1/pci address offset: 2e-2fh default value: 0000h access: ro size: 16 bits 9.2.13 romadr?video bios rom base address b/d/f/type: 0/2/1/pci address offset: 30-33h default value: 00000000h access: ro size: 32 bits the igd does not use a separate bios rom, therefore this register is hardwired to 0s. 9.2.14 cappoint?capabilities pointer b/d/f/type: 0/2/1/pci address offset: 34h default value: d0h access: ro size: 8 bits bit access default value rst/pwr description 15:0 ro 0000h core subsystem identification (subid): this value is used to identify a particular subs ystem. this field should be programmed by bios during b oot-up. once written, this register becomes read only. this register can only be cleared by a reset. bit access default value rst/pwr description 31:18 ro 0000h core rom base address (rba): hardwired to 0s. 17:11 ro 00h core address mask (admsk): hardwired to 0s to indicate 256 kb address range. 10:1 ro 000h core reserved: hardwired to 0s. 0r o 0 b c o r e rom bios enable (rbe): 0 = rom not accessible. bit access default value rst/pwr description 7:0 ro d0h core capabilities pointer value (cpv): this field contains an offset into the function's pc i configuration space for the first item in the new capabilities linked list, the power management capability at d0h. datasheet 305 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.2.15 mingnt?minimum grant b/d/f/type: 0/2/1/pci address offset: 3eh default value: 00h access: ro size: 8 bits 9.2.16 maxlat?maximum latency b/d/f/type: 0/2/1/pci address offset: 3fh default value: 00h access: ro size: 8 bits 9.2.17 capid0?mirror of dev0 capability identifier b/d/f/type: 0/2/1/pci address offset: 40-4ch default value: 000000000000000000010c0009h access: ro size: 104 bits bios optimal default 0h bit access default value rst/pwr description 7:0 ro 00h core minimum grant value (mgv): the igd does not burst as a pci compliant master. bit access default value rst/pwr description 7:0 ro 00h core maximum latency value (mlv): the igd has no specific requirements for how often it needs to access the pci bus. bit access default value rst/pwr description 103:28 ro 0000b core reserved 27:24 ro 1h core capid version (capidv): this field has the value 0001b to identify the first revision of the capid register definition. 23:16 ro 0ch core capid length (capidl): this field has the value 0ch to indicate the structure length (12 bytes). 15:8 ro 00h core next capability pointer (ncp): this field is hardwired to 00h indicating the end of th e capabilities linked list. 7:0 ro 09h core capability identifier (cap_id): this field has the value 1001b to identify the cap_id assigned by the pci sig for vendor dependent capability pointers. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 306 datasheet 9.2.18 mggc?mirror of device 0 gmch graphics control register b/d/f/type: 0/2/1/pci address offset: 52-53h default value: 0030h access: ro size: 16 bits note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/ pwr description 15:12 ro 0h core reserved 11:8 ro 0h core gtt graphics memory size (ggms): this field is used to select the amount of main memory that is pr e-allocated to support the internal graphics translation table. the bios ensures that memory is pre-allocated only when internal graphics is enabled. gsm is assumed to be a contiguous physical dram spac e with dsm, and bios needs to allocate a contiguous memory chunk. hardware will drive the base of gsm from dsm only using the gs m size programmed in the register. 0000 = no memory pre-allocated. 0001 = no vt mode, 1 mb of memory pre-allocated for gtt. 0011 = no vt mode, 2 mb of memory pre-allocated for gtt 1001 = vt mode, 2 mb of memory pre-allocated for 1 mb of global gtt and 1 mb for shadow gtt (82q45 gmch only) 1010 = vt mode, 3 mb of memory pre-allocated for 1.5 mb of global gtt and 1.5 mb for shadow gtt (82q45 gmch only) 1011 = vt mode, 4 mb of memory pre-allocated for 2 mb of global gtt and 2 mb for shadow gtt (82q45 gmch only) note: all unspecified encodings of this re gister field are reserved; hardware functionality is not ensured if us ed. this register is locked and becomes read only when the d_lck bit in the smram register is set. datasheet 307 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 7:4 ro 0011b core graphics mode select (gms): this field is used to select the amount of main memory that is pre-allocated to su pport the internal graphics device in vga (non-linear) and native (linear) modes. the bios ensures that memory is pre-allocated only when internal graphics is enabled. 0000 = no memory pre-allocated. de vice 2 (igd) does not claim vga cycles (memory and i/o), and th e sub-class code field within device 2, function 0 clas s code register is 80h. 0001 = reserved 0010 = reserved 0011 = reserved 0100 = reserved 0101 = dvmt (uma) mode, 32 mb of memory pre-allocated for frame buffer. 0110 = dvmt (uma) mode, 48 mb of memory pre-allocated for frame buffer. 0111 = dvmt (uma) mode, 64 mb of memory pre-allocated for frame buffer. 1000 = dvmt (uma) mode, 128 mb of memory pre-allocated for frame buffer. 1001 = dvmt (uma) mode, 256 mb of memory pre-allocated for frame buffer. 1010 = dvmt (uma) mode, 96 mb of memory pre-allocated (0 + 96). 1011 = dvmt (uma) mode, 160 mb of memory pre-allocated (64 + 96). 1100 = dvmt (uma) mode, 224 mb of memory pre-allocated (128 + 96). 1101 = dvmt (uma) mode, 352 mb of memory pre-allocated (256 + 96). note: this register is locked and become s read only when the d_lck bit in the smram register is set. hardware does not clear or set any of these bits automatically based on igd being disabled/enabled. bios requirement: bios must not set this field to 000 if ivd (bit 1 of this register) is 0. 3:2 ro 00b core reserved 1ro 0bcore igd vga disable (ivd): 0 = enable. device 2 (igd) claims vga memory and i/o cycles, and the sub-class code within device 2 class code register is 00h. 1 = disable. device 2 (igd) does not claim vga cycles (memory and i/o), and the sub-class code field within device 2, function 0 class code register is 80h. bios requirement: bios must not set this bit to 0 if the gms field (bits 6:4 of this register) pre-allocates no memory. this bit must be set to 1 if device 2 is disabled either via a fuse or fuse override (capid0[38] = 1) or via a register (deven[3] = 0). 0 ro 0b core reserved bit access default value rst/ pwr description integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 308 datasheet 9.2.19 deven?device enable b/d/f/type: 0/2/1/pci address offset: 54-57h default value: 000023dbh access: ro size: 32 bits this register allows for enabling/disabling of pci devices and functions that are within the gmch. note: all the bits in this register are locked in intel txt mode (82q45/82q43 gmch only). bit access default value rst/pwr description 31:15 ro 00000h core reserved 14 ro 0b core chap enable (d7en): 0 = bus 0, device 7 is disa bled and not visible. 1 = bus 0, device 7 is enabled and visible. non-production bios code sh ould provide a setup option to enable bus 0, device 7. wh en enabled, bus 0, device 7 must be initialized in accordance to standard pci device initialization procedures. 13 ro 1b core peg1 enable (d6en): 0 = bus 0 device 6 is disabled and hidden. 1 = bus 0, device 6 is enabled and visible. 12:10 ro 00b core reserved 9r o 1 b c o r e ep function 3 (d3f3en): 0 = bus 0, device 3, function 3 is disabled and hidden 1 = bus 0, device 3, function 3 is enabled and visible if device 3, function 0 is di sabled and hidden, then device 3, function 3 is also disabl ed and hidden independent of the state of this bit. 8r o 1 b c o r e ep function 2 (d3f2en): 0 = bus 0, device 3, function 2 is disabled and hidden 1 = bus 0, device 3, function 2 is enabled and visible if device 3, function 0 is di sabled and hidden, then device 3, function 2 is also disabl ed and hidden independent of the state of this bit. 7r o 1 b c o r e ep function 1 (d3f1en): 0 = bus 0, device 3, functi on 1 is disabled and hidden 1 = bus 0, device 3, function 1 is enabled and visible. if this gmch does not have me capability (capid0[??] = 1), then device 3 function 1 is disabled and hidden independent of the state of this bit. 6r o 1 b c o r e ep function 0 (d3f0en): 0 = bus 0, device 3, function 0 is disabled and hidden 1 = bus 0, device 3, function 0 is enabled and visible. if this gmch does not have me capability (capid0[??] = 1), then device 3, function 0 is disabled and hidden independent of the state of this bit. datasheet 309 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.2.20 ssrw?mirror of function 0 software scratch read write b/d/f/type: 0/2/1/pci address offset: 58-5bh default value: 00000000h access: ro size: 32 bits 5 ro 0b core reserved 4r o 1 b c o r e internal graphics engine function 1 (d2f1en): 0 = bus 0, device 2, functi on 1 is disabled and hidden 1 = bus 0, device 2, function 1 is enabled and visible if device 2, function 0 is di sabled and hidden, then device 2, function 1 is also disabl ed and hidden independent of the state of this bit. if this component is not ca pable of dual independent display (capid0[78] = 1), then this bit is hardwired to 0b to hide device 2 function 1. 3r o 1 b c o r e internal graphics engine function 0 (d2f0en): 0 = bus 0, device 2, functi on 0 is disabled and hidden 1 = bus 0, device 2, function 0 is enabled and visible if this gmch does not have internal graphi cs capability (capid0[46] = 1), then device 2, function 0 is disabled and hidden independent of the state of this bit. 2 ro 0b core reserved 1r o 1 b c o r e pci express port (d1en): 0 = bus 0, device 1, function 0 is disabled and hidden. 1 = bus 0, device 1, function 0 is enabled and visible. default value is determined by the device capabilities (see capid0[44]), sdvo presence hardware strap and the sdvo/pcie concurrent hardware strap. device 1 is disabled on reset if the sdvo presence strap was sampled high, and the sdvo/pcie conc urrent strap was sampled low at the last assertion of pwrok, and is enabled by default otherwise. 0r o 1 b c o r e host bridge (d0en): bus 0, device 0, function 0 may not be disabled and is therefore hardwired to 1. bit access default value rst/pwr description bit access default value rst/pwr description 31:0 ro 00000000h core reserved integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 310 datasheet 9.2.21 bsm?mirror of function 0 base of stolen memory b/d/f/type: 0/2/1/pci address offset: 5c-5fh default value: 07800000h access: ro size: 32 bits graphics stolen memory and tseg are within dram space defined under tolud. from the top of low used dram, gmch claims 1 to 64 mb of dram for internal graphics if enabled. the base of stolen memory will always be below 4 gb. this is required to prevent aliasing between stolen range and the reclaim region. 9.2.22 hsrw?mirror of device 2 function 0 hardware scratch read write b/d/f/type: 0/2/1/pci address offset: 60-61h default value: 0000h access: ro size: 16 bits bit access default value rst/pwr description 31:20 ro 078h core base of stolen memory (bsm): this register contains bits 31:20 of the base addr ess of stolen dram memory. the host interface determines the base of graphics stolen memory by subtracting the gr aphics stolen memory size from tolud. see device 0 tolud for more explanation. 19:0 ro 00000h core reserved bit access default value rst/pwr description 15:0 ro 0000h core reserved datasheet 311 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.2.23 gdrst?mirror of device 2 function 0 graphics reset b/d/f/type: 0/2/1/pci address offset: c0h default value: 00h access: ro size: 8 bits this register is a mirror of graphics reset register in device 2. bit access default value rst/ pwr description 7:4 ro 0h core reserved 3:2 ro 00b flr, core graphics reset domain (grdom): 00 = full graphics reset will be performed (both render and display clock domain resets asserted) 01 = render only reset (render clock domain reset asserted) 10 = reserved (invalid programming) 11 = media only reset (media domain reset get asserted) 1ro 0bcore reserved 0ro 0bcore graphics reset enable (gr): setting this bit asserts graphics-only reset. the clock domains to be reset are determined by grdom. hardware resets this bit when the reset is complete. setting this bit without waiting for it to clear, is undefined behavior. once this bit is set to a 1, all graphics core mmio registers are returned to power on default stat e. all ring buffer pointers are reset, command stream fetches are dropped and ongoing render pipeline processing is halted, state machines and state variables returned to power on de fault state. if the display is reset, all display engines are ha lted (garbage on screen). vga memory is not available, store dwords and interrupts are not ensured to be completed. de vice 2 i/o registers are not available. device 2 configuration registers continue to be available while graphics reset is asserted. this bit is hardware auto-clear. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 312 datasheet 9.2.24 pmcapid?mirror of fun 0 power management capabilities id b/d/f/type: 0/2/1/pci address offset: d0-d1h default value: 0001h access: r/wo, ro size: 16 bits this register is a mirror of function 0 with the same r/w attributes. 9.2.25 pmcap?mirror of fun 0 power management capabilities b/d/f/type: 0/2/1/pci address offset: d2-d3h default value: 0022h access: ro size: 16 bits this register is a mirror of function 0 with the same read/write attributes. the hardware implements a single physical register common to both functions 0 and 1. bit access default value rst/pwr description 15:8 r/wo 00h core next capability po inter (next_ptr): this field contains a pointer to next item in capabilities list. bios is responsible for writing this to the flr capability when applicable. 7:0 ro 01h core capability identifier (cap_id): sig defines this id is 01h for power management. bit access default value rst/pwr description 15:11 ro 00h core pme support (pmes): this field indi cates the power states in which the igd may assert pme#. hardwired to 0 to indicate that the igd does not assert the pme# signal. 10 ro 0b core d2 support (d2): the d2 power management state is not supported. this bit is hardwired to 0. 9ro 0b core d1 support (d1): hardwired to 0 to indicate that the d1 power management state is not supported. 8:6 ro 000b core reserved 5ro 1b core device specific initialization (dsi): hardwired to 1 to indicate that special initialization of the igd is required before generic class device driver is to use it. 4 ro 0b core reserved 3ro 0b core pme clock (pmeclk): hardwired to 0 to indicate igd does not support pme# generation. 2:0 ro 010b core version (ver): hardwired to 010b to indicate that there are 4 bytes of power manage ment register s implemented and that this device complies with revision 1.1 of the pci power management interface specification . datasheet 313 integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 9.2.26 pmcs?power mana gement control/status b/d/f/type: 0/2/1/pci address offset: d4-d5h default value: 0000h access: ro, r/w size: 16 bits 9.2.27 swsmi?mirror of func0 software smi b/d/f/type: 0/2/1/pci address offset: e0-e1h default value: 0000h access: ro size: 16 bits since there is the potential that dvo port lega cy drivers exist that expect this register at this address, device 2, function 0, ad dress e0h?e1h is reserved for this register. bit access default value rst/ pwr description 15 ro 0b core pme status (pmests): this bit is 0 to indicate that igd does not support pme# generation from d3 (cold). 14:13 ro 00b core data scale (dscale): the igd does not support data register. this bit always returns 0 when read, write operations have no effect. 12:9 ro 0h core data select (datasel): the igd does not support data register. this bit always return s 0 when read, write operations have no effect. 8ro 0bcore pme enable (pme_en): this bit is 0 to indicate that pme# assertion from d3 (c old) is disabled. 7:2 ro 00h core reserved 1:0 r/w 00b flr, core power state (pwrstat): this field indicates the current power state of the igd and can be used to set the igd into a new power state. if software attempts to wr ite an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. on a transition from d3 to d0 the graphics controll er is optionally reset to initial values. 00 = default 01 = d1 (not supported) 10 = d2 (not supported) 11 = d3 bit access default value rst/ pwr description 15:8 ro 00h core software scratch bits (swsb): 7:1 ro 00h core software flag (swf): used to indicate caller and smi function desired, as well as return result. 0ro0bcore gmch software smi event (gssmie): when set, this bit will trigger an smi. software must write a 0 to clear this bit. integrated graphics registers (device 2) (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 314 datasheet datasheet 315 intel ? manageability engine subsystem registers 10 intel ? manageability engine subsystem registers 10.1 heci function in me subsystem registers table 17. heci function in me subsystem register address map address offset register symbol register name default value access 0?3h id identifiers 2e048086h ro 4?5h cmd command 0000h ro, r/w 6?7h sts device status 0010h ro 8h rid revision id see description ro 9?bh cc class code 0c8001h ro ch cls cache line size 00h ro dh mlt master latency timer 00h ro eh htype header type 80h ro fh bist built in self test 00h ro 10?17h heci_mbar heci mmio base address 0000000000 000004h ro, r/w 2c?2fh ss sub system identifiers 00000000h r/wo 34h cap capabilities pointer 50h ro 3c?3dh intr interrupt information 0100h ro, r/w 3eh mgnt minimum grant 00h ro 3f mlat maximum latency 00h ro 40?43h hfs host firmware status 00000000h ro 50?51h pid pci power management capability id 8c01h ro 52?53h pc pci power management capabilities c803h ro 54?55h pmcs pci power management control and status 0008h r/wc, ro, r/w 8c?8dh mid message signaled interrupt identifiers 0005h ro 8e?8fh mc message signaled interrupt message control 0080h ro, r/w 90?93h ma message signaled interrupt message address 00000000h r/w, ro 94?97h mua message signaled interrupt upper address (optional) 00000000h r/w 98?99h md message signaled interrupt message data 0000h r/w intel ? manageability engine subsystem registers 316 datasheet 10.1.1 id? identifiers b/d/f/type: 0/3/0/pci address offset: 0-3h default value: 2e048086h access: ro size: 32 bits 10.1.2 cmd? command b/d/f/type: 0/3/0/pci address offset: 4-5h default value: 0000h access: ro, r/w size: 16 bits bit access default value rst/pwr description 31:16 ro 2e04h core device id (did): indicates what device number assigned by intel. 15:0 ro 8086h core vendor id (vid): 16-bit field which indicates intel is the vendor, assigned by the pci sig. bit access default value rst/pwr description 15:11 ro 00000b core reserved 10 r/w 0b core interrupt disable (id): disables this device from generating pci line based interru pts. this bit does not have any effect on msi operation. 9ro 0b core fast back-to-back enable (fbe): not implemented, hardwired to 0. 8ro 0b core serr# enable (see): not implemented, hardwired to 0. 7ro 0b core wait cycle enable (wcc): not implemented, hardwired to 0. 6ro 0b core parity error response enable (pee): not implemented, hardwired to 0. 5ro 0b core vga palette snooping enable (vga): not implemented, hardwired to 0 4ro 0b core memory write and invalidate enable (mwie): not implemented, ha rdwired to 0. 3ro 0b core special cycle enable (sce): not implemented, hardwired to 0. datasheet 317 intel ? manageability engine subsystem registers 10.1.3 sts? device status b/d/f/type: 0/3/0/pci address offset: 6-7h default value: 0010h access: ro size: 16 bits 2r/w 0b core bus master enable (bme): this bit controls the heci host controller's ability to ac t as a system memory master for data transfers. when this bit is cleared, heci bus master activity stops and any active dma engines return to an idle condition. this bit is made visible to firmware through the h_pci_csr register , and changes to this bit may be configured by the h_pci_csr register to generate an me msi. when this bit is 0, heci is blocked from generating msi to the host processor. note that this bit does not bl ock heci accesses to me-uma (i.e., writes or reads to th e host and me circular buffers through the read window and write window registers still cause me backbone transactions to me-uma). 1r/w 0b core memory space enable (mse): this bit controls access to the heci host controller?s me mory mapped register space. 0ro 0b core i/o space enable (iose): not implemented, hardwired to 0. bit access default value rst/pwr description bit access default value rst/pwr description 15 ro 0b core detected parity error (dpe): not implemented, hardwired to 0. 14 ro 0b core signaled system error (sse): not implemented, hardwired to 0. 13 ro 0b core received master-abort (rma): not implemented, hardwired to 0. 12 ro 0b core received target abort (rta): not implemented, hardwired to 0. 11 ro 0b core signaled target-abort (sta): not implemented, hardwired to 0. 10:9 ro 00b core devsel# timing (devt): these bits are hardwired to 00. 8ro 0b core master data parity error detected (dpd): not implemented, hardwired to 0. 7ro 0b core fast back-to-back capable (fbc): not implemented, hardwired to 0. 6 ro 0b core reserved 5ro 0b core 66 mhz capable (c66): not implemented, hardwired to 0. intel ? manageability engine subsystem registers 318 datasheet 10.1.4 rid? revision id b/d/f/type: 0/3/0/pci address offset: 8h default value: see description below access: ro size: 8 bits 10.1.5 cc? class code b/d/f/type: 0/3/0/pci address offset: 9-bh default value: 0c8001h access: ro size: 24 bits 4r o 1 b c o r e capabilities list (cl): indicates the presence of a capabilities list, hardwired to 1. 3r o 0 b c o r e interrupt status (is): indicates the interrupt status of the device (1 = asserted). 2:0 ro 000b core reserved bit access default value rst/pwr description bit access default value rst/pwr description 7:0 ro see description core revision id (rid): indicates stepping of the heci host controller. refer to the intel ? 4 series chipset family specification update for the value of this register. bit access default value rst/pwr description 23:16 ro 0ch core base class code (bcc): this field indi cates the base class code of the heci host controller device. 15:8 ro 80h core sub class code (scc): this field indicates the sub class code of the heci host controller device. 7:0 ro 01h core programming interface (pi): this field indicates the programming interface of the he ci host controller device. datasheet 319 intel ? manageability engine subsystem registers 10.1.6 cls? cache line size b/d/f/type: 0/3/0/pci address offset: ch default value: 00h access: ro size: 8 bits 10.1.7 mlt? master latency timer b/d/f/type: 0/3/0/pci address offset: dh default value: 00h access: ro size: 8 bits 10.1.8 htype? header type b/d/f/type: 0/3/0/pci address offset: eh default value: 80h access: ro size: 8 bits bit access default value rst/pwr description 7:0 ro 00h core cache line size (cls): not implemented, hardwired to 0. bit access default value rst/pwr description 7:0 ro 00h core master latency timer (mlt): not implemented, hardwired to 0. bit access default value rst/pwr description 7ro 1b core multi-function device (mfd): this bit indicates the heci host controller is part of a multi-function device. 6:0 ro 0000000b core header layout (hl): this field indicates that the heci host controller uses a target device layout. intel ? manageability engine subsystem registers 320 datasheet 10.1.9 bist? built in self test b/d/f/type: 0/3/0/pci address offset: fh default value: 00h access: ro size: 8 bits 10.1.10 heci_mbar? heci mmio base address b/d/f/type: 0/3/0/pci address offset: 10-17h default value: 0000000000000004h access: ro, r/w size: 64 bits this register allocates space for the heci memory mapped registers. bit access default value rst/pwr description 7ro 0b core bist capable (bc): not implemented, hardwired to 0. 6:0 ro 0000000b core reserved bit access default value rst/pwr description 63:4 r/w 000000000 000000h core base address (ba): base address of register memory space. 3ro 0b core prefetchable (pf): this bit indicates that this range is not pre-fetchable 2:1 ro 10b core type (tp): this field indicates that this range can be mapped anywhere in 64-bit a ddress space. note that the (g)mch only uses bits 35:4 of the base address field as the (g)mch only decodes fs b address bits 35:4. 0ro 0b core resource type indicator (rte): indicates a request for register memory space. datasheet 321 intel ? manageability engine subsystem registers 10.1.11 ss? sub syst em identifiers b/d/f/type: 0/3/0/pci address offset: 2c-2fh default value: 00000000h access: r/wo size: 32 bits 10.1.12 cap? capabilities pointer b/d/f/type: 0/3/0/pci address offset: 34h default value: 50h access: ro size: 8 bits bit access default value rst/pwr description 31:16 r/wo 0000h core subsystem id (ssid): this field indicates the sub- system identifier. this field should be programmed by bios during boot-up. once wr itten, this re gister becomes read only. this field can only be cleared by pltrst#. 15:0 r/wo 0000h core subsystem vendor id (ssvid): this field indicates the sub-system vendor identifi er. this field should be programmed by bios during boot-up. once written, this register becomes read only. this field can only be cleared by pltrst#. bit access default value rst/pwr description 7:0 ro 50h core capability pointer (cp): this field indicates the first capability pointer offset. it points to the pci power management capability offset. intel ? manageability engine subsystem registers 322 datasheet 10.1.13 intr? interr upt information b/d/f/type: 0/3/0/pci address offset: 3c-3dh default value: 0100h access: ro, r/w size: 16 bits 10.1.14 mgnt? minimum grant b/d/f/type: 0/3/0/pci address offset: 3eh default value: 00h access: ro size: 8 bits 10.1.15 mlat? maximum latency b/d/f/type: 0/3/0/pci address offset: 3fh default value: 00h access: ro size: 8 bits bit access default value rst/pwr description 15:8 ro 01h core interrupt pin (ipin): this field indicates the interrupt pin the heci host controller uses. the value of 01h selects inta# interrupt pin. note: as heci is an internal device in the (g)mch, the inta# pin is implemented as an inta# message to the ich. 7:0 r/w 00h core interrupt line (iline): software written value to indicate which interrupt line (vector) the interrupt is connected to. no hardware action is taken on this register. bit access default value rst/pwr description 7:0 ro 00h core grant (gnt): not implemented, hardwired to 0. bit access default value rst/pwr description 7:0 ro 00h core latency (lat): not implemented, hardwired to 0. datasheet 323 intel ? manageability engine subsystem registers 10.1.16 hfs? host firmware status b/d/f/type: 0/3/0/pci address offset: 40-43h default value: 00000000h access: ro size: 32 bits 10.1.17 pid? pci power ma nagement capability id b/d/f/type: 0/3/0/pci address offset: 50-51h default value: 8c01h access: ro size: 16 bits bit access default value rst/pwr description 31:0 ro 00000000h core firmware status ho st access (fs_ha): this field indicates current status of the firmware for the heci controller. this field is the host's read only access to the fs field in the me firmware status aux register. bit access default value rst/pwr description 15:8 ro 8ch core next capability (next): this field indicates the location of the next capability item in the list. this is the message signaled interrupts capability. 7:0 ro 01h core cap id (cid): this field indicates that this pointer is a pci power management. intel ? manageability engine subsystem registers 324 datasheet 10.1.18 pc? pci power ma nagement capabilities b/d/f/type: 0/3/0/pci address offset: 52-53h default value: c803h access: ro size: 16 bits bit access default value rst/pwr description 15:11 ro 11001b core pme_support (psup): this field indicates the states that can generate pme#. heci can assert pme# from an y d-state except d1 or d2 which are not supported by heci. 10 ro 0b core d2_support (d2s): the d2 state is not supported for the heci host controller. 9ro 0b core d1_support (d1s): the d1 state is not supported for the heci host controller. 8:6 ro 000b core aux_current (auxc): this field reports the maximum suspend well current required when in the d3cold state. value of tbd is reported. 5ro 0b core device specific initialization (dsi): this bit indicates whether device-specific initialization is required. 4ro 0b core reserved 3ro 0b core pme clock (pmec): this bit indicates that pci clock is not required to generate pme#. 2:0 ro 011b core version (vs): this field indicates support for revision 1.2 of the pci power management specification . datasheet 325 intel ? manageability engine subsystem registers 10.1.19 pmcs? pci power mana gement control and status b/d/f/type: 0/3/0/pci address offset: 54-55h default value: 0008h access: r/wc, ro, r/w size: 16 bits bit access default value rst/pwr description 15 r/wc 0b core pme status (pmes): the pme status bit in heci space can be set to 1 by arc fw performing a write into aux register to set pmes. this bit is cleared by host processor writing a 1 to it. arc cannot clear this bit. host processor writes with valu e 0 have no e ffect on this bit. this bit is reset to 0 by mrst#. 14:9 ro 000000b core reserved. 8r/w 0b core pme enable (pmee): this bit is read/write, under control of host sw. it does not dire ctly have an effect on pme events. however, this bit is shadowed into aux space so arc fw can monitor it. the arc fw is responsible for ensuring that fw does not cause the pme-s bit to transition to 1 while the pmee bit is 0, indicating that host software had disabled pme. this bit is reset to 0 by mrst#. 7:4 ro 0000b core reserved 3ro 1b core no_soft_reset (nsr): this bit indicates that when the heci host controller is transitioning from d3hot to d0 due to power state command. it do es not perform an internal reset. configuration context is reserved. 2ro 0b core reserved 1:0 r/w 00b core power state (ps): this field is used both to determine the current power state of the heci host controller and to set a new power state. the values are: 00 = d0 state 11 = d3hot state the d1 and d2 states are not supported for this heci host controller. when in the d3hot state, the hba?s configuration space is available, but the register memory spaces are not. additionally, interrupts are blocked. this field is visible to firmware through the h_pci_csr register, and changes to this field may be configured by the h_pci_csr register to generate an me msi. intel ? manageability engine subsystem registers 326 datasheet 10.1.20 mid? message signal ed interrupt identifiers b/d/f/type: 0/3/0/pci address offset: 8c-8dh default value: 0005h access: ro size: 16 bits 10.1.21 mc? message signaled interrupt message control b/d/f/type: 0/3/0/pci address offset: 8e-8fh default value: 0080h access: ro, r/w size: 16 bits 10.1.22 ma? message signaled interrupt message address b/d/f/type: 0/3/0/pci address offset: 90-93h default value: 00000000h access: r/w, ro size: 32 bits bit access default value rst/pwr description 15:8 ro 00h core next pointer (next): indicates the next item in the list. this can be other capability po inters (such as pci-x or pci- express) or it can be the last item in the list. 7:0 ro 05h core capability id (cid): capabilities id indicates msi. bit access default value rst/pwr description 15:8 ro 00h core reserved 7ro 1b core 64 bit address capable (c64): specifies whether capable of generating 64-bit messages. 6:4 ro 000b core multiple message enable (mme): not implemented, hardwired to 0. 3:1 ro 000b core multiple message capable (mmc): not implemented, hardwired to 0. 0r/w 0b core msi enable (msie): if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. bit access default value rst/pwr description 31:2 r/w 00000000h core address (addr): lower 32 bits of the system specified message address, alwa ys dword aligned. 1:0 ro 00b core reserved datasheet 327 intel ? manageability engine subsystem registers 10.1.23 mua? messag e signaled interrupt upper address (optional) b/d/f/type: 0/3/0/pci address offset: 94-97h default value: 00000000h access: r/w size: 32 bits 10.1.24 md? message signaled interrupt message data b/d/f/type: 0/3/0/pci address offset: 98-99h default value: 0000h access: r/w size: 16 bits bit access default value rst/pwr description 31:0 r/w 00000000h core upper address (uaddr): upper 32 bits of the system specified message address. this register is optional and only implemented if mc.c64=1. bit access default value rst/pwr description 15:0 r/w 0000h core data (data): this 16-bit field is programmed by system software if msi is enabled. it s content is driven onto the fsb during the data phase of the msi memory write transaction. intel ? manageability engine subsystem registers 328 datasheet 10.2 second heci function in me subsystem registers table 18. second heci function in me subsystem regi ster address map address offset register symbol register name default value access 0?3h id identifiers 2e058086h ro 4?5h cmd command 0000h ro, r/w 6?7h sts device status 0010h ro 8h rid revision id see register description ro 9?bh cc class code 0c8001h ro ch cls cache line size 00h ro dh mlt master latency timer 00h ro eh htype header type 80h ro 10?17h heci_mbar heci mmio base address 0000000000 000004h r/w, ro 2c?2fh ss sub system identifiers 00000000h r/wo 34h cap capabilities pointer 50h ro 3c?3dh intr interrupt information 0100h r/w, ro 3eh mgnt minimum grant 00h ro 3fh mlat maximum latency 00h ro 40?43h hfs host firmware status 00000000h ro 50?51h pid pci power management capability id 8c01h ro 52?53h pc pci power management capabilities c803h ro 54?55h pmcs pci power management control and status 0008h r/w, ro, r/ wc 8c?h8d mid message signaled interrupt identifiers 0005h ro 8e?8fh mc message signaled interrupt message control 0080h r/w, ro 90?93h ma message signaled interrupt message address 00000000h r/w, ro 94?97h mua message signaled interrupt upper address (optional) 00000000h r/w 98?99h md message signaled interrupt message data 0000h r/w a0h hidm heci interrupt delivery mode 00h r/w datasheet 329 intel ? manageability engine subsystem registers 10.2.1 id? identifiers b/d/f/type: 0/3/1/pci address offset: 0-3h default value: 2e058086h access: ro size: 32 bits 10.2.2 cmd? command b/d/f/type: 0/3/1/pci address offset: 4-5h default value: 0000h access: ro, r/w size: 16 bits bit access default value rst/pwr description 31:16 ro 2e05h core device id (did): indicates what device number assigned by intel. 15:0 ro 8086h core vendor id (vid): 16-bit field which indicates intel is the vendor, assigned by the pci sig. bit access default value rst/pwr description 15:11 ro 00000b core reserved 10 r/w 0b core interrupt di sable (id): disables this device from generating pci line based interr upts. this bit does not have any effect on msi operation. 9ro 0b core fast back-to-back enable (fbe): not implemented, hardwired to 0. 8ro 0b core serr# enable (see): not implemented, hardwired to 0. 7ro 0b core wait cycle enable (wcc): not implemented, hardwired to 0. 6ro 0b core parity error response enable (pee): not implemented, hardwired to 0. 5ro 0b core vga palette snooping enable (vga): not implemented, hardwired to 0 4ro 0b core memory write and invalidate enable (mwie): not implemented, hardwired to 0. 3ro 0b core special cycle enable (sce): not implemented, hardwired to 0. intel ? manageability engine subsystem registers 330 datasheet 10.2.3 sts? device status b/d/f/type: 0/3/1/pci address offset: 6-7h default value: 0010h access: ro size: 16 bits 2r/w 0b core bus master enable (bme): this bit controls the heci host controller's ability to act as a system memory master for data transfers. when this bit is cleared, heci bus master activity stops and any active dma engines return to an idle condition. this bit is made visible to firmware through the h_pci_csr register , and changes to this bit may be configured by the h_pc i_csr register to generate an me msi. when this bit is 0, heci is blocked from generating msi to the host processor. note that this bit does not block heci accesses to me-uma (i.e., writes or reads to the host and me circular buffers through the read window and write window registers still cause me backbone transactions to me-uma). 1r/w 0b core memory space enable (mse): this bit controls access to the heci host controller?s me mory mapped regi ster space. 0ro 0b core i/o space enable (iose): not implemented, hardwired to 0. bit access default value rst/pwr description bit access default value rst/pwr description 15 ro 0b core detected parity error (dpe): not implemented, hardwired to 0. 14 ro 0b core signaled system error (sse): not implemented, hardwired to 0. 13 ro 0b core received master-abort (rma): not implemented, hardwired to 0. 12 ro 0b core received target abort (rta): not implemented, hardwired to 0. 11 ro 0b core signaled target-abort (sta): not implemented, hardwired to 0. 10:9 ro 00b core devsel# timing (devt): these bits are hardwired to 00. 8ro 0b core master data parity error detected (dpd): not implemented, ha rdwired to 0. 7ro 0b core fast back-to-back capable (fbc): not implemented, hardwired to 0. 6 ro 0b core reserved 5ro 0b core 66 mhz capable (c66): not implemented, hardwired to 0. datasheet 331 intel ? manageability engine subsystem registers 10.2.4 rid?revision id b/d/f/type: 0/3/1/pci address offset: 8h default value: 02hsee description below access: ro size: 8 bits 10.2.5 cc? class code b/d/f/type: 0/3/1/pci address offset: 9-bh default value: 0c8001h access: ro size: 24 bits 4r o 1 b c o r e capabilities list (cl): indicates the presence of a capabilities list, hardwired to 1. 3r o 0 b c o r e interrupt status (is): indicates the inte rrupt status of the device (1 = asserted). 2:0 ro 000b core reserved bit access default value rst/pwr description bit access default value rst/pwr description 7:0 ro see description core revision id (rid): this field indicates stepping of the heci host controller. refer to the intel ? 4 series chipset family specification update for the value of this register. bit access default value rst/pwr description 23:16 ro 0ch core base class code (bcc): this field indicates the base class code of the heci host controller device. 15:8 ro 80h core sub class code (scc): this field indica tes the sub class code of the heci host controller device. 7:0 ro 01h core programming interface (pi): this field indicates the programming interface of the he ci host contro ller device. intel ? manageability engine subsystem registers 332 datasheet 10.2.6 cls? cache line size b/d/f/type: 0/3/1/pci address offset: ch default value: 00h access: ro size: 8 bits 10.2.7 mlt? master latency timer b/d/f/type: 0/3/1/pci address offset: dh default value: 00h access: ro size: 8 bits 10.2.8 htype? header type b/d/f/type: 0/3/1/pci address offset: eh default value: 80h access: ro size: 8 bits bit access default value rst/pwr description 7:0 ro 00h core cache line size (cls): not implemented, hardwired to 0. bit access default value rst/pwr description 7:0 ro 00h core master latency timer (mlt): not implemented, hardwired to 0. bit access default value rst/pwr description 7ro 1b core multi-function device (mfd): this bit indicates the heci host controller is part of a multi-fu nction device. 6:0 ro 0000000b core header layout (hl): this field indicates that the heci host controller uses a target device layout. datasheet 333 intel ? manageability engine subsystem registers 10.2.9 heci_mbar? heci mmio base address b/d/f/type: 0/3/1/pci address offset: 10-17h default value: 0000000000000004h access: r/w, ro size: 64 bits this register allocates space for the heci memory mapped registers. 10.2.10 ss? sub syst em identifiers b/d/f/type: 0/3/1/pci address offset: 2c-2fh default value: 00000000h access: r/wo size: 32 bits bit access default value rst/pwr description 63:4 r/w 000000000 000000h core base address (ba): base address of register memory space. 3ro 0b core prefetchable (pf): this bit indicates that this range is not pre-fetchable 2:1 ro 10b core type (tp): this field indicates that this range can be mapped anywhere in 32-bit address space 0ro 0b core resource type indicator (rte): this bit indicates a request for register memory space. bit access default value rst/pwr description 31:16 r/wo 0000h core subsystem id (ssid): this field indicates the sub- system identifier. this field should be programmed by bios during boot-up. once written, this register becomes read only. this field can only be cleared by pltrst#. 15:0 r/wo 0000h core subsystem vendor id (ssvid): this field indicates the sub-system vendor identifi er. this field should be programmed by bios during boot-up. once written, this register becomes read only. th is field can on ly be cleared by pltrst#. intel ? manageability engine subsystem registers 334 datasheet 10.2.11 cap? capabi lities pointer b/d/f/type: 0/3/1/pci address offset: 34h default value: 50h access: ro size: 8 bits 10.2.12 intr? interr upt information b/d/f/type: 0/3/1/pci address offset: 3c-3dh default value: 0100h access: r/w, ro size: 16 bits 10.2.13 mgnt? minimum grant b/d/f/type: 0/3/1/pci address offset: 3eh default value: 00h access: ro size: 8 bits bit access default value rst/pwr description 7:0 ro 50h core capability pointer (cp): this field indicates the first capability pointer offset. it points to the pci power management capa bility offset. bit access default value rst/pwr description 15:8 ro 01h core interrupt pin (ipin): this field indicates the interrupt pin the heci host controller uses. the value of 01h selects inta# interrupt pin. note: as heci is an internal device in the (g)mch, the inta# pin is implemented as an inta# message to the ich. 7:0 r/w 00h core interrupt line (iline): software written value to indicate which interrupt line (vector) the interrupt is connected to. no hardware action is taken on this register. bit access default value rst/pwr description 7:0 ro 00h core grant (gnt): not implemented, hardwired to 0. datasheet 335 intel ? manageability engine subsystem registers 10.2.14 mlat? maximum latency b/d/f/type: 0/3/1/pci address offset: 3fh default value: 00h access: ro size: 8 bits 10.2.15 hfs? host firmware status b/d/f/type: 0/3/1/pci address offset: 40-43h default value: 00000000h access: ro size: 32 bits 10.2.16 pid? pci power ma nagement capability id b/d/f/type: 0/3/1/pci address offset: 50-51h default value: 8c01h access: ro size: 16 bits bit access default value rst/pwr description 7:0 ro 00h core latency (lat): not implemented, hardwired to 0. bit access default value rst/pwr description 31:0 ro 00000000h core firmware status ho st access (fs_ha): this field indicates current status of the firmware for the heci controller. this field is the host's read only access to the fs field in the me firmware status aux register. bit access default value rst/pwr description 15:8 ro 8ch core next capability (next): this field indicates the location of the next capability item in the list. this is the message signaled interrupts capability. 7:0 ro 01h core cap id (cid): this field indicates that this pointer is a pci power management. intel ? manageability engine subsystem registers 336 datasheet 10.2.17 pc? pci power ma nagement capabilities b/d/f/type: 0/3/1/pci address offset: 52-53h default value: c803h access: ro size: 16 bits bit access default value rst/pwr description 15:11 ro 11001b core pme_support (psup): this field indicates the states that can generate pme#. heci can assert pme# from an y d-state except d1 or d2 which are not supported by heci. 10 ro 0b core d2_support (d2s): the d2 state is not supported for the heci host controller. 9ro 0b core d1_support (d1s): the d1 state is not supported for the heci host controller. 8:6 ro 000b core aux_current (auxc): this field reports the maximum suspend well current required when in the d3cold state. 5ro 0b core device specific initialization (dsi): this bit indicates whether device-specific initialization is required. 4 ro 0b core reserved 3ro 0b core pme clock (pmec): this bit indicates that pci clock is not required to generate pme#. 2:0 ro 011b core version (vs): indicates support for the pci power management specification, revision 1.2 . datasheet 337 intel ? manageability engine subsystem registers 10.2.18 pmcs? pci power mana gement control and status b/d/f/type: 0/3/1/pci address offset: 54-55h default value: 0008h access: r/w, ro, r/wc size: 16 bits bit access default value rst/pwr description 15 r/wc 0b core pme status (pmes): the pme status bit in heci space can be set to 1 by arc fw performing a write into aux register to set pmes. this bit is cleared by host processor writing a 1 to it. arc cannot clear this bit. host processor writes with valu e 0 have no e ffect on this bit. this bit is reset to 0 by mrst#. 14:9 ro 000000b core reserved. 8r/w 0b core pme enable (pmee): this bit is read/write, under control of host software. it does not di rectly have an effect on pme events. however, this bit is shadowed into aux space so arc fw can monitor it. the arc fw is responsible for ensuring that fw does not cause the pme-s bit to transition to 1 while the pmee bit is 0, indicating that host sw had disabled pme. this bit is reset to 0 by mrst#. 7:4 ro 0000b core reserved 3ro 1b core no_soft_reset (nsr): this bit indicates that when the heci host controller is transitioning from d3hot to d0 due to power state command, it does not perform and internal reset. configuration context is reserved. 2 ro 0b core reserved 1:0 r/w 00b core power state (ps): this field is used both to determine the current power state of the heci host controller and to set a new power state. the values are: 00 = d0 state 11 = d3hot state the d1 and d2 states are not supported for this heci host controller. when in the d3hot state, the hba?s configuration space is available, but the register memory spaces are not. additionally, interrupts are blocked. this field is visible to firmware through the h_pci_csr register, and changes to this field may be configured by the h_pci_csr register to generate an me msi. intel ? manageability engine subsystem registers 338 datasheet 10.2.19 mid? message signal ed interrupt identifiers b/d/f/type: 0/3/1/pci address offset: 8c-8dh default value: 0005h access: ro size: 16 bits 10.2.20 mc? message signaled interrupt message control b/d/f/type: 0/3/1/pci address offset: 8e-8fh default value: 0080h access: r/w, ro size: 16 bits 10.2.21 ma? message signaled interrupt message address b/d/f/type: 0/3/1/pci address offset: 90-93h default value: 00000000h access: r/w, ro size: 32 bits bit access default value rst/pwr description 15:8 ro 00h core next pointer (next): this field indicates the next item in the list. this can be other capa bility pointers (such as pci- x or pci-express) or it can be the last item in the list. 7:0 ro 05h core capability id (cid): capabilities id indicates msi. bit access default value rst/pwr description 15:8 ro 00h core reserved 7ro 1b core 64 bit address capable (c64): specifies whether capable of generating 64-bit messages. 6:4 ro 000b core multiple message enable (mme): not implemented, hardwired to 0. 3:1 ro 000b core multiple message capable (mmc): not implemented, hardwired to 0. 0r/w 0b core msi enable (msie): if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. bit access default value rst/pwr description 31:2 r/w 00000000h core address (addr): lower 32 bits of the system specified message address, al ways dw aligned. 1:0 ro 00b core reserved datasheet 339 intel ? manageability engine subsystem registers 10.2.22 mua? messag e signaled interrupt upper address (optional) b/d/f/type: 0/3/1/pci address offset: 94-97h default value: 00000000h access: r/w size: 32 bits 10.2.23 md? message signaled interrupt message data b/d/f/type: 0/3/1/pci address offset: 98-99h default value: 0000h access: r/w size: 16 bits 10.2.24 hidm?heci inte rrupt delivery mode b/d/f/type: 0/3/1/pci address offset: a0h default value: 00h access: r/w size: 8 bits bios optimal default 00h this register is used to select interrupt delivery mechanism for heci to host processor interrupts. bit access default value rst/pwr description 31:0 r/w 00000000h core upper address (uaddr): upper 32 bits of the system specified message address. this register is optional and only implemented if mc.c64=1. bit access default value rst/pwr description 15:0 r/w 0000h core data (data): this 16-bit field is programmed by system software if msi is enabled. it s content is driven onto the fsb during the data phase of the msi memory write transaction. bit access default value rst/pwr description 7:2 ro 0h reserved 1:0 r/w 00b core heci interrupt delivery mode (hidm): these bits control what type of interrupt the heci will send when arc writes to set the m_ig bit in aux space. they are interpreted as follows: 00 = generate legacy or msi interrupt 01 = generate sci 10 = generate smi intel ? manageability engine subsystem registers 340 datasheet 10.3 heci pci mmio space registers 10.3.1 h_cb_ww? host circular buffer write window b/d/f/type: 0/3/0/mmio address offset: 0-3h default value: 00000000h access: w size: 32 bits this register is for host to write into its circular buffer (h_cb). the host?s circular buffer is located at the me subsystem address specified in the host cb base address register. table 19. heci pci mmio space register address map address offset register symbol register name default value access 0?3h h_cb_ww host circular buffer write window 00000000h w 4?7h h_csr host control status 02000000h ro, r/w, r/wc 8?bh me_cb_rw me circular buffer read window ffffffffh ro c?fh me_csr_ha me control status host access 02000000h ro bit access default value rst/pwr description 31:0 w 00000000h core host circular buffer write window field (h_cb_wwf): this bit field is for host to write into its circular buffer. the host's circ ular buffer is located at the me subsystem address specifie d in the host cb base address register. this field is write only, reads will return arbitrary data. writes to this register will increment the h_cbwp as long as me_rdy is 1. when me_rdy is 0, writes to this register have no effect and are not delivered to the h_cb, nor is h_cbwp incremented. datasheet 341 intel ? manageability engine subsystem registers 10.3.2 h_csr? host control status b/d/f/type: 0/3/0/mmio address offset: 4-7h default value: 02000000h access: ro, r/w, r/wc size: 32 bits this register reports status information about the host circular buffer (h_cb) and allows host software to control interrupt gene ration. note to software: reserved bits in this register must be set to 0 whenever this register is written. bit access default value rst/pwr description 31:24 ro 02h core host circular buffer depth (h_cbd): this field indicates the maximum number of 32 bit entries available in the host circular buffer (h_c b). host software uses this field along with the h_cbrp and h_cbwp fields to calculate the number of valid entries in the h_cb to read or number of entries available for write. this field is a read only version of h_cbd_merwa field which is programmed by the me firmware during me initialization. programmer's note: this field is implemented with a "1- hot" scheme. only one bit will be set to a 1 at a time. each bit position represents the value n of a buffer depth of (2^n). for example, when bit 1 is 1, the buffer depth is 2; when bit 2 is 1, the buffer de pth is 4, etc. the allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128. this field is re set by merst#. 23:16 ro 00h core host cb write pointer (h_cbwp): this field points to next location in the h_cb for host to write the data. software uses this field al ong with h_cbrp and h_cbd fields to calculate the number of valid entries in the h_cb to read or number of entries available for write. 15:8 ro 00h core host cb read pointer (h_cbrp): this field points to next location in the h_cb wher e a valid data is available for embedded controller to read. so ftware uses this field along with h_cbwr and h_cbd fields to calculate the number of valid entries in the host cb to read or number of entries available for write. 7:5 ro 000b core reserved 4r/w 0b core host reset (h_rst): setting this bit to 1 will initiate a heci reset sequence to get the circular buffers into a known good state for host an d me communication. when this bit transitions from 0-to-1, hardware will clear the h_rdy and me_rdy bits. 3r/w 0b core host ready (h_rdy): this bit indicates that the host is ready to process messages. intel ? manageability engine subsystem registers 342 datasheet 10.3.3 me_cb_rw? me circ ular buffer read window b/d/f/type: 0/3/0/mmio address offset: 8-bh default value: ffffffffh access: ro size: 32 bits this register is for host to read from the me circular buffer (me_cb). the me's circular buffer is located at the me subsystem address specified in the me cb base address register. 2r/w 0b core host interrupt generate (h_ig): once message(s) are written into its cb, the host sets this bit to 1 for the hardware to set the me_is bit in the me_csr and to generate an interrupt message to me. hardware will send the interrupt message to me only if the me_ie is enabled. hardware then clears this bit to 0. 1r/wc 0b core host interrupt status (h_is): hardware sets this bit to 1 when me_ig bit is set to 1. host clears this bit to 0 by writing a 1 to this bit position . h_ie has no e ffect on this bit. 0r/w 0b core host interrupt enable (h_ie): host sets this bit to 1 to enable the host interrupt (int r# or msi) to be asserted when h_is is set to 1. bit access default value rst/pwr description bit access default value rst/pwr description 31:0 ro ffffffffh core me circular buffer read window field (me_cb_rwf): this bit field is for host to read from the me circular buffer. the me's circular buffer is located at the me subsystem address specified in the me cb base address register. this field is read only, writes have no effect. reads to this register will increment the me_cbrp as long as me_rdy is 1. when me_rdy is 0, reads to this register have no effect, all 1s are returned, and me_cbrp is not incremented. datasheet 343 intel ? manageability engine subsystem registers 10.3.4 me_csr_ha? me control status host access b/d/f/type: 0/3/0/mmio address offset: c-fh default value: 02000000h access: ro size: 32 bits this register allows host software to read the me control status register (me_csr). this register is reset by merst#. bit access default value rst/pwr description 31:24 ro 02h core me circular buffer depth host read access (me_cbd_hra): host read only access to me_cbd. 23:16 ro 00h core me cb write pointer host read access (me_cbwp_hra): host read only access to me_cbwp. 15:8 ro 00h core me cb read pointer host read access (me_cbrp_hra): host read only access to me_cbrp. 7:5 ro 000b core reserved 4ro 0b core me reset host read access (me_rst_hra): host read access to me_rst. 3ro 0b core me ready host read access (me_rdy_hra): host read access to me_rdy. 2ro 0b core me interrupt generate host read access (me_ig_hra): host read only access to me_ig. 1ro 0b core me interrupt status host read access (me_is_hra): host read only access to me_is. 0ro 0b core me interrupt enable host read access (me_ie_hra): host read only access to me_ie. intel ? manageability engine subsystem registers 344 datasheet 10.4 second heci function mmio space registers 10.4.1 h_cb_ww? host circular buffer write window b/d/f/type: 0/3/1/mmio address offset: 0-3h default value: 00000000h access: w size: 32 bits this register is for host to write into its circular buffer (h_cb). the host?s circular buffer is located at the me subsystem address specified in the host cb base address register. table 20. second heci function mmio space register address map address offset register symbol register name default value access 0?3h h_cb_ww host circular buffer write window 00000000h w 4?7h h_csr host control status 02000000h ro, r/w, r/wc 8?bh me_cb_rw me circular buffer read window ffffffffh ro c?fh me_csr_ha me control status host access 02000000h ro bit access default value rst/pwr description 31:0 w 00000000h core host circular buffer write window field (h_cb_wwf): this bit field is for host to write into its circular buffer. the host's circ ular buffer is located at the me subsystem address specifie d in the host cb base address register. this field is write only, reads will return arbitrary data. writes to this register will increment the h_cbwp as long as me_rdy is 1. when me_rdy is 0, writes to this register have no effect and are not delivered to the h_cb, nor is h_cbwp incremented. datasheet 345 intel ? manageability engine subsystem registers 10.4.2 h_csr? host control status b/d/f/type: 0/3/1/mmio address offset: 4-7h default value: 02000000h access: ro, r/w, r/wc size: 32 bits this register reports status information about the host circular buffer (h_cb) and allows host software to control interrupt generation. note: reserved bits in this register must be se t to 0 whenever this register is written. bit access default value rst/pwr description 31:24 ro 02h core host circular buffer depth (h_cbd): this field indicates the maximum number of 32 bit entries available in the host circular buffer (h_c b). host software uses this field along with the h_cbrp and h_cbwp fields to calculate the number of valid entries in the h_cb to read or number of entries available for write. this field is a read only version of h_cbd_merwa field which is programmed by the me firmware during me initialization. programer's note: this field is implemented with a "1- hot" scheme. only one bit will be set to a 1 at a time. each bit position represents the value n of a buffer depth of (2^n). for example, when bit 0 is 1, the buffer depth is 1; when bit 1 is 1, the buffer de pth is 2, etc. the allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128. this field is re set by merst#. 23:16 ro 00h core host cb write pointer (h_cbwp): this field points to next location in the h_cb for host to write the data. software uses this field al ong with h_cbrp and h_cbd fields to calculate the number of valid entries in the h_cb to read or number of entries available for write. 15:8 ro 00h core host cb read pointer (h_cbrp): this field points to next location in the h_cb wher e a valid data is available for embedded controller to read. so ftware uses this field along with h_cbwr and h_cbd fields to calculate the number of valid entries in the host cb to read or number of entries available for write. 7:5 ro 000b core reserved 4r/w 0b core host reset (h_rst): setting this bit to 1 will initiate a heci reset sequence to get the circular buffers into a known good state for host an d me communication. when this bit transitions from 0 to 1, hardware will clear the h_rdy and me_rdy bits. 3r/w 0b core host ready (h_rdy): this bit indicates that the host is ready to process messages. intel ? manageability engine subsystem registers 346 datasheet 10.4.3 me_cb_rw? me circ ular buffer read window b/d/f/type: 0/3/1/mmio address offset: 8-bh default value: ffffffffh access: ro size: 32 bits this register is for host to read from the me circular buffer (me_cb). the me's circular buffer is located at the me subsystem address specified in the me cb base address register. 2r/w 0b core host interrupt generate (h_ig): once message(s) are written into its cb, the host sets this bit to 1 for the hardware to set the me_is bit in the me_csr and to generate an interrupt message to me. hardware will send the interrupt message to me only if the me_ie is enabled. hardware then clears this bit to 0. 1r/wc 0b core host interrupt status (h_is): hardware sets this bit to 1 when me_ig bit is set to 1. host clears this bit to 0 by writing a 1 to this bit position . h_ie has no e ffect on this bit. 0r/w 0b core host interrupt enable (h_ie): the host sets this bit to 1 to enable the host interru pt (intr# or msi) to be asserted when h_is is set to 1. bit access default value rst/pwr description bit access default value rst/pwr description 31:0 ro ffffffffh core me circular buffer read window field (me_cb_rwf): this bit field is for host to read from the me circular buffer. the me's circular buffer is located at the me subsystem address specified in the me cb base address register. this field is read only, writes have no effect. reads to this register will increment the me_cbrp as long as me_rdy is 1. when me_rdy is 0, reads to this register have no effect, all 1s are returned, and me_cbrp is not incremented. datasheet 347 intel ? manageability engine subsystem registers 10.4.4 me_csr_ha? me control status host access b/d/f/type: 0/3/1/mmio address offset: c-fh default value: 02000000h access: ro size: 32 bits this register allows host software to read the me control status register (me_csr). this register is reset by merst#. bit access default value rst/pwr description 31:24 ro 02h core me circular buffer depth host read access (me_cbd_hra): host read only access to me_cbd. 23:16 ro 00h core me cb write pointer host read access (me_cbwp_hra): host read only access to me_cbwp. 15:8 ro 00h core me cb read pointer host read access (me_cbrp_hra): host read only access to me_cbrp. 7:5 ro 000b core reserved 4ro 0b core me reset host read access (me_rst_hra): host read access to me_rst. 3ro 0b core me ready host read access (me_rdy_hra): host read access to me_rdy. 2ro 0b core me interrupt generate host read access (me_ig_hra): host read only access to me_ig. 1ro 0b core me interrupt status host read access (me_is_hra): host read only access to me_is. 0r o 0 b c o r e me interrupt enable host read access (me_ie_hra): host read only access to me_ie. intel ? manageability engine subsystem registers 348 datasheet 10.5 ide function for remote boot and installations pt ider registers table 21. ide function for remo te boot and installations pt ider register address map address offset register symbol register name default value access 0?3h id identification 2e068086h ro 4?5h cmd command register 0000h ro, r/w 6?7h sts device status 00b0h ro 8h rid revision id see register description ro 9?bh cc class codes 010185h ro ch cls cache line size 00h ro dh mlt master latency timer 00h ro 10?13h pcmdba primary command block io bar 00000001h ro, r/w 14?17h pctlba primary control block base address 00000001h ro, r/w 18?1bh scmdba secondary command block base address 00000001h ro, r/w 1c?1fh sctlba secondary control block base address 00000001h ro, r/w 20?23h lbar legacy bus master base address 00000001h ro, r/w 2c?2fh ss sub system identifiers 00008086h r/wo 30?33h erom expansion rom base address 00000000h ro 34h cap capabiliti es pointer c8h ro 3c?3dh intr interrupt information 0300h r/w, ro 3eh mgnt minimum grant 00h ro 3fh mlat maximum latency 00h ro c8?c9h pid pci power management capability id d001h ro ca?cbh pc pci power management capabilities 0023h ro cc?cfh pmcs pci power management control and status 00000000h ro, r/w, ro/v d0?d1h mid message signaled interrupt capability id 0005h ro d2?d3h mc message signaled interrupt message control 0080h ro, r/w d4?d7h ma message signaled interrupt message address 00000000h r/w, ro d8?dbh mau message signaled inte rrupt message upper address 00000000h ro, r/w dc?ddh md message signaled interrupt message data 0000h r/w datasheet 349 intel ? manageability engine subsystem registers 10.5.1 id?identification b/d/f/type: 0/3/2/pci address offset: 0-3h default value: 2e068086h access: ro size: 32 bits this register, combined with the device identification register, uniquely identifies any pci device. 10.5.2 cmd?command register b/d/f/type: 0/3/2/pci address offset: 4-5h default value: 0000h access: ro, r/w size: 16 bits reset: host system reset or d3->d0 transition of function. this register provides basic control over the device's ability to respond to and perform host system related acesses. bit access default value rst/pwr description 31:16 ro 2e06h core device id (did): assigned by manufacturer, identifies the type of device 15:0 ro 8086h core vendor id (vid): 16-bit field which indicates intel is the vendor, assigned by the pci sig. bit access default value rst/pwr description 15:11 ro 00h core reserved 10 r/w 0b core interrupt di sable (id): this disables pin-based intx# interrupts. this bit has no e ffect on msi operation. when set, internal intx# messages wi ll not be generated. when cleared, internal intx# messages are generated if there is an interrupt and msi is not enabled. 9ro 0b core fast back-to-back enable (fbe) : reserved 8ro 0b core serr# enable (see): the pt function never generates an serr#. reserved 7ro 0b core wait cycle enable (wcc): reserved 6ro 0b core parity error response enable (pee): no parity detection in pt fu nctions. reserved 5r o 0 b c o r e vga palette snooping enable (vga): reserved 4r o 0 b c o r e memory write and invalidate enable (mwie): reserved 3r o 0 b c o r e special cycle enable (sce): reserved intel ? manageability engine subsystem registers 350 datasheet 10.5.3 sts?device status b/d/f/type: 0/3/2/pci address offset: 6-7h default value: 00b0h access: ro size: 16 bits this register is used by the function to reflect its pci status to the host for the functionality that it implements. 2r/w 0b core bus master enable (bme): this bit controls the pt function's ability to act as a ma ster for data transfers. this bit does not impact the genera tion of completions for split transaction commands. 1ro 0b core memory space enable (mse): pt function does not contain target memory space. 0r/w 0b core i/o space enable (iose): this bit controls access to the pt function's ta rget i/o space. bit access default value rst/pwr description bit access default value rst/pwr description 15 ro 0b core detected parity error (dpe): no parity error on its interface. 14 ro 0b core signaled system error (sse): the pt function will never generate an serr#. 13 ro 0b core received master-abort status (rma): reserved 12 ro 0b core received target-abort status (rta): reserved 11 ro 0b core signaled target-abort status (sta): the pt function will never generate a target abort. reserved 10:9 ro 00b core devsel# timing status (devt): this bit controls the device select time for the pt function's pci interface. 8ro 0b core master data parity error detected) (dpd): pt function (ider), as a master, does not detect a parity error. other pt function is not a master an d hence this bit is reserved also. 7ro 1b core fast back to back capable: reserved 6 ro 0b core reserved 5ro 1b core 66mhz capable: reserved 4ro 1b core capabilities list (cl): this bit indicates that there is a capabilities pointer impl emented in the device. 3r o 0 b c o r e interrupt status (is): this bit reflects the state of the interrupt in the func tion. setting of th e interrupt disable bit to 1 has no affect on this bit. only when this bit is a 1 and id bit is 0 is the intc in terrupt asserted to the host. 2:0 ro 000b core reserved datasheet 351 intel ? manageability engine subsystem registers 10.5.4 rid?revision id b/d/f/type: 0/3/2/pci address offset: 8h default value: 02hsee description below access: ro size: 8 bits this register specifies a device specific revision. 10.5.5 cc?class codes b/d/f/type: 0/3/2/pci address offset: 9-bh default value: 010185h access: ro size: 24 bits this register identifies the basic functionality of the device ie ide mass storage. 10.5.6 cls?cache line size b/d/f/type: 0/3/2/pci address offset: ch default value: 00h access: ro size: 8 bits this register defines the system cache line size in dword increments. mandatory for master which use the memory-write and invalidate command. bit access default value rst/pwr description 7:0 ro see description core revision id. refer to the intel ? 4 series chipset family specification update for the value of this register. bit access default value rst/pwr description 23:0 ro 010185h core programming interface bcc scc (pi bcc scc): bit access default value rst/pwr description 7:0 ro 00h core cache line size (cls): all writes to system memory are memory writes. intel ? manageability engine subsystem registers 352 datasheet 10.5.7 mlt?master latency timer b/d/f/type: 0/3/2/pci address offset: dh default value: 00h access: ro size: 8 bits this register defines the minimum number of pci clocks the bus master can retain ownership of the bus whenever it initiates new transactions. 10.5.8 pcmdba?primary command block io bar b/d/f/type: 0/3/2/pci address offset: 10-13h default value: 00000001h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition of the function this 8-byte i/o space is used in native mode for the primary controller's command block ie bar0 bit access default value rst/pwr description 7:0 ro 00h core master latency timer (mlt): not implemented since the function is in (g)mch. bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:3 r/w 0000h core base address (bar): base address of the bar0 i/o space (8 consecutive i/o locations). 2:1 ro 00b core reserved 0r o 1 b c o r e resource type indicator (rte): this bit indicates a request for i/o space. datasheet 353 intel ? manageability engine subsystem registers 10.5.9 pctlba?primary cont rol block base address b/d/f/type: 0/3/2/pci address offset: 14-17h default value: 00000001h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition of the function this 4-byte i/o space is used in native mo de for the primary controller's control block ie bar1 10.5.10 scmdba?secondary command block base address b/d/f/type: 0/3/2/pci address offset: 18-1bh default value: 00000001h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition of the function this 8-byte i/o space is used in native mode for the secondary controller's command block. secondary channel is not implemen ted and reads return 7f7f7f7fh and all writes are ignored. bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:2 r/w 0000h core base address (bar): base address of the bar1 i/o space (4 consecutive i/o locations) 1 ro 0b core reserved 0r o 1 b c o r e resource type indicator (rte): this bit indicates a request for i/o space bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:3 r/w 0000h core base address (bar): base address of the i/o space (8 consecutive i/o locations). 2:1 ro 00b core reserved 0r o 1 b c o r e resource type indicator (rte): this bit indicates a request for i/o space. intel ? manageability engine subsystem registers 354 datasheet 10.5.11 sctlba?secondary co ntrol block base address b/d/f/type: 0/3/2/pci address offset: 1c-1fh default value: 00000001h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition this 4-byte i/o space is used in native mo de for secondary controller's control block. secondary channel is not implemented and reads return 7f7f7f7fh and all writes are ignored. 10.5.12 lbar?legacy bus master base address b/d/f/type: 0/3/2/pci address offset: 20-23h default value: 00000001h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition this bar is used to allocate i/o space for the sff-8038i mode of operation (aka bus master ide). bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:2 r/w 0000h core base address (bar): base address of the i/o space (4 consecutive i/o locations). 1 ro 0b core reserved 0r o 1 b c o r e resource type indicator (rte): this bit indicates a request for i/o space. bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:4 r/w 000h core base address (ba): base address of the i/o space (16 consecutive i/o locations). 3:1 ro 000b core reserved 0r o 1 b c o r e resource type indicator (rte): this bit indicates a request for i/o space. datasheet 355 intel ? manageability engine subsystem registers 10.5.13 ss?sub system identifiers b/d/f/type: 0/3/2/pci address offset: 2c-2fh default value: 00008086h access: r/wo size: 32 bits reset: host system reset these registers are used to uniquely identify the add-in card or the subsystem that the device resides within. 10.5.14 erom?expansion rom base address b/d/f/type: 0/3/2/pci address offset: 30-33h default value: 00000000h access: ro size: 32 bits this optional register is not implemented. 10.5.15 cap?capabilities pointer b/d/f/type: 0/3/2/pci address offset: 34h default value: c8h access: ro size: 8 bits this optional register is used to point to a linked list of new capabilities implemented by the device. bit access default value rst/pwr description 31:16 r/wo 0000h core subsystem id (ssid): this is written by bios. no hardware action taken on this value 15:0 r/wo 8086h core subsystem vendor id (ssvid): this is written by bios. no hardware action taken on this value bit access default value rst/pwr description 31:11 ro 000000h core expansion rom base address (erbar): 10:1 ro 000h core reserved 0ro 0b core enable (en): enable expansion rom access. bit access default value rst/pwr description 7:0 ro c8h core capability pointer (cp): this field indicate s that the first capability pointer is offset c8h (the power management capability). intel ? manageability engine subsystem registers 356 datasheet 10.5.16 intr?interrupt information b/d/f/type: 0/3/2/pci address offset: 3c-3dh default value: 0300h access: r/w, ro size: 16 bits reset: host system reset or d3->d0 reset of the function see definitions in the registers below 10.5.17 mgnt?minimum grant b/d/f/type: 0/3/2/pci address offset: 3eh default value: 00h access: ro size: 8 bits this optional register is not implemented. 10.5.18 mlat?maximum latency b/d/f/type: 0/3/2/pci address offset: 3fh default value: 00h access: ro size: 8 bits this optional register is not implemented. bit access default value rst/pwr description 15:8 ro 03h core interrupt pin (ipin): a value of 0x1/0x2/0x3/0x4 indicates that this function implements legacy interrupt on inta/intb/intc/intd, respectively function value intx (2 ide) 03h intc 7:0 r/w 00h core interrupt line (iline): the value written in this register indicates which input of the system interrupt controller, the device's interrupt pin is connec ted to. this value is used by the os and the device driver, and has no affect on the hardware. bit access default value rst/pwr description 7:0 ro 00h core reserved bit access default value rst/pwr description 7:0 ro 00h core reserved datasheet 357 intel ? manageability engine subsystem registers 10.5.19 pid?pci power mana gement capability id b/d/f/type: 0/3/2/pci address offset: c8-c9h default value: d001h access: ro size: 16 bits 10.5.20 pc?pci power ma nagement capabilities b/d/f/type: 0/3/2/pci address offset: ca-cbh default value: 0023h access: ro size: 16 bits this register implements the power management capabilities of the function. bit access default value rst/pwr description 15:8 ro d0h core next capability (next): its value of d0h points to the msi capability. 7:0 ro 01h core cap id (cid): this field indicates that this pointer is a pci power management. bit access default value rst/pwr description 15:11 ro 00000b core pme support (pme): this field indicates no pme# in the pt function 10 ro 0b core d2 support (d2s): the d2 state is not supported 9ro 0b core d1 support (d1s): the d1 state is not supported 8:6 ro 000b core aux current (auxc): pme# from d3 (cold) state is not supported, therefore this field is 000b 5ro 1b core device specific initialization (dsi): this bit indicates that no device-specific initialization is required. 4 ro 0b core reserved 3ro 0b core pme clock (pmec): this bit indicates th at pci clock is not required to generate pme#. 2:0 ro 011b core version (vs): this field indicates support for revision 1.2 of the pci power management specification . intel ? manageability engine subsystem registers 358 datasheet 10.5.21 pmcs?pci power mana gement control and status b/d/f/type: 0/3/2/pci address offset: cc-cfh default value: 00000000h access: ro, r/w, ro/v size: 32 bits bios optimal default 0000h reset: host system reset or d3->d0 transition this register implements the pci pm control and status register to allow pm state transitions and wake up note: nsr bit of this register. all registers (pci configuration and device specific) marked with d3->d0 transition reset will only do so if the nsr bit reads a 0. if this bit is a 1, the d3->d0 transition will not reset the registers. bit access default value rst/pwr description 31:16 ro 0h reserved 15 ro 0b core pme status (pmes): this bit is set when a pme event is to be requested. not supported 14:9 ro 00h core reserved 8ro 0b core pme enable (pmee): not supported 7:4 ro 0000b core reserved 3ro/v 0b core no soft reset (nsr): when set to 1, this bit indicates that devices transitioning from d3hot to d0 because of powerstate commands do not perform an inte rnal reset. configuration context is pres erved. upon transition from the d3hot to the d0 initialized state, no additional operating system intervention is required to preserve configuration context beyond writing the powerstate bits. when cleared to 0, devices do perform an internal reset upon transitioning from d3hot to d0 via software control of the powerstate bits. configur ation context is lost when performing the soft reset. upon transition from the d3hot to the d0 state, full re-initial ization sequence is needed to return the device to d0 initialized. value in this bit is reflects chicken bit in me-aux register x13900, bit [7] which is as follows: 0 = device performs internal reset 1 = device does not pe rform internal reset 2 ro 0b core reserved 1:0 r/w 00b core power state (ps): this field is used both to determine the current power state of the pt function and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller's configuration space is available, but the i/ o and memory spaces are not. additionally, interrupts are blocked. if software attempts to write a '10' or '01' to these bits, the write will be ignored. datasheet 359 intel ? manageability engine subsystem registers 10.5.22 mid?message signaled interrupt capability id b/d/f/type: 0/3/2/pci address offset: d0-d1h default value: 0005h access: ro size: 16 bits message signalled interrupt is a feature that allows the device/function to generate an interrupt to the host by performing a dword memory write to a system specified address with system specified data. this register is used to identify and configure an msi capable device. 10.5.23 mc?message signaled interrupt message control b/d/f/type: 0/3/2/pci address offset: d2-d3h default value: 0080h access: ro, r/w size: 16 bits reset: host system reset or d3->d0 transition this register provides system software control over msi. bit access default value rst/pwr description 15:8 ro 00h core next pointer (next): this value indicates this is the last item in the capabilities list. 7:0 ro 05h core capability id (cid): the capabilities id value indicates device is capable of generating an msi. bit access default value rst/pwr description 15:8 ro 00h core reserved 7ro 1b core 64 bit address capable (c64): capable of generating 64-bit and 32-bit messages. 6:4 r/w 000b core multiple message enable (mme): these bits are r/w for software compatibility, but on ly one message is ever sent by the pt function. 3:1 ro 000b core multiple message capable (mmc): only one message is required. 0r/w 0b core msi enable (msie): if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. intel ? manageability engine subsystem registers 360 datasheet 10.5.24 ma?message signaled interrupt message address b/d/f/type: 0/3/2/pci address offset: d4-d7h default value: 00000000h access: r/w, ro size: 32 bits reset: host system reset or d3->d0 transition this register specifies the dword aligned ad dress programmed by system software for sending msi. 10.5.25 mau?message signaled in terrupt message upper address b/d/f/type: 0/3/2/pci address offset: d8-dbh default value: 00000000h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition upper 32 bits of the message address for the 64bit address capable device. 10.5.26 md?message signaled interrupt message data b/d/f/type: 0/3/2/pci address offset: dc-ddh default value: 0000h access: r/w size: 16 bits reset: host system reset or d3->d0 transition this 16-bit field is programmed by system software if msi is enabled. bit access default value rst/pwr description 31:2 r/w 00000000h core address (addr): this field contains the lower 32 bits of the system specified message address, always dword aligned 1:0 ro 00b core reserved bit access default value rst/pwr description 31:4 ro 0000000h core reserved 3:0 r/w 0000b core address (addr): this field contains the upper 4 bits of the system specified message address. bit access default value rst/pwr description 15:0 r/w 0000h core data (data): this content is driven onto the lower word of the data bus of the msi memory write transaction. datasheet 361 intel ? manageability engine subsystem registers 10.6 ide bar0 table 22. ide bar0 re gister address map address offset register symbol register name default value access 0h idedata ide data register 00h r/w 1h ideerd1 ide error register dev1 00h r/w/v 1h ideerd0 ide error register dev0 00h r/w/v 1h idefr ide features register 00h r/w/v 2h idescir ide sector co unt in register 00h r/w/v 2h idescor1 ide sector count ou t register device 1 00h r/w/v 2h idescor0 ide sector count ou t register device 0 00h r/w/v 3h idesnor0 ide sector number out register device 0 00h r/w/v 3h idesnor1 ide sector number out register device 1 00h r/w/v 3h idesnir ide sector number in register 00h r/w/v 4h ideclir ide cylinder low in register 00h r/w/v 4h idclor1 ide cylinder low ou t register device 1 00h r/w/v 4h idclor0 ide cylinder low ou t register device 0 00h r/w/v 5h idchor0 ide cylinder high ou t register device 0 00h r/w/v 5h idchor1 ide cylinder high ou t register device 1 00h r/w/v 5h idechir ide cylinder hi gh in register 00h r/w/v 6h idedhir ide drive/head in register 00h r/w/v 6h iddhor1 ide drive head out register device 1 00h r/w/v 6h iddhor0 ide drive head out register device 0 00h r/w/v 7h idesd0r ide status device 0 register 80h r/w/v 7h idesd1r ide status device 1 register 80h r/w/v 7h idecr ide comman d register 00h r/w/v intel ? manageability engine subsystem registers 362 datasheet 10.6.1 idedata?ide data register b/d/f/type: 0/3/2/ide io bar0 address offset: 0h default value: 00h access: r/w size: 8 bits the ide data interface is a special interface that is implemented in the hw. this data interface is mapped to io space from the host and takes read and write cycles from the host targeting master or slave device. writes from host to this register result in the data being written to me memory. reads from host to this register result in the data being fetched from me memory. data is typically written/ read in word's. me-fw must enable hardware to allow it to accept host initiated read/ write cycles, else the cycles are dropped. 10.6.2 ideerd1?ide erro r register device 1 b/d/f/type: 0/3/2/ide io bar0 address offset: 1h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the error register of the command block of the ide function. this register is read only by the host interface when dev = 1 (slave device). when the host writes the same address it writes to the features register. bit access default value rst/pwr description 7:0 r/w 00h core ide data register (idedr): data register implements the data interface for ide. al l writes and reads to this register translate into one or more corresponding write/ reads to me memory bit access default value rst/pwr description 7:0 r/w/v 00h core ide error data (ideed): drive reflects its error/ diagnostic code to the host vi a this register at different times. datasheet 363 intel ? manageability engine subsystem registers 10.6.3 ideerd0?ide error register dev0 b/d/f/type: 0/3/2/ide io bar0 address offset: 1h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the error register of the command block of the ide function. this register is read only by the host interface when dev = 0 (master device). when the host writes the same address it writes to the features register. 10.6.4 idefr?ide features register b/d/f/type: 0/3/2/ide io bar0 address offset: 1h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the feature register of the command block of the ide function. this register can be written only by the host. when the host reads the same address, it reads the error register of device 0 or device 1 depending on the device_select bit (bit 4 of the drive/head register). bit access default value rst/pwr description 7:0 r/w/v 00h core ide error data (ideed): drive reflects its error/ diagnostic code to the host vi a this register at different times. bit access default value rst/pwr description 7:0 r/w/v 00h core ide feature data (idefd): ide drive specific data written by the host intel ? manageability engine subsystem registers 364 datasheet 10.6.5 idescir?ide sect or count in register b/d/f/type: 0/3/2/ide io bar0 address offset: 2h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the sector count register of the command block of the ide function. this register can be written only by the host. when host writes to this register, all 3 registers (idescir, idescor0, idescor1) are updated with the written value. a host read to this register address reads the ide sector count out register idescor0 if dev=0 or idescor1 if dev=1 10.6.6 idescor1?ide sector count out register dev1 b/d/f/type: 0/3/2/ide io bar0 address offset: 2h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read by the host interfac e if dev = 1. me-firmw are writes to this register at the end of a command of the selected device. when the host writes to this address, the id e sector count in register (idescir), this register is updated. bit access default value rst/pwr description 7:0 r/w/v 00h core ide sector count data (idescd): host writes the number of sectors to be read or written. bit access default value rst/pwr description 7:0 r/w/v 00h core ide sector count out dev1 (iscod1): sector count register for slave device ie device 1 datasheet 365 intel ? manageability engine subsystem registers 10.6.7 idescor0?ide sector co unt out register device 0 b/d/f/type: 0/3/2/ide io bar0 address offset: 2h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read by the host interfac e if dev = 0. me-firmware writes to this register at the end of a command of the selected device. when the host writes to this address, the id e sector count in register (idescir), this register is updated. 10.6.8 idesnor0?ide se ctor number out register device 0 b/d/f/type: 0/3/2/ide io bar0 address offset: 3h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read by the host if dev = 0. me-firmware writes to this register at the end of a command of the selected device. when the host writes to the ide sector number in register (idesnir), this register is updated with that value. bit access default value rst/pwr description 7:0 r/w/v 00h core ide sector count out dev0 (iscod0): sector count register for master device ie device 0. bit access default value rst/pwr description 7:0 r/w/v 00h core ide sector number out dev 0 (idesno0): sector number out register for master device. intel ? manageability engine subsystem registers 366 datasheet 10.6.9 idesnor1?ide sector numb er out regist er device 1 b/d/f/type: 0/3/2/ide io bar0 address offset: 3h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read by the host if dev = 1. me-firmware writes to this register at the end of a command of the selected device. when the host writes to the ide sector number in register (idesnir), this register is updated with that value. 10.6.10 idesnir?ide sector number in register b/d/f/type: 0/3/2/ide io bar0 address offset: 3h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the sector number register of the command block of the ide function. this register can be written only by the host. when host writes to this register, all 3 registers (idesnir, idesnor0 , idesnor1) are updated with the written value. host read to this register address reads the ide sector number out register idesnor0 if dev=0 or idesnor1 if dev=1. bit access default value rst/pwr description 7:0 r/w/v 00h core ide sector number out dev 1 (idesno1): sector number out register for slave device. bit access default value rst/pwr description 7:0 r/w/v 00h core ide sector number data (idesnd): this register contains the number of the fi rst sector to be transferred. datasheet 367 intel ? manageability engine subsystem registers 10.6.11 ideclir?ide cylinder low in register b/d/f/type: 0/3/2/ide io bar0 address offset: 4h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the cylinder low register of the command block of the ide function. this register can be written only by the host. when host writes to this register, all 3 registers (ideclir, ideclor0 , ideclor1) are updated with the written value. host read to this register address reads the ide cylinder low out register ideclor0 if dev=0 or ideclor1 if dev=1. 10.6.12 idclor1?ide cylinder lo w out register device 1 b/d/f/type: 0/3/2/ide io bar0 address offset: 4h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read by the host if dev = 1. me-firmware writes to this register at the end of a command of the selected device. when the host writes to the ide cylinder low in register (ideclir), this register is updated with that value. bit access default value rst/pwr description 7:0 r/w/v 00h core ide cylinder low data (idecld): cylinder low register of the command block of the ide function. bit access default value rst/pwr description 7:0 r/w/v 00h core ide cylinder low out dev 1. (ideclo1): cylinder low out register for slave device. intel ? manageability engine subsystem registers 368 datasheet 10.6.13 idclor0?ide cylinder low out register device 0 b/d/f/type: 0/3/2/ide io bar0 address offset: 4h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read by the host if dev = 0. me-firmware writes to this register at the end of a command of the select ed device. when the host writes to the ide cylinder low in register (ideclir), this register is updated with that value. 10.6.14 idchor0?ide cylinder high out register device 0 b/d/f/type: 0/3/2/ide io bar0 address offset: 5h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read by the host if device = 0. me-firmware writes to this register at the end of a command of the selected device . when the host writes to the ide cylinder high in register (idechir), this register is updated with that value. bit access default value rst/pwr description 7:0 r/w/v 00h core ide cylinder low out dev 0. (ideclo0): cylinder low out register for master device. bit access default value rst/pwr description 7:0 r/w/v 00h core ide cylinder high out dev 0 (idecho0): cylinder high out register for master device. datasheet 369 intel ? manageability engine subsystem registers 10.6.15 idchor1?ide cylinder hi gh out register device 1 b/d/f/type: 0/3/2/ide io bar0 address offset: 5h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read by the host if device = 1. me-firmware writes to this register at the end of a command of the selected device . when the host writes to the ide cylinder high in register (idechir), this register is updated with that value. 10.6.16 idechir?ide cylinder high in register b/d/f/type: 0/3/2/ide io bar0 address offset: 5h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the cylinder high register of the command block of the ide function. this register can be written only by the host. when host writes to this register, all 3 registers (idechir, idechor0 , idechor1) are updated with the written value. host read to this register address reads the ide cylinder high out register idechor0 if dev=0 or idechor1 if dev=1. bit access default value rst/pwr description 7:0 r/w/v 00h core ide cylinder high out dev 1 (idecho1): cylinder high out register for slave device. bit access default value rst/pwr description 7:0 r/w/v 00h core ide cylinder high data (idechd): cylinder high data register for ide command block. intel ? manageability engine subsystem registers 370 datasheet 10.6.17 idedhir?ide driv e/head in register b/d/f/type: 0/3/2/ide io bar0 address offset: 6h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the drive/head register of the command block of the ide. this register can be written only by the host. when host writes to this register, all 3 registers (idedhir, idedhor0, idedhor1 ) are updated with the written value. host read to this register address reads the ide drive/head out register (idedhor0) if dev=0 or idedhor1 if dev=1. bit 4 of this register is the dev (master/slav e) bit. this bit is cleared by hardware on ide software reset (s_rst toggles to '1') in addition to host system reset and d3->d0 transition of the function. 10.6.18 iddhor1?ide drive head out register device 1 b/d/f/type: 0/3/2/ide io bar0 address offset: 6h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read only by the host. host read to this drive/head in register address reads the ide drive/head out register (idedhor0) if dev=1 bit 4 of this register is the dev (master/slav e) bit. this bit is cleared by hardware on ide software reset (s_rst toggles to '1') in addition to the host system reset and d3 to d0 transition of the ide function. when the host writes to this address, it updates the value of the idedhir register. bit access default value rst/pwr description 7:0 r/w/v 00h core ide drive/head data (idedhd): register defines the drive number, head number and addressing mode. bit access default value rst/pwr description 7:0 r/w/v 00h core ide drive head out dev 1 (idedho1): drive/head out register of slave device. datasheet 371 intel ? manageability engine subsystem registers 10.6.19 iddhor0?ide drive head out register device 0 b/d/f/type: 0/3/2/ide io bar0 address offset: 6h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register is read only by the host. host read to this drive/head in register address reads the ide drive/head out register (idedhor0) if dev=0. bit 4 of this register is the dev (master/slave) bit. this bit is cleared by hardware on ide software reset (s_rst toggles to 1) in addition to the host system reset and d3 to d0 transition of the ide function. when the host writes to this address, it updates the value of the idedhir register. bit access default value rst/pwr description 7:0 r/w/v 00h core ide drive head out dev 0 (idedho0): drive/head out register of master device. intel ? manageability engine subsystem registers 372 datasheet 10.6.20 idesd0r?ide status device 0 register b/d/f/type: 0/3/2/ide io bar0 address offset: 7h default value: 80h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the status register of the master device (dev = 0). this register is read only by the host. host read of this register clears the master device's interrupt. when the host writes to the same address it writes to the command register the bits description is for ata mode. bit access default value rst/pwr description 7 r/w/v 1b core busy (bsy): this bit is set by hw when the idecr is being written and dev=0, or wh en srst bit is asserted by host or host system reset or d3-to-d0 transition of the ide function. this bit is cleared by fw write of 0. 6 r/w/v 0b core drive ready (drdy): when set, this bit indicates drive is ready for command. 5 r/w/v 0b core drive fault (df): indicates error on the drive. 4 r/w/v 0b core drive seek complete (dsc): indicates heads are positioned over the desired cylinder. 3 r/w/v 0b core data request (drq): set when, the drive wants to exchange data with the ho st via the data register. 2 r/w/v 0b core corrected data (corr): when set, this bit indicates a correctable read error has occurred. 1 r/w/v 0b core index (idx): this bit is set once per rotation of the medium when the index mark passes under the read/write head. 0 r/w/v 0b core error (err): when set, this bit indicates an error occurred in the process of executing the previous command. the error register of the selected device contains the error information. datasheet 373 intel ? manageability engine subsystem registers 10.6.21 idesd1r?ide status device 1 register b/d/f/type: 0/3/2/ide io bar0 address offset: 7h default value: 80h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition this register implements the status register of the slave device (dev = 1). this register is read only by the host. host read of this register clears the slave device's interrupt. when the host writes to the same address it writes to the command register. the bits description is for ata mode. bit access default value rst/pwr description 7 r/w/v 1b core busy (bsy): this bit is set by hardware when the idecr is being written and dev=0, or when srst bit is asserted by the host or host system re set or d3-to-d0 transition of the ide function. this bit is cleared by fw write of 0. 6 r/w/v 0b core drive ready (drdy): when set, indicates drive is ready for command. 5 r/w/v 0b core drive fault (df): indicates error on the drive. 4 r/w/v 0b core drive seek complete (dsc): indicates heads are positioned over the desired cylinder. 3 r/w/v 0b core data request (drq): set when the drive wants to exchange data with the ho st via the data register. 2 r/w/v 0b core corrected data (corr): when set indicates a correctable read error has occurred. 1 r/w/v 0b core index (idx): this bit is set once per rotation of the medium when the index mark passes under the read/write head. 0 r/w/v 0b core error (err): when set, this bit indicates an error occurred in the process of executing the previous command. the error register of the selected device contains the error information intel ? manageability engine subsystem registers 374 datasheet 10.6.22 idecr?ide command register b/d/f/type: 0/3/2/ide io bar0 address offset: 7h default value: 00h access: r/w/v size: 8 bits reset: host system reset and d3->d0 transition this register implements the command register of the command block of the ide function. this register can be written only by the host. when the host reads the same address it re ads the status register dev0 if dev=0 or status register dev1 if dev=1 (drive/head register bit [4]). bit access default value rst/pwr description 7:0 r/w/v 00h core ide command data (idecd): host sends the commands (read/ write, etc.) to the drive via this register. datasheet 375 intel ? manageability engine subsystem registers 10.7 ide bar1 10.7.1 iddcr?ide device control register b/d/f/type: 0/3/2/ide io bar1 address offset: 2h default value: 00h access: ro, wo size: 8 bits reset: host system reset or d3->d0 transition this register implements the device control register of the control block of the ide function. this register is write only by the host. when the host reads to the same address it reads the alternate status register. address offset register symbol register name default value access 2h iddcr ide device control register 00h ro, wo 2h idasr ide alternate st atus register 00h ro/v bit access default value rst/pwr description 7:3 ro 00000b core reserved: writable by host, bu t no hardware affect due to writes. 2wo 0b core software reset (s_rst): when this bit is set by the host, it forces a reset to the device. 1wo 0b core host interrupt disable (nien): when set, this bit disables hardware from send ing interrupt to the host. 0ro 0b core reserved: writable by host, bu t no hardware affect due to writes intel ? manageability engine subsystem registers 376 datasheet 10.7.2 idasr?ide alternate status register b/d/f/type: 0/3/2/ide io bar1 address offset: 2h default value: 00h access: ro/v size: 8 bits reset: this is not a physical register hence no reset associated with it. this register implements the alternate status register of the control block of the ide function. this register is a mirror register to the status register in the command block. reading this register by the host does not clear the ide interrupt of the dev selected device host read of this register when dev=0 (master), host gets the mirrored data of idesd0r register. host read of this register when dev=1 (slave), host gets the mirrored data of idesd1r register. bit access default value rst/pwr description 7:0 ro/v 00h core ide alternate status register (ideasr): this field mirrors the value of the de v0/ dev1 status register, depending on the state of the dev bit on host reads. datasheet 377 intel ? manageability engine subsystem registers 10.8 ide bar4 table 23. ide bar4 re gister address map address offset register symbol register name default value access 0h idepbmcr ide primary bus master command register 00h ro, r/w 1h idepbmds0r ide primary bus master device specific 0 register 00h r/w 2h idepbmsr ide primary bus master status register 80h ro, r/w, r/wc 3h idepbmds1r ide primary bus master device specific 1 register 00h r/w 4h idepbmdtpr0 ide primary bus master descriptor table pointer register byte 0 00h r/w 5h idepbmdtpr1 ide primary bus master descriptor table pointer register byte 1 00h r/w 6h idepbmdtpr2 ide primary bus master descriptor table pointer register byte 2 00h r/w 7h idepbmdtpr3 ide primary bus master descriptor table pointer register byte 3 00h r/w 8h idesbmcr ide secondary bus master command register 00h ro, r/w 9h idesbmds0r ide secondary bus master device specific 0 register 00h r/w ah idesbmsr ide secondary bus master status register 00h r/w, ro bh idesbmds1r ide secondary bus master device specific 1 register 00h r/w ch idesbmdtpr0 ide secondary bus master descriptor table pointer register byte 0 00h r/w dh idesbmdtpr1 ide secondary bus master descriptor table pointer register byte 1 00h r/w eh idesbmdtpr2 ide secondary bus master descriptor table pointer register byte 2 00h r/w fh idesbmdtpr3 ide secondary bus master descriptor table pointer register byte 3 00h r/w intel ? manageability engine subsystem registers 378 datasheet 10.8.1 idepbmcr?ide primary bu s master command register b/d/f/type: 0/3/2/ide io bar4 address offset: 0h default value: 00h access: ro, r/w size: 8 bits reset: see specific bits. this register implements the bus master command register of the primary channel. this register is programmed by the host. 10.8.2 idepbmds0r?ide primary bu s master device specific 0 register b/d/f/type: 0/3/2/ide io bar4 address offset: 1h default value: 00h access: r/w size: 8 bits reset: me system reset this register implements the bus master de vice specific 1 register of the primary channel. this register is programmed by the host. bit access default value rst/pwr description 7:4 ro 0h core reserved 3r/w 0b core read write command (rwc): this bit sets the direction of bus master transfer. 0 = reads are performed from system memory 1 = writes are performed to system memory. this bit should not be ch anged when the bus master function is active. reset: host system reset or d3->d0 transition 2:1 ro 00b core reserved 0r/w 0b core start/stop bus master (ssbm): this bit gates the bus master operation of ide function when 0. writing 1 enables the bus master operation. bus master operation can be halted by writing a 0 to th is bit. operation cannot be stopped and resumed. this bit is cleared after data transfer is complete as indicated by either the bmia bit or the int bit of the bus master status register is set or both are set. reset: host system reset or d3->d0 transition. bit access default value rst/pwr description 7:0 r/w 00h core device specific data0 (dsd0): device specific datasheet 379 intel ? manageability engine subsystem registers 10.8.3 idepbmsr?ide primary bu s master status register b/d/f/type: 0/3/2/ide io bar4 address offset: 2h default value: 80h access: ro, r/w, r/wc size: 8 bits reset: see bit definitions. this register implements the bus master status register of the primary channel. bit access default value rst/pwr description 7ro 1b core simplex only (so): value indicates whether both bus master channels can be operat ed at the same time or not. 0 = both can be operated independently 1 = only one can be operated at a time. reset: me system reset 6r/w 0b core drive 1 dma capable (d1dc): this bit is read/write by the host (not write 1 clear). reset: host system reset or d3->d0 transition of the function 5r/w 0b core drive 0 dma capable (d0dc): this bit is read/write by the host (not write 1 clear). reset: host system reset or d3->d0 transition of the function 4:3 ro 00b core reserved 2r/wc 0b core interrupt (int): this bit is set by th e hardware when it detects a positive transition in the interrupt logic (refer to ide host interrupt ge neration diagram).the hardware will clear this bit when the host sw writes 1 to it. reset: me system reset 1r/wc 0b core error (er): bit is typically set by fw. hardware will clear this bit when the host sw writes 1 to it. reset: me system reset 0r o 0 b c o r e bus master ide active (bmia): this bit is set by hardware when ssbm register is set to 1 by the host. when the bus master operation ends (for the whole command) this bit is cleared by fw. this bit is not cleared when the host writes 1 to it. reset: me system reset intel ? manageability engine subsystem registers 380 datasheet 10.8.4 idepbmds1r?ide primary bu s master device specific 1 register b/d/f/type: 0/3/2/ide io bar4 address offset: 3h default value: 00h access: r/w size: 8 bits reset: me system reset this register implements the bus master de vice specific 1 register of the primary channel. this register is programmed by th e host for device specific data if any. 10.8.5 idepbmdtpr0?ide primary bus master descriptor table pointer register byte 0 b/d/f/type: 0/3/2/ide io bar4 address offset: 4h default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition this register implements the byte 0 (1 of 4 bytes) of the descriptor table pointer (four i/o byte addresses) for bus master operation of the primary channel. this register is read/write by th e host interface. 10.8.6 idepbmdtpr1?ide primary bus master descriptor table pointer register byte 1 b/d/f/type: 0/3/2/ide io bar4 address offset: 5h default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition this register implements the byte 1 (of four bytes) of the descriptor table pointer (four i/o byte addresses) for bus master operation of the primary channel. this register is programmed by the host. bit access default value rst/pwr description 7:0 r/w 00h core device specific data1 (dsd1): device specific data. bit access default value rst/pwr description 7:0 r/w 00h core descriptor table pointer byte 0 (dtpb0): bit access default value rst/pwr description 7:0 r/w 00h core descriptor table pointer byte 1 (dtpb1): datasheet 381 intel ? manageability engine subsystem registers 10.8.7 idepbmdtpr2?ide primary bus master descriptor table pointer register byte 2 b/d/f/type: 0/3/2/ide io bar4 address offset: 6h default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition this register implements the byte 2 (of four bytes) of the descriptor table pointer (four i/o byte addresses) for bus master operation of the primary channel. this register is programmed by the host. 10.8.8 idepbmdtpr3?ide primary bus master descriptor table pointer register byte 3 b/d/f/type: 0/3/2/ide io bar4 address offset: 7h default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition this register implements the byte 3 (of four bytes) of the descriptor table pointer (four i/o byte addresses) for bus master operation of the primary channel. this register is programmed by the host bit access default value rst/pwr description 7:0 r/w 00h core descriptor table pointer byte 2 (dtpb2): bit access default value rst/pwr description 7:0 r/w 00h core descriptor table pointer byte 3 (dtpb3): intel ? manageability engine subsystem registers 382 datasheet 10.8.9 idesbmcr?ide secondary bus master command register b/d/f/type: 0/3/2/ide io bar4 address offset: 8h default value: 00h access: ro, r/w size: 8 bits reset: see specific bits this register implements the bus master command register of the secondary channel. this register is programmed by the host. 10.8.10 idesbmds0r?ide secondary bus master device specific 0 register b/d/f/type: 0/3/2/ide io bar4 address offset: 9h default value: 00h access: r/w size: 8 bits reset: me system reset this register implements the bus master de vice specific 1 register of the secondary channel. this register is programmed by the host. bit access default value rst/pwr description 7:4 ro 0h core reserved 3r/w 0b core read write command (rwc): this bit sets the direction of bus master transfer. when 0, reads are performed from system memory; when 1, writes are performed to system memory. this bit should not be changed when the bus master function is active. reset: host system reset or d3->d0 transition of function 2:1 ro 00b core reserved 0r/w 0b core start/stop bus master (ssbm): this bit gates the bus master operation of ide function when zero. writing 1 enables the bus master operation. bus master operation can be halted by writing a 0 to this bit. operation cannot be stopped and resumed. this bit is cleared after data transfer is complete as indicated by either the bmia bit or the int bit of the bus master status register is set or both are set. reset: host system reset or d3->d0 transition of function bit access default value rst/pwr description 7:0 r/w 00h core device specific data0 (dsd0): device specific datasheet 383 intel ? manageability engine subsystem registers 10.8.11 idesbmsr?ide secondary bus master status register b/d/f/type: 0/3/2/ide io bar4 address offset: ah default value: 00h access: r/w, ro size: 8 bits reset: see bit definitions this register implements the bus master status register of the secondary channel. 10.8.12 idesbmds1r?ide secondary bus master device specific 1 register b/d/f/type: 0/3/2/ide io bar4 address offset: bh default value: 00h access: r/w size: 8 bits reset: me system reset. this register implements the bus master device specific 1 register of the secondary channel. this register is programmed by the host for device specific data if any. bit access default value rst/pwr description 7r/w 0b core simplex only (so): this bit indicates whether both bus master channels can be operat ed at the same time or not. 0 = both can be operated independently 1 = only one can be operated at a time. reset: host system reset or d3->d0 transition. 6r/w 0b core drive 1 dma capable (d1dc): this bit is read/write by the host. reset: host system reset or d3->d0 transition of the function. 5r/w 0b core drive 0 dma capable (d0dc): this bit is read/write by the host. reset: host system reset or d3->d0 transition of the function. 4:3 ro 00b core reserved 2r/w 0b core interrupt (int): no functionality implemented. read/ write by host. reset: host system reset or d3->d0 transition. 1ro 0b core error (er): not implemented. 0ro 0b core bus master ide active (bmia): not implemented. bit access default value rst/pwr description 7:0 r/w 00h core device specific data1 (dsd1): device specific data. intel ? manageability engine subsystem registers 384 datasheet 10.8.13 idesbmdtpr0?ide second ary bus master descriptor table pointer register byte 0 b/d/f/type: 0/3/2/ide io bar4 address offset: ch default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition of the function. this register implements the byte 0 (1 of 4 bytes) of the descriptor table pointer (four i/o byte addresses) for bus master operation of the secondary channel. this register is read/write by th e host interface. 10.8.14 idesbmdtpr1?ide second ary bus master descriptor table pointer register byte 1 b/d/f/type: 0/3/2/ide io bar4 address offset: dh default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition of the function. this register implements the byte 1 (of four bytes) of the descriptor table pointer (four i/o byte addresses) for bus master operation of the secondary channel. this register is programmed by the host. 10.8.15 idesbmdtpr2?ide second ary bus master descriptor table pointer register byte 2 b/d/f/type: 0/3/2/ide io bar4 address offset: eh default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition of the function. this register implements the byte 2 (of four bytes) of the descriptor table pointer (four i/o byte addresses) for bus master operation of the secondary channel. this register is programmed by the host. bit access default value rst/pwr description 7:0 r/w 00h core descriptor table pointer byte 0 (dtpb0): bit access default value rst/pwr description 7:0 r/w 00h core descriptor table pointer byte 1 (dtpb1): bit access default value rst/pwr description 7:0 r/w 00h core descriptor table pointer byte 2 (dtpb2): datasheet 385 intel ? manageability engine subsystem registers 10.8.16 idesbmdtpr3?ide second ary bus master descriptor table pointer register byte 3 b/d/f/type: 0/3/2/ide io bar4 address offset: fh default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition of the function. this register implements the byte 3 (of four bytes) of the descriptor table pointer (four i/o byte addresses) for bus master operation of the secondary channel. this register is programmed by the host. bit access default value rst/pwr description 7:0 r/w 00h core descriptor table pointer byte 3 (dtpb3): intel ? manageability engine subsystem registers 386 datasheet 10.9 serial port for remote keyboard and text (kt) redirection table 24. serial port for remote keyboard an d text (kt) redirect ion register address map address offset register symbol register name default value access 0?3h id identification 2e078086h ro 4?5h cmd command register 0000h ro, r/w 6?7h sts device status 00b0h ro 8h rid revision id see register description ro 9?bh cc class codes 070002h ro ch cls cache line size 00h ro dh mlt master latency timer 00h ro eh htype header type not defined not defined fh bist built in self test not defined not defined 10?13h ktiba kt io block base address 00000001h ro, r/w 14?17h ktmba kt memory block base address 00000000h ro, r/w 2c?2fh ss sub system identifiers 00008086h r/wo 30?33h erom expansion rom base address 00000000h ro 34h cap capabilities pointer c8h ro 3c?3dh intr interrupt information 0200h r/w, ro 3eh mgnt minimum grant 00h ro 3fh mlat maximum latency 00h ro c8?c9h pid pci power management capability id d001h ro ca?cbh pc pci power management capabilities 0023h ro cc?cfh pmcs pci power management control and status 00000000h ro/v, ro, r/w d0?d1h mid message signaled interrupt capability id 0005h ro d2?d3h mc message signaled interrupt message control 0080h ro, r/w d4?d7h ma message signaled interrupt message address 00000000h ro, r/w d8?dbh mau message signaled interrupt message upper address 00000000h ro, r/w dc?ddh md message signaled interrupt message data 0000h r/w datasheet 387 intel ? manageability engine subsystem registers 10.9.1 id?identification b/d/f/type: 0/3/3/pci address offset: 0-3h default value: 2e078086h access: ro size: 32 bits this register, combined with the device identification register, uniquely identifies any pci device. 10.9.2 cmd?command register b/d/f/type: 0/3/3/pci address offset: 4-5h default value: 0000h access: ro, r/w size: 16 bits reset: host system reset or d3->d0 transition this register provides basic control over the device's ability to respond to and perform host system related accesses. bit access default value rst/pwr description 31:16 ro 2e07h core device id (did): assigned by manufacturer, identifies the device. 15:0 ro 8086h core vendor id (vid): 16-bit field which indicates intel is the vendor, assigned by the pci sig. bit access default value rst/pwr description 15:11 ro 00h core reserved 10 r/w 0b core interrupt di sable (id): this bit disables pin-based intx# interrupts. this bit has no effect on msi operation. 1 = internal intx# messages will not be generated. 0 = internal intx# messages are generated if there is an interrupt and msi is not enabled. 9ro 0b core fast back-to-back enable (fbe): reserved 8ro 0b core serr# enable (see): the pt function never generates an serr#. reserved 7ro 0b core wait cycle enable (wcc): reserved 6ro 0b core parity error response enable (pee): no parity detection in pt fu nctions. reserved 5ro 0b core vga palette snooping enable (vga): reserved 4ro 0b core memory write and invalidate enable (mwie): reserved 3ro 0b core special cycle enable (sce): reserved intel ? manageability engine subsystem registers 388 datasheet 10.9.3 sts?device status b/d/f/type: 0/3/3/pci address offset: 6-7h default value: 00b0h access: ro size: 16 bits this register is used by the function to reflect its pci status to the host for the functionality that it implements 2r/w 0b core bus master enable (bme): this bit controls the kt function's ability to act as a ma ster for data transfers. this bit does not impact the genera tion of completions for split transaction commands. for kt, the only bus mastering activity is msi generation. 1r/w 0b core memory space enable (mse): this bit controls access to the pt function's ta rget memory space. 0r/w 0b core i/o space enable (iose): this bit controls access to the pt function's ta rget i/o space. bit access default value rst/pwr description bit access default value rst/pwr description 15 ro 0b core detected parity error (dpe): no parity error on its interface. 14 ro 0b core signaled system error (sse): the pt function will never generate an serr#. 13 ro 0b core received master-abort status (rma): reserved 12 ro 0b core received target-abort status (rta): reserved 11 ro 0b core signaled target-abort status (sta): the pt function will never generate a target abort. reserved 10:9 ro 00b core devsel# timing status (devt): this field controls the device select time for the pt function's pci interface. 8ro 0b core master data parity error detected) (dpd): pt function (ider), as a master, does not detect a parity error. other pt function is not a master an d hence this bit is reserved also. 7ro 1b core fast back to back capable: reserved 6 ro 0b core reserved 5ro 1b core 66mhz capable: reserved 4ro 1b core capabilities list (cl): this bit indicates that there is a capabilities pointer impl emented in the device. 3r o 0 b c o r e interrupt status (is): this bit reflects the state of the interrupt in the func tion. setting of th e interrupt disable bit to 1 has no affect on this bit. only when this bit is a 1 and id bit is 0 is the intb in terrupt asserted to the host. 2:0 ro 000b core reserved datasheet 389 intel ? manageability engine subsystem registers 10.9.4 rid?revision id b/d/f/type: 0/3/3/pci address offset: 8h default value: 00hsee description below access: ro size: 8 bits this register specifies a device specific revision. 10.9.5 cc?class codes b/d/f/type: 0/3/3/pci address offset: 9-bh default value: 070002h access: ro size: 24 bits this register identifies the basic functionality of the device ie serial com port. 10.9.6 cls?cache line size b/d/f/type: 0/3/3/pci address offset: ch default value: 00h access: ro size: 8 bits this register defines the system cache line size in dword increments. mandatory for master which use the memory-write and invalidate command. bit access default value rst/pwr description 7:0 ro see description core revision id (rid): this field indicates stepping of the silicon. refer to the intel ? 4 series chipset family specification update for the value of this register. bit access default value rst/pwr description 23:0 ro 070002h core programming interface bcc scc (pi bcc scc): bit access default value rst/pwr description 7:0 ro 00h core cache line size (cls): all writes to system memory are memory writes. intel ? manageability engine subsystem registers 390 datasheet 10.9.7 mlt?master latency timer b/d/f/type: 0/3/3/pci address offset: dh default value: 00h access: ro size: 8 bits this register defines the minimum number of pci clocks the bus master can retain ownership of the bus whenever it initiates new transactions. 10.9.8 htype?header type b/d/f/type: 0/3/3/pci address offset: eh default value: < not defined > access: < not defined > size: 8 bits register is not implemented. reads return 0. 10.9.9 bist?built in self test b/d/f/type: 0/3/3/pci address offset: fh default value: not defined access: not defined size: 8 bits this optional register is not implemented. bit access default value rst/pwr description 7:0 ro 00h core master latency timer (mlt): not implemented since the function is in mch. datasheet 391 intel ? manageability engine subsystem registers 10.9.10 ktiba?kt io block base address b/d/f/type: 0/3/3/pci address offset: 10-13h default value: 00000001h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition. base address for the 8byte io space for kt. 10.9.11 ktmba?kt memory block base address b/d/f/type: 0/3/3/pci address offset: 14-17h default value: 00000000h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition base address of memory mapped space. bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:3 r/w 0000h core base address (bar): this field prov ides the base address of the i/o space (8 consecutive i/o locations). 2:1 ro 00b core reserved 0ro 1b core resource type indicator (rte): this bit indicates a request for i/o space bit access default value rst/pwr description 31:12 r/w 00000h core base address (bar): this field prov ides the base address for memory mappe d i,o bar. bits 31:12 correspond to address signals 31:12. 11:4 ro 00h core reserved 3r o 0 b c o r e prefetchable (pf): this bit indicates that this range is not pre-fetchable. 2:1 ro 00b core type (tp): this field indicates that this range can be mapped anywhere in 32-bit address space. 0r o 0 b c o r e resource type indicator (rte): this bit indicates a request for register memory space. intel ? manageability engine subsystem registers 392 datasheet 10.9.12 rsvd?reserved b/d/f/type: 0/3/3/pci address offset: 18-1bh default value: 00000000h access: ro size: 32 bits 10.9.13 rsvd?reserved b/d/f/type: 0/3/3/pci address offset: 1c-1fh default value: 00000000h access: ro size: 32 bits 10.9.14 rsvd?reserved b/d/f/type: 0/3/3/pci address offset: 20-23h default value: 00000000h access: ro size: 32 bits 10.9.15 rsvd?reserved b/d/f/type: 0/3/3/pci address offset: 24-28h default value: 0000000000h access: ro size: 40 bits bios optimal default 00h bit access default value rst/pwr description 31:0 ro 00000000h core reserved bit access default value rst/pwr description 31:0 ro 00000000h core reserved bit access default value rst/pwr description 31:0 ro 00000000h core reserved bit access default value rst/pwr description 39:32 ro 0h reserved 31:0 ro 00000000h core reserved datasheet 393 intel ? manageability engine subsystem registers 10.9.16 ss?sub system identifiers b/d/f/type: 0/3/3/pci address offset: 2c-2fh default value: 00008086h access: r/wo size: 32 bits reset: host system reset these registers are used to uniquely identify the add-in card or the subsystem that the device resides within. 10.9.17 erom?expansion rom base address b/d/f/type: 0/3/3/pci address offset: 30-33h default value: 00000000h access: ro size: 32 bits this optional register is not implemented. 10.9.18 cap?capabilities pointer b/d/f/type: 0/3/3/pci address offset: 34h default value: c8h access: ro size: 8 bits this optional register is used to point to a linked list of new capabilities implemented by the device. bit access default value rst/pwr description 31:16 r/wo 0000h core subsystem id (ssid): this is written by bios. no hardware action taken on this value. 15:0 r/wo 8086h core subsystem vendor id (ssvid): this is written by bios. no hardware action taken on this value. bit access default value rst/pwr description 31:11 ro 000000h core expansion rom base address (erbar): 10:1 ro 000h core reserved 0ro 0b core enable (en): enable expansion rom access. bit access default value rst/pwr description 7:0 ro c8h core capability pointer (cp): this field indicate s that the first capability pointer is offset c8h (the power management capability). intel ? manageability engine subsystem registers 394 datasheet 10.9.19 intr?interrupt information b/d/f/type: 0/3/3/pci address offset: 3c-3dh default value: 0200h access: r/w, ro size: 16 bits reset: host system reset or d3->d0 reset of the function. see individual registers below. 10.9.20 mgnt?minimum grant b/d/f/type: 0/3/3/pci address offset: 3eh default value: 00h access: ro size: 8 bits this optional register is not implemented 10.9.21 mlat?maximum latency b/d/f/type: 0/3/3/pci address offset: 3fh default value: 00h access: ro size: 8 bits this optional register is not implemented. bit access default value rst/pwr description 15:8 ro 02h core interrupt pin (ipin): a value of 0x1/0x2/0x3/0x4 indicates that this function implements legacy interrupt on inta/intb/intc/intd, respectively function value intx (3 kt/serial port) 02h intb 7:0 r/w 00h core interrupt line (iline): the value written in this register tells which input of the syst em interrupt controller, the device's interrupt pin is connec ted to. this value is used by the os and the device driver, and has no affect on the hardware. bit access default value rst/pwr description 7:0 ro 00h core reserved bit access default value rst/pwr description 7:0 ro 00h core reserved datasheet 395 intel ? manageability engine subsystem registers 10.9.22 pid?pci power mana gement capability id b/d/f/type: 0/3/3/pci address offset: c8-c9h default value: d001h access: ro size: 16 bits see register definitions below. 10.9.23 pc?pci power ma nagement capabilities b/d/f/type: 0/3/3/pci address offset: ca-cbh default value: 0023h access: ro size: 16 bits this register implements the power management capabilities of the function. bit access default value rst/pwr description 15:8 ro d0h core next capability (next): a value of d0h points to the msi capability. 7:0 ro 01h core cap id (cid): this field indicates th at this pointer is a pci power management. bit access default value rst/pwr description 15:11 ro 00000b core pme support (pme): this field indicates no pme# in the pt function. 10 ro 0b core d2 support (d2s): the d2 state is not supported 9r o 0 b c o r e d1 support (d1s): the d1 state is not supported 8:6 ro 000b core aux current (auxc): pme# from d3 (cold) state is not supported; therefore, this field is 000b. 5r o 1 b c o r e device specific initialization (dsi): this bit indicates that no device-specific initialization is required. 4 ro 0b core reserved 3r o 0 b c o r e pme clock (pmec): this bit indicates th at pci clock is not required to generate pme# 2:0 ro 011b core version (vs): this field indicates support for the pci power management specification, revision 1.2 . intel ? manageability engine subsystem registers 396 datasheet 10.9.24 pmcs?pci power mana gement control and status b/d/f/type: 0/3/3/pci address offset: cc-cfh default value: 00000000h access: ro/v, ro, r/w size: 32 bits bios optimal default 0000h reset: host system reset or d3->d0 transition this register implements the pci pm control and status register to allow pm state transitions and wake up note: nsr bit of this register. all registers (pci configuration and device specific) marked with d3->d0 transition reset will only do so if the nsr bit reads a 0. if this bit is a 1, the d3->d0 transition will not reset the registers. bit access default value rst/pwr description 31:16 ro 0h reserved 15 ro 0b core pme status (pmes): this bit is set when a pme event is to be requested. not supported 14:9 ro 00h core reserved 8ro 0b core pme enable (pmee): not supported 7:4 ro 0h core reserved 3ro/v 0b core no soft reset (nsr): when set to1, this bit indicates that devices transitioning from d3hot to d0 because of powerstate commands do not perform an inte rnal reset. configuration context is pres erved. upon transition from the d3hot to the d0 initialized state, no additional operating system intervention is required to preserve configuration context beyond writing the powerstate bits. when clear to 0, devices do pe rform an internal reset upon transitioning from d3hot to d0 via software control of the powerstate bits. configuration context is lost when performing the soft reset. upon transition from the d3hot to the d0 state, full re-initial ization sequence is needed to return the device to d0 initialized. value in this bit is reflects chicken bit in me-aux register x13900, bit [6] which is as follows: 0 = device performs internal reset 1 = device does not pe rform internal reset 2 ro 0b core reserved 1:0 r/w 00b core power state (ps): this field is used both to determine the current power state of the pt function and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller's configuration space is available, but the i/ o and memory spaces are not. additionally, interrupts are blocked. if software attempts to write a '10' or '01' to these bits, the write will be ignored. datasheet 397 intel ? manageability engine subsystem registers 10.9.25 mid?message signaled interrupt capability id b/d/f/type: 0/3/3/pci address offset: d0-d1h default value: 0005h access: ro size: 16 bits message signalled interrupt is a feature that allows the device/function to generate an interrupt to the host by performing a dw ord memory write to a system specified address with system specified data. this register is used to identify and configure an msi capable device. 10.9.26 mc?message signaled interrupt message control b/d/f/type: 0/3/3/pci address offset: d2-d3h default value: 0080h access: ro, r/w size: 16 bits reset: host system reset or d3->d0 transition. this register provides system software control over msi. bit access default value rst/pwr description 15:8 ro 00h core next pointer (next): this value indicates this is the last item in the list. 7:0 ro 05h core capability id (cid): this field value of capabilities id indicates device is capa ble of generating msi. bit access default value rst/pwr description 15:8 ro 00h core reserved 7ro 1b core 64 bit address capable (c64): capable of generating 64-bit and 32-bit messages. 6:4 r/w 000b core multiple message enable (mme): these bits are r/w for software compatibility, but on ly one message is ever sent by the pt function. 3:1 ro 000b core multiple message capable (mmc): only one message is required. 0r/w 0b core msi enable (msie): if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. intel ? manageability engine subsystem registers 398 datasheet 10.9.27 ma?message signaled interrupt message address b/d/f/type: 0/3/3/pci address offset: d4-d7h default value: 00000000h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition this register specifies the dword aligned ad dress programmed by system software for sending msi. 10.9.28 mau?message signaled in terrupt message upper address b/d/f/type: 0/3/3/pci address offset: d8-dbh default value: 00000000h access: ro, r/w size: 32 bits reset: host system reset or d3->d0 transition upper 32 bits of the message address for the 64bit address capable device. 10.9.29 md?message signaled interrupt message data b/d/f/type: 0/3/3/pci address offset: dc-ddh default value: 0000h access: r/w size: 16 bits reset: host system reset or d3->d0 transition this 16-bit field is programmed by system software if msi is enabled bit access default value rst/pwr description 31:2 r/w 00000000h core address (addr): lower 32 bits of the system specified message address, al ways dword aligned. 1:0 ro 00b core reserved bit access default value rst/pwr description 31:4 ro 0000000h core reserved 3:0 r/w 0000b core address (addr): upper 4 bits of th e system specified message address. bit access default value rst/pwr description 15:0 r/w 0000h core data (data): this msi data is driven onto the lower word of the data bus of the msi memory write transaction. datasheet 399 intel ? manageability engine subsystem registers 10.10 kt io/ memory mapped device registers 10.10.1 ktrxbr?kt receive buffer register b/d/f/type: 0/3/3/kt mm/io address offset: 0h default value: 00h access: ro/v size: 8 bits reset: host system reset or d3->d0 transition. this implements the kt receiver data regist er. host access to this address, depends on the state of the dlab bit {ktlcr[7]). it must be "0" to access the ktrxbr. rxbr: host reads this register when fw provides it the receive data in non-fifo mode. in fifo mode, host reads to this register translate into a read from me memory (rbr fifo). table 25. kt io/ memory mapped device register address map address offset register symbol register name default value access 0h ktrxbr kt receive buffer register 00h ro/v 0h ktthr kt transmit holding register 00h wo 0h ktdllr kt divisor latch lsb register 00h r/w/v 1h ktier kt interrupt enable register 00h r/w/v, ro/v 1h ktdlmr kt divisor latch msb register 00h r/w/v 2h ktiir kt interrupt identification register 01h ro 2h ktfcr kt fifo control register 00h wo 3h ktlcr kt line control register 03h r/w 4h ktmcr kt modem control register 00h ro, r/w 5h ktlsr kt line status register 00h ro, ro/cr 6h ktmsr kt modem status register 00h ro, ro/cr 7h ktscr kt scratch register 00h r/w bit access default value rst/pwr description 7:0 ro/v 00h core receiver buffer register (rbr): implements the data register of the serial interface. if the ho st does a read, it reads from the receive data buffer. intel ? manageability engine subsystem registers 400 datasheet 10.10.2 ktthr?kt transm it holding register b/d/f/type: 0/3/3/kt mm/io address offset: 0h default value: 00h access: wo size: 8 bits reset: host system reset or d3->d0 transition. this implements the kt transmit data register. host access to this address, depends on the state of the dlab bit {ktlcr[7]). it must be "0" to access the ktthr. thr: when host wants to transmit data in the non-fifo mode, it writes to this register. in fifo mode, writes by host to this address cause the data byte to be written by hardware to me memory (thr fifo). 10.10.3 ktdllr?kt divisor latch lsb register b/d/f/type: 0/3/3/kt mm/io address offset: 0h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition. this register implements the kt dll register. host can read/write to this register only when the dlab bit (ktlcr[7]) is 1. when this bit is 0, host accesses the ktthr or the ktrbr depending on read or write. this is the standard serial port divisor latch register. this register is only for software compatibility and does not affect performance of the hardware. bit access default value rst/pwr description 7:0 wo 00h core transmit holding register (thr): implements the transmit data register of the serial interface . if the host does a write, it writes to the transmit holding register. bit access default value rst/pwr description 7:0 r/w/v 00h core divisor latch lsb (dll): implements the dll register of the serial interface. datasheet 401 intel ? manageability engine subsystem registers 10.10.4 ktier?kt interrupt enable register b/d/f/type: 0/3/3/kt mm/io address offset: 1h default value: 00h access: r/w/v, ro/v size: 8 bits reset: host system reset or d3 -> d0 transition this implements the kt interrupt enable register. host access to this address, depends on the state of the dlab bit {ktlcr[7]). it must be "0" to access this register. the bits enable specific events to interrupt the host. 10.10.5 ktdlmr?kt diviso r latch msb register b/d/f/type: 0/3/3/kt mm/io address offset: 1h default value: 00h access: r/w/v size: 8 bits reset: host system reset or d3->d0 transition. host can read/write to this register only when the dlab bit (ktlcr[7]) is 1. when this bit is 0, host accesses the ktier. this is the standard serial interface's divisor latch register's msb. this register is only for sw compatibility and does not affect performance of the hardware. bit access default value rst/pwr description 7:4 ro/v 0h core reserved 3 r/w/v 0b core msr (ier2): when set, this bit enables bits in the modem status register to cause an interrupt to the host. 2 r/w/v 0b core lsr (ier1): when set, this bit enables bits in the receiver line status register to cause an interrupt to the host. 1 r/w/v 0b core thr (ier1): when set, this bit enables an interrupt to be sent to the host when the transmit holding register is empty. 0 r/w/v 0b core dr (ier0): when set, the received data ready (or receive fifo timeout) interrupts are enabled to be sent to host. bit access default value rst/pwr description 7:0 r/w/v 00h core divisor latch msb (dlm): implements the divisor latch msb register of the serial interface. intel ? manageability engine subsystem registers 402 datasheet 10.10.6 ktiir?kt interrupt identification register b/d/f/type: 0/3/3/kt mm/io address offset: 2h default value: 01h access: ro size: 8 bits reset: see specific bit descriptions. the kt iir register prioritizes the interrupts from the function into 4 levels and records them in the iir_stat field of the register. when host accesses the iir, hardware freezes all interrupts and provides the priority to the host. hardware continues to monitor the interrupts but does not change its current indication until the host read is over. table in the host interrupt generation section shows the contents. bit access default value rst/pwr description 7ro 0b core fifo enable (fien1): this bit is connected by hardware to bit 0 in the fcr register. reset: host system reset or d3->d0 transition. 6ro 0b core fifo enable (fien0): this bit is connected by hardware to bit 0 in the fcr register. reset: host system reset or d3->d0 transition. 5:4 ro 00b core reserved 3:1 ro 000b core iir status (iirsts): these bits are asserted by the hardware according to the sour ce of the interrupt and the priority level. reset: me system reset. 0ro 1b core interrupt status (intsts): 0 = pending interrupt to host 1 = no pending interrupt to host reset: host system reset or d3->d0 transition datasheet 403 intel ? manageability engine subsystem registers 10.10.7 ktfcr?kt fifo control register b/d/f/type: 0/3/3/kt mm/io address offset: 2h default value: 00h access: wo size: 8 bits reset: host system reset or d3->d0 transition when host writes to this address, it writes to the ktfcr. the fifo control register of the serial interface is used to enable the fi fos, set the receiver fifo trigger level and clear fifos under the direction of the host. when host reads from this address, it reads the ktiir. bit access default value rst/pwr description 7:6 wo 00b core receiver trigger level (rtl): trigger level in bytes for the rcv fifo. once the trigger level number of bytes is reached, an interrupt is sent to the host. 00 = 01 01 = 04 10 = 08 11 = 14 5:4 wo 00b core reserved 3wo 0b core rdy mode (rdym): this bit has no affect on hardware performance. 2w o 0 b c o r e xmt fifo clear (xfic): when the host writes one to this bit, the hardware will clear the xmt fifo. this bit is self- cleared by hardware. 1w o 0 b c o r e rcv fifo clear (rfic): when the host writes one to this bit, the hardware will clear the rcv fifo. this bit is self- cleared by hardware. 0w o 0 b c o r e fifo enable (fie): when set, this bit indicates that the kt interface is working in fifo node. when this bit value is changed the rcv and xmt fifo are cleared by hardware. intel ? manageability engine subsystem registers 404 datasheet 10.10.8 ktlcr?kt line control register b/d/f/type: 0/3/3/kt mm/io address offset: 3h default value: 03h access: r/w size: 8 bits reset: host system reset or d3->d0 transition. the line control register specifies the format of the asynchronous data communications exchange and sets the dlab bit. most bits in this register have no affect on hardware and are only used by the fw. bit access default value rst/pwr description 7r/w 0b core divisor latch address bit (dlab): this bit is set when the host wants to read/write the divisor latch lsb and msb registers. this bit is cleared when the host wants to access the receive buffer register or the transmit holding register or the interru pt enable register. 6r/w 0b core break control (bc): this bit has no affect on hardware. 5:4 r/w 00b core parity bit mode (pbm): this bit has no affect on hardware. 3r/w 0b core parity enable (pe): this bit has no affect on hardware. 2r/w 0b core stop bit select (sbs): this bit has no affect on hardware. 1:0 r/w 11b core word select byte (wsb): this bit has no affect on hardware. datasheet 405 intel ? manageability engine subsystem registers 10.10.9 ktmcr?kt modem control register b/d/f/type: 0/3/3/kt mm/io address offset: 4h default value: 00h access: ro, r/w size: 8 bits reset: host system reset or d3->d0 transition. the modem control register controls the interface with the modem. since the fw emulates the modem, the host communicates to the fw via this register. register has impact on hardware when the loopback mode is on. bit access default value rst/pwr description 7:5 ro 000b core reserved 4r/w 0b core loop back mode (lbm): when set by the host, this bit indicates that the serial port is in loop back mode. this means that the data that is transmitted by the host should be received. helps in debug of the interface. 3r/w 0b core output 2 (out2): this bit has no affe ct on hardware in normal mode. in loop back mode the value of this bit is written by hardware to the modem status register bit 7. 2r/w 0b core output 1 (out1): this bit has no affe ct on hardware in normal mode. in loop back mode the value of this bit is written by hardware to mo dem status register bit 6. 1r/w 0b core request to send out (rtso): this bit has no affect on hardware in normal mode. in loopback mode, the value of this bit is written by hardwa re to modem status register bit 4. 0r/w 0b core data terminal ready out (drto): this bit has no affect on hardware in normal mode. in loopback mode, the value in this bit is written by hardware to modem status register bit 5. intel ? manageability engine subsystem registers 406 datasheet 10.10.10 ktlsr?kt line status register b/d/f/type: 0/3/3/kt mm/io address offset: 5h default value: 00h access: ro, ro/cr size: 8 bits reset: host system reset or d3->d0 transition this register provides status information of the data transfer to the host. error indication, etc. are provided by the hw/fw to the host via this register. bit access default value rst/pwr description 7ro 0b core rx fifo error (rxfer): this bit is cleared in non fifo mode. this bit is connected to bi bit in fifo mode. 6ro 0b core transmit shift register empty (temt): this bit is connected by hw to bit 5 (thre) of this register. 5r o 0 b c o r e transmit holding register empty (thre): this bit is always set when the mode (f ifo/non-fifo) is changed by the host. this bit is active only when the thr operation is enabled by the fw. this bit has acts differe ntly in the different modes: non fifo : this bit is cleared by hardware when the host writes to the thr registers an d set by hardware when the fw reads the thr register. fifo mode : this bit is set by hardware when the thr fifo is empty, and cleared by hardware when the thr fifo is not empty. this bit is reset on host system reset or d3->d0 transition. 4 ro/cr 0b core break interrupt (bi): this bit is cleared by hardware when the lsr register is being read by the host. this bit is set by hardware in two cases: ? in fifo mode the fw sets the bi bit by setting the sbi bit in the ktrivr register (see kt aux registers) ? in non-fifo mode the fw sets the bi bit by setting the bia bit in the ktrxbr regist er (see kt aux registers) 3r o 0 b c o r e framing error (fe): this bit is not implemented 2r o 0 b c o r e parity error (pe): this bit is not implemented 1 ro/cr 0b core overrun error (oe): this bit is cleared by hardware when the lsr register is being read by the host. the fw typically sets this bit, but it is clea red by hardware when the host reads the lsr. 0r o 0 b c o r e data ready (dr): non-fifo mode: this bit is set when the fw writes to the rbr register and cleared by hardware when the rbr register is being read by the host. fifo mode: this bit is set by hardware when the rbr fifo is not empty and cleare d by hardware when the rbr fifo is empty. this bit is reset on host system reset or d3->d0 transition. datasheet 407 intel ? manageability engine subsystem registers 10.10.11 ktmsr?kt modem status register b/d/f/type: 0/3/3/kt mm/io address offset: 6h default value: 00h access: ro, ro/cr size: 8 bits reset: host system reset or d3->d0 transition the functionality of the modem is emulated by the fw. this register provides the status of the current state of the control lines from the modem. 10.10.12 ktscr?kt scratch register b/d/f/type: 0/3/3/kt mm/io address offset: 7h default value: 00h access: r/w size: 8 bits reset: host system reset or d3->d0 transition this register has no affect on hardware. this is for the programmer to hold data temporarily. bit access default value rst/pwr description 7ro 0b core data carrier detect (dcd): in loop back mode this bit is connected by hardware to the value of mcr bit 3. 6ro 0b core ring indicator (ri): in loop back mode this bit is connected by hardware to the value of mcr bit 2. 5ro 0b core data set ready (dsr): in loop back mode this bit is connected by hardware to the value of mcr bit 0. 4ro 0b core clear to send (cts): in loop back mode this bit is connected by hardware to the value of mcr bit 1. 3 ro/cr 0b core delta data carrier detect (ddcd): this bit is set when bit 7 is changed. th is bit is cleared by hardware when the msr register is being read by the host driver. 2 ro/cr 0b core trailing edge of read detector (teri): this bit is set when bit 6 is changed from 1 to 0. this bit is cleared by hardware when the msr register is being read by the host driver. 1 ro/cr 0b core delta data set ready (ddsr): this bit is set when bit 5 is changed. this bit is clea red by hardware when the msr register is being read by the host driver. 0 ro/cr 0b core delta clear to send (dcts): this bit is set when bit 4 is changed. this bit is cleare d by hardware when the msr register is being read by the host driver. bit access default value rst/pwr description 7:0 r/w 00h core scratch register data (scrd): intel ? manageability engine subsystem registers 408 datasheet datasheet 409 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 11 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) this section covers the intel ? trusted execution technology specific registers implemented in the (g)mch. fo r more information on intel ? trusted execution technology enabled platform, refer to the intel ? trusted execution technology bios writer?s guide. 11.1 intel trusted execution technology specific registers address offset symbol register name srlz default value access 0h txt.sts txt status register 000010h ro 8h txt.ests txt error status register 00h rwc, ro 10?17h txt.thread.exist s txt thread exists register 000000000000 0000h ro 20?27h txt.threads.join txt threads join register 000000000000 0000h ro 30?33h txt.errorcode (aka txt.crash) txt errorcode register (also known as txt crash) 00000000h rwc 38?3fh txt.cmd.reset txt system reset command fa n/a wo 48?4fh txt.cmd.close- private txt close private command n/a wo 110?117h txt.did txt device id register 8003h rw, ro 258?25fh txt.cmd.flush-wb txt flush write buffer command fa n/a wo 270?277h t x t. s i n i t. m e m o r y. base txt sinit code base register 000000000000 0000h rw, ro 278?27fh t x t. s i n i t. m e m o r y. size txt sinit memory size register 000000000000 0000h rw, 290?297h txt.mle.join txt mle join base register 000000000000 0000h rw, ro 300?307h txt.heap.base txt heap base register 000000000000 0000h rw 308?30fh txt.heap.size txt heap size register 000000000000 0000h rw 310?317h txt.mseg.base txt mseg base register 000000000000 0000h rw/l intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 410 datasheet note: srlz : indicates if a serializing step is required by software (for example, a read) before or after a write to the register. note that th is is referring to serializing at the chipset hardware level. since txt space is memory -mapped, multiple commands or writes can be enqueued in a back-to-back sequence . if a preceding command or write takes several clocks to be fully processed, the subsequent accesses may be handled incorrectly. therefore, simply serializing these cycles as they leave the processor may not be sufficient to guarantee that they ar e appropriately serialized by the time they are processed in the chipset. a read following the write does guarantee that a subsequent write is serialized after the first write. fa=fence after. fb=fence before. 318?31fh txt.mseg.size txt mseg size address register 000000000000 0000h rw/l 320?327h txt.scratchpad.0 txt scratch pad 0 register 000000000000 0000h rw 328?32fh txt.scratchpad.1 txt scratch pad 1 register 000000000000 0000h rw 330?337h txt.dpr dma protected range 000000000000 0000h ro, rw/l, rwo 380?387h txt.cmd.open.loc ality1 txt open locality 1 command fa n/a wo 388?38fh txt.cmd.close.lo cality1 txt close locality 1 command fa n/a wo 390?397h txt.cmd.open.loc ality2 txt open locality 2 command fa n/a wo 398?39fh txt.cmd.close.lo cality2 txt close locality 2 command fa n/a wo 400?41fh txt.public.key txt chipset public key hash 00000000de44 98a3619fa4f4e 5e30200613d4 a51a6f9e712h ro 8e0?8e7h txt.cmd.secrets txt secrets command fa n/a wo 8e8?8efh txt.cmd.no- secrets txt no secrets command fa n/a wo 8f0?8f7h txt.e2sts txt extended error status register 000000000000 0000h ro address offset symbol register name srlz default value access datasheet 411 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 11.1.1 txt.sts?txt status register b/d/f/type: 0/0/0/txt specific address offset: 0-2h default value: 000010h access: ro size: 24 bits bios optimal default 00h this register is used to read the status of the txt command/status engine functional block in the chipset. bit access default value description 23:17 ro 0h reserved 16 ro 0b txt.locality2.open.sts (t xt.locality2.open.sts): this bit is set when either the txt.cmd.open.locality2 command or the txt.cmd.open.private is seen by the chip set. it is cleared on reset or when either txt.cmd.close.locality2 or txt.cmd.close.private is seen. this bit can be used by sw as a positive indica tion that the command has taken effect. 15 ro 0b txt.locality1.open.sts (t xt.locality1.open.sts): this bit is set when the txt.cmd.open .locality1 command is seen by the chipset. it is cleared on reset or when txt.cmd.close.locality1 is seen. this bit can be used by sw as a positive indication that the command has taken effect. 14:8 ro 0b reserved 7ro 0b txt private-open status (txt.private-open.sts): this bit will be set to 1 when the txt private address is opened. this bit cleared by the txt.cmd.close-private or by a system reset. 6:5 ro 0b reserved 4:4 ro 1b reserved 3:2 ro 0b reserved 1ro 0b sexit done status (sexit.done.sts): this bit is set when all of the bits in the txt.threads.join register are cl ear 0. thus, this bit will be set immediately after reset (since the bits are all 0). this bit will be cleared on the receipt of the first txt.cyc.senter-a ck. once all threads have done the txt.cyc.sexit-ack, the txt.thread.join regi ster will be 0, so the chipset will set this bit. 0ro 0b senter done status (senter.done.sts): the chipset sets this bit when it sees all of the threads have done the txt.cyc.senter-ack. when any of the threads does the txt.cyc.sexit-ack, the txt.threads.join and txt.threads.exists registers will not be equal, so the chipset will clear this bit. intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 412 datasheet 11.1.2 txt.ests?txt e rror status register b/d/f/type: 0/0/0/txt specific address offset: 8h default value: 00h access: rwc, ro size: 8 bits this register is used to read the status associated with various errors that might be detected. all defined bits in this register are sticky. bit access default value description 7rwc 0breserved 6rwc 0b txt wake error status (txt.wake-error.sts): the chipset sets this bit when it detects that there might have been secrets in memory and a reset or power failure occurred. if this bit is set after a system reset, the chipset will prevent memory accesses until specifically enabled. the software that is author ized to enable the memory accesses will also be responsible for clearing the secrets from memory. software can read chipset-sp ecific registers to determine the specific cause of the error. the location of th ose bits is beyond the scope of this specification. on a reset, if cpu_reset_done_ack_secret is received, then this bit is set to '1'. on a reset, if cpu_reset_done_ack is re ceived, then this bit is cleared to '0'. software can clear this bit by writing a '1' to it. this bit must be cleared if a read to 0xfed4_0000 returns a 1 in bit 0. 5:1 rwc 0b reserved 0ro 0b txt reset status (txt.txt_reset.sts): the chipset sets this bit to ?1? to indicate that the platform experienced a txt reset. to maintain txt integrity, while this bit is set, a txt measured environment cannot be established; consequently safer mode extension (smx) instructions getsec [enteraccs] and getsec [senter] will fail. see chapter 6, ?safer mode extens ions reference? of intel ? 64 and ia-32 architectures software developer?s manual, volume 2b. reads to the txt public space and other non-smx instructions will continue to work. this bit must be cleared to re-enable txt on the platform. note: this bit is sticky and will only be cleared on a power cycle. datasheet 413 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 11.1.3 txt.thread.exists?txt thread exists register b/d/f/type: 0/0/0/txt specific address offset: 10-17h default value: 0000000000000000h access: ro size: 64 bits this register is used to read which threads are registered as txt capable bit access default value description 63:32 ro 0000000 0h txt threads exists (reserve d) (txt.thrds.exists_r): this bit field indicates the threads on the fsb that have issued a cycle. the bit is set based on any processor cycle initiated by the thread after reset. the ge tsec instruction is expected to be performed after each th read has performed at least one cycle. when the chipset detects the presence of a particular thread, it sets the corresponding bit in this register. this register is locked when senter is seen on the fsb. the following bit mapping is used: bits usage 7:0 cpu #0, threads # 1-4 15:8 cpu #1, threads # 1-4 23:16 cpu #2, threads # 1-4 31:24 cpu #3, threads # 1-4 63:32 reserved notes: the processor is defined by the defe r id bits, did[6:5]. the thread is defined by attr[6:5]. at the moment that defines only 4 processor's and 4 threads. the other bits are reserved for future changes. 31:0 ro 0000000 0h txt thread exists (txt.thrds.exists): this bit field indicates the threads on the fsb that have issued a cycle. the bit is set based on any processor cycle initiated by the thread after reset. the getsec instruction is expected to be performed after each thread has performed at least one cycle. when the chipset detects the presence of a particular thread , it sets the corres ponding bit in this register. this register is locked when senter is seen on the fsb. the following bit mapping is used: bits usage 7:0 cpu #0, threads # 1-4 15:8 cpu #1, threads # 1-4 23:16 cpu #2, threads # 1-4 31:24 cpu #3, threads # 1-4 63:32 reserved note: the cpu is defined by the defer id bi ts, did[6:5]. the th read is defined by attr[6:5]. at the moment that defines only 4 processors and 4 threads. the other bits are re served for future changes. intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 414 datasheet 11.1.4 txt.threads.join?tx t threads join register b/d/f/type: 0/0/0/txt specific address offset: 20-27h default value: 0000000000000000h access: ro size: 64 bits this register is used to count the threads that have joined the txt environment. bit access default value description 63:32 ro 00000000h txt threads join (reserve d) (txt.thrds.join_r): this bit field indicates the threads that have issued an senter-ack cycle. each bit corresponds to a separate thread. wh en the chipset observes the senter- ack from the thread, it sets the co rresponding bit in this register. the format of the bits in this register is the same as in the txt.threads.exists register. the chipset will set the senter.done.sts bit when the txt.threads.exists and txt.threads.jo in fields match and at least one bit in the txt.threads.ex ists register is set. when the chipset observes the sexit.ack cycle, it will clear the corresponding bit in this register. when it has cleared all the bits, it will set sexit.done. 31:0 ro 00000000h txt threads join (txt.thrds.join): this bit field indicates the threads that have issued an senter-ack cycle. each bit corresponds to a separate thread. when the chipset observes the senter-ack from the thread, it sets the corresponding bit in this register. the format of the bits in this register is the same as in the txt.threads.exists register. the chipset will set the senter.done.sts bit when the txt.threads.exists and txt.threads.jo in fields match and at least one bit in the txt.threads.ex ists register is set. when the chipset observes the sexit.ack cycle, it will clear the corresponding bit in this register. when it has cleared all the bits, it will set sexit.done. datasheet 415 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 11.1.5 txt.errorcode (aka tx t.crash)?txt error code register b/d/f/type: 0/0/0/txt specific address offset: 30-33h default value: 00000000h access: rw size: 32 bits when software discovers an error, it can write this scratchpad register. the register is not reset by a standard reset, and thus allows diagnostic software (after the reset) to determine why the senter sequence failed (by examining various status bits). all defined bits in this register are sticky across soft reboot. 11.1.6 txt.cmd.reset?txt system reset command when this command is invoked, the chipset resets the entire platform. hardware naturally delays the assertion of reset sufficiently such that any previous writes to errorcode register should have completed. if software wants to guarantee that it is not reliant upon this race, it must read back the errorcode register before writing the system reset command. 11.1.7 txt.cmd.close-private?t xt close private command the processor that authenticates the sexit co de does this to prevent the txt private address space from being accessed using standard memory read/write cycles. system software (i.e. mle - measured launched environment) is required to fence after this command is performed. this can be achieved by reading back the sts flag to see that it is no longer set after performing the close-private command. bit access default value description 31:0 rwc 00000000h error code (crash): default 0 on power-up. ot herwise, previous value on reset. intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 416 datasheet 11.1.8 txt.did?txt device id register b/d/f/type: 0/0/0/txt specific address offset: 110-117h default value: 8003h access: rw, ro size: 64 bits contains the txt id for the mch or root ch ipset component. this register is sticky. 11.1.9 txt.cmd.flush-wb?txt fl ush write buffer command this command flushes the chipset write buffers. the mle writes to this register as part of the mpt update sequence. 11.1.10 txt.sinit.memory.base?tx t sinit code base register b/d/f/type: 0/0/0/txt specific address offset: 270-277h default value: 0000000000000000h access: rw, ro size: 64 bits this register contains the physical base address of the memory region set aside by the bios for loading an sinit ac module. the syst em software reads this register to locate the sinit module (which may have been loaded by the bios) or to find a location to load the sinit module. bit access default value description 63:48 rw 0000h txt id extensions (txt.id.ext): this field is read/write. the default value for this register is 0. this is an extension onto th e other id fields. 47:32 ro 00000000000 01111b revision id (txt.rid): 31:16 ro 8003h device id (txt.did): 8003h for intel 4 series chipset 82q45 and 82q43. 15:0 ro 8086h vendor id (txt.vid): this register field cont ains the pci standard identification for intel, 8086h. bit access default value description 63:36 ro 0000000h reserved 35:12 rw 000000h sinit code base (txt.sinit.memory.base): base address of the sinit code. hardware does not use the in formation contained in this register. it is used as a mailbox betw een two pieces of software. note: bits 11:0 are not implemented be cause the sinit code must be aligned to a 4k page boundary. systems supporting a 36 bit address spac e may make bits 63:36 as ro with reads returning '0'. 11:0 ro 000h reserved datasheet 417 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 11.1.11 txt.sinit.memory.siz e?txt sinit memory size register b/d/f/type: 0/0/0/txt specific address offset: 278-27fh default value: 0000000000000000h access: rw size: 64 bits this register contains the size in bytes of the memory region set aside by the bios for loading an sinit ac module. this register is initialized by the bios. the system software may read this register when loading an sinit module. 11.1.12 txt.mle.join?txt mle join base register b/d/f/type: 0/0/0/txt specific address offset: 290-297h default value: 0000000000000000h access: rw, ro size: 64 bits holds a physical address pointer to the base of the join data structure referenced by rlps in response to a getsec[wakeup] while operating between senter and sexit. bit access default value description 63:0 rw 0000000000 000000h txt.sinit.size (txt.sinit.size): base address of the sinit code. hardware does not use the information cont ained in this regist er. it is used as a mailbox between two pieces of software. note: bits 11:0 are not implemented because the sinit code must be aligned to a 4k page boundary. systems supporting a 36 bit address spac e may make bits 63:36 as ro with reads returning '0'. bit access default value description 63:36 ro 0000000h txt mle join base (reserved) (txt.mle.join_r): base address of the mle join code. for chipsets that only support 64gb fsb addressing (36b addressing), bits 63:36 may be ro ? reserved(0) 35:0 rw 00000000 0h txt mle join base (txt.mle.join): base address of the mle join code. for chipsets that only support 64 gb fsb addressing (36b addressing), bits 63:36 may be ro ? reserved(0) intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 418 datasheet 11.1.13 txt.heap.base?txt heap base register b/d/f/type: 0/0/0/txt specific address offset: 300-307h default value: 0000000000000000h access: rw size: 64 bits this register contains the physical base address of the txt heap memory region. the bios initializes this register. the system software and mle read this register to locate the txt heap. 11.1.14 txt.heap.size?tx t heap size register b/d/f/type: 0/0/0/txt specific address offset: 308-30fh default value: 0000000000000000h access: rw; size: 64 bits this register contains the size in bytes of the txt heap memory region. the bios initializes this register. the system software and the mle read this register to determine the txt heap size. 11.1.15 txt.mseg.base?tx t mseg base register b/d/f/type: 0/0/0/txt specific address offset: 310-317h default value: 0000000000000000h access: rw/l size: 64 bits this register provides the base address of mseg. this register is locked by smm d_lck and when locked neither public nor private writes can change its value. bit access default value description 63:0 rw 000000000 0000000h heap base address (txt.heap.base): base address of the heap. systems must implement all 64 bits as rw. bit access default value description 63:0 rw 000000000 0000000h heap size (txt.heap.size): size of the total device space in bytes bit access default value description 63:0 rw/l 000000000 0000000h mseg base address (mseg.base): bios writes the base of mseg into this register. datasheet 419 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 11.1.16 txt.mseg.size?txt mseg size address register b/d/f/type: 0/0/0/txt specific address offset: 318-31fh default value: 0000000000000000h access: rw/l size: 64 bits this register provides the size of mseg. this register is locked by smm d_lck and when locked neither public nor private writes can change its value. 11.1.17 txt.scratchpad.0?txt scratch pad 0 register b/d/f/type: 0/0/0/txt specific address offset: 320-327h default value: 0000000000000000h access: rw size: 64 bits scratchpad register 0 11.1.18 txt.scratchpad.1?txt scratch pad 1 register b/d/f/type: 0/0/0/txt specific address offset: 328-32fh default value: 0000000000000000h access: rw size: 64 bits scratchpad register 1 bit access default value description 63:0 rw/l 0000000000 000000h mseg size value (mseg.size): this is the size of the mseg region in bytes. bit access default value description 63:0 rw 0000000000 000000h scratch pad 0 (scratch0): general scratch pad 0 bit access default value description 63:0 rw 0000000000 000000h scratch pad 1 (scratch1): general scratch pad 1 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 420 datasheet 11.1.19 txt.dpr?dma protected range b/d/f/type: 0/0/0/txt specific address offset: 330-337h default value: 0000000000000000h access: ro, rw/l, rwo size: 64 bits dma protected range register. 11.1.20 txt.cmd.open.localit y1?txt open locality 1 command this command will open locality1 for decode as an txt space by the chipset. if the locality is closed, then cycles to the locality 1 address range are not decoded as txt cycles. note: private space must also be open for locality 1 to be decoded as txt space. bit access default value description 63:32 ro 00000000h reserved 31:20 ro 000h top of dpr (topofdpr): top address + 1 of dpr. this is the base of tseg. bits 19:0 of the base reported here are 0x0_0000. 19:12 ro 00h reserved 11:4 rw/l 00h dma protected memory size (dpr.size): this is the size of memory, in mb, that will be protected from dma acce sses. a value of 0x00 in this field means no additional memory is protected. the maximum amount of memory that will be protected is 255 mb. the amount of memory reported in this field will be protected from all dma accesses, including translated cpu ac cesses and graphics. the top of the protected range is the base of tseg?1. note: if tseg is not enabled, then the top of this range becomes the base of stolen graphics, or me stolen space or tolud, whichever would have been the location of tseg, assuming it had been enabled. the dpr range works independently of any other range, including the pmrc checks in vtd, and is done post any vtd translation. therefore, incoming cycles are checked against this range af ter the vtd translation and faulted if they hit this protected range, even if they passed the vtd translation. all the memory checks are or'ed with re spect to not being allowed to go to memory. so if either pmrc, dpr or a vtd translation disallows the cycle, then the cycle is not allowed to go to memory. or in other words, all the above checks must pass before a cycle is allowed to dram. 3:1 ro 000b reserved 0rwo 0b lock (lock): bits 19:0 are locked down in this register when this bit is set. datasheet 421 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 11.1.21 txt.cmd.close.locali ty1?txt close locality 1 command this command closes the locality 1 address space as an txt range. when closed, the chipset may decode this range as normal memo ry space, or it may abort cycles to this range. 11.1.22 txt.cmd.open.localit y2?txt open locality 2 command this command will open locality2 for decode as an txt space by the chipset. this command is either an ltmw or a private write when private is open. note: open.private will open locality 2 and cl ose.private will close locality2. the open/ close locality2 commands are to be used in the window while private is open, but the mle wants to close or re-open the loca lity 2 space while still leaving private open. if the locality is closed, then cycles to the locality 2 address range are not decoded as txt cycles. private space must also be open for locality 2 to be decoded as txt space. 11.1.23 txt.cmd.close.locali ty2?txt close locality 2 command this command closes the locality 2 address space as an txt range. when closed, the chipset may decode this range as normal memo ry space, or it may abort cycles to this range. this command is either an ltmw or a private write when private is open. 11.1.24 txt.public.key?txt chipset public key hash b/d/f/type: 0/0/0/txt specific address offset: 400-41fh default value: 00000000de4498a3619fa4f4e5e30200613d4a51a6f9e712h access: ro size: 256 bits these registers hold the hash of the chipset's public key. bit access default value description 255: 192 ro 00000000000 00000h reserved 191:0 ro 00000000de4 498a3619fa4f 4e5e3020061 3d4a51a6f9e7 12h public key hash (txt.public.key hash): this is a field that contains the hash of the chipset's public key. public key: 00000000de4498a3619fa4f4e5e30200613d4a51a6f9e712h note: the public key is chipset specific, intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 422 datasheet 11.1.25 txt.cmd.secrets?txt secrets command the ilp sinit code does this to tell the chipset that there are going to be secrets in memory. this is used when determining whether to block memory after a reset or power failure. 11.1.26 txt.cmd.no-secrets ?txt secrets command the cpu that authenticates the sexit code does this to tell the chipset that there are no more secrets in memory. it is also used by the authenticated code that wipes secrets from memory after a reset. 11.1.27 txt.e2sts?txt extend ed error status register b/d/f/type: 0/0/0/txt specific address offset: 8f0-8f7h default value: 0000000000000000h access: ro size: 64 bits this register is used to read the status associated with various errors that might be detected. the bits in this register are only valid if the txt.wake-error.sts bit is set in the txt.ests register. the bits in this re gister are all sticky. the default value is undefined. bit access default value description 63:33 ro 0h reserved 32 ro 0b txt reset policy (txt.reset.policy): when cleared to '0', an assertion of the txtreset# pin will cause a full system reset, whereby the ich does a handshake with the mch before asserting the platform reset. when set to '1', the ich will do a power cycle of the pl atform on an assertion of txtreset#. default=0. 31:3 ro 0b reserved 2ro 0b txt memory block status (txt.block-mem.sts): this bit indicates if the ich has indicated to the mch that it sh ould block memory ac cesses. reset only by rtest#. 1ro 0b txt secrets status (txt.secrets.sts): this bit indicates if there are any potential secrets in memory. this is used in the setting of the various flags. reset only by rtest#. 0ro 0b txt sleep entry error status (txt.slp-entry-error.sts): this bit indicates if there has been an improp er attempt to go to sleeping state. reset only by rtest#. datasheet 423 intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 11.2 intel ? txt memory map intel txt introduces a new memory configuration space and requires physical memory be allocated from the physical memory map. the intel txt configuration space is located just below the top of the 4 gb addre ssable space. the intel txt device memory is allocated from the top of the physical memory below 4 gb and must be allocated below other chipset memory regions. both the intel txt configuration space and intel txt device memory must be reported as unavailable to the operating system. 11.2.1 intel ? txt private space the intel txt private configuration space is decoded beginning at the fixed address fed20000h and is only accessible by the ac modules and mle. special txt.rd and txt.wt cycles have been defined to access this space. intel txt management registers are located in this space and are used by the authenticated code modules and the mle to launch and maintain the intel txt enviro nment. any attempt by the bios to read intel txt private space will return invalid data. bios must report this region as unavailable to the os. 11.2.2 intel ? txt public space the intel txt public configuration space is decoded beginning at the fixed address fed30000h. the registers located in the intel txt public space can be accessed using standard memory reads and writes. general purpose intel txt configuration registers are located in this space and the bios must report this region as unavailable to the os. 11.2.3 tpm decode area the tpm decode area provides access to tpm configuration registers and is decoded beginning at the fixed address fed40000h. this space is divided into multiple 4k pages, also known as localities, with each page controlled by a different set of attributes. the pages may be accessed by intel txt cycles only or intel txt cycles and private cycles, or intel txt cycles, private cycles, and public cycles. see the tpm pc client specifications for details re garding the tpm configuration space. intel ? trusted execution technology registers (intel ? 82q45 and 82q43 gmch only) 424 datasheet datasheet 425 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12 intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.1 dmi and peg vc0/vcp remap registers table 26. intel ? virtualization technology for di rected i/o regist er address map address offset register symbol register name default value access 0?3h ver_reg version register 00000010h ro 8?fh cap_reg capability register 00c9008020 630272h ro 10?17h ecap_reg extended capability register 00000000000 01000h ro 18?1bh gcmd_reg global command register 00000000h ro, w 1c?1fh gsts_reg global status register 00000000h ro 20?27h rtaddr_reg root-entry table address register 00000000000 00000h r/w, ro 28?2fh ccmd_reg context command register 00000000000 00000h w, r / w, r o 34?37h fsts_reg fault status register 00000000h ro, ro/p, r/wc/p 38?3bh fectl_reg fault event control register 80000000h r/w, ro 3c?3fh fedata_reg fault event data register 00000000h ro, r/w 40?43h feaddr_reg fault event address register 00000000h ro, r/w 44?47h feuaddr_reg fault event upper address register 00000000h ro 58?5fh aflog_reg advanced fault log register 00000000000 00000h ro 64?67h pmen_reg protected memory enable register 00000000h ro, r/w 68?6bh plmbase_reg protected low-memory base register 00000000h r/w, ro 6c?6fh plmlimit_reg protected low-memory limit register 00000000h r/w, ro 70?77h phmbase_reg protected high-memory base register 00000000000 00000h ro, r/w 78?7fh phmlimit_re g protected high-memory limit register 00000000000 00000h r/w, ro 100?107h iva_reg invalidate address register 00000000000 00000h w, r o intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 426 datasheet 12.1.1 ver_reg?version register b/d/f/type: 0/0/0/vc0premap address offset: 0-3h default value: 00000010h access: ro size: 32 bits this register reports the architecture vers ion supported. backward compatibility for the architecture is maintained with new revisi on numbers, allowing software to load dma- remapping drivers written for prior architecture versions. 12.1.2 cap_reg?capability register b/d/f/type: 0/0/0/vc0premap address offset: 8-fh default value: 00c9008020630272h access: ro size: 64 bits this register reports general dma remapping hardware capabilities. bit access default value rst/pwr description 31:8 ro 000000000 000000000 000000b core reserved 7:4 ro 0001b core major version number (max): this field indicates supported architecture version. 3:0 ro 0000b core minor version number (min): this field indicates supported architecture minor version. bit access default value rst/pwr description 63:56 ro 00h core reserved 55 ro 1b core dma read draining (drd): 0 = on iotlb invalidations, hardware does not support draining of translated dm a read requests queued within the root complex. 1 = on iotlb invalidations, hardware supports draining of translated dma read requests queued within the root complex. indicates supported ar chitecture version. 54 ro 1b core dma write draining (dwd): 0 = on iotlb invalidations, hardware does not support draining of translated dma writes queued within the root complex. 1 = on iotlb invalidations, hardware supports draining of translated dma writes queued within the root complex. 53:48 ro 001001b core maximum address ma sk value (mamv): the value in this field indicates the maximum supported value for the address mask (am) field in the invalidation address (iva_reg) register. datasheet 427 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 47:40 ro 00000000b core number of faultrecording registers (nfr): this field indicates a value of n-1, where n is the number of fault recording registers supported by hardware. implementations must support at least one fault recording register (nfr = 0) for each dmaremapping hardware unit in the platform. the maximum number of fault recording registers per dma-remapping hardware unit is 256. bit 40 in the capability register is the least significant bit of the nfr field (47:40). 39 ro 1b core page selective invalidation support (psi): 0 = dmar engine does not support page selective invalidations 1 = dmar engine does support page-selective iotlb invalidations. the mamv fi eld indicates the maximum number of contiguous translations that may be invalidated in a single request. 38 ro 0b core reserved 37:34 ro 0000b core super page support (sps): this field indicates the super page sizes supported by hardware. a value of 1 in any of these bits indicates the corresp onding super-page size is supported. the super-page size s corresponding to various bit positions within this field are: 0 = 21-bit offset to page frame 1 = 30-bit offset to page frame 2 = 39-bit offset to page frame 3 = 48-bit offset to page frame 33:24 ro 020h core fault-recording register offset (fro): this field specifies the location to the first fault recording register relative to the register base address of this dma- remapping hardware unit. if the register base address is x, and the value reported in this field is y, the address for the first fault recording register is calculated as x+(16*y). 23 ro 0b core isochrony (isoch): 0 = dma-remapping hardware unit has no critical isochronous requeste rs in its scope. 1 = dma-remapping hardware unit has one or more critical isochronous requeste rs in its scope. to ensure isochronous perform ance, software must ensure invalidation operations do no t impact active dma streams. this implies that when dma is active, software perform page-selective in validations (instead of coarser invalidations). 22 ro 1b core zero length read (zlr): 0 = remapping hardware unit blocks (and treats as fault) zero length dma read requ ests to write-only pages. 1 = remapping hardware unit supports zero length dma read requests to write-only pages. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 428 datasheet 21:16 ro 100011b core maximum guest address width (mgaw): this field indicates the maximum dma virtual addressability supported by remapping hardware. the maximum guest address wi dth (mgaw) is computed as (n+1), where n is the value reported in this field. for example, a hardware implem entation supporting 48-bit mgaw reports a value of 47 (101111b) in this field. if the value in this field is x, dma requests to addresses above 2(x+1)?1 are always blocked by hardware. guest addressability for a given dma request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page-table structur e. (adjusted gues t address widths supported by hardware are reported through the sagaw field). 15:13 ro 000b core reserved 12:8 ro 00010b core supported adjusted guest address widths (sagaw): this 5-bit field indicates th e supported adjusted guest address widths (which in turn represents the levels of page-table walks) suppo rted by the hardware implementation. a value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported. the adjusted guest address widths corresponding to various bit positions within this field are: 0 = 30-bit agaw (2-level page table) 1 = 39-bit agaw (3-level page table) 2 = 48-bit agaw (4-level page table) 3 = 57-bit agaw (5-level page table) 4 = 64-bit agaw (6-level page table) software must ensure that the adjusted guest address width used to setup the page ta bles is one of the supported guest address widths re ported in this field. 7ro 0b core caching mode (cm): 0 = hardware does not cache not present and erroneous entries in the context-cache and iotlb. invalidations are not required for modifications to individual not present or invalid entries. however, any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective. 1 = hardware may cache not present and erroneous mappings in the context-cache or iotlb. any software updates to the dma-remapping structures (including updates to not-present or erroneous entries) require explicit invalidation. hardware implementations ar e recommended to support operation corresponding to cm=0. bit access default value rst/pwr description datasheet 429 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 6r o 1 b c o r e protected high-memory region (phmr): 0 = indicates protected high-memory region not supported. 1 = indicates protec ted high-memory regi on is supported. dma-remapping hardware impl ementations on intel txt platforms supporting main memory above 4 gb are required to support prot ected high-memory region. 5r o 1 b c o r e protected low-memory region (plmr): 0 = indicates protected low-me mory region not supported. 1 = indicates protected low-me mory region is supported. dma-remapping hardware impl ementations on intel txt platforms are required to su pport protected low-memory region. 4r o 1 b c o r e required write-buffer flushing (rwbf): 0 = indicates no write-buffer flushing needed to ensure changes to memory-resident structures are visible to hardware. 1 = indicates software must explicitly flush the write buffers (through the global command register) to ensure updates made to memory-resident dma- remapping structures are visible to hardware. 3r o 0 b c o r e advanced fault logging (afl): 0 = indicates advanced fault logging not supported. only primary fault logging is supported. 1 = indicates advanced fa ult logging is supported. 2:0 ro 010b core number of domains supported (nd): 000 = hardware supports 4-bit domain-ids with support for up to 16 domains. 001 = hardware supports 6-bit domain-ids with support for up to 64 domains. 010 = hardware supports 8-bit domain-ids with support for up to 256 domains. 011 = hardware supports 10-bit domain-ids with support for up to 1024 domains. 100 = hardware supports 12-bit domain-ids with support for up to 4 kb domains. 100 = hardware supports 14-bit domain-ids with support for up to 16 kb domains. 110 = hardware supports 16-bit domain-ids with support for up to 64 kb domains. 111 = reserved. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 430 datasheet 12.1.3 ecap_reg?extended capability register b/d/f/type: 0/0/0/vc0premap address offset: 10-17h default value: 0000000000001000h access: ro size: 64 bits this register reports dma-remapping hardware extended capabilities bit access default value rst/pwr description 63:24 ro 0s core r eserved 23:20 ro 0000b core maximum handle mask value (mhmv): the value in this field indicates the maximum supported value for the handle mask (hm) field in the interrupt entry cache invalidation descriptor ( iec_inv_dsc ). this field is valid only when th e ir field is reported as set. 19:18 ro 00b core reserved 17:8 ro 010h core invalidation unit offset (ivo): this field specifies the location to the first iotlb invalidation unit relative to the register base address of th is dma-remapping hardware unit. if the register base address is x, and the value reported in this field is y, the address fo r the first iotlb invalidation unit is calculated as x+(16*y). if n is the value reported in niu field, the address for the last iotlb invalidation unit is calculated as x+(16*y)+(16*n). 7ro 0b core snoop control (sc): 0 = hardware does not support 1-setting of the snp field in the page-table entries. 1 = hardware supports the 1-sett ing of the snp field in the page-table entries. 6ro 0b core pass through (pt): 0 = hardware does not support passthrough translation type in context entries. 1 = hardware supports pass-through translation type in context entries. 5r o 0 b c o r e caching hints (ch): 0 = hardware does not support iotlb caching hints (alh and eh fields in context-entries are treated as reserved). 1 = hardware supports ioltb caching hints through the alh and eh fields in context-entries. 4r o 0 b c o r e extended interrupt mode (eim): 0 = hardware supports only 8-bit apicids (legacy interrupt mode ) on intel ? 64 and ia-32 platforms and 16- bit apic-ids on itanium? platforms. 1 = hardware supports extended interrupt mode (32-bit apic-ids) on intel ? 64 platforms. this field is valid only when th e ir field is reported as set. datasheet 431 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 3r o 0 b c o r e interrupt remapping support (ir): 0 = hardware does not support interrupt remapping. 1 = hardware supports interrupt remapping. implementations reporting this field as set must also support queued invalidation (qi = 1b). 2r o 0 b c o r e device iotlb support (di): 0 = ? 0: hardware does not support device- iotlbs. 1 = ? 1: hardware suppo rts device-iotlbs. implementations reporting this field as set must also support queued invalidation (qi = 1b). 1r o 0 b c o r e queued invalidation support (qi): 0 = hardware does not support queued invalidations. 1 = hardware supports queued invalidations. 0r o 0 b c o r e coherency (c): 0 = hardware accesses to the root, context, and page table structures are non-coherent (non-snoop) 1 = hardware accesses to the root, context, and page table structures are coherent (snoop). hardware writes to the advanced fault log is required to be coherent. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 432 datasheet 12.1.4 gcmd_reg?global command register b/d/f/type: 0/0/0/vc0premap address offset: 18-1bh default value: 00000000h access: ro, w size: 32 bits this register controls dma-remapping hardware. if multiple control fields in this register need to be modified, software must serialize through multiple writes to this register. bit access default value rst/pwr description 31 w 0b core translation enable (te): software writes to this field to request hardware to enab le/disable dma-remapping hardware. 0 = disable dma-remapping hardware 1 = enable dma-remapping hardware hardware reports the status of the translation enable operation through the tes field in the global status register. before enabling (or re-enabl ing) dma-remapping hardware through this field, software must: ? setup the dma-remapping structures in memory ? flush the write buffers (thr ough wbf fiel d), if write buffer flushing is re ported as required. ? set the root-entry table po inter in hardware (through srtp field). ? perform global invalidation of the context-cache and global invalidation of iotlb ? if advanced fault logging supported, setup fault log pointer (through sfl field) and enable advanced fault logging (through eafl field). there may be active dma requ ests in the platform when software updates this field. hardware must enable or disable remapping lo gic only at deterministic transaction boundaries, so that any in-f light transaction is either subject to remapping or not at all. hardware implementations su pporting dma draining must drain any in-flight translated dma read/write requests queued within the root comp lex before completing the translation enable command an d reflecting the status of the command through the tes field in the gsts_reg. value returned on read of this field is undefined. datasheet 433 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 30 w 0b core set root table pointer (srtp): software sets this field to set/update the root-entry table pointer used by hardware. the root-entry table pointer is specified through the root-entry table address register. hardware reports the status of the root table pointer set operation through the rtps field in the global status register. the root table pointer set operation must be performed before enabling or re-enabl ing (after disabling) dma- remapping hardware. after a root table pointer se t operation, so ftware must globally invalidate the context cache followed by global invalidate of iotlb. this is required to ensure hardware uses only the remapping struct ures referenced by the new root table pointer, and not any stale cached entries. while dma-remapping hardware is active, software may update the root table pointer through this field. however, to ensure valid in-flight dma requests are deterministically remapped, software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previo us root table pointer. clearing this bit has no effect . value returned on read of this field is undefined. 29 ro 0b core set fault log (sfl): this field is valid only for implementations supporting ad vanced fault logging. if advanced fault logging is not supported, writes to this field are ignored. software sets this field to request hard ware to set/update the fault-log pointer used by hardware. the fault-log pointer is specified through advanced fault log register. hardware reports the status of the fault log set operation through the fls field in th e global status register. the fault log pointer must be set before enabling advanced fault logging (through eafl field). once advanced fault logging is enabled, the faul t log pointer may be updated through this field while dma-re mapping hardware is active. clearing this bit has no effect . value returned on read of this field is undefined. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 434 datasheet 28 ro 0b core enable advanced fault logging (eafl): this field is valid only for implementations supporting advanced fault logging. if advanced fault loggi ng is not supported, writes to this field are ignored. soft ware writes to this field to request hardware to enable or disable advanced fault logging. 0 = disable advanced fault logging. in this case, translation faults are re ported through the fault recording registers. 1 = enable use of memory-r esident fault log. when enabled, translation faul ts are recorded in the memory-resident log. the faul t log pointer must be set in hardware (through sfl field) before enabling advanced fault logging. hardware reports the status of the advanced fault logging enable operation through the afls field in the global status register. value returned on read of this field is undefined. note: this field is reserved as this feature is not supported. 27 w 0b core write buffer flush (wbf): this bit is valid only for implementations requ iring write buffer flushing. if write buffer flushing is not required, writes to this field are ignored. software sets this field to request hardware to flush the root-complex internal write buff ers. this is done to ensure any updates to the memory-resident dma-remapping structures are not held in any internal write posting buffers. refer to section 9.1 for details on write-buffer flushing requirements. hardware reports the status of the write buffer flushing operation through the wbfs fi eld in the global status register. clearing this bit has no effect. value returned on read of this field is undefined. 26 ro 0b core queued invalidation enable (qie): this field is valid only for implementations suppo rting queued invalidations. software writes to this field to enable or disable queued invalidations. 0 = disable queued invalidations. 1 = enable use of queued invalidations. hardware reports the status of queued invalidation enable operation through qies field in the global status register. the value returned on a read of this field is undefined. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description datasheet 435 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 25 ro 0b core interrupt remapping enable (ire): this field is valid only for implementations su pporting interrupt remapping. 0 = disable interrupt-remapping hardware 1 = enable interrupt-remapping hardware hardware reports the status of the interrupt remapping enable operation through the ires field in the global status register. there may be active interrupt requests in the platform when software updates this fiel d. hardware must enable or disable interrupt-remapping lo gic only at deterministic transaction boundaries, so that any in-flight interrupts are either subject to rema pping or not at all. hardware implementations must drain any in-flight interrupts requests queued in the root-complex before completing the interrupt-rem apping enable command and reflecting the status of th e command through the ires field in the global status register. the value returned on a read of this field is undefined. note: this field is reserved as this feature is not supported. 24 ro 0b core set interrupt remap table pointer (sirtp): this field is valid only for implemen tations supporting interrupt- remapping. software sets this field to set/update the interrupt remapping table pointer used by hardware. the interrupt remapping table pointer is sp ecified through the interrupt remapping table a ddress register. hardware reports the status of the interrupt remapping table pointer set operation through the irtps field in the global status register. the interrupt remap table pointer set operation must be performed before enabling or re- enabling (after disabling) interrupt-remapping hardware through the ire field. after an interrupt remap table pointer set operation, software must globally invalida te the interrupt entry cache. this is required to ensure hardware uses only the interrupt-remapping entrie s referenced by the new interrupt remap tabl e pointer, and not any stale cached entries. while interrupt remapping is active, software may update the interrupt remapping table pointer through this field. however, to ensure valid in-f light interrupt requests are deterministically rema pped, software must ensure that the structures referenced by th e new interrupt remap table pointer are programmed to provide the same remapping results as the stru ctures referenced by the previous interrupt remap table pointer. clearing this bit has no effe ct. the value returned on a read of this field is undefined. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 436 datasheet 23 ro 0b core compatibility format interrupt (cfi): this field is valid only for intel 64 implemen tations supporting interrupt- remapping. software writes to this field to enable or disable compatibilit y format interrupts on intel 64 platforms. the value in this field is effective only when interrupt-remapping is enable d and legacy interrupt mode is active. 0 = block compatibility format interrupts. 1 = process compatibility fo rmat interrupts as pass- through (bypass interrupt remapping). hardware reports the status of updating this field through the cfis field in the gl obal status register. the value returned on a read of this field is undefined. this field is not im plemented on itanium? implementations. note: this field is reserved as this feature is not supported. 22:0 ro 000000h core reserved bit access default value rst/pwr description datasheet 437 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.1.5 gsts_reg?global status register b/d/f/type: 0/0/0/vc0premap address offset: 1c-1fh default value: 00000000h access: ro size: 32 bits this register reports general dma-remapping hardware status. bit access default value rst/pwr description 31 ro 0b core translation enable status (tes): this field indicates the status of dma-remapping hardware. 0 = dma-remapping hardware is not enabled 1 = dma-remapping hardware is enabled 30 ro 0b core root table pointer status (rtps): this field indicates the status of the root- table pointer in hardware. this field is cleared by hard ware when software sets the srtp field in the global command register. this field is set by hardware when hardware completes the set root-table pointer operation using the value provided in the root- entry table address register. 29 ro 0b core fault log status (fls): this field is valid only for implementations supporting advanced fault logging. this field indicates the status of the fault-log pointer in hardware. this field is cleared by hard ware when software sets the sfl field in the global command register. this field is set by hardware when hardware completes the set fault-log pointer operation using the value provided in the advanced fault log register. 28 ro 0b core advanced fault logging status (afls): this field is valid only for implementation s supporting advanced fault logging. this field in dicates advanced fault logging status. 0 = advanced fault logging is not enabled 1 = advanced fault lo gging is enabled 27 ro 0b core write buffer flush status (wbfs): this bit is valid only for implementations requir ing write buffer flushing. this field indicates the stat us of the write buffer flush operation. this field is set by hardware when software sets the wbf field in the global co mmand register. this field is cleared by hardware when ha rdware comple tes the write buffer flushing operation. 26 ro 0b core queued invalidation enable status (qies): this field indicates queued invalidation enable status. 0 = queued invalidation is not enabled 1 = queued invalidation is enabled 25 ro 0b core interrupt remapping enable status (ires): this field indicates the status of in terrupt-remapping hardware. 0 = interrupt-remapping hardware is not enabled 1 = interrupt-remapping hardware is enabled intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 438 datasheet 12.1.6 rtaddr_reg?root-entr y table address register b/d/f/type: 0/0/0/vc0premap address offset: 20-27h default value: 0000000000000000h access: r/w, ro size: 64 bits this register provides the base address of root-entry table. 24 ro 0b core interrupt remapping table pointer status (irtps): this field indicates the status of the interrupt remapping table pointer in hardware. this field is cleared by hard ware when software sets the sirtp field in the global comma nd register. this field is set by hardware when hardware completes the set interrupt remap tabl e pointer operation using the value provided in the interrupt remapping table address register. 23 ro 0b core compatibility format interrupt status (cfis): this field indicates the status of compatibility format interrupts on intel 64 implementations supporting interrupt- remapping. the value reported in this field is applicable only when interrupt-remappi ng is enabled and legacy interrupt mode is active. 0 = compatibility format interrupts are blocked. 1 = compatibility format interr upts are processed as pass- through (bypassing interrupt remapping). 22:0 ro 000000h core reserved bit access default value rst/pwr description bit access default value rst/pwr description 63:12 r/w 000000000 0000h core root table address (rta): this register points to base of page aligned, 4 kb-sized r oot-entry table in system memory. hardware may ignore and not implement bits 63:haw, where haw is the host address width. software specifies the base a ddress of the root-entry table through this register, and prog rams it in hardware through the srtp field in the gl obal command register. reads of this register re turns value that was last programmed to it. 11:0 ro 000h core reserved datasheet 439 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.1.7 ccmd_reg?context command register b/d/f/type: 0/0/0/vc0premap address offset: 28-2fh default value: 0000000000000000h access: w, r/w, ro size: 64 bits register to manage context cache. the act of writing the uppermost byte of the ccmd_reg with icc field set causes the hardware to perform the context-cache invalidation. bit access default value rst/pwr description 63 r/w 0h core invalidate context-cache (icc): software requests invalidation of context-cache by setting this field. software must also set the requested invalidation granularity by programming the cirg field. software must read back an d check the icc field to be clear to confirm the invalidation is complete. software must not update this regist er when this field is set. hardware clears the icc field to indicate the invalidation request is complete. hardware also indicates the granularity at which the invalidation operation was performed through the caig field. software must not submit another invalidation re quest through this register while the icc field is set. software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this dma-remapping hardware unit. refer to section 9 for software programming requirements. since information from the cont ext-cache may be used by hardware to tag iotlb entrie s, software must perform domain-selective (or global) in validation of iotlb after the context cache invalidation has completed. hardware implementations repo rting write-buffer flushing requirement (rwbf=1 in ca pability register) must implicitly perform a write buffer flushing before reporting invalidation complete to soft ware through th e icc field. refer to section 9.1 for write buffer flushing requirements. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 440 datasheet 62:61 r/w 0h core context invalidation request granularity (cirg): software provides the reques ted invalidation granularity through this field when setting the icc field. 00 = reserved. 01 = global invalidation request. 10 = domain-selective invalidation request. the target domain-id must be specified in the did field. 11 = device-selective invalidation request. the target source-id(s) must be specified through the sid and fm fields, and the domain-id (that was programmed in the context-entry for these device(s)) must be provided in the did field. hardware implementations may process an invalidation request by performing invalida tion at a coarser granularity than requested. hardware in dicates completion of the invalidation request by clearing the icc field. at this time, hardware also indicates the gr anularity at which the actual invalidation was performed through the caig field. 60:59 ro 0h core context actual invalidation granularity (caig): hardware reports the granularit y at which an invalidation request was processed through the caig field at the time of reporting invalidation completion (by clearing the icc field). 00 =reserved. 01= global invalidation performed. this could be in response to a global, doma in-selective or device- selective invalidation request. 10 =domain-selective invalida tion performed using the domain-id specified by software in the did field. this could be in response to a domain-selective or device- selective invalidation request. 11 =device-selective invalidation performed using the source-id and domain-id specified by software in the sid and fm fields. this can only be in response to a device-selective inva lidation request. 58:34 ro 000000000h core reserved bit access default value rst/pwr description datasheet 441 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 33:32 w 0h core function mask (fm): this field specifies which bits of the function number portion (least significant three bits) of the sid field to mask when pe rforming device-selective invalidations. 00 =no bits in the sid field masked. 01 =mask most significant bi t of function number in the sid field. 10 =mask two most significant bit of function number in the sid field. 11 =mask all three bits of function number in the sid field. the device(s) specified through the fm and sid fields must correspond to the domain-id specified in the did field. value returned on read of this field is undefined. 31:16 w 0000h core source id (sid): this field indicates the source-id of the device whose corresponding context-entry needs to be selectively invalidated. this field along with the fm field must be programmed by soft ware for device-selective invalidation requests. value returned on read of this field is undefined. 15:0 r/w 0000h core domain-id (did): this field indicates the id of the domain whose context-entries needs to be selectively invalidated. this field must be programmed by software for both domain-selective and device-selective invalidation requests. the capability register re ports the domain-id width supported by hardware. softwa re must ensure that the value written to this field is within this limit. hardware may ignore and not implement bits 15:n where n is the supported domain-id width reported in the capability register. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 442 datasheet 12.1.8 fsts_reg?fault status register b/d/f/type: 0/0/0/vc0premap address offset: 34-37h default value: 00000000h access: ro, ro/p, r/wc/p size: 32 bits this register indicates the primary fault logging status. section 8.4.18.1 describes hardware behavior for primary fault logging. bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:8 ro/p 00h core fault record index (fri): this field is valid only when the ppf field is set. the fri field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the ppf field was set by hardware. valid values for this field are from 0 to n, where n is the value reported throug h nfr field in the capability register. the value read from this fiel d is undefined when the ppf field is clear. 7 ro 0b core reserved 6ro 0b core invalidation time-out error (ite): hardware detected a device-iotlb invalidation completion time-out. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations no t supporting device-iotlbs implement this bit as reserved . note: this field is reserved as this feature is not supported. 5r o 0 b c o r e invalidation completion error (ice): hardware received an unexp ected or invalid device-iotlb invalidation completion. this could be due to either an invalid itag or invalid source-id in an invalidation completion response. at this time, a fault event may be generated based on the prog ramming of the fault event control register. hardware implementations no t supporting device-iotlbs implement this bit as reserved. note: this field is reserved as this feature is not supported. datasheet 443 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 4r o 0 b c o r e invalidation queue error (iqe): hardware detected an error associated with the invali dation queue. this could be due to either a hardware erro r while fetching a descriptor from the invalidation queue, or hardware detecting an erroneous or invalid descriptor in the invalidation queue. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations not supporting queued invalidations implement this bit as reserved . note: this field is reserved as this feature is not supported. 3r o 0 b c o r e advanced pending fault (apf): when this field is clear, hardware sets this field when the first fault record (at index 0) is written to a fault log. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supportin g advanced fault logging implement this bit as reserved . note: this field is reserved as this feature is not supported. 2r o 0 b c o r e advanced fault ov erflow (afo): hardware sets this field to indicate advanced fault log overflow condition. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supportin g advanced fault logging implement this bit as reserved . note: this field is reserved as this feature is not supported. 1ro/p 0h core primary pending fault (ppf): this field indicates if there are one or more pending faults logged in the fault recording registers. hardware computes this field as the logical or of fault (f) fields across all the fault recording registers of this dma-remapping hardware unit. 0 = no pending faults in any of the fault recording registers. 1 = one or more fault reco rding registers has pending faults. the fri field is updated by hardware whenever the ppf field is set by ha rdware. also, depending on the programming of fault event control register, a fault event is generated when hardware sets this field. 0r/wc/p 0h core primary fault overflow (pfo): hardware sets this field to indicate overflow of fault recording registers. software writing 1 clears this field. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 444 datasheet 12.1.9 fectl_reg?fault event control register b/d/f/type: 0/0/0/vc0premap address offset: 38-3bh default value: 80000000h access: r/w, ro size: 32 bits this register specifies the fault event interrupt message control bits. bit access default value rst/pwr description 31 r/w 1h core interrupt mask (im): 0 = no masking of interrupt. wh en an interrupt condition is detected, hardware issues an interrupt message (using the fault event data and fault event address register values). 1 = this is the value on reset. software may mask interrupt message ge neration by sett ing this field. hardware is prohibited from sending the interrupt message when this field is set. 30 ro 0h core interrupt pending (ip): hardware sets the ip field whenever it detects an inte rrupt condition. interrupt condition is defined as: ? when primary fault logging is active, an interrupt condition occurs when hardware records a fault through one of the fault recording registers and sets the ppf field in fault status register. if the ppf field was already set at the ti me of recording a fault, it is not treated as a new interrupt condition. ? when advanced fault logging is active, an interrupt condition occurs when hardware records a fault in the first fault record (at index 0) of the current fault log and sets the apf field in the advanced fault log register. if the apf field was already set at the time of detecting/recording a fault, it is not treated as a new interrupt condition. the ip field is kept set by hardware while the interrupt message is held pending. th e interrupt message could be held pending due to interrupt ma sk (im field) being set, or due to other transient hardware conditions. the ip field is cleared by hard ware as soon as the interrupt message pending condition is serviced. this could be due to either: ? hardware issuing the interru pt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the im field. ? software servicing the interrupting condition through one of the following ways: ? when primary fault logging is active, software clearing the fault (f) field in all the fault recording registers with faults, causing the ppf field in fault status register to be evaluated as clear. ? when advanced fault logging is active, software clearing the apf field in advanced fault log register. 29:0 ro 00000000h core reserved datasheet 445 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.1.10 fedata_reg?fault event data register b/d/f/type: 0/0/0/vc0premap address offset: 3c-3fh default value: 00000000h access: ro, r/w size: 32 bits this register specifies the interrupt message data. 12.1.11 feaddr_reg?fault event address register b/d/f/type: 0/0/0/vc0premap address offset: 40-43h default value: 00000000h access: ro, r/w size: 32 bits this register specifies the interrupt message address. bit access default value rst/pwr description 31:16 ro 0000h core extended interrupt message data (eimd): this field is valid only for implementation s supporting 32-bit msi data fields.hardware implementati ons supporting only 16-bit msi data may treat this field as read only (0). 15:0 r/w 0000h core interrupt message data (imd): data value in the fault- event interrupt message. bit access default value rst/pwr description 31:2 r/w 00000000h core message address (ma): when fault events are enabled, the contents of this register specify the dword aligned address (bits 31:2) for the ms i memory write transaction. 1:0 ro 0h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 446 datasheet 12.1.12 feuaddr_reg?fault ev ent upper address register b/d/f/type: 0/0/0/vc0premap address offset: 44-47h default value: 00000000h access: ro size: 32 bits this register specifies the interrupt message address. for platforms supporting only interrupt messages in the 32-bit address range, this register is treated as read-only (0). bit access default value rst/pwr description 31:0 ro 00000000h core message upper address (mua): this field needs to be implemented only if hardware supports 64-bit message address. if implemented, the contents of this register specify the upper 32-bits of a 64- bit msi write transaction. if hardware does not support 64-bit messages, the register is treated as read only (0). note: this field is reserved as this feature is not supported. datasheet 447 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.1.13 aflog_reg?advanced fault log register b/d/f/type: 0/0/0/vc0premap address offset: 58-5fh default value: 0000000000000000h access: ro size: 64 bits this register specifies the base address of memory-resident fault-log region. this register is treated as read only (0) for implementations not supporting advanced translation fault logging (afl field reported as 0 in the capability register). this register is sticky and can be cleared only through po wergood reset or via software clearing the rw1c fields by writing a 1. bit access default value rst/pwr description 63:12 ro 000000000 0000h core fault log address (fla): this field specifies the base of size-aligned fault-log region in system memory. hardware may ignore and not implement bits 63:haw, where haw is the host address width. software specifies the base address and size of the fault log region through this regi ster, and programs it in hardware through the sfl field in the global command register. when implemented, reads of this field returns value that was last programmed to it. note: this field is reserved as this feature is not supported. 11:9 ro 0h core fault log size (fls): this field specifies the size of the fault log region pointed by the fla field. the size of the fault log region is 2x * 4kb, where x is the value programmed in this register. when implemented, reads of th is field returns value that was last programmed to it. note: this field is reserved as this feature is not supported. 8:0 ro 0s core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 448 datasheet 12.1.14 pmen_reg?protected memory enable register b/d/f/type: 0/0/0/vc0premap address offset: 64-67h default value: 00000000h access: ro, r/w size: 32 bits this register is used to enable the dma protected memory regions setup through the plmbase, plmlimt, phmbase, phmlimit registers. when lt.cmd.lock.pmrc command is invoked, this register is lock ed (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro (0) for implementations not supporting protected memory regions (plmr and phmr fields reported as 0 in the capability register). bit access default value rst/pwr description 31 r/w 0h core enable protected memory (epm): this field controls dma accesses to the protecte d low-memory and protected high-memory regions. 0 = dma accesses to prot ected memory regions are handled as follows: ? if dma-remapping hardware is not enabled, dma requests (including those to protected regions) are not blocked. ? if dma-remapping hardware is enabled, dma requests are translated per the programming of the dma-remapping structures . software may program the dma-remapping structur es to allow or block dma to the protected memory regions. 1 = dma accesses to prot ected memory regions are handled as follows: ? if dma-remapping hardware is not enabled, dma to protected memory regions are bloc ked. these dma requests are not recorded or reported as dma- remapping faults. ? if dma-remapping hardware is enabled, hardware may or may not block dma to the protected memory region(s). softwa re must not depend on hardware protection of the protected memory regions, and must ensu re the dma-remapping structures are properly programmed to not allow dma to the protected memory regions. hardware reports the status of the protected memory enable/disable operation through the prs field in this register. hardware implementations su pporting dma draining must drain any in-flight translated dma requests queued within the root complex before indicating the protected memory region as enabled through the prs field. 30:1 ro 00000000h core reserved 0ro 0h core protected region status (prs): this field indicates the status of protecte d memory region. 0 = protected memory region(s) not enabled. 1 = protected memory region(s) enabled. datasheet 449 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.1.15 plmbase_reg?protected low-memory base register b/d/f/type: 0/0/0/vc0premap address offset: 68-6bh default value: 00000000h access: r/w, ro size: 32 bits this register is used to setup the base address of dma protected low-memory region. this register must be setup before en abling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as 0 in the capability register). the alignment of the protected low memory re gion base depends on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1's to this register, and finding most significant zero bit position with 0 in the value read back from the register. bits n:0 of this register is decoded by hardware as all 0s. bit access default value rst/pwr description 31:21 r/w 000h core protected low-memory base (plmb): this register specifies the base of size al igned, protected low-memory region in system memory. the protected low-memory region has a minimum size of 2 mb and must be size aligned. 20:0 ro 000000h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 450 datasheet 12.1.16 plmlimit_reg?protected low-memory limit register b/d/f/type: 0/0/0/vc0premap address offset: 6c-6fh default value: 00000000h access: r/w, ro size: 32 bits this register is used to setup the limit address of dma protected low-memory region. this register must be setup before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as 0 in the capability register). the alignment of the protected low memory region limit depends on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position with 0 in the value read back from the register. bits n:0 of the limit register are decoded by hardware as all 1s. the protected low-memory base and limit registers functions as follows: ? programming the protected low-memory base and limit registers with the same value in bits 31:(n+1) specifies a protec ted low-memory region of size 2(n+1) bytes. ? programming the protected low-memory limit register with a value less than the protected low-memory base register disables the protected low-memory region. bit access default value rst/pwr description 31:21 r/w 000h core protected low-memory limit (plml): this field specifies the last host physical addr ess of the dma protected low- memory region in system memory. 20:0 ro 000000h core reserved datasheet 451 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.1.17 phmbase_reg?protected high-memory base register b/d/f/type: 0/0/0/vc0premap address offset: 70-77h default value: 0000000000000000h access: ro, r/w size: 64 bits this register is used to setup the base address of dma protected high-memory region. this register must be setup before en abling protected memory through pmen_reg, and must not be updated when protecte d memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as 0 in the capability register). the alignment of the protected high memory region base depends on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 0s. bit access default value rst/pwr description 63:21 r/w 000000000 00h core protected high-memory base (phmb): this register specifies the base of size alig ned, protected memory region in system memory. hardware may not use bits 63:haw, where haw is the host address width. the protected high-m emory region has a minimum size of 2 mb and must be size aligned. 20:0 ro 000000h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 452 datasheet 12.1.18 phmlimit_reg?protected high-memory limit register b/d/f/type: 0/0/0/vc0premap address offset: 78-7fh default value: 0000000000000000h access: r/w, ro size: 64 bits this register is used to setup the limit address of dma protected high-memory region. this register must be setup before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as 0 in the capability register). the alignment of the protected high memory region limit depe nds on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected high-memory base and limit registers functions as follows. ? programming the protected low-memory base and limit registers with the same value in bits haw:(n+1) specifies a protec ted low-memory region of size 2(n+1) bytes. ? programming the protected high-memory limit register with a value less than the protected high-memory base register disa bles the protected high-memory region. bit access default value rst/pwr description 63:21 r/w 000000000 00h core protected high-memory limit (phml): this register specifies the last host physical address of the dma protected high-memory regi on in system memory. hardware may not use bits 63:haw, where haw is the host address width. 20:0 ro 000000h core reserved datasheet 453 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.1.19 iva_reg?invalidate address register b/d/f/type: 0/0/0/vc0premap address offset: 100-107h default value: 0000000000000000h access: w, ro size: 64 bits this register provides the dma address whose corresponding iotlb entry needs to be invalidated through the corresponding iotlb invalidate register. this register is a write only register. the value returned on reads of this register is undefined. there is an iva_reg for each iotlb invalidation unit supported by hardware. bit access default value rst/pwr description 63:12 w 000000000 0000h core address (addr): software provides the dma address that needs to be page-s electively invalidated. to request a page-selective invali dation request to hardware, software must first write the appropriate fields in this register, and then issue appropriate page-s elective invalidate command through the iotlb_reg. hardware ignores bits 63:n , where n is the maximum guest address width (mgaw) supported. value returned on read of this field is undefined. 11:7 ro 00h core reserved 6w 0hcore invalidation hint (ih): the field provides hints to hardware to preserve or flush the non-leaf (page- directory) entries that ma y be cached in hardware. 0 = software may have modified both leaf and non-leaf page-table entries corresponding to mappings specified in the addr and am fields. on a pageselective invalidation request, hardware must flush both the cached leaf and non-leaf page-table value returned on read of this field is undefined. entries corresponding to mappings specified by addr and am fields. 1 = software has not modified any non-leaf page-table entries corresponding to mappings specified in the addr and am fields. on a page-selective invalidation request, hardware may pres erve the cached non-leaf page-table entries corresponding to mappings specified by addr and am fields. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 454 datasheet 5:0 w 00h core address mask (am): the value in this field specifies the number of low order bits of th e addr field that must be masked for the invalidation op eration. mask field enables software to request invalidati on of contiguous mappings for size-aligned regions. for example: mask value addr bits masked pages invalidated mask value addr bits masked pg inval 0n i l 1 11 2 2 21 3 : 1 2 4 31 4 : 1 2 8 4 15:12 16 5 16:12 32 6 17:12 64 7 18:12 128 8 19:12 256 hardware implementations re port the maximum supported mask value through the capabili ty register. value returned on read of this field is undefined. bit access default value rst/pwr description datasheet 455 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2 dmi vc1 remap engine registers table 27. dmi vc1 remap engine register address map address offset register symbol register name default value access 0?3h ver_reg version register 00000010h ro 8?fh cap_reg capability register 00c9008020 e30272h ro 10?17h ecap_reg extended capability register 0000000000 001000h ro 18?1bh gcmd_reg global command register 00000000h ro, w 1c?1fh gsts_reg global status register 00000000h ro 20?27h rtaddr_reg root-entry table address register 0000000000 000000h r/w, ro 28?2fh ccmd_reg context command register 0000000000 000000h ro, r/w, w 34?37h fsts_reg fault status register 00000000h ro, ro/p, r/wc/p 38?3bh fectl_reg fault event control register 80000000h ro, r/w 3c?3fh fedata_reg fault event data register 00000000h ro, r/w 40?43h feaddr_reg fault event address register 00000000h r/w, ro 44?h feuaddr_reg fault event upper address register 00000000h ro 58?5fh aflog_reg advanced fault log register 0000000000 000000h ro 64?67h pmen_reg protected memory enable register 00000000h ro, r/w 68?6bh plmbase_reg protected low-memory base register 00000000h r/w, ro 6c?6fh plmlimit_reg protected low-memory limit register 00000000h r/w, ro 70?77h phmbase_reg protected high-memory base register 0000000000 000000h r/w, ro 78?7fh phmlimit_re g protected high -memory limit register 0000000000 000000h ro, r/w 100?107h iva_reg invalidate address register 0000000000 000000h w, r o 108?10fh iotlb_reg iotlb invalidate register 0000000000 000000h r/w, ro 200?20fh frcd_reg fault recording registers 0000000000 0000000000 0000000000 00h ro, ro/p, r/wc/p intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 456 datasheet 12.2.1 ver_reg?version register b/d/f/type: 0/0/0/dmivc1remap address offset: 0-3h default value: 00000010h access: ro size: 32 bits this register reports the architecture vers ion supported. backward compatibility for the architecture is maintained with new revisi on numbers, allowing software to load dma- remapping drivers written for prior architecture versions. 12.2.2 cap_reg?capability register b/d/f/type: 0/0/0/dmivc1remap address offset: 8-fh default value: 00c9008020e30272h access: ro size: 64 bits this register reports general dma remapping hardware capabilities bit access default value rst/pwr description 31:8 ro 000000000 000000000 000000b core reserved 7:4 ro 0001b core major version number (max): this field indicates supported architecture version. 3:0 ro 0000b core minor version number (min): this field indicates supported architecture minor version. bit access default value rst/pwr description 63:56 ro 00h core reserved 55 ro 1b core dma read draining (drd): indicates supported architecture version. 0 = on iotlb invalidations, hardware does not support draining of translated dm a read requests queued within the root complex. 1 = on iotlb invalidations, hardware supports draining of translated dma read requests queued within the root complex. 54 ro 1b core dma write draining (dwd): 0 = on iotlb invalidations, hardware does not support draining of translated dma writes queued within the root complex. 1 = on iotlb invalidations, hardware supports draining of translated dma writes queued within the root complex. 53:48 ro 001001b core maximum address ma sk value (mamv): the value in this field indicates the maximum supported value for the address mask (am) field in the invalidation address (iva_reg) register. datasheet 457 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 47:40 ro 00000000b core number of faultrecording registers (nfr): this field indicates a value of n-1, where n is the number of fault recording registers supported by hardware. implementations must support at least one fault recording register (nfr = 0) for each dmaremapping hardware unit in the platform. the maximum number of fault recording registers per dma-remapping hardware unit is 256. 39 ro 1b core page selective invalidation support (psi): 0 = indicates that the dmar engine does not support page selective invalidations 1 = indicates the dmar engine does support page- selective iotlb invalidations. the mamv field indicates the maximum number of contiguous translations that may be invalidated in a single request. 38 ro 0b core reserved 37:34 ro 0000b core super page support (sps): this field indi cates the super page sizes supported by hardware. a value of 1 in any of these bits indicates the corresponding super-page size is supported. the super- page sizes corresponding to vari ous bit positions within this field are: 0 = 21-bit offset to page frame 1 = 30-bit offset to page frame 2 = 39-bit offset to page frame 3 = 48-bit offset to page frame 33:24 ro 020h core fault-recording register offset (fro): this field specifies the location to the first fault recording register relative to the register base address of this dma- remapping hardware unit. if the register base address is x, and the value reported in this field is y, the address for the first fault recording register is calculated as x+(16*y). 23 ro 1b core isochrony (isoch): 0 = indicates this dma-remapping hardware unit has no critical isochronous re questers in its scope. 1 = indicates this dma-remapping hardware unit has one or more critical isochronou s requesters in its scope. to ensure isochronous perform ance, software must ensure invalidation operations do no t impact active dma streams. this implies that when dma is active, software perform page-selective in validations (instead of coarser invalidations). 22 ro 1b core zero length read (zlr): 0 = indicates the remapping hardware unit blocks (and treats as fault) zero leng th dma read requests to write-only pages. 1 = indicates the remapping hardware unit supports zero length dma read requests to write-only pages. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 458 datasheet 21:16 ro 100011b core maximum guest address width (mgaw): this field indicates the maximum dma virtual addressability supported by remapping hardware. the maximum guest address wi dth (mgaw) is computed as (n+1), where n is the value reported in this field. for example, a hardware implem entation supporting 48-bit mgaw reports a value of 47 (101111b) in this field. if the value in this field is x, dma requests to addresses above 2(x+1)-1 are always blocked by hardware. guest addressability for a given dma request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page-table structur e. (adjusted gues t address widths supported by hardware are reported through the sagaw field). 15:13 ro 000b core reserved 12:8 ro 00010b core supported adjusted guest address widths (sagaw): this 5-bit field indicates th e supported adjusted guest address widths (which in turn represents the levels of page-table walks) suppo rted by the hardware implementation. a value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported. the adjusted guest address widths corresponding to various bit positions within this field are: 0 = 30-bit agaw (2-level page table) 1 = 39-bit agaw (3-level page table) 2 = 48-bit agaw (4-level page table) 3 = 57-bit agaw (5-level page table) 4 = 64-bit agaw (6-level page table) software must ensure that the adjusted guest address width used to setup the page ta bles is one of the supported guest address widths re ported in this field. 7ro 0b core caching mode (cm): 0 = hardware does not cache not present and erroneous entries in the context-cache and iotlb. invalidations are not required for modifications to individual not present or invalid entries. however, any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective. 1 = hardware may cache not present and erroneous mappings in the context-cache or iotlb. any software updates to the dma-remapping structures (including updates to not-present or erroneous entries) require explicit invalidation. hardware implementations ar e recommended to support operation corresponding to cm=0. bit access default value rst/pwr description datasheet 459 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 6r o 1 b c o r e protected high-memory region (phmr): 0 = indicates protected high-memory region not supported. 1 = indicates protec ted high-memory regi on is supported. dma-remapping hardware impl ementations on intel txt platforms supporting main memory above 4 gb are required to support prot ected high-memory region. 5r o 1 b c o r e protected low-memory region (plmr): 0 = 0: indicates protected low-memory region not supported. 1 = 1: indicates protected low-memory region is supported. dma-remapping hardware impl ementations on intel txt platforms are required to su pport protected low-memory region. 4r o 1 b c o r e required write-buffer flushing (rwbf): 0 = indicates no write-buffer flushing needed to ensure changes to memory-resident structures are visible to hardware. 1 = indicates software must explicitly flush the write buffers (through the global command register) to ensure updates made to memory-resident dma-remapping structures are visible to hardware. 3r o 0 b c o r e advanced fault logging (afl): 0 = indicates advanced fault logging not supported. only primary fault logging is supported. 1 = indicates advanced fa ult logging is supported. 2:0 ro 010b core number of domains supported (nd): 000 = hardware supports 4-bit domain-ids with support for up to 16 domains. 001 = hardware supports 6-bit domain-ids with support for up to 64 domains. 010 = hardware supports 8-bit domain-ids with support for up to 256 domains. 011 = hardware supports 10-bit domain-ids with support for up to 1024 domains. 100 = hardware supports 12-bit domain-ids with support for up to 4k domains. 100 = hardware supports 14-bit domain-ids with support for up to 16k domains. 110 = hardware supports 16-bit domain-ids with support for up to 64k domains. 111 = reserved. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 460 datasheet 12.2.3 ecap_reg?extended capability register b/d/f/type: 0/0/0/dmivc1remap address offset: 10-17h default value: 0000000000001000h access: ro size: 64 bits this register reports dma-remapping hardware extended capabilities bit access default value rst/pwr description 63:24 ro 0s core reserved 23:20 ro 0000b core maximum handle mask value (mhmv): the value in this field indicates the maximum supported value for the handle mask (hm) field in the interrupt entry cache invalidation descriptor ( iec_inv_dsc ). this field is valid only when th e ir field is reported as set. 19:18 ro 00b core reserved 17:8 ro 010h core invalidation unit offset (ivo): this field specifies the location to the first iotlb invalidation unit relative to the register base address of th is dma-remapping hardware unit. if the regist er base address is x, and the value reported in this field is y, the address for the first iotlb invalidation unit is calculated as x+(16*y). if n is the value reported in niu field, the address for the last iotlb invalidation unit is calculated as x+(16*y)+(16*n). 7ro 0b core snoop control (sc): 0 = hardware does not support 1-setting of the snp field in the page-table entries. 1 = hardware supports the 1-sett ing of the snp field in the page-table entries. 6ro 0b core pass through (pt): 0 = hardware does not support passthrough translation type in context entries. 1 = hardware supports pass-through translation type in context entries. 5ro 0b core caching hints (ch): 0 = hardware does not support iotlb caching hints (alh and eh fields in context-entries are treated as reserved). 1 = hardware supports ioltb caching hints through the alh and eh fields in context-entries. 4ro 0b core extended interrupt mode (eim): 0 = hardware supports only 8-bit apicids (legacy interrupt mode) on intel?64 and ia-32 platforms and 16- bit apic-ids on itanium tm platforms. 1 = hardware supports extended interrupt mode (32-bit apic-ids) on intel?64 platforms. this field is valid only when th e ir field is reported as set. datasheet 461 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 3r o 0 b c o r e interrupt remapping support (ir): 0 = hardware does not support interrupt remapping. 1 = hardware supports interrupt remapping. implementations reporting this field as set must also support queued invalidation (qi = 1b). 2r o 0 b c o r e device iotlb support (di): 0 = hardware does not support device- iotlbs. 1 = hardware supports device-iotlbs. implementations reporting this field as set must also support queued invalidation (qi = 1b). note: this field is reserved as this feature is not supported. 1r o 0 b c o r e queued invalidation support (qi): 0 = hardware does not support queued invalidations. 1 = hardware supports queued invalidations. 0r o 0 b c o r e coherency (c): 0 = hardware accesses to the root, context, and page table structures are non-coherent (non-snoop). 1 = hardware accesses to the root, context, and page table structures are coherent (snoop). hardware writes to the advanced fault log is required to be coherent. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 462 datasheet 12.2.4 gcmd_reg?global command register b/d/f/type: 0/0/0/dmivc1remap address offset: 18-1bh default value: 00000000h access: ro, w size: 32 bits this register controls dma-remapping hardware. if multiple control fields in this register need to be modified, software must serialize through multiple writes to this register. bit access default value rst/pwr description 31 w 0b core translation enable (te): software writes to this field to request hardware to enab le/disable dma-remapping hardware. 0 = disable dma-remapping hardware 1 = enable dma-remapping hardware hardware reports the status of the translation enable operation through the tes field in the global status register. before enabling (or re-enabl ing) dma-remapping hardware through this field, software must: ? setup the dma-remapping structures in memory ? flush the write buffers (thr ough wbf fiel d), if write buffer flushing is re ported as required. ? set the root-entry table po inter in hardware (through srtp field). ? perform global invalidation of the context-cache and global invalidation of iotlb ? if advanced fault logging supported, setup fault log pointer (through sfl field) and enable advanced fault logging (through eafl field). there may be active dma requ ests in the platform when software updates this field. hardware must enable or disable remapping lo gic only at deterministic transaction boundaries, so that any in-f light transaction is either subject to remapping or not at all. hardware implementations su pporting dma draining must drain any in-flight translated dma read/write requests queued within the root comp lex before completing the translation enable command an d reflecting the status of the command through the tes field in the gsts_reg. value returned on read of this field is undefined. datasheet 463 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 30 w 0b core set root table pointer (srtp): software sets this field to set/update the root-entry table pointer used by hardware. the root-entry table pointer is specified through the root-entry table address register. hardware reports the status of the root table pointer set operation through the rtps field in the global status register. the root table pointer set operation must be performed before enabling or re-ena bling (after disabling) dmaremapping hardware. after a root table pointer se t operation, so ftware must globally invalidate the context cache followed by global invalidate of iotlb. this is required to ensure hardware uses only the remapping struct ures referenced by the new root table pointer, and no t any stale cached entries. while dma-remapping hardware is active, software may update the root table pointer through this field. however, to ensure valid in-flight dma requests are deterministically remapped, software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previo us root table pointer. clearing this bit has no effect. value returned on read of this field is undefined. 29 ro 0b core set fault log (sfl): this field is valid only for implementations supporting ad vanced fault logging. if advanced fault logging is not supported, writes to this field are ignored. software sets this field to request hard ware to set/update the fault-log pointer used by hardware. the fault-log pointer is specified through advanced fault log register. hardware reports the status of the fault log set operation through the fls field in the glob al status register. the fault log pointer must be set befo re enabling advanced fault logging (through eafl field). once advanced fault logging is enabled, the fault log po inter may be updated through this field while dma-remapping hardware is active. clearing this bit has no effect . value returned on read of this field is undefined. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 464 datasheet 28 ro 0b core enable advanced fault logging (eafl): this field is valid only for implementations supporting advanced fault logging. if advanced fault loggi ng is not supported, writes to this field are ignored. software writes to this field to request hardware to enable or disable advanced fault logging. 0 = disable advanced fault logging. in this case, translation faults are re ported through the fault recording registers. 1 = enable use of memory-r esident fault log. when enabled, translation faul ts are recorded in the memory-resident log. the faul t log pointer must be set in hardware (through sfl field) before enabling advanced fault logging. hardware reports the status of the advanced fault logging enable operation through the afls field in the global status register. value returned on read of this field is undefined. note: this field is reserved as this feature is not supported. 27 w 0b core write buffer flush (wbf): this bit is valid only for implementations requ iring write buffer flushing. if write buffer flushing is not required, writes to this field are ignored. software sets this field to request hardware to flush the root-complex internal write buff ers. this is done to ensure any updates to the memory-resident dma-remapping structures are not held in any internal write posting buffers. refer to section 9.1 for details on write-buffer flushing requirements. hardware reports the status of the write buffer flushing operation through the wbfs fi eld in the global status register. clearing this bit has no effect. value returned on read of this field is undefined. note: this field is reserved as this feature is not supported. 26 ro 0b core queued invalidation enable (qie): this field is valid only for implementations suppo rting queued invalidations. software writes to this field to enable or disable queued invalidations. 0 = disable queued invalidations. 1 = enable use of queued invalidations. hardware reports the status of queued invalidation enable operation through qies field in the global status register. refer to section 6.2.2 for software requirements for enabling/disabling queued invalidations. the value returned on a read of this field is undefined. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description datasheet 465 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 25 ro 0b core interrupt remapping enable (ire): this field is valid only for implementations su pporting interrupt remapping. 0 = disable interrupt-remapping hardware 1 = enable interrupt-remapping hardware hardware reports the status of the interrupt remapping enable operation through the ires field in the global status register. there may be active interrupt requests in the platform when software updates this fiel d. hardware must enable or disable interrupt-remapping lo gic only at deterministic transaction boundaries, so that any in-flight interrupts are either subject to rema pping or not at all. hardware implementations must drain any in-flight interrupts requests queued in the root-complex before completing the interrupt-rem apping enable command and reflecting the status of th e command through the ires field in the global status register. the value returned on a read of this field is undefined. notes: this field is reserved as this feature is not supported. 24 ro 0b core set interrupt remap table pointer (sirtp): this field is valid only for implemen tations supporting interrupt- remapping. software sets this field to set/update the interrupt remapping table pointer used by hardware. the interrupt remapping table pointer is sp ecified through the interrupt remapping table a ddress register. hardware reports the status of the interrupt remapping table pointer set operation through the irtps field in the global status register. the interrupt remap table pointer set operation must be performed before enabling or re- enabling (after disabling) interrupt-remapping hardware through the ire field. after an interrupt remap table pointer set operation, software must globally invalida te the interrupt entry cache. this is required to ensure hardware uses only the interrupt-remapping entrie s referenced by the new interrupt remap tabl e pointer, and not any stale cached entries. while interrupt remapping is active, software may update the interrupt remapping table pointer through this field. however, to ensure valid in-f light interrupt requests are deterministically rema pped, software must ensure that the structures referenced by th e new interrupt remap table pointer are programmed to provide the same remapping results as the stru ctures referenced by the previous interrupt remap table pointer. clearing this bit has no effe ct. the value returned on a read of this field is undefined. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 466 datasheet 12.2.5 gsts_reg?global status register b/d/f/type: 0/0/0/dmivc1remap address offset: 1c-1fh default value: 00000000h access: ro size: 32 bits this register reports general dma-remapping hardware status. 23 ro 0b core compatibility format interrupt (cfi): this field is valid only for intel?64 implemen tations supporting interrupt- remapping. software writes to this field to enable or disable compatibil ity format interr upts on intel?64 platforms. the value in this field is effective only when interrupt-remapping is enable d and legacy interrupt mode is active. 0 = block compatibility format interrupts. 1 = process compatibility fo rmat interrupts as pass- through (bypass interrupt remapping). hardware reports the status of updating this field through the cfis field in the gl obal status register. refer to section 5.4.1 for deta ils on compatibility format interrupt requests. the value returned on a read of this field is undefined. note: this field is not im plemented on itanium? implementations. note: this field is reserved as this feature is not supported. 22:0 ro 000000h core reserved bit access default value rst/pwr description bit access default value rst/pwr description 31 ro 0b core translation enable status (tes): this field indicates the status of dma-remapping hardware. 0 = dma-remapping hardware is not enabled 1 = dma-remapping hardware is enabled 30 ro 0b core root table pointer status (rtps): this field indicates the status of the root- table pointer in hardware. this field is cleared by hard ware when software sets the srtp field in the global comman d register. this field is set by hardware when hardware completes the set root-table pointer operation using the value provided in the root- entry table address register. datasheet 467 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 29 ro 0b core fault log status (fls): this field is valid only for implementations supporting advanced fault logging. this field indicates the status of the fault-log pointer in hardware. this field is cleared by hard ware when software sets the sfl field in the global command register. this field is set by hardware when hardware completes the set fault-log pointer operation using the value provided in the advanced fault log register. 28 ro 0b core advanced fault logging status (afls): this field is valid only for implementation s supporting advanced fault logging. this field indicates advanced fault logging status. 0 = advanced fault logging is not enabled 1 = advanced fault lo gging is enabled 27 ro 0b core write buffer flush status (wbfs): this bit is valid only for implementations requir ing write buffer flushing. this field indicates the stat us of the write buffer flush operation. this field is set by hardware when software sets the wbf field in the global co mmand register. this field is cleared by hardware when ha rdware comple tes the write buffer flushing operation. 26 ro 0b core queued invalidation enable status (qies): this field indicates queued invalidation enable status. 0 = queued invalidation is not enabled 1 = queued invalidation is enabled 25 ro 0b core interrupt remapping enable status (ires): this field indicates the status of in terrupt-remapping hardware. 0 = interrupt-remapping hardware is not enabled 1 = interrupt-remapping hardware is enabled 24 ro 0b core interrupt remapping table pointer status (irtps): this field indicates the status of the interrupt remapping table pointer in hardware. this field is cleared by hard ware when software sets the sirtp field in the global comm and register. this field is set by hardware when hardware completes the set interrupt remap table pointe r operation using the value provided in the interrupt remapping table address register. 23 ro 0b core compatibility format in terrupt status (cfis): this field indicates the st atus of compatibility format interrupts on intel?64 implementati ons supporting interrupt- remapping. the value reported in this field is applicable only when interrupt-remappi ng is enabled and legacy interrupt mode is active. 0 = compatibility format interrupts are blocked. 1 = compatibility format inte rrupts are processed as pass- through (bypassing interrupt remapping). 22:0 ro 000000h core reserved bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 468 datasheet 12.2.6 rtaddr_reg?root-entr y table address register b/d/f/type: 0/0/0/dmivc1remap address offset: 20-27h default value: 0000000000000000h access: r/w, ro size: 64 bits this register provides the base address of root-entry table. bit access default value rst/pwr description 63:12 r/w 000000000 0000h core root table address (rta): this field points to the base of page aligned, 4 kb-sized root-entry table in system memory. hardware may ignore and not implement bits 63:haw, where haw is the host address width. software specifies the base a ddress of the root-entry table through this register, and prog rams it in hardware through the srtp field in the gl obal command register. reads of this register re turns value that was last programmed to it. 11:0 ro 000h core reserved datasheet 469 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.7 ccmd_reg?context command register b/d/f/type: 0/0/0/dmivc1remap address offset: 28-2fh default value: 0000000000000000h access: ro, r/w, w size: 64 bits this register is used to manage context cach e. the act of writing the uppermost byte of the ccmd_reg with icc field set causes the hardware to perform the context-cache invalidation. bit access default value rst/pwr description 63 r/w 0h core invalidate context-cache (icc): software requests invalidation of context-cache by setting this field. software must also set the requested invalidation granularity by programming the cirg field. software must read back an d check the icc field to be clear to confirm the invalidation is complete. software must not update this register when this fi eld is set. hardware clears the icc field to indicate the invalidation request is complete. hardware also indicates the granularity at which the invalidation operation was performed through the caig field. software must not submit another invalidation re quest through this register while the icc field is set. software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this dma-remapping hardware unit. refer to section 9 for software programming requirements. since information from the cont ext-cache may be used by hardware to tag iotlb entrie s, software must perform domain-selective (or global) in validation of iotlb after the context cache invalidation has completed. hardware implementations repo rting write-buffer flushing requirement (rwbf=1 in ca pability register) must implicitly perform a write buffer flushing before reporting invalidation complete to soft ware through the icc field. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 470 datasheet 62:61 r/w 0h core context invalidation request granularity (cirg): software provides the reques ted invalidation granularity through this field when setting the icc field. 00 =reserved. 01 =global invali dation request. 10 =domain-selective invalida tion request. the target domain-id must be specified in the did field. 11 =device-selective invalidation request. the target source-id(s) must be specified through the sid and fm fields, and the domain-id (that was programmed in the context-entry for these device(s)) must be provided in the did field. hardware implementations may process an invalidation request by performing invalida tion at a coarser granularity than requested. hardware in dicates completion of the invalidation request by clearing the icc field. at this time, hardware also indicates the gr anularity at which the actual invalidation was performed through the caig field. 60:59 ro 0h core context actual invalidation granularity (caig): hardware reports the granularit y at which an invalidation request was processed through the caig field at the time of reporting invalidation completion (by clearing the icc field). 00 = reserved. 01 = global invalidation perfo rmed. this could be in response to a global, doma in-selective or device- selective invalidation request. 10 = domain-selective invalida tion performed using the domain-id specified by soft ware in the did field. this could be in response to a domain-selective or device-selective invalidation request. 11 = device-selective invalidation performed using the source-id and domain-id specified by software in the sid and fm fields. this can only be in response to a device-selective invalidation request. 58:34 ro 000000000h core reserved 33:32 w 0h core function mask (fm): this field specifies which bits of the function number portion (least significant three bits) of the sid field to mask when pe rforming device-selective invalidations. 00 = no bits in the sid field masked. 01 = mask most significant bit of function number in the sid field. 10 = mask two most significant bit of function number in the sid field. 11 = mask all three bits of fu nction number in the sid field. the device(s) specified through the fm and sid fields must correspond to the doma in-id specified in the did field. value returned on read of this field is undefined. bit access default value rst/pwr description datasheet 471 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.8 fsts_reg?fault status register b/d/f/type: 0/0/0/dmivc1remap address offset: 34-37h default value: 00000000h access: ro, ro/p, r/wc/p size: 32 bits this register indicates the primary fault logging status. 31:16 w 0000h core source id (sid): this field indicates the source-id of the device whose corresponding context-entry needs to be selectively invalidated. this field along with the fm field must be programmed by soft ware for device-selective invalidation requests. value returned on read of this field is undefined. 15:0 r/w 0000h core domain-id (did): this field indicates the id of the domain whose context-entries needs to be selectively invalidated. this field must be programmed by software for both domain-selective and device-selective invalidation requests. the capability register re ports the domain-id width supported by hardware. softwa re must ensure that the value written to this field is within this limit. hardware may ignore and not implement bits 15:n where n is the supported domain-id width reported in the capability register. bit access default value rst/pwr description bit access default value rst/pwr description 31:16 ro 0000h core reserved 15:8 ro/p 00h core fault record index (fri): this field is valid only when the ppf field is set. the fri field indicates the in dex (from base) of the fault recording register to which the first pending fault was recorded when the ppf field was set by hardware. valid values for this field are from 0 to n, where n is the value reported through nfr field in the capability register. the value read from this field is undefined when the ppf field is clear. 7 ro 0b core reserved 6r o 0 b c o r e invalidation time-out error (ite): hardware detected a device-iotlb invalidation completion time-out. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations no t supporting device-iotlbs implement this bit as reserved. note: this field is reserved as this feature is not supported. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 472 datasheet 5r o 0 b c o r e invalidation completion error (ice): hardware received an unexp ected or invalid device-iotlb invalidation completion. this could be due to either an invalid itag or invalid source-id in an invalidation completion response. at this time, a fault event may be generated based on the prog ramming of the fault event control register. hardware implementations no t supporting device-iotlbs implement this bit as reserved. note: this field is reserved as this feature is not supported. 4r o 0 b c o r e invalidation queue error (iqe): this field indicates that hardware detected an error associated with the invalidation queue. this could be due to either a hardware error while fetching a descriptor from th e invalidation queue, or hardware detecting an erroneou s or invalid descriptor in the invalidation queue. at this time, a fault event may be generated based on the prog ramming of the fault event control register. hardware implementation s not supporting queued invalidations implement this bit as reserved . note: this field is reserved as this feature is not supported. 3r o 0 b c o r e advanced pending fault (apf): when this field is clear, hardware sets this field when the first fault record (at index 0) is written to a fault log. at this time, a fault event is generated based on the prog ramming of the fault event control register. software writing 1 to this field clears it. hardware implementations no t supporting advanced fault logging implement this bit as reserved. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description datasheet 473 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.9 fectl_reg?fault event control register b/d/f/type: 0/0/0/dmivc1remap address offset: 38-3bh default value: 80000000h access: ro, r/w size: 32 bits this register specifies the fault event interrupt message control bits. 2r o 0 b c o r e advanced fault ov erflow (afo): hardware sets this field to indicate advanced fault log overflow condition. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supportin g advanced fault logging implement this bit as reserved. note: this field is reserved as this feature is not supported. 1ro/p 0h core primary pending fault (ppf): this field indicates if there are one or more pending faults logged in the fault recording registers. hardware computes this field as the logical or of fault (f) fields across all the fault recording registers of this dma-remapping hardware unit. 0 = no pending faults in any of the fault recording registers 1 = one or more fault reco rding registers has pending faults. the fri field is updated by hardware whenever the ppf field is set by ha rdware. also, depending on the programming of fault event control register, a fault event is generated when hardware sets this field. 0r/wc/p 0h core primary fault overflow (pfo): hardware sets this field to indicate overflow of fault recording registers. software writing 1 clears this field. bit access default value rst/pwr description bit access default value rst/pwr description 31 r/w 1h core interrupt mask (im): 0 = no masking of interrupt. when a interrupt condition is detected, hardware issues an interrupt message (using the fault event data & fault event address register values). 1 = this is the value on reset. software may mask interrupt message generation by setting this field. hardware is prohibited from sending the interrupt message when this field is set. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 474 datasheet 30 ro 0h core interrupt pending (ip): hardware sets the ip field whenever it detects an inte rrupt condition. interrupt condition is defined as: ? when primary fault logging is active, an interrupt condition occurs when hardware records a fault through one of the fault recording registers and sets the ppf field in fault status register. if the ppf field was already set at the ti me of recording a fault, it is not treated as a new interrupt condition. ? when advanced fault logging is active, an interrupt condition occurs when hardware records a fault in the first fault record (at index 0) of the current fault log and sets the apf field in the advanced fault log register. if the apf field was already set at the time of detecting/recording a fault, it is not treated as a new interrupt condition. the ip field is kept set by hardware while the interrupt message is held pending. th e interrupt message could be held pending due to interrupt ma sk (im field) being set, or due to other transient hardware conditions. the ip field is cleared by hard ware as soon as the interrupt message pending condition is serviced. this could be due to either: ? hardware issuing the interru pt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the im field. ? software servicing the interrupting condition through one of the following ways: ? when primary fault logging is active, software clearing the fault (f) field in all the fault recording registers with faults, causing the ppf field in fault status register to be evaluated as clear. ? when advanced fault logging is active, software clearing the apf field in advanced fault log register. 29:0 ro 00000000h core reserved bit access default value rst/pwr description datasheet 475 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.10 fedata_reg?fault event data register b/d/f/type: 0/0/0/dmivc1remap address offset: 3c-3fh default value: 00000000h access: ro, r/w size: 32 bits this register specifies the interrupt message data 12.2.11 feaddr_reg?fault event address register b/d/f/type: 0/0/0/dmivc1remap address offset: 40-43h default value: 00000000h access: r/w, ro size: 32 bits this register specifies the interrupt message address. bit access default value rst/pwr description 31:16 ro 0000h core extended interrupt message data (eimd): this field is valid only for implementation s supporting 32-bit msi data fields.hardware implementati ons supporting only 16-bit msi data may treat this field as read only (0). 15:0 r/w 0000h core interrupt message data (imd): data value in the fault- event interrupt message. bit access default value rst/pwr description 31:2 r/w 00000000h core message address (ma): when fault events are enabled, the contents of this register specify the dword aligned address (bits 31:2) for the ms i memory write transaction. 1:0 ro 0h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 476 datasheet 12.2.12 feuaddr_reg?fault ev ent upper address register b/d/f/type: 0/0/0/dmivc1remap address offset: 44-47h default value: 00000000h access: ro size: 32 bits this register specifies the interrupt message address. for platforms supporting only interrupt messages in the 32-bit address range, this register is treated as read-only (0). bit access default value rst/pwr description 31:0 ro 00000000h core message upper address (mua): this register need to be implemented only if hardware supports 64-bit message address. if implemented, the contents of this register specify the upper 32-bits of a 64- bi t msi write transaction. if hardware does not support 64-bit messages, the register is treated as read-only (0). note: this field is reserved as th is feature is not supported. datasheet 477 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.13 aflog_reg?advanced fault log register b/d/f/type: 0/0/0/dmivc1remap address offset: 58-5fh default value: 0000000000000000h access: ro size: 64 bits this register specifies the base address of memory-resident fault-log region. this register is treated as read only (0) for implementations not supporting advanced translation fault logging (afl field reported as 0 in the capability register). this register is sticky and can be cleared only through po wergood reset or via software clearing the rw1c fields by writing a 1. bit access default value rst/pwr description 63:12 ro 000000000 0000h core fault log address (fla): this field specifies the base of size-aligned fault-log region in system memory. hardware may ignore and not implement bits 63:haw, where haw is the host address width. software specifies the base address and size of the fault log region through this regi ster, and programs it in hardware through the sfl field in the global command register. when implemented, reads of th is field returns value that was last programmed to it. note: this field is reserved as this feature is not supported. 11:9 ro 0h core fault log size (fls): this field specifies the size of the fault log region pointed by the fla field. 00 = 4 kb 01 = 8 kb 10 = 16 kb 11 = 32 kb when implemented, reads of th is field returns value that was last programmed to it. note: this field is reserved as this feature is not supported. 8:0 ro 00h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 478 datasheet 12.2.14 pmen_reg?protected memory enable register b/d/f/type: 0/0/0/dmivc1remap address offset: 64-67h default value: 00000000h access: ro, r/w size: 32 bits this register is used to enable the dma protected memory regions setup through the plmbase, plmlimt, phmbase, phmlimit registers. when lt.cmd.lock.pmrc command is invoked, this register is lock ed (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro (0) for implementations not supporting protected memory regions (plmr and phmr fields reported as 0 in the capability register). bit access default value rst/pwr description 31 r/w 0h core enable protected memory (epm): this field controls dma accesses to the protecte d low-memory and protected high-memory regions. 0 = dma accesses to prot ected memory regions are handled as follows: ? if dma-remapping hardware is not enabled, dma requests (including those to protected regions) are not blocked. ? if dma-remapping hardware is enabled, dma requests are translated per the programming of the dma-remapping structures . software may program the dma-remapping structur es to allow or block dma to the protected memory regions. 1 = dma accesses to prot ected memory regions are handled as follows: ? if dma-remapping hardware is not enabled, dma to protected memory regions are bloc ked. these dma requests are not recorded or reported as dma- remapping faults. ? if dma-remapping hardware is enabled, hardware may or may not block dma to the protected memory region(s). softwa re must not depend on hardware protection of the protected memory regions, and must ensu re the dma-remapping structures are properly programmed to not allow dma to the protected memory regions. hardware reports the status of the protected memory enable/disable operation through the prs field in this register. hardware implementations su pporting dma draining must drain any in-flight translated dma requests queued within the root complex before indicating the protected memory region as enabled through the prs field. 30:1 ro 00000000h core reserved 0ro 0h core protected region status (prs): this field indicates the status of protecte d memory region. 0 = protected memory region(s) not enabled. 1 = protected memory region(s) enabled. datasheet 479 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.15 plmbase_reg?protected low-memory base register b/d/f/type: 0/0/0/dmivc1remap address offset: 68-6bh default value: 00000000h access: r/w, ro size: 32 bits this register is used to setup the base address of dma protected low-memory region. this register must be setup before en abling protected memory through pmen_reg, and must not be updated when protecte d memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as 0 in the capability register). the alignment of the protected low memory region base depend s on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position with 0 in the value read back from the register. bits n:0 of this register is decoded by hardware as all 0s. bit access default value rst/pwr description 31:21 r/w 000h core protected low-memory base (plmb): this register specifies the base of size al igned, protected low-memory region in system memory. the protected low-memory region has a minimum size of 2 mb and must be size aligned. 20:0 ro 000000h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 480 datasheet 12.2.16 plmlimit_reg?protected low-memory limit register b/d/f/type: 0/0/0/dmivc1remap address offset: 6c-6fh default value: 00000000h access: r/w, ro size: 32 bits this register is used to setup the limit address of dma protected low-memory region. this register must be setup before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as 0 in the capability register). the alignment of the protected low memory region limit depends on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position with 0 in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected low-memory base & limit registers functions as follows: ? programming the protected low-memory base and limit registers with the same value in bits 31:(n+1) specifies a protec ted low-memory region of size 2(n+1) bytes. ? programming the protected low-memory limit register with a value less than the protected low-memory base register disables the protected low-memory region. bit access default value rst/pwr description 31:21 r/w 000h core protected low-memory limit (plml): this register specifies the last host physical address of the dma protected low-memory regi on in system memory. 20:0 ro 000000h core reserved datasheet 481 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.17 phmbase_reg?protected high-memory base register b/d/f/type: 0/0/0/dmivc1remap address offset: 70-77h default value: 0000000000000000h access: r/w, ro size: 64 bits this register is used to setup the base address of dma protected high-memory region. this register must be setup before en abling protected memory through pmen_reg, and must not be updated when protecte d memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as 0 in the capability register). the alignment of the protected high memory region base depends on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 0s. bit access default value rst/pwr description 63:21 r/w 000000000 00h core protected high-memory base (phmb): this field specifies the base of size alig ned, protected memory region in system memory. hardware may not utilize bits 63:haw, where haw is the host address width. the protected high-m emory region has a minimum size of 2 mb and must be size aligned. 20:0 ro 000000h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 482 datasheet 12.2.18 phmlimit_reg?protected high-memory limit register b/d/f/type: 0/0/0/dmivc1remap address offset: 78-7fh default value: 0000000000000000h access: ro, r/w size: 64 bits this register is used to setup the limit address of dma protected high-memory region. this register must be setup before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as 0 in the capability register). the alignment of the protected high memory region limit depe nds on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected high-memory base and limit registers functions as follows: ? programming the protected low-memory base and limit registers with the same value in bits haw:(n+1) specifies a protec ted low-memory region of size 2(n+1) bytes. ? programming the protected high-memory limit register with a value less than the protected high-memory base register disa bles the protected high-memory region. bit access default value rst/pwr description 63:21 r/w 000000000 00h core protected high-memory limit (phml): this field specifies the last host physical address of the dma protected high-memory regi on in system memory. hardware may not use bits 63:haw, where haw is the host address width. 20:0 ro 000000h core reserved datasheet 483 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.19 iva_reg?invalidate address register b/d/f/type: 0/0/0/dmivc1remap address offset: 100-107h default value: 0000000000000000h access: w, ro size: 64 bits this register provides the dma address whose corresponding iotlb entry needs to be invalidated through the corresponding iotlb invalidate register. this register is a write-only register. value returned on reads of this register is undefined. there is an iva_reg for each iotlb invalidation unit supported by hardware. bit access default value rst/pwr description 63:12 w 0s core address (addr): software provides the dma address that needs to be page-s electively invalidated. to request a page-selective invali dation request to hardware, software must first write the appropriate fields in this register, and then issue appropriate page-s elective invalidate command through the iotlb_reg. hardware ignores bits 63: n, where n is the maximum guest address width (mgaw) supported. value returned on read of this field is undefined. 11:7 ro 0s core reserved 6w 0 core invalidation hint (ih): the field provides hint to hardware to preserve or flush the non-leaf (page- directory) entries that ma y be cached in hardware. 0 = software may have modified both leaf and non-leaf page-table entries corresponding to mappings specified in the addr and am fields. on a pageselective invalidation request, hardware must flush both the cached leaf and non-leaf page-table entries corresponding to mappings specified by addr and am fields. 1 = software has not modified any non-leaf page-table entries corresponding to mappings specified in the addr and am fields. on a page-selective invalidation request, hardware may pres erve the cached non-leaf page-table entries corresponding to mappings specified by addr and am fields. value returned on read of this field is undefined. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 484 datasheet 5:0 w 0s core address mask (am): the value in this field specifies the number of low order bits of th e addr field that must be masked for the invalidation op eration. mask field enables software to request invalidati on of contiguous mappings for size-aligned regions. for example: mask value addr bits masked pages invalidated. mask value addr bits masked pg inval 0n i l 1 11 2 2 2 13:12 4 3 14:12 8 4 15:12 16 5 16:12 32 6 17:12 64 7 18:12 128 8 19:12 256 hardware implementations re port the maximum supported mask value through the capability register. value returned on read of this field is undefined. bit access default value rst/pwr description datasheet 485 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.2.20 iotlb_reg?iotlb invalidate register b/d/f/type: 0/0/0/dmivc1remap address offset: 108-10fh default value: 0000000000000000h access: r/w, ro size: 64 bits this register is used to control page-table entry caching. the act of writing the upper byte of the iotlb_reg with ivt field set causes the hardware to perform the iotlb invalidation. there is an iotlb_reg for each iotlb invalidation unit supported by hardware. bit access default value rst/pwr description 63 r/w 0 core invalidate iotlb (ivt): software requests iotlb invalidation by setting this fiel d. software must also set the requested invalidation granularity by programming the iirg field. hardware clears the ivt field to indicate the invalidation request is complete. hard ware also indicates the granularity at which the invalidation operation was performed through the iaig field. software must not submit another invalidation re quest through th is register while the ivt field is set, nor update the associated invalidate address register. software must not submit io tlb invalidation requests through any of the iotlb invalidation units when there is a context-cache invalidation re quest pending at this dma- remapping hardware unit. when more than one iotlb invalidation units are supported by a dma-remapping hardware unit, software may submit iotlb invalidation request through any of the currently free units while ther e are pending requests on other units. hardware implementations repo rting write-buffer flushing requirement (rwbf=1 in ca pability register) must implicitly perform a write buffe r flushing before reporting invalidation complete to soft ware through the ivt field. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 486 datasheet 62:60 r/w 0s core iotlb invalidation request granularity (iirg): when requesting hardware to invalidate the iotlb (by setting the ivt field), soft ware writes the requested invalidation granularity through this iirg field. 000 = reserved. 001 = global invalidation request. 010 = domain-selective invalida tion request. the target domain-id must be specified in the did field. 011 = domain-page-selective invalidation request. the target address, mask and invalidation hint must be specified in the invalidate address register, and the domain-id must be prov ided in the did field. 100?111 =reserved. hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested. hardware in dicates completion of the invalidation request by clearing the ivt field. at this time, the granularity at which actual invalidation was performed is reported through the iaig field. 59:57 ro 0s core iotlb actual invalidation granularity (iaig): hardware reports the granularity at which an invalidation request was processed through this field at the time of reporting invalidation comple tion (by clearing the ivt field). 000 = reserved. this indica tes hardware detected an incorrect invalidation request and ignored the request. examples of incorrect invalidation requests include detecting an unsupported address mask value in invalidate address register for page- selective invalidation requests. 001 = global invalidation performed. this could be in response to a global, domain-selective, domain- page-selective, or de vice-page-selective invalidation request. 010 = domain-selective invali dation performed using the domain-id specified by software in the did field. this could be in response to a domain-selective, domain-page-selective, or device-page-selective invalidation request. 011 = domain-page-s elective invalidation performed using the address, mask and hint specified by software in the invalidate address register and domain-id specified in did field. this can be in response to a domain-page-selective or device- page-selective inva lidation request. 100 ? 111 =reserved. 56:50 ro 00h core reserved bit access default value rst/pwr description datasheet 487 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 49 r/w 000000h core drain reads (dr): this field is ignored by hardware if the drd field is reported as clear in the capability register. when drd field is reported as set in the capability register, the following encodings are supported for this field: 0 = hardware may complete the iotlb invalidation without draining any translated dma reads that are queued in the root-complex and yet to be processed. 1 = hardware must drain all/ relevant translated dma reads that are queued in the root-complex before indicating iotlb invalidation completion to software. a dma read request to syst em memory is defined as drained when root-complex has finished fetching all of its read response data from memory. 48 r/w 00h core drain writes (dw): this field is ignored by hardware if the dwd field is reported as cl ear in the capability register. when dwd field is reported as set in th e capability register, the following encodings are supported for this field: 0 = hardware may complete the iotlb invalidation without draining any translated dma writes that are queued in the root-com plex for processing. 1 = hardware must drain all/ relevant translated dma writes that are queued in the root-complex before indicating iotlb invalidation completion to software. a dma write request to syst em memory is defined as drained when the effects of the write is visible to processor accesses to all addresses targeted by the dma write. 47:32 r/w 0000h core domain-id (did): this field indicates the id of the domain whose iotlb entries needs to be selectively invalidated. this field must be programmed by software for domain-selective, domainpage -selective and device-page- selective invalidation requests. the capability register re ports the domain-id width supported by hardware. softwa re must ensu re that the value written to this field is within this limit. hardware may ignore and no t implement bits 47:(32+n) where n is the supported domain-id width reported in the capability register. 31:0 ro 00000000h core reserved bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 488 datasheet 12.2.21 frcd_reg?fault recording registers b/d/f/type: 0/0/0/dmivc1remap address offset: 200-20fh default value: 00000000000000000000000000000000h access: ro, ro/p, r/wc/p size: 128 bits this registers is used to record dma-remapping fault information when primary fault logging is active. hardware reports the number and location of fault recording registers through the capability register. this register is relevant only for primary fault logging. these registers are sticky and can be cleared only through powergood reset or via software clearing the rw1c fields by writing a 1. bit access default value rst/pwr description 127 r/wc/p 0s core fault (f): hardware sets this field to indicate a fault is logged in this fault recording re gister. the f field is set by hardware after the details of the fault is recorded in the paddr, sid, fr and t fields. when this field is set, hard ware may collapse additional faults from the same requestor (sid). software writes the value read from this field to clear it. 126 ro/p 0s core type (t): type of the faulted dma request. 0 = dma write 1 = dma read request this field is relevant only when the f field is set. 125:124 ro 0s core address type (at): this field captures the at field from the faulted dma request. ha rdware implementations not supporting device- iotlbs (d i field clear in extended capability register) treat this field as reserved. when supported, this field is va lid only when the f field is set, and when the fault reason (fr) indicates one of the dma-remapping fault conditions. note: this field is reserved as this feature is not supported. 123:104 ro 0s core reserved 103:96 ro/p 0s core fault reason (fr): reason for the fault. appendix b enumerates the various transl ation fault reason encodings. this field is relevant only when the f field is set. 95:80 ro 0s core reserved 79:64 ro/p 0s core source identifier (sid): requester-id of the faulted dma request. this field is rele vant only when the f field is set. 63:12 ro/p 0s core fault info (fi): this field contains the address (page- granular) in the faulted dma request. hardware may treat bits 63: n as reserved (0), where n is the maximum guest address width (mgaw) supported. this field is relevant only when the f field is set. 11:0 ro 0s core reserved datasheet 489 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.3 gfxvtbar table 28. gfxvtbar register address map address offset register symbol register name default value access 0?3h ver_reg version register 00000010h ro 8?fh cap_reg capability register 00c00000 20230272h ro 10?17h ecap_reg extended capability register 000000000 0001000h ro 18?1bh gcmd_reg global command register 00000000h wo, ro 1c?1fh gsts_reg global status register 00000000h ro 20?27h rtaddr_reg root-entry table address register 000000000 0000000h ro, r/w 28?2fh ccmd_reg context command register 080000000 0000000h r/w, ro, wo 34?37h fsts_reg fault status register 00000000h r/wc/p, ro/p, ro 38?3bh fectl_reg fault event control register 80000000h ro, r/w 3c?3fh fedata_reg fault event data register 00000000h ro, r/w 40?43h feaddr_reg fault event address register 00000000h r/w, ro 44?47h feuaddr_reg fault event upper address register 00000000h ro 58?5fh aflog_reg advanced fault log register 000000000 0000000h ro 64?67h pmen_reg protected memory enable register 00000000h r/w, ro 68?6bh plmbase_reg protected low memory base register 00000000h ro, r/w 6c?6fh plmlimit_reg protected low memory limit register 00000000h r/w, ro 70?77h phmbase_reg protected high memory base register 000000000 0000000h ro, r/w 78?7fh phmlimit_reg protected high memory limit register 000000000 0000000h ro, r/w 100?107h iva_reg invalidate address register 000000000 0000000h wo, ro 108?10fh iotlb_reg iotlb invalidate register 020000000 0000000h r/w, ro 200?20fh frcd_reg fault recording registers 000000000 000001000 000000000 00000h ro/p, r/wc/p, ro intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 490 datasheet 12.3.1 ver_reg?version register b/d/f/type: 0/2/0/gfxvtbar address offset: 0-3h default value: 00000010h access: ro size: 32 bits this register reports the architecture vers ion supported. backward compatibility for the architecture is maintained with new revisi on numbers, allowing software to load dma- remapping drivers written for prior architecture versions. 12.3.2 cap_reg?capability register b/d/f/type: 0/2/0/gfxvtbar address offset: 8-fh default value: 00c0000020630272h access: ro size: 64 bits this register reports general tr anslation hardware capabilities. bit access default value rst/pwr description 31:8 ro 000000h core reserved 7:4 ro 1h core major version number (max): this field indicates supported architecture version. 3:0 ro 0h core minor version number (min): this field indicates supported architecture minor version. bit access default value rst/pwr description 63:56 ro 00h core reserved 55 ro 1h core dma read draining (drd): 0 = as part of iotlb invalidations, hardware does not support draining of transl ated dma read requests queued within the root complex 1 = as part of iotlb invalidations, hardware supports draining of translated dm a read requests queued within the root complex 54 ro 1h core dma write draining (dwd): 0 = on iotlb invalidations, hardware does not support draining of translated dma writes queued within the root complex. 0 = on iotlb invalidations, hardware supports draining of translated dma writes queued within the root complex. 53:48 ro 00h core maximum address ma sk value (mamv): the value in this field indicates the maximum supported value for the address mask (am) field in the invalidation address (iva_reg) register. note: this field is reserved as this feature is not supported. datasheet 491 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 47:40 ro 00h core number of faultrecording registers (nfr): this field indicates a value of n-1, where n is the number of fault recording registers supported by hardware. implementations must support at least one fault recording register ( nfr = 0) for each dmaremapping hardware unit in the platform. the maximum number of fault recording registers per dma-remapping hardware unit is 256. 39 ro 0b core page-selective invalidation support (psi): 0 = hardware does not suppo rt page-selective iotlb invalidations. 1 = hardware supports page-selective iotlb invalidations. the mamv field indicates the maximum number of contiguous translations that may be invalidated in a single request. note: this field is reserved as this feature is not supported. 38 ro 0b core reserved 37:34 ro 0h core super-page support (sps): this field indicates the super page sizes supported by hardware. a value of 1 in any of these bits indicates the corresponding super-page size is supported. the super- page sizes corresponding to vari ous bit positions within this field are: 0 = 21-bit offset to page frame 1 = 30-bit offset to page frame 2 = 39-bit offset to page frame 3 = 48-bit offset to page frame 33:24 ro 020h core fault-recording register offset (fro): this field specifies the location to the first fault recording register relative to the register base address of this dma- remapping hardware unit. if the register base address is x, and the value reported in this field is y, the address for the first fault recording register is calculated as x+(16*y). 23 ro 0h core isochrony (isoch): 0 = remapping hardware unit has no critical isochronous requesters in its scope. 1 = remapping hardware unit has one or more critical isochronous reques ters in its scope. to ensure isochronous performance, software must ensure invalidation operations do not impact active dma streams from such requeste rs. this implies, when isochronous dma is active , software performs page selective invalidations (and not coarser invalidations) note: this field is reserved as this feature is not supported. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 492 datasheet 22 ro 1b core zero length read (zlr): 0 = remapping hardware unit blocks (and treats as fault) zero length dma read requ ests to write-only pages. 1 = remapping hardware unit supports zero length dma read requests to write-only pages. 21:16 ro 23h core maximum guest address width (mgaw): this field indicates the maximum dma virtual addressability supported by remapping hardware. the maximum guest address wi dth (mgaw) is computed as (n+1), where n is the value reported in this field. for example, a hardware implem entation supporting 48-bit mgaw reports a value of 47 (101111b) in this field. if the value in this field is x, dma requests to addresses above 2(x+1)-1 are always blocked by hardware. guest addressability for a given dma request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page-table structur e. (adjusted gues t address widths supported by hardware are reported through the sagaw field). 15:13 ro 0h core reserved 12:8 ro 02h core supported adjusted guest address width (sagaw): this 5-bit field indicates th e supported adjusted guest address widths (which in turn represents the levels of page-table walks) suppo rted by the hardware implementation. a value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported. the adjusted guest address widths corresponding to various bit positions within this field are: 0 = 30-bit agaw (2-level page table) 1 = 39-bit agaw (3-level page table) 2 = 48-bit agaw (4-level page table) 3 = 57-bit agaw (5-level page table) 4 = 64-bit agaw (6-level page table) software must ensure that the adjusted guest address width used to setup the page ta bles is one of the supported guest address widths re ported in this field. bit access default value rst/pwr description datasheet 493 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 7r o 0 h c o r e caching mode (cm): 0 = hardware does not cache not present and erroneous entries in the context-cache and iotlb. invalidations are not required for modifi cations to individual not present or invalid entries. however, any modifications that result in decreasing the effective permissions or partial permission increase s require invalidations for them to be effective. 1 = hardware may cache not present and erroneous mappings in the context-cache or iotlb. any software updates to the dma-remapping structures (including updates to not-present or erroneous entries) require explicit invalidation. hardware implementations ar e recommended to support operation corresponding to cm=0. 6r o 1 h c o r e protected high-memory region (phmr): 0 = protected high-memor y region not supported. 1 = protected high-memor y region is supported. dma-remapping hardware impl ementations on intel txt platforms supporting main memory above 4 gb are required to support prot ected high-memory region. 5r o 1 h c o r e protected low-memory region (plmr): 0 = protected low-memory region not supported. 1 = protected low-memory region is supported. dma-remapping hardware impl ementations on intel txt platforms are required to su pport protected low-memory region. 4r o 1 h c o r e required write-buffer flushing (rwbf): 0 = no write-buffer flushing ne eded to ensure changes to memory-resident structures are visible to hardware. 1 = software must explicitly flush the write buffers (through the global command register) to ensure updates made to memory-resident dma-remapping structures are visible to hardware. 3r o 0 h c o r e advanced fault logging (afl): 0 = advanced fault logging through memory-resident fault log not supported. only primary fault logging is supported. 1 = advanced fault logging is supported. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 494 datasheet 2:0 ro 2h core number of domains supported (nd): 000 = hardware supports 4-bit domain-ids with support for up to 16 domains. 001 = hardware supports 6-bit domain-ids with support for up to 64 domains. 010 = hardware supports 8-bit domain-ids with support for up to 256 domains. 011 = hardware supports 10-bit domain-ids with support for up to 1024 domains. 100 = hardware supports 12-bit domain-ids with support for up to 4k domains. 100 = hardware supports 14-bit domain-ids with support for up to 16k domains. 110 = hardware supports 16-bit domain-ids with support for up to 64k domains. 111 = reserved. bit access default value rst/pwr description datasheet 495 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.3.3 ecap_reg?extended capability register b/d/f/type: 0/2/0/gfxvtbar address offset: 10-17h default value: 0000000000001000h access: ro size: 64 bits the register reports dma-remappin g hardware extended capabilities. bit access default value rst/pwr description 63:24 ro 00000000h core reserved 23:20 ro 0h core maximum handle mask value (mhmv): the value in this field indicates the maxi mum supported value for the handle mask (hm) field in the interrupt entry cache invalidation descriptor ( iec_inv_dsc ). this field is valid only when th e ir field is reported as set. note: this field is reserved as this feature is not supported. 19:18 ro 00b core reserved 17:8 ro 010h core invalidation unit offset (ivo): this field specifies the location to the first iotlb invalidation unit relative to the register base address of this dma-remapping hardware unit. if the register base addr ess is x, and the value reported in this field is y, the address for the first iotlb invalidation unit is calculated as x+(16*y). if n is the value reported in niu field, the address for the last iotlb invalidation unit is calculated as x+(16*y)+(16*n). 7ro 0b core snoop control (sc): 0 = hardware does not support 1-setting of the snp field in the page-table entries. 1 = hardware supports the 1-setting of the snp field in the page-table entries. note: this field is reserved as this feature is not supported. 6r o 0 b c o r e pass through (pt): 0 = hardware does not support pass through translation type in context entries. 1 = hardware supports pass-thr ough translation type in context entries. note: this field is reserved as this feature is not supported. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 496 datasheet 5r o 0 b c o r e caching hints (ch): 0 = hardware does not support iotlb caching hints (alh and eh fields in context-entries are treated as reserved). 1 = hardware supports ioltb caching hints through the alh and eh fields in context-entries. note: this field is reserved as this feature is not supported. 4r o 0 b c o r e extended interrupt mode (eim): 0 = hardware supports only 8-bit apicids (legacy interrupt mode) on intel?64 and ia-32 platforms and 16-bit apic-ids on itanium tm platforms. 1 = hardware supports extended interrupt mode (32-bit apic-ids) on intel?64 platfo rms. this field is valid only when the ir field is reported as set. note: this field is reserved as this feature is not supported. 3r o 0 b c o r e interrupt remapping support (ir): 0 = hardware does not support interrupt remapping. 1 = hardware supports interrupt remapping. implementations reporting this field as set must also support queued invalidation (qi = 1b). note: this field is reserved as this feature is not supported. 2r o 0 b c o r e device iotlb support (di): 0 = hardware does not support device-iotlbs. 1 = hardware supports device-iotlbs. implementations reporting this field as set must also support queued invalidation (qi = 1b). note: this field is reserved as this feature is not supported. 1r o 0 b c o r e queued invalidation support (qi): 0 = hardware does not support queued invalidations. 1 = hardware supports queued invalidations. note: this field is reserved as this feature is not supported. 0r o 0 b c o r e coherency (c): 0 = indicates hardware accesses to root, context and page-table structures are not coherent (non-snooped). 1 = indicates hardware accesses to root, context and page-table stru ctures are coherent (snooped). hardware writes to the advanced fault log is required to be coherent. bit access default value rst/pwr description datasheet 497 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.3.4 gcmd_reg?global command register b/d/f/type: 0/2/0/gfxvtbar address offset: 18-1bh default value: 00000000h access: wo, ro size: 32 bits this register is used to control dma-remapp ing hardware. if multiple control fields in this register need to be modified, software must serialize through multiple accesses to this register. bit access default value rst/pwr description 31 wo 0 core translation enable (te): software writes to this field to request hardware to enable/disable dma-remapping hardware. 0 = disable dma-remapping hardware 1 = enable dma-remapping hardware hardware reports the status of the translation enable operation through the tes field in the global status register. before enabling (or re-e nabling) dma-remapping hardware through this field, software must: ? setup the dma-remapping structures in memory ? flush the write buffers (thr ough wbf field), if write buffer flushing is reported as required. ? set the root-entry table po inter in hardware (through srtp field). ? perform global invalidation of the context-cache and global invalidation of iotlb ? if advanced fault logging supported, setup fault log pointer (through sfl field) and enable advanced fault logging (through eafl field). there may be active dma requ ests in the pl atform when software updates this field. hardware must enable or disable remapping logic only at deterministic transaction boundaries, so that any in-f light transaction is either subject to remapping or not at all. hardware implementations su pporting dma draining must drain any in-flight translated dma read/write requests queued within the root comp lex before completing the translation enable command an d reflecting the status of the command through the tes field in the gsts_reg. value returned on read of this field is undefined. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 498 datasheet 30 wo 0 core set root table pointer (srtp): software sets this field to set/update the root-ent ry table pointer used by hardware. the root-entry table pointer is specified through the root-entry table address register. hardware reports the status of the root table pointer set operation through the rtps field in the global status register. the root table pointer set op eration must be performed before enabling or re-enabl ing (after disabling) dma- remapping hardware. after a root table pointer se t operation, software must globally invalidate the context cache followed by global invalidate of iotlb. this is required to ensure hardware uses only the remapping struct ures referenced by the new root table pointer, and not any stale cached entries. while dma-remapping hardware is active, software may update the root table pointer through this field. however, to ensure valid in-flight dma requests are de terministically remapped, software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previo us root table pointer. clearing this bit has no effect. value returned on read of this field is undefined. 29 ro 0 core set fault log (sfl): this field is valid only in implementations supporting ad vanced fault logging. if advanced fault logging is not supported, writes to this field are ignored. software sets this field to request hardware to set/update the fault-log pointer used by hardware. the fault-log pointer is specified through advanced fault log register. hardware reports the status of the fault log set operation through the fls field in the glob al status register. the fault log pointer must be set befo re enabling advanced fault logging (through eafl field). once advanced fault logging is enabled, the fault log pointer may be updated through this field while dma-remapping hardware is active. clearing this bit has no effect. value returned on read of this field is undefined. bit access default value rst/pwr description datasheet 499 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 28 ro 0 core enable advanced fault logging (eafl): this field is valid only in implementation s supporting advanced fault logging. if advanced fault logging is not supported, writes to this field are ignored. software writes to this field to request hardware to enable or disable advanced fault logging. 0 = disable advanced fault logging. in this case, translation faults are re ported through the fault recording registers. 1 = enable use of memory-resident 4 kb fault log. when enabled, translation faults are recorded in the memory-resident log. the fault log pointer must be set in hardware (through sfl field) before enabling advanced fault logging. hardware reports the status of the advanced fault logging enable operation through the afls field in the global status register. value returned on read of this field is undefined. 27 wo 0 core write buffer flush (wbf): this bit is valid only in implementations requiring writ e buffer flushing. if write buffer flushing is not required , writes to this field are ignored. software sets this field to request hardware to flush the root-complex internal write buffe rs. this is do ne to ensure any updates to the memory-resident dma-remap structures are not held in any internal write posting buffers. hardware reports the status of the write bu ffer flushing operation through the wbfs fi eld in the global status register. clearing this bit has no effect . value returned on read of this field is undefined. 26 ro 0b core queued invalidation enable (qie): this field is valid only for implementations suppo rting queued invalidations. software writes to this field to enable or disable queued invalidations. 0 = disable queued invalidations. 1 = enable use of queued invalidations. hardware reports the status of queued invalidation enable operation through qies field in the global status register. the value returned on a read of this field is undefined. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 500 datasheet 25 ro 0b core interrupt remapping enable (ire): this field is valid only for implementations su pporting interrupt remapping. 0 = disable interrupt-remapping hardware 1 = enable interrupt-remapping hardware hardware reports the status of the interrupt remapping enable operation through the ires field in the global status register. there may be active interrupt requests in the platform when software updates this fiel d. hardware must enable or disable interrupt-remapping lo gic only at deterministic transaction boundaries, so that any in-flight interrupts are either subject to remapping or not at all. hardware implementations must drain any in-flight interrupts reques ts queued in the root-complex before completing the interrupt-remapping enable command and reflecting the status of th e command through the ires field in the global status register. the value returned on a read of this field is undefined. note: this field is reserved as this feature is not supported. 24 ro 0b core set interrupt remap table pointer (sirtp): this field is valid only for implemen tations supporting interrupt- remapping. software sets this field to set/update the interrupt remapping table pointer used by hardware. the interrupt remapping table pointer is sp ecified through the interrupt remapping table address register. hardware reports the status of the interrupt remapping table pointer set operation th rough the irtps field in the global status register. the interrupt remap table poin ter set operation must be performed before enabling or re-enabling (aft er disabling) interrupt-remapping hardware through the ire field. after an interrupt remap table pointer set operation, software must globally invalidate the interrupt entry cache. this is required to ensure hardware uses only the interrupt-remapping entrie s referenced by the new interrupt remap table pointer, and not any stale cached entries. while interrupt remapping is active, software may update the interrupt remapping table pointer through this field. however, to ensure valid in-f light interrupt requests are deterministically rema pped, software must ensure that the structures referenced by th e ew interrupt remap table pointer are programmed to provide the same remapping results as the structures re ferenced by the previous interrupt remap table pointer. clearing this bit has no effe ct. the value returned on a read of this field is undefined. note: this field is reserved as this feature is not supported. bit access default value rst/pwr description datasheet 501 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 23 ro 0b core compatibility format interrupt (cfi): this field is valid only for intel 64 implemen tations supporting interrupt- remapping. software writes to this fi eld to enable or disable compatibility format interrupts on intel ? 64 architecture platforms. the value in this field is effective only when interrupt-remapping is enable d and legacy interrupt mode is active. 0 = block compatibility format interrupts. 1 = process compatibility fo rmat interrupts as pass- through (bypass in terrupt remapping). hardware reports the status of updating this field through the cfis field in the global status register. the value returned on a read of this field is undefined. this field is not implemented on itanium tm implementations. note: this field is reserved as this feature is not supported. 22:0 ro 0s core reserved bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 502 datasheet 12.3.5 gsts_reg?global status register b/d/f/type: 0/2/0/gfxvtbar address offset: 1c-1fh default value: 00000000h access: ro size: 32 bits this register reports general dma-remapping hardware status. bit access default value rst/pwr description 31 ro 0 core translation enable status (tes): this field indicates the status of dma-remapping hardware. 0 = dma-remapping hardware is not enabled 1 = dma-remapping hardware is enabled 30 ro 0 core root table pointer status (rtps): this field indicates the status of the root- table pointer in hardware. this field is cleared by hard ware when software sets the srtp field in the global comman d register. this field is set by hardware when hardware finishes the set root-table pointer operation (by perform ing an implicit global invalidation of the context-cache and iotlb, and setting/ updating the root-table pointe r in hardware with the value provided in the root-entry table address register). 29 ro 0 core fault log status (fls): this field is valid only in implementations supporting advanced fault logging. this field indicates the status of the fault-log pointer in hardware. this field is cleare d by hardware when software sets the sfl field in the gl obal command register. this field is set by hardware when hardware finishes the set fault-log pointer operation (by setting/updating the faultlog pointer in hardware with the value provided in the advanced fault log register). 28 ro 0 core advanced fault logging status (afls): this field is valid only for implementations supporting advanced fault logging. this field indicates advanc ed fault logging status. 0 = advanced fault logging is not enabled 1 = advanced fault logging is enabled 27 ro 0 core write buffer flush status (wbfs): this bit is valid only in implementations requir ing write buffer flushing. this field indicates the stat us of the write buffer flush operation. this field is set by hardware when software sets the wbf field in the global co mmand register. this field is cleared by hardware when hardware finishes the write buffer flush operation. 26 ro 0 core queued invalidation enable status (qies): this field indicates queued invalidation enable status. 0 = queued invalidation is not enabled 1 = queued invalidation is enabled datasheet 503 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.3.6 rtaddr_reg?root-entry table address register b/d/f/type: 0/2/0/gfxvtbar address offset: 20-27h default value: 0000000000000000h access: ro, r/w size: 64 bits this register is used to set up location of root-entry table. 25 ro 0b core interrupt remapping enable status (ires): this field indicates the status of in terrupt-remapping hardware. 0 = interrupt-remapping hardware is not enabled 1 = interrupt-remapping hardware is enabled 24 ro 0b core interrupt root table po inter status (irtps): this field indicates the st atus of the interrupt remapping table pointer in hardware. this field is cleared by hard ware when software sets the sirtp field in the glob al command register. this field is set by hardware when hardware completes the set interrupt remap table poin ter operation using the value provided in the interrupt remapping table address register. 23 ro 0b core compatibility format in terrupt status (cfis): this field indicates the st atus of compatibility format interrupts on intel ? 64 architecture impl ementations supporting interrupt-remapping. the value reported in this field is applicable only when interru pt-remapping is enabled and legacy interrupt mode is active. 0 = compatibility format interrupts are blocked. 1 = compatibility format inte rrupts are processed as pass- through (bypassing interrupt remapping). 22:0 ro 0s core reserved bit access default value rst/pwr description bit access default value rst/pwr description 63:36 ro 0s core rta63:haw (rta_r): made read only as hardware ignores bits 63:haw. 35:12 r/w 0s core root table address (rta): this register points to base of page aligned, 4 kb-sized r oot-entry table in system memory. hardware ignores bits 63:haw, where haw is the host address width. software specifies the base a ddress of the root-entry table through this register, and prog rams it in hardware through the srtp field in the global command register. reads of this register re turns value that was last programmed to it. 11:0 ro 0s core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 504 datasheet 12.3.7 ccmd_reg?contex t command register b/d/f/type: 0/2/0/gfxvtbar address offset: 28-2fh default value: 0800000000000000h access: r/w, ro, wo size: 64 bits this register is used to manage context-en try cache. the act of writing the uppermost byte of the ccmd_reg with icc field set ca uses the hardware to perform the context- cache invalidation. bit access default value rst/pwr description 63 r/w 0 core invalidate context-entry cache (icc): software requests invalidation of contex t-cache by setting this field. software must also set th e requested in validation granularity by programming the cirg field. software must read back and check the icc field to be clear to confirm the invalidation is complete. software must not update this regist er when this field is set. hardware clears the icc field to indicate the invalidation request is complete. hardware also indicates the granularity at which the invalidation operation was performed through the c aig field. soft ware must not submit another invalidation re quest through this register while the icc field is set. software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this dma-remapping hardware unit. since information from the context-cache may be used by hardware to tag iotlb entries, software must perform domain-selective (or global) in validation of iotlb after the context cache invalidation has completed. hardware implementations repo rting write-buffer flushing requirement (rwbf=1 in ca pability register) must implicitly perform a write buffer flushing before reporting invalidation complete to soft ware through the icc field. 62:61 r/w 00b core context-cache invalidation request granularity (cirg): software provides the requested invalidation granularity through this fiel d when setting the icc field. 00 = reserved. 01 = global invalidation request. 10 = domain-selective invalida tion request. the target domain-id must be specified in the did field. 11 = device-selective invalidation request. the target source-id(s) must be specified through the sid and fm fields, and the domain -id (that was programmed in the context-entry for these device(s)) must be provided in the did field. hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested. hardware in dicates completion of the invalidation request by clearing the icc field. at this time, hardware also indicates the gr anularity at which the actual invalidation was performed through the caig field. datasheet 505 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 60:59 ro 11b core context-cache actual invalidation granularity (caig): hardware reports the granularity at which an invalidation request was proc essed through the caig field at the time of reporting invalidation completion (by clearing the icc field). 00 = reserved. this is the value on reset. 01 =global invalidation pe rformed. this could be in response to a global, doma in-selective or device- selective invalidation request. 10 =domain-selective invali dation performed using the domain-id specified by softwa re in the did field. this could be in response to a domain-selective or device- selective invalidation request. 11 =device-selective invalidation performed using the source-id and domain-id specified by software in the sid and did fields. this can only be in response to a device-selective in validation request. 58:34 ro 0s core reserved 33:32 wo 00b core function mask (fm): this field specifies which bits of the function number portion (least significant three bits) of the sid field to mask when pe rforming device -selective invalidations. 00 = no bits in the sid field masked. 01 = mask most significant bi t of function number in the sid field. 10 = mask two most significant bit of function number in the sid field. 11 = mask all three bits of function number in the sid field. the sids specified through the fm and sid mask fields must correspond to the domain-id specified in the did field. value returned on read of this field is undefined. 31:16 wo 0s core source-id (sid): this field indicates the source-id of the device whose corresponding context-entry needs to be selectively invalidated. this fi eld, along with the fm field, must be programmed by soft ware for device-selective invalidation requests. value returned on read of this field is undefined. 15:0 r/w 0s core domain-id (did): this field indicates the id of the domain whose context-entries needs to be selectively invalidated. this field must be programmed by software for both domain-selective and de vice-selective invalidation requests. the capability register re ports the domain-id width supported by hardware. softwa re must ensu re that the value written to this field is within this limit. hardware may ignore and no t implement bi ts15:n where n is the supported domain-id widt h reported in the capability register. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 506 datasheet 12.3.8 fsts_reg?fault status register b/d/f/type: 0/2/0/gfxvtbar address offset: 34-37h default value: 00000000h access: ro, r/wc/p, ro/p size: 32 bits this register indicates the primary fault logging status. bit access default value rst/pwr description 31:16 ro 0s core reserved 15:8 ro/p 0s core fault record index (fri): this field is valid only when the ppf field is set. the fri field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the ppf field was set by hardware. valid values for this field are from 0 to n, where n is the value reported through nfr field in the capability register. the value read from this fiel d is undefined when the ppf field is clear. 7 ro 0b core reserved 6ro 0b core invalidation time-out error (ite): hardware detected a device-iotlb invalidation completion time-out. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations no t supporting device-iotlbs implement this bit as reserved. note: this field is reserved as this feature is not supported. 5r o 0 b c o r e invalidation completion error (ice): hardware received an unexp ected or invalid device-iotlb invalidation completion. this could be due to either an invalid itag or invalid source-id in an invalidation completion response. at this time, a fault event may be generated based on the prog ramming of the fault event control register. hardware implementations no t supporting device-iotlbs implement this bit as reserved. note: this field is reserved as this feature is not supported. datasheet 507 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 4r o 0 b c o r e invalidation queue error (iqe): hardware detected an error associated with the invali dation queue. this could be due to either a hardware erro r while fetching a descriptor from the invalidation queue, or hardware detecting an erroneous or invalid descriptor in the invalidation queue. at this time, a fault event may be generated based on the programming of the fault event control register. hardware implementations not supporting queued invalidations implement this bit as reserved. note: this field is reserved as this feature is not supported. 3r o 0 b c o r e advanced pending fault (apf): when this field is clear, hardware sets this field when the first fault record (at index 0) is written to a fault log. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supportin g advanced fault logging implement this bit as reserved. note: this field is reserved as this feature is not supported. 2r o 0 b c o r e advanced fault ov erflow (afo): hardware sets this field to indicate advanced fault log overflow condition. at this time, a fault event is generated based on the programming of the fault event control register. software writing 1 to this field clears it. hardware implementations not supportin g advanced fault logging implement this bit as reserved. note: this field is reserved as this feature is not supported. 1ro/p 0b core primary pending fault (ppf): this field indicates if there are one or more pending faults logged in the fault recording registers. hardware computes this field as the logical or of fault (f) fields across all the fault recording registers of this dma-remap hardware unit. 0 = no pending faults in any of the fault recording registers 1 = one or more fault reco rding registers has pending faults. the fri field is updated by hardware whenever the ppf field is set by ha rdware. also, depending on the programming of fault event control register, a fault event is generated when hardware sets this bit. 0r/wc/p 0b core primary fault overflow (pfo): hardware sets this bit to indicate overflow of fault recording registers. software writing 1 clears this field. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 508 datasheet 12.3.9 fectl_reg?fault event control register b/d/f/type: 0/2/0/gfxvtbar address offset: 38-3bh default value: 80000000h access: ro, r/w size: 32 bits this register specifies the fault event interrupt message control bits. bit access default value rst/pwr description 31 r/w 1 core interrupt-message mask (im): 0 = no masking of interrupt. wh en a interrupt condition is detected, hardware issues an interrupt message (using the fault event data & fault event address register values). 1 = this is the value on reset. software may mask interrupt message ge neration by sett ing this field. hardware is prohibited from sending the interrupt message when this field is set. 30 ro 0 core interrupt-message pending (ip): hardware sets the ip bit whenever it detects an in terrupt condition. interrupt condition is defined as: ? when primary fault logging is active, an interrupt condition occurs when hardware records a fault through one of the fault recording registers and sets the ppf field in fault status register. if the ppf field was already set at the ti me of recording a fault, it is not treated as a new interrupt condition. ? when advanced fault logging is active, an interrupt condition occurs when hardware records a fault in the first fault record (at index 0) of the current fault log and sets the apf field in the advanced fault log register. if the apf field was already set at the time of detecting/recording a fault, it is not treated as a new interrupt condition. the ip field is kept set by hardware while the interrupt message is held pending. th e interrupt message could be held pending due to interrupt ma sk (im field) being set, or due to other transient hardware conditions. the ip field is cleared by hard ware as soon as the interrupt message pending condition is serviced. this could be due to either: ? hardware issuing the interru pt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the im field. ? software servicing the interrupting condition through one of the following ways: ? when primary fault logging is active, software clearing the fault (f) field in all the fault recording registers with faults, causing the ppf field in fault status register to be evaluated as clear. ? when advanced fault logging is active, software clearing the apf field in advanced fault log register. 29:0 ro 0s core reserved datasheet 509 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.3.10 fedata_reg?fault event data register b/d/f/type: 0/2/0/gfxvtbar address offset: 3c-3fh default value: 00000000h access: ro, r/w size: 32 bits this register specifies the interrupt message data. 12.3.11 feaddr_reg?fault event address register b/d/f/type: 0/2/0/gfxvtbar address offset: 40-43h default value: 00000000h access: r/w, ro size: 32 bits this register specifies the interrupt message address. bit access default value rst/pwr description 31:16 ro 0000h core extended interrupt message data (eid): this field is valid only for implementation s supporting 32-bit msi data fields. hardware implementa tions supporting only 16-bit msi data treats this field as read only (0). 15:0 r/w 0000h core interrupt message data (id): data value in the fault- event interrupt message. bit access default value rst/pwr description 31:2 r/w 00000000h core message address (ma): when fault events are enabled, the contents of this register specify the dword aligned address (bits 31:2) for the ms i memory write transaction. 1:0 ro 0h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 510 datasheet 12.3.12 feuaddr_reg?fault ev ent upper address register b/d/f/type: 0/2/0/gfxvtbar address offset: 44-47h default value: 00000000h access: ro size: 32 bits this register specifies the interrupt message address. for platforms supporting only interrupt messages in the 32-bit address range, this register is treated as read-only (0). 12.3.13 aflog_reg?advanc ed fault log register b/d/f/type: 0/2/0/gfxvtbar address offset: 58-5fh default value: 0000000000000000h access: ro size: 64 bits this register specifies the base address of memory-resident fault-log region. this register is treated as read only (0) fo r implementations not supporting advanced translation fault logging (afl field reported as 0 in the capability register). this register is sticky and can be cleared only through po wergood reset or via software clearing the rw1c fields by writing a 1. bit access default value rst/pwr description 31:0 ro 00000000h core message upper address (mua): this register need to be implemented only if hardware supports 64-bit message address. if implemented, the contents of this register specify the upper 32-bits of a 64- bit msi write transaction. if hardware does not support 64-bit messages, the register is treated as read only (0). bit access default value rst/pwr description 63:12 ro 0s core fault log address (fla): this field specifies the base of size-aligned fault-log region in system memory. hardware may ignore bits 63: n, wh ere n is the host address width. software specifies the base a ddress and size of the fault log region through this register, and programs it in hardware through the sfl field in the global command register. when implemented, reads of th is field returns value that was last programmed to it. 11:9 ro 0s core fault log size (fls): this field specifies the size of the fault log region poin ted by the fla field. the size of the fault log region is 2x * 4kb, where x is the value programmed in this register. when implemented, reads of th is field returns value that was last programmed to it. 8:0 ro 0s core reserved datasheet 511 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.3.14 pmen_reg?protected memory enable register b/d/f/type: 0/2/0/gfxvtbar address offset: 64-67h default value: 00000000h access: r/w, ro size: 32 bits this register is used to enable the dma protected memory regions setup through the plmbase, plmlimt, phmbase, phmlimit registers. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated read-only). when the lt.cmd.unlock.pmrc command is invoked, th is register is unlocked (treated read/ write). this register is always treated as read only (0) for implementations not supporting protected memory regions (plmr and phmr fields reported as 0 in the capability register). bit access default value rst/pwr description 31 r/w 0 core enable protected memory region (epm): this field controls dma access es to the protected low-memory and protected high-m emory regions. 0 = dma accesses to prot ected memory regions are handled as follows: ? if dma-remapping hardware is not enabled, dma requests (inc luding those to prot ected regions) are not blocked. ? if dma-remapping hardware is enabled, dma requests are translated pe r the programming of the dma-remapping structures . software may program the dma-remapping structur es to allow or block dma to the protecte d memory regions. 1 = dma accesses to prot ected memory regions are handled as follows: ? if dma-remapping hardware is not enabled, dma to protected memory regions are blocked. these dma requests are not recorded or reported as dma- remapping faults. ? if dma-remapping hardware is enabled, hardware may or may not block dma to the protected memory region(s). softwa re must not depend on hardware protection of the protected memory regions, and must ensu re the dma-remapping structures are properly programmed to not allow dma to the protecte d memory regions. hardware reports the status of the protected memory enable/disable operation thro ugh the prs field in this register. hardware implementations su pporting dma draining must drain any in-flight translated dma requests queued within the root complex before indi cating the protected memory region as enabled th rough the prs field. 30:1 ro 0s core reserved 0ro 0s core protected region status (prs): this field indicates the status of protecte d memory region. 0 = protected memory region(s) not enabled. 1 = protected memory region(s) enabled. intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 512 datasheet 12.3.15 plmbase_reg?protected low memory base register b/d/f/type: 0/2/0/gfxvtbar address offset: 68-6bh default value: 00000000h access: ro, r/w size: 32 bits this register is used to setup the base address of dma protected low-memory region. this register must be setup before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as 0 in the capability register). the alignment of the protected low memory region base depend s on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position with 0 in the value read back from the register. bits n:0 of this register is decoded by hardware as all 0s. bit access default value rst/pwr description 31:21 r/w 000h core protected low-memory base (plmb): this register specifies the base of protec ted low-memory region in system memory. 20:0 ro 000000h core reserved datasheet 513 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.3.16 plmlimit_reg?protected low memory limit register b/d/f/type: 0/2/0/gfxvtbar address offset: 6c-6fh default value: 00000000h access: r/w, ro size: 32 bits this register is used to setup the limit address of dma protected low-memory region. this register must be setup before en abling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected low memory region (plmr field reported as 0 in the capability register). the alignment of the protected low memory region limit depend s on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position with 0 in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected low-memory base & limit registers functions as follows: ? programming the protected low-memory base and limit registers with the same value in bits 31:(n+1) specifies a protected low-memory region of size 2(n+1) bytes. ? programming the protected low-memory limit register with a value less than the protected low-memory base register disables the protected low-memory region. bit access default value rst/pwr description 31:21 r/w 000h core protected low-memo ry limit (plml): this field specifies the last host physical address of the dma protected low-memory regi on in system memory. 20:0 ro 000000h core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 514 datasheet 12.3.17 phmbase_reg?protected high memory base register b/d/f/type: 0/2/0/gfxvtbar address offset: 70-77h default value: 0000000000000000h access: ro, r/w size: 64 bits this register is used to setup the base address of dma protected high-memory region. this register must be setup before enabling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated as ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as 0 in the capability register). the alignment of the protected high memory region base depe nds on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 0s. bit access default value rst/pwr description 63:36 ro 0s core protected high-memory base (phmb_r) 35:21 r/w 0s core protected high-memory base (phmb): this field specifies the base of size alig ned, protected memory region in system memory. hardware may ignore and not implement bits 63:haw, wher e haw is the host address width. 20:0 ro 0s core reserved datasheet 515 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 12.3.18 phmlimit_reg?protected high memory limit register b/d/f/type: 0/2/0/gfxvtbar address offset: 78-7fh default value: 0000000000000000h access: ro, r/w size: 64 bits this register is used to setup the limit address of dma protected high-memory region. this register must be setup before en abling protected memory through pmen_reg, and must not be updated when protected memory regions are enabled. when lt.cmd.lock.pmrc command is invoked, this register is locked (treated as ro). when lt.cmd.unlock.pmrc command is invoked, this register is unlocked (treated as r/w). this register is always treated as ro for implementations not supporting protected high memory region (phmr field reported as 0 in the capability register). the alignment of the protected high memory region limit depe nds on the number of reserved bits (n) of this register. software may determine the value of n by writing all 1s to this register, and finding most significant zero bit position below host address width (haw) in the value read back from the register. bits n:0 of the limit register is decoded by hardware as all 1s. the protected high-memory base & limit registers functions as follows: ? programming the protected low-memory base and limit registers with the same value in bits haw:(n+1) specifies a protected low-memory region of size 2(n+1) bytes. ? programming the protected high-memory limit register with a value less than the protected high-memory base register disables the protected high-memory region. bit access default value rst/pwr description 63:36 ro 0s core protected high-memory limit (phml_r): 35:21 r/w 0s core protected high-memory limit (phml): this register specifies the last host physical address of the dma protected high-memory region in system memory. hardware may ignore and no t implement bits 63:haw, where haw is the host address width. 20:0 ro 0s core reserved intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 516 datasheet 12.3.19 iva_reg?invalidate address register b/d/f/type: 0/2/0/gfxvtbar address offset: 100-107h default value: 0000000000000000h access: wo, ro size: 64 bits this register is used to provide the dma address whose corresponding iotlb entry needs to be invalidated through the iotlb inva lidate register. this register is a write only register. the value returned on reads of this register is undefined. there is an iva_reg for each iotlb invalidation unit supported by hardware. bit access default value rst/pwr description 63:12 wo 0s core address (addr): software provides the dma address that needs to be pa ge-selectively invali dated. to request a page-selective invalidation request to hardware, software must first write the appropriate fields in this register, and then issue appropriate page-s elective invalidate command through the iotlb_reg. hard ware ignores bits 63:n, where n is the maximum guest address width (mgaw) supported. the value returned on read of this field is undefined. 11:7 ro 0s core reserved 6wo 0 core invalidation hint (ih): the field provides hints to hardware to preserve or flush the non-leaf (page- directory) entries that ma y be cached in hardware. 0 = software may have modified both leaf and non-leaf page-table entr ies corresponding to mappings specified in the addr and am fields. on a pageselective invalidation request, hardware must flush both the cached leaf and non-leaf page-table entries corresponding to ma ppings specified by addr and am fields. 1 = software has not modified any non-leaf page-table entries corresponding to mappings specified in the addr and am fields. on a pa ge-selective invalidation request, hardware may pres erve the cached non-leaf page-table entr ies corresponding to mappings specified by addr and am fields. value returned on read of this field is undefined. datasheet 517 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 5:0 wo 0s core address mask (am): the value in this field specifies the number of low-order bits of the addr field that must be masked for the invalidation op eration. mask field enables software to request invalidation of contiguous mappings for size-aligned regions. for exam ple: mask value addr bits masked pages invalidated 0 none 1 1 12 2 2 13 : 12 4 3 14 : 12 8 4 15 : 12 16 ...... ....... ....... hardware implementations re port the maximum supported mask value through the capability register. value returned on read of this field is undefined. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 518 datasheet 12.3.20 iotlb_reg?iotlb invalidate register b/d/f/type: 0/2/0/gfxvtbar address offset: 108-10fh default value: 0200000000000000h access: r/w, ro size: 64 bits this register is used to control page-table entry caching. the act of writing the upper byte of the iotlb_reg with ivt field set causes the hardware to perform the iotlb invalidation. there is an iotlb_reg for each iotlb invalidation unit supported by hardware. bit access default value rst/pwr description 63 r/w 0 core invalidate iotlb (ivt): software requests iotlb invalidation by setting this field. software must also set the requested invalidation gran ularity by programming the iirg field. hardware clears the ivt field to indicate the invalidation request is complete. hardware also indicates the granularity at which the invalidation operation was performed through the iaig field. software must not submit another invalidation re quest through this register while the ivt field is set, nor update the associated invalidate address register. software must not submit io tlb invalidation requests through any of the iotlb invalidation units when there is a context-cache invalidation re quest pending at this dma- remapping hardware unit. when more than one iotlb invalidation units are supported by a dma-remapping hardware unit, software may submit iotlb invalidation request through any of the currently free units while there are pending requests on other units. hardware implementations repo rting write-buffer flushing requirement (rwbf=1 in ca pability register) must implicitly perform a write buffer flushing before reporting invalidation complete to soft ware through the ivt field. datasheet 519 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 62:60 r/w 0s core iotlb invalidation request granularity (iirg): when requesting hardware to invalidate the iotlb (by setting the ivt field), soft ware writes the requested invalidation granularity through this iirg field. 000 = reserved. hardware ignores the invalidation request and reports inva lidation complete by clearing the ivt field and reporting 000 in the iaig field. 001 = global invalidation request. 010 = domain-selective invalidation request. the target domain-id must be specified in the did field. 011 = domain-page-selective invalidation request. the target address, mask and invalidation hint must be specified in the invalidate address register, and the domain-id must be provided in the did field. 100 = device-page-selective invalidation request. the target address, mask and invalidation hint must be specified in the invalida te address register, the domain-id must be provided in the did field, and the device requestor-id mu st be provided in sid field. 101 - 111 =reserved. hardware ignores the invalidation request and reports inva lidation complete by clearing the ivt field and reporting 000 in the iaig field. depending on the invalidation granularities supported by a hardware implementation, an invalidation request may be processed by performing invalidation at a coarser granularity. hardware indicates completion of the invalidation request by clearing the ivt field. at this time, the granularity at which actual invalidation was performed is reported through the iaig field. bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 520 datasheet 59:57 ro 1h core iotlb actual invalidation granularity (iaig): hardware reports the granularity at which an invalidation request was proceed through th is field at the time of reporting invalidation comple tion (by clearing the ivt field). 000 = reserved. this indica tes hardware detected an incorrect invalidation requ est and hence ignored the request. examples of incorre ct invalidation requests include specifying a reserved value in the iirg field or specifying an unsupported address mask value in iva_reg for page-selective invalidation requests. 001 = global invalidation performed. this could be in response to a global, do main-selective, domain- page-selective, or device-page-selectiveinvalidation request. 010 = domain-selective invali dation performed using the domain-id specified by soft ware in the did field. this could be in response to a domain-selective, domain-page-selective, or device-page-selective invalidation request. 011 = domain-page-selective in validation performed using the address, mask and hint specified by software in the invalidate address register and domain-id specified in did field. this can be in response to a domain-page-selective or device-page-selective invalidation request. 100 = device-page-selective invalidation performed using the address, mask and hint specified by software in the invalidate address register and device-id specified in sid field. this can only be in response to a device-page-selective invalidation request. 101 - 111 =reserved. 56:50 ro 0 core reserved 49 r/w 0 core drain reads (dr): this field is treated as reserved if the drd field is reported as clea r in the capability register. 0 = hardware may complete the iotlb invalidation without draining any translated dma reads that are queued in the root-complex and yet to be processed. 1 = hardware must drain all/relevant translated dma reads that are queued in the root -complex before indicating iotlb invalidation completion to software. a dma read request to system memory is defined as drained when root-complex has finished fetching all of its read response data from memory. bit access default value rst/pwr description datasheet 521 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 48 r/w 0 core drain writes (dw): this field is treated as reserved (0) if the dwd field is reported as cl ear in the capability register. 0 = hardware may complete the iotlb invalidation without draining any translated dma writes that are queued in the root-complex and yet to be processed. 1 = hardware must drain all/ relevant translated dma writes that are queued in the root-complex before indicating iotlb invalidation completion to software. a dma write request to system memory is defined as drained when the effects of the write is visible to processor accesses to all addresses targeted by the dma write. 47:32 r/w 0s core domain-id (did): this field indicates the id of the domain whose iotlb entries needs to be selectively invalidated. this field must be programmed by software for domain-selective, and page-selec tive invalidation requests. the capability register re ports the domain-id width supported by hardware. softwa re must ensu re that the value written to this field is within this limit. hardware may ignore and no t implement bits 47:(32+n) where n is the supported domain-id width reported in the capability register. 31:0 ro 0s core reserved bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 522 datasheet 12.3.21 frcd_reg?fault recording registers b/d/f/type: 0/2/0/gfxvtbar address offset: 200-20fh default value: 00000000000000100000000000000000h access: ro/p, ro, r/wc/p size: 128 bits this register is used to record dma-rema pping fault information when primary fault logging is active. hardware reports the number and location of fault recording registers through the capability register. this register is relevant only for primary fault logging. these registers are sticky and can be cleared only through powergood reset or via software clearing the rw1c fields by writing a 1. bit access default value rst/pwr description 127 r/wc/p 0 core fault (f): hardware sets this field to indicate a fault is logged in this fault recording re gister. the f field is set by hardware after the details of the fault is recorded in other fields. when this field is set, hard ware may collapse additional faults from the same source-id (sid). software writes the value read from this field to clear it. 126 ro/p 0 core type (t): type of the faulted dma request 0 = dma write 1 = dma read request this field is relevant only when the f field is set. 125:124 ro 00b core address type (at): this field captures the at field from the faulted dma request. hardware implementations no t supporting device-iotlbs (di field clear in extended ca pability register) treat this field as reserved. when supported, this field is va lid only when the f field is set, and when the fault reason (fr) indicates one of the dma-remapping fault conditions. note: this field is reserved as this feature is not supported. 123:104 ro 0s core reserved 103:96 ro/p 0s core fault reason (fr): reason for the fault. this field is relevant only when the f field is set. 95:80 ro 0s core reserved 79:64 ro/p 0010h core source identifier (sid): requester-id of the faulted dma request. this field is relevant only when the f field is set. datasheet 523 intel ? virtualization technology for di rected i/o registers (d0:f0) (intel ? 82q45 gmch only) 63:36 ro/p 0s core fault info (fi): when the fault reason (fr) field indicates one of the dma-rema pping fault conditions, bits 63:12 of this field contains th e page address in the faulted dma request. hardware treat bits 63:n as reserved (0), where n is the maximum gu est address width (mgaw) supported. when the fault reason (fr) field indicates one of the interrupt-remapping fault cond itions, bits 63:48 of this field indicate the interrupt_ind ex computed for the faulted interrupt request, and bits 47:12 are cleared. this field is relevant only when the f field is set. 35:32 ro/p 0h core fault info (fi): when the fault reason (fr) field indicates one of the dma-rema pping fault conditions, bits 63:12 of this field contains th e page address in the faulted dma request. hardware treat bits 63:n as reserved (0), where n is the maximum gu est address width (mgaw) supported. when the fault reason (fr) field indicates one of the interrupt-remapping fault cond itions, bits 63:48 of this field indicate the interrupt_ind ex computed for the faulted interrupt request, and bits 47:12 are cleared. this field is relevant only when the f field is set. 31:12 ro/p 0s core fault info (fi): when the fault reason (fr) field indicates one of the dma-rema pping fault conditions, bits 63:12 of this field contains th e page address in the faulted dma request. hardware treat bits 63:n as reserved (0), where n is the maximum gu est address width (mgaw) supported. when the fault reason (fr) field indicates one of the interrupt-remapping fault cond itions, bits 63:48 of this field indicate the interrupt_ind ex computed for the faulted interrupt request, and bits 47:12 are cleared. this field is relevant only when the f field is set. 11:0 ro 0s core reserved bit access default value rst/pwr description intel ? virtualization technology for directed i/o registers (d0:f0) (intel ? 82q45 gmch only) 524 datasheet datasheet 525 functional description 13 functional description 13.1 host interface the (g)mch supports the intel ? core?2 extreme processor qx9000 series, intel ? core?2 quad processor q9000 series, and intel ? core?2 duo processor e8000 and e7000 series in the lga775 land grid array package. the cache line size is 64 bytes. source synchronous transfer is used for the address and data signals. the address signals are double pumped and a new address can be generated every other bus clock. at 200/267/333mhz bus clock the address signals run at 667mt/s. the data is quad pumped and an entire 64b cache line can be transferred in two bus clocks. at 200/266/ 333 mhz bus clock, the data signals run at 800/1066/1333 mt/s for a maximum bandwidth of 6.4/8.5/10.6 gb/s. 13.1.1 fsb ioq depth the scalable bus supports up to 12 simultaneous outstanding transactions. 13.1.2 fsb ooq depth the (g)mch supports only one outstanding deferred transaction on the fsb. 13.1.3 fsb gtl+ termination the (g)mch integrates gtl+ termination resistors on die. 13.1.4 fsb dynamic bus inversion the (g)mch supports dynamic bus inversion (dbi) when driving and when receiving data from the processor. dbi limits the number of data signals that are driven to a low voltage on each quad pumped data phase. this decreases the worst-case power consumption of the (g)mch. fsb_dinvb_[3:0] indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase: whenever the processor or the (g)mch drives data, each 16-bit segment is analyzed. if more than 8 of the 16 signals would normally be driven low on the bus, the corresponding fsb_dinvb signal will be asserted, and the data will be inverted prior to being driven on the bus. whenever the pr ocessor or the (g)mch receives data, it monitors fsb_dinvb_[3:0] to determine if the corresponding data segment should be inverted. fsb_dinvb_[3:0] data bits fsb_dinvb_0 fsb_db_[15:0]# fsb_dinvb_1 fsb_db_[31:16]# fsb_dinvb_2 fsb_db_[47:32]# fsb_dinvb_3 fsb_db_[63:48]# functional description 526 datasheet 13.1.5 apic cluster mode support apic cluster mode support is required for backwards compatibility with existing software, including various operating systems. the (g)mch supports three type s of interrupt re-direction: ? physical ?flat-logical ? clustered-logical if more than one xtpr register set in the arbitration pool has the same lowest value, or if all enabled xtpr task priority fields are 1111b, the xtpr register set referenced by the lowest value tpr_sel[3:0] is the ?winner?. the ?winning? xtpr register set provides the values to be substituted in the aa[19:12]# and aa[7:4]# fields of the fs b interrupt message transaction driven by the (g)mch. table 29. host interface 4x, 2x, and 1x signal groups signals associated clock or strobe signal group fsb_adsb, fsb_bnrb, fsb_bprib, fsb_deferb, fsb_dbsyb, fsb_drdyb, fsb_hitb, fsb_hitmb, fsb_lockb, fsb_rsb_[2:0], fsb_trdyb, rstinb hpl_clkinp hpl_clkinn 1x fsb_ab_[16:3], fsb_reqb_[4:0] fsb_adstbb_0 2x fsb_ab_[35:17] fsb_adstbb_1 fsb_db_[15:0], fsb_dinvb_0 fsb_dstbpb_0, fsb_dstbnb_0 4x fsb_db_[31:16], fsb_dinvb_1 f sb_dstbpb_1, fsb_dstbnb_1 fsb_db_[47:32], fsb_dinvb_2 f sb_dstbpb_2, fsb_dstbnb_2 fsb_db_[63:48], fsb_dinvb_3 f sb_dstbpb_3, fsb_dstbnb_3 datasheet 527 functional description 13.2 system memory controller the (g)mch system memory controller suppor ts both ddr2 and ddr3 protocols with two independent 64 bit wide channels each accessing one or two dimms. the controller supports a maximum of two non-ecc ddr2 dimms or two un-buffered non-ecc ddr3 dimms per channel; thus, allowing up to four device ranks per channel. intel ? fast memory access (fma) supported. note: the 82g41 gmch only supports 1 dimm per channel. references to 2 dimms per channel only apply to the 82q45, 82q43, 82b43, 82g45, 82g43 gmch and 82p45, 82p43 mch. the 82g43 supports 1 or 2 dimms per channel depending upon part. 13.2.1 system memory organization modes the system memory controller supports two memory organization modes: single channel and dual channel. 13.2.1.1 single channel mode in this mode, all memory cycles are directed to a single channel. single channel mode is used when either channel a or channel b dimms are populated in any order, but not both. 13.2.1.2 dual channel modes 13.2.1.2.1 dual channel symmetric mode this mode provides maximum performance on real applications. addresses are ping- ponged between the channels after each ca che line (64 byte boundary). if there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned. if two consecutive cache lines are requested, both may be retrieved simultaneously, since they are assured to be on opposite channels. dual channel symmetric mode is used when both channel a and channel b dimms are populated in any order with the total amount of memory in each channel being the same, but the dram device technology and width may vary from one channel to the other. ta b l e 3 0 is a sample dual channel symmetric memory configuration showing the rank organization. table 30. sample system memory dual channel symmetric organization mode rank channel 0 population cumulative top address in channel 0 channel 1 population cumulative top address in channel 1 rank 3 0 mb 2560 mb 0 mb 2560 mb rank 2 256 mb 2560 mb 256 mb 2560 mb rank 1 512 mb 2048 mb 512 mb 2048 mb rank 0 512 mb 1024 mb 512 mb 1024 mb functional description 528 datasheet 13.2.1.2.2 dual channel asym metric mode with intel ? flex memory mode enabled in this addressing mode the lowest dram me mory is mapped to dual channel operation and the top most dram memory is mapped to single channel operation. in this mode the system can run at one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array. this mode is used when intel ? flex memory mode is enab led and both channel a and channel b dimms are populated in any order wi th the total amount of memory in each channel being different. ta b l e 3 1 is a sample dual channel asymmetric memory configuration showing the rank organization with intel ? flex memory mode enabled. 13.2.1.2.3 dual channel asym metric mode with intel ? flex memory mode disabled (stacked mode) in this addressing mode addresses start in channel 0 and stay there until the end of the highest rank in channel 0, and then addresses continue from the bottom of channel 1 to the top. this mode is used when intel ? flex memory mode is disabled and both channel a and channel b dimms are populated in any order wi th the total amount of memory in each channel being different. ta b l e 3 2 is a sample dual channel asymmetric memory configuration showing the rank organization with intel ? flex memory mode disabled. table 31. sample system memory dual chan nel asymmetric organi zation mode with intel ? flex memory mode enabled rank channel 0 population cumulative top address in channel 0 channel 1 population cumulative top address in channel 1 rank 3 0 mb 2048 mb 0 mb 2304 mb rank 2 0 mb 2048 mb 256 mb 2304 mb rank 1 512 mb 2048 mb 512 mb 2048 mb rank 0 512 mb 1024 mb 512 mb 1024 mb table 32. sample system memory dual chan nel asymmetric organi zation mode with intel ? flex memory mode disabled rank channel 0 population cumulative top address in channel 0 channel 1 population cumulative top address in channel 1 rank 3 0 mb 1280 mb 0 mb 2304 mb rank 2 256 mb 1280 mb 0 mb 2304 mb rank 1 512 mb 1024 mb 512 mb 2304 mb rank 0 512 mb 512 mb 512 mb 1792 mb datasheet 529 functional description 13.2.2 system memory te chnology supported the (g)mch supports the following ddr2 and ddr3 data transfer rates, dimm modules, and dram device technologies: ? ddr2 data transfer rates: 667 (pc2-5300) and 800 (pc2-6400) ? ddr3 data transfer rates: 800 (pc3-6400) and 1066 (pc3-8500) ?ddr2 dimm modules: ? raw card c - single sided x16 un-buffered non-ecc ? raw card d - single sided x8 un-buffered non-ecc ? raw card e - double sided x8 un-buffered non-ecc ?ddr3 dimm modules: ? raw card a - single sided x8 un-buffered non-ecc ? raw card b - double sided x8 un-buffered non-ecc ? raw card c - single sided x16 un-buffered non-ecc ? raw card f - double sided x16 un-buffered non-ecc ? ddr2 dram device technology: 512-mb, 1-gb, and 2-gb ? ddr3 dram device technology: 512-mb and 1-gb table 33. supported dimm module configurations memory type raw card version dimm capacity dram device technology dram organization # of dram devices # of physical device ranks # of row/ col address bits # of banks inside dram page size ddr2 667 and 800 (see note) c 256mb 512mb 32m x 16 4 1 13/10 4 8k 512mb 1gb 64m x 16 4 1 13/10 8 8k d 512mb 512mb 64m x 8 8 1 14/10 4 8k 1gb 1gb 128m x 8 8 1 14/10 8 8k e 1gb 512mb 64m x 8 16 2 14/10 4 8k 2gb 1gb 128m x 8 16 2 14/10 8 8k f 512mb 512mb 64m x 8 9 1 14/10 4 8k 1gb 1gb 128m x 8 9 1 14/10 8 8k g 1gb 512mb 64m x 8 18 2 14/10 4 8k 2gb 1gb 128m x 8 18 2 14/10 8 8k ddr3 800 and 1066 a 512 mb 512mb 64m x 8 8 1 13/10 8 8k 1 gb 1gb 128m x 8 8 1 14/10 8 8k b 1 gb 512mb 64m x 8 16 2 13/10 8 8k 2 gb 1gb 128m x 8 16 2 14/10 8 8k c 256 mb 512mb 32m x 16 4 1 12/10 8 8k 512 mb 1gb 64m x 16 4 1 13/10 8 8k f 512 mb 512mb 32m x 16 8 2 12/10 8 8k 1 gb 1gb 64m x 16 8 2 13/10 8 8k functional description 530 datasheet 13.3 pci express* see section 1.2 for a list of pci express features, and the pci express specification for further details. this (g)mch is part of a pci express root complex. this means it connects a host processor/memory subsystem to a pci express hierarchy. the control registers for this functionality are located in device 1 and device 6 configuration space and two root complex register blocks (rcrbs). the dmi rcrb contains registers for control of the ich10/ich7 attach ports. 13.3.1 pci express* architecture the pci express architecture is specifie d in layers. compatibility with the pci addressing model (a load-store architecture with a flat address space) is maintained to ensure that all existing applications an d drivers operate unchanged. the pci express configuration uses standard mechanisms as defined in the pci plug-and-play specification. the initial sp eed of 1.25 ghz (250 mhz internally) results in 2.5 gb/s each direction which provides a 250 mb/s communications channel in each direction (500 mb/s total) that is close to twice the data rate of classic pci per lane. 13.3.1.1 transaction layer the upper layer of the pci express architecture is the transaction layer. the transaction layer?s primary responsibilit y is the assembly and disassembly of transaction layer packets (tlps). tlps are used to communicate transactions, such as read and write, as well as certain types of events. the transaction layer also manages flow control of tlps. 13.3.1.2 data link layer the middle layer in the pci express stack, the data link layer, serves as an intermediate stage between the transaction layer and the physical layer. responsibilities of data link layer include link management, error detection, and error correction. 13.3.1.3 physical layer the physical layer includes all circuitry fo r interface operation, including driver and input buffers, parallel-to-serial and serial-t o-parallel conversion, pll(s), and impedance matching circuitry. 13.3.2 pci express* on (g)mch the (g)mch has two pcie gen 2.0 controllers to support 1x16 graphics or 2x8 graphics modes. to support 1x16 and 2x8 graphics th e system should incorporate two graphics ports- primary port and secondary port. each port is a 1x16 physical connector but 1x8 electrically. note: not all of the above configurations are supp orted on all intel 4 series chipset (g)mch components. refer to ta b l e 1 in chapter 1 for (g)mch components supporting specific features. on plugging a pci express gen 2.0 1x16 pcie graphics card into the primary port the transaction between the (g)mch and the pci express graphics card will take place along all the 16 pci express lanes. when graphic cards are plugged into both the primary and secondary ports transaction between the (g)mch and the graphics card datasheet 531 functional description will take place along 8 of the pci express la nes through each ports. this means that when two x16 graphics cards are plugged into both the slots, the (g)mch will dynamically down sample and transaction takes place only through 8 lanes. the pci express controllers on the (g)mch has been designed to support add2 and mec only the primary slot. when a add2 or mec card is plugged into the secondary slot, the card will not function. ta b l e 3 4 shows the usage models supported on the (g)mch for pci express graphics cards, add2 and add2+ cards. note: x indicates support available is n/a - support not available. table 34. supported usage models ports pcie graphics card mec add2 primary slot pciex16 card in stand alone pcie x8 card in dual graphics mode xx secondary slot pcie x8 card in dual graphics mode no support available with card only in secondary slot n/a n/a functional description 532 datasheet 13.4 integrated graphics device (intel ? 82q45, 82q43, 82b43, 82g45, 82g43 gmch only) this section details the chipset integrated graphics engines (3d, 2d, and video), 3d pipeline, and the respective capabilities. the gmch graphics device supports ten fully programmable execution cores, enabling greater performance than previous generation chipsets. the gmch internal graphics devices (igd) contain several types of components. the major components in the igd are the engines, planes, pipes, and ports. the gmch has a 3d/2d instruction processing unit to contro l the 3d and 2d engines, respectively. the igd?s 3d and 2d engines are fed with data through the memory controller. the outputs of the engines are surfaces sent to memory, which are then retrieved and processed by gmch planes. 13.4.1 3d and video engines for graphics processing the 3d graphics pipeline for the chipset has a deep pipelined architecture in which each stage can simultaneously operate on different primitives or on different portions of the same primitive. all the cores are fully prog rammable, increasing the versatility of the 3d engine. the 3d engine also has a number of performance and power-management enhancements, providing improved power/pe rformance ratios over the igd. these include: ? execution units increased to 10 from the previous 8 eus ? improved hddvd hardware acceleration ? graphics support for intel virtualization technology dma ? graphics support for intel txt (82q45/82q43 gmch only) ? intel hd audio playback avc/vc1 decoding in hardware figure 10. gmch graphics controller block diagram plane b cursor c sprite c plane c cursor b sprite b pipe c pipe b memory m u l t i p l e x e r crt sdvo b/c vga video engine 2d engine 3d engine clipper strip & fan/setup alpha blend/ gamma/panel fitter geometry shader vertex fetch/vertex shader windower/iz ihdmi dp datasheet 533 functional description 13.4.1.1 3d engine execution units (eus) the 3d processing hardware includes su pport for 2 more eus over the previous generation. the eus perform 128-bit wide execution per clock and are support simd8 instructions for vertex processing and simd16 instructions for pixel processing. 13.4.1.2 3d pipeline 13.4.1.2.1 vertex fetch (vf) stage the vf stage performs one major function: executing 3dprimitive commands. some enhancements have been included to better support legacy directx 3d apis as well as opengl. 13.4.1.2.2 vertex sh ader (vs) stage the vs stage of the 3d pipeline is used to pe rform shading of vertices output by the vf function. the vs unit will, thus, produce an output vertex reference for every input vertex reference received from th e vf unit, in the order received. 13.4.1.2.3 geometry shader (gs) stage the gs stage receives inputs from the previous vs stage. compiled application- provided gs shader programs specify an algo rithm to convert the vertices of an input object into some output primitives. for ex ample, a gs shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line. or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the those edges. 13.4.1.2.4 clip stage the clip stage can be used to perform gene ral processing on incoming 3d objects. however, it also includes specialized logic to perform a cliptest function on incoming object. the clip test optimizes generalized 3d clipping. the c lip unit examines the position of incoming vertices, and accepts/rejects 3d objects based on its clip algorithm. 13.4.1.2.5 strips and fans stage the strips and fans (sf) stage of the 3d pipeline is responsible for performing setup operations required to rasterize 3d object s. the outputs from the sf stage to the windower stage comprise of implementation-specific information required for the rasterization of objects and also supports clipping of primitives to some extent. 13.4.1.2.6 windower/iz (wiz) stage the wiz unit performs an early depth test, a major performance-optimization feature where failing pixels are removed; thus, eliminating unnecessary processing overhead. the windower uses the parameters provided by the sf unit in the object-specific rasterization algorithms. the wiz unit rasterizes objects into the corresponding set of pixels. the windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible. color dithering tends to diffuse the sharp color ba nds seen on smooth-shaded objects. functional description 534 datasheet 13.4.2 video engine the video engine handles the non-3d (media /video) applications. it includes support for vld and mpeg2 decode in hardware. the gmch engine includes a number of encompassments over the previous generation capabilities, which have been listed above. 13.4.3 2d engine the gmch contains blt (block level transfer) functionality and an extensive set of 2d instructions. to take advantage of the 3d drawing engine?s functionality, some blt functions make use of the 3d renderer. 13.4.3.1 chipset vga registers the 2d registers are a combination of registers for the original video graphics array (vga) and others to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original vga standard. 13.4.3.2 logical 128-bit fi xed blt and 256 fill engine use of this blt engine accelerates the graphical user interface (gui) of microsoft windows* operating systems. the 128-bi t gmch blt engine provides hardware acceleration of block transfers of pixel da ta for many common windows operations. the term blt refers to a block transfer of pixel data between memory locations. the blt engine can be used for the following: ? move rectangular blocks of data between memory locations ? data alignment ? perform logical operations (raster ops) the rectangular block of data does not change as it is transferred between memory locations. the allowable memory transfer s are between: cacheable system memory and frame buffer memory, frame buffer memory and frame buffer memory, and within system memory. data to be transferred can consist of regions of memory, patterns, or solid color fills. a pattern will always be 8x8 pixels wide and may be 8, 16, or 32 bits per pixel. the blt engine has the ability to expand mono chrome data into a color depth of 8, 16, or 32 bits. blts can be either opaque or tr ansparent. opaque transfers move the data specified to the destination. transparent tr ansfers compare destination color to source color and write according to the mode of transparency selected. data is horizontally and vertically aligned at the destination. if the destination for the blt overlaps with the source memory location, the gmch can specify which area in memory to begin the blt transfer. hardware is included for all 256 raster operations (source, pattern, and destination) defined by microsoft, including transparent blt. the gmch has instructions to invoke blt and stretch blt operations, permitting software to set up instruction buffers and use batch processing. the gmch can perform hardware clipping during blts. datasheet 535 functional description 13.5 display interfaces (intel ? 82q45, 82q43, 82b 43, 82g45, 82g43, 82g41 gmch only) the gmch has three display ports, one analog and two digital ports b and c. each port can transmit data according to one or more protocols. the digital ports b and c can be configured to drive natively hdmi, dvi and display port or can be connected to an external device (sdvo) that converts one protocol to another. examples of sdvo devices are tv encoders, external dacs, lv ds transmitters, hdmi transmitters, and tmds transmitters. each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. the gmch has one dedicated display port, the analog port. digital ports b and c are multiplexed with the pci express graphics (p eg) interface and are not available if an external peg device is in use. the digital ports can also be configured to drive sdvo data. when a system uses a peg connector, sdvo ports b and c can be used via an add2 (advanced digital display 2) or mec (media expansion card). ? the gmch?s analog port uses an integrated 350 mhz ramdac that can directly drive a standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 75 hz. ? the gmch?s sdvo ports are each capable of driving a 400 mp pixel rate. each port is capable of driving a digital display up to 2560x1600 @ 60hz. integrated hdmi, dvi, and display port supp ort multiplexed over pci express graphics port for native connection to a compatible display. 13.5.1 analog display port characteristics the analog display port provides a rgb si gnal output along with a hsync and vsync signal. there is an associated ddc signal pair that is implemented using gpio pins dedicated to the analog port. the intended target device is for a crt based monitor with a vga connector. display devices such as lcd panels with analog inputs may work satisfactory but no functionality added to the signals to enhance that capability. table 35. analog port characteristics signal port characteristic support rgb voltage range 0.7 v p-p only monitor sense analog compare analog copy protection no sync on green no hsync vsync voltage 2.5 v enable/disable port control polarity adjust vga or port control composite sync support no special flat panel sync no stereo sync no ddc voltage externally buffered to 5v control through gpio interface functional description 536 datasheet 13.5.1.1 integrated ramdac the display function contains a ram-based digital-to-analog converter (ramdac) that transforms the digital data from the graphics and video subsystems to analog data for the crt monitor. gmch?s integrated 350 mhz ramdac supports resolutions up to 2048 x 1536 @ 75 hz. three 8-bit dacs provide the r, g, and b signals to the monitor. 13.5.1.2 sync signals hsync and vsync signals are digital and conform to ttl signal levels at the connector. since these levels cannot be generated intern al to the device, external level shifting buffers are required. these signals can be pola rity adjusted and individually disabled in one of the two possible states. the sync signals should power up disabled in the high state. no composite sync or special fl at panel sync support will be included. 13.5.1.3 vesa/vga mode vesa/vga mode provides compatibility for pr e-existing software that set the display mode using the vga crtc registers. timings are generated based on the vga register values and the timing generator registers are not used. 13.5.1.4 ddc (display data channel) ddc is a standard defined by vesa. its purpose is to allow communication between the host system and display. both configuration and control information can be exchanged allowing plug- and-play systems to be realized. support for ddc 1 and ddc 2 is implemented. the gmch uses the crt_ ddc_clk and crt_ddc_data signals to communicate with the analog monitor. the gm ch will generate these signals at 2.5 v. external pull-up resistors and level shifting circuitry should be implemented on the board. the gmch implements a hardware gmbus cont roller that can be used to control these signals allowing for transactions speeds up to 400 khz. 13.5.2 digital display interface the gmch can drive hdmi, dvi, and display port natively. the digital ports b and/or c can be configured to drive hdmi, dvi, and display port. the digital ports are multiplexed on to the peg interface. 13.5.2.1 high definition multimedia interface (intel ? 82g45, 82g43, 82g41, 82b43 gmch only) the high-definition multimedia interface (hdmi) is provided for transmitting uncompressed digital audio and video signals from dvd players, set-top boxes, and other audiovisual sources to television sets, projectors, and other video displays. it can carry high-quality multi-channel audio data and all standard and high-definition consumer electronics video formats. hdmi display interface connecting the gmch and display devices uses transition minimized differential signaling (tmds) to carry audiovisual information through the same hdmi cable. hdmi includes three separate communication s channels: tmds, ddc, and the optional cec (consumer electronics control). as shown in figure 11 , the hdmi cable carries four differential pairs that make up the tmds data and clock channels. these channels are used to carry video, audio and auxiliary data . in addition, hdmi carries a vesa display data channel (ddc). the ddc channel is used by an hdmi source to determine the capabilities and characteristics of the sink. datasheet 537 functional description audio, video and auxiliary (control/status) data is transmitted across the three tmds data channels. the video pixel clock is tran smitted on the tmds clock channel and is used by the receiver for data recovery on the three data channels. the digital display data signals driven natively through the gmch are ac coupled and needs level shifter to convert the ac coupled signals to the hdmi compliant digital signals. note: hdmi support on 82b43 is enabled via intel? upgrade service 13.5.2.2 digital video interface (dvi) gmch digital ports can be configured to dr ive dvi-d. dvi uses tmds for transmitting data from the transmitter to the receiver which is similar to the hdmi protocol but the audio and cec. refer to the hdmi section for more information on the signals and data transmission. to drive dvi-i through the back panel the vga ddc signals are connected along with the digital data and clock signals from one of the digital ports. when a system has support for dvi-i port, then either vga or the dvi-d through a single dvi-i connector can be driven but not both simultaneously. the digital display data signals driven natively through the gmch are ac coupled and needs level shifter to convert the ac coupled signals to the hdmi compliant digital signals. 13.5.2.3 ddpc_ctrldata and ddpc_ctrlclk the gmch incorporates an i 2 c bus for digital port c to allow communication between the host system and display. both configuration and control information can be exchanged between the system and the digital monitor allowing plug- and-play systems to be realized. the gmch generates these signals at 3.3 v. ex ternal pull-up resistors and level shifting circuitry should be implemented on the board. this signal shall be used to configure digital port c as either hdmi or dvi. figure 11. hdmi overview tmds data channel 0 tmds data channel 1 tmds data channel 2 tmds clock channel hot plug detect display data channel (ddc) hdmi tx hdmi rx cec line hdmi sink gmch/ hdmi source functional description 538 datasheet 13.5.2.4 display port display port is a digital communication inte rface that utilizes differential signalling to achieve a high bandwidth bus interface designed to support connections between pcs and monitors, projectors, and tv displays. display port is also suitable for display connections between consumer electronics devices such as high definition optical disc players, set top boxes, and tv displays. a display port consists of a main link, auxiliary channel, and a hot plug detect signal. the main link is a uni-directional, high-b andwidth, and low latency channel used for transport of isochronous data streams such as uncompressed video and audio. the auxiliary channel (aux ch) is a half-duplex bi-directional channel used for link management and device control. the hot plug detect (hpd) signal serves as an interrupt request for the sink device. 13.5.2.5 auxiliary channel (aux ch) the auxiliary channel consists of an ac-coupled, bi-directional differential pair, providing a data rate of 1 mbps. it is used for link management and device control (that is, for transmitting control and status information). aux ch is multiplexed to the pci express rx lanes. 13.5.2.6 peg mapping of digital display signals ta b l e 3 6 shows the peg mapping of hdmi(dvi), display port, and sdvo signals. figure 12. display port overview main link (isochronous streams) display port tx display port rx sink device source device aux channel (link/device management) hot plug detect (interrupt request) datasheet 539 functional description table 36. (g)mch pci express tx/rx mapp ing of supported display technologies pci express differential pair lanes pci express differential pair lanes with lane reversal displayport signals hdmi/dvi signals sdvo signals description peg_txp_7 peg_txp_8 dpc_lane3 tmdsc_clk1 sdvoc_clk displayport c or hdmi c or sdvo c peg_txn_7 peg_txn_8 dpc_lane3# tmdsc_clk1# sdvoc_clk# peg_txp_6 peg_txp_9 dpc_lane2 tmdsc_data0 sdvoc_blue peg_txn_6 peg_txn_9 dpc_lane2# tmdsc_data0# sdvoc_blue# peg_txp_5 peg_txp_10 dpc_lane1 tmdsc_data1 sdvoc_green peg_txn_5 peg_txn_10 dpc_lane1# tmdsc_data1# sdvoc_green# peg_txp_4 peg_txp_11 dpc_lane0 tmdsc_data2 sdvoc_red peg_txn_4 peg_txn_11 dpc_lane0# tmdsc_data2# sdvoc_red# peg_txp_3 peg_txp_12 dpb_lane3 tmd sb_clk2 sdvob_clk displayport b or hdmi b or sdvo b peg_txn_3 peg_txn_12 dpb_lane3# tmdsb_clk2# sdvob_clk# peg_txp_2 peg_txp_13 dpb_lane2 tmdsb_data0 sdvo_blue peg_txn_2 peg_txn_13 dpb_lane2# tmdsb_data0# sdvo_blue# peg_txp_1 peg_txp_14 dpb_lane1 tmdsb_data1 sdvob_green peg_txn_1 peg_txn_14 dpb_lane1# tmdsb_data1# sdvob_green# peg_txp_0 peg_txp_15 dpb_lane0 tmdsb_data2 sdvob_red peg_txn_0 peg_txn_15 dpb_lane0# tmdsb_data2# sdvob_red# peg_rxp_7 peg_rxp_8 dpc_hpd tmdsc_hpd hpd for dp c and hdmi c peg_rxn_7 peg_rxn_8 peg_rxp_6 peg_rxp_9 dpc_aux aux ch for display port c peg_rxn_6 peg_rxn_9 dpc_aux# peg_rxp_5 peg_rxp_10 sdvoc_int peg_rxn_5 peg_rxn_10 sdvoc_intb peg_rxp_4 peg_rxp_11 peg_rxn_4 peg_rxn_11 peg_rxp_3 peg_rxp_12 dpc_hpd hdmib_hpd hpd for dp b and hdmi b peg_rxn_3 peg_rxn_12 peg_rxp_2 peg_rxp_13 dpb_aux sdvo_fldstall sdvo peg_rxn_2 peg_rxn_13 dpb_aux# sdvo_fldstall# peg_rxp_1 peg_rxp_14 sdvo_int peg_rxn_1 peg_rxn_14 sdvo_int# peg_rxp_0 peg_rxp_15 sdvo_tvclkin peg_rxn_0 peg_rxn_15 sdvo_tvclkin# functional description 540 datasheet 13.5.2.7 multiplexed digital display channels ? intel ? sdvob and intel ? sdvoc the gmch supports digital display devices through two sdvo ports multiplexed with the peg signals. when an exte rnal graphics accelerator is used via the peg port, these sdvo ports are not available. the shared sdvo ports each support a pixel clock up to 200 mhz and can support a variety of transmission devices. sdvo_ctrldata is an open-drain signal that acts as a strap during reset to tell the gmch whether the interface is a pci expre ss interface or an sdvo interface. when implementing sdvo, either using add2 cards or with a down device, a pull-up resistor is placed on this line to signal to the gmch to run in sdvo mode and for proper gmbus operation. 13.5.2.7.1 add2/media expansion card(mec) when a peg connector is used in the plat form, the multiplexed sdvo ports may be used via an add2 or mec card . the add2 card will be desi gned to fit a standard pci express (x16) connector. figure 13. display configur ations on atx platforms 0 15 0 15 (g)mch peg signals (g)mch peg pins x16 pcie connector x1 pcie card x16 pcie card 0 15 x16 pcie connector x4 sdvo add2/+ card x8 sdvo (add2/+) card 0 15 non reversed mode x16 pcie connector digital port b hdmi/dp/dvi 0 pcie lane 3 pcie lane 3 pcie lane 7 pcie lane 7 x16 pcie connector sdvo/digital port c 0 sdvo/digital port b pcie lane 11 pcie lane 15 15 pcie lane 8 mec card digital port c hdmi/dp/dvi x1 pcie atx form factor 15 concurrency mode add2+/mec card sdvo card add card datasheet 541 functional description 13.5.2.7.2 tv-in capabilities the gmch, in conjunction with add2/media expansion card, can function as a tv- tuner card capable of taking in both analog or hd signals. 13.5.2.7.3 analog content protection analog content protection will be provid ed through the external encoder using macrovision 7.01. dvd software. it must ve rify the presence of a macrovision tv encoder before playback continues. simple attempts to disable the macrovision operation must be detected. 13.5.2.7.4 connectors target tv connectors support hdmi. the exte rnal tv encoder in use will determine the method of support. 13.5.2.7.5 control bus communication to sdvo registers (and if used, add2/mec proms and monitor ddcs) is accomplished by using the sdvo_ctr ldata and sdvo_ctrlclk signals through the sdvo device. these signals run up to 1 mhz and connect directly to the sdvo figure 14. display configurations on bala nced technology extended (btx) platforms 0 15 15 0 (g)mch peg signals (g)mch peg pins x16 pcie connector x1 pcie card x16 pcie card 15 0 x16 pcie connector x4 sdvo add2/+ card x8 sdvo (add2/+) card 15 0 reversed mode x16 pcie connector digital port c hdmi/dp/dvi 15 pcie lane 3 pcie lane 3 pcie lane 0 pcie lane 0 x16 pcie connector sdvo/digital port c 15 sdvo/digital port b pcie lane 15 0 pcie lane 8 mec card digital port b hdmi/dp/dvi x1 pcie btx form factor 0 pcie lane 11 concurrency mode add2+/mec card sdvo card add card pcie lane 7 functional description 542 datasheet device. the sdvo device is then responsible for routing the ddc and prom data streams to the appropriate location. consult sdvo device datasheets for level shifting requirements of these signals. 13.5.2.7.6 intel ? sdvo modes the port can be dynamically configured in several modes: ? standard ? baseline sdvo functionality. this mode supports pixel rates between 25 and 200 mp/s. the mode uses three data pairs to transfer rgb data. ? dual standard ? this mode uses standard data streams across both sdvob and sdvoc. both channels can only run in standard mode (3 data pairs) and each channel supports pixel rates between 25 mp/s and 200 mp/s. ? dual independent standard ? in dual independent standard mode, each sdvo channel will transmit a different pixel stream. the data stream across sdvob will not be the same as the data stream across sdvoc. ? dual simultaneous standard ? in dual simultaneous standard mode, both sdvo channels will transmit the same pixel stream. the data stream across sdvob will be the same as the data stream across sdvoc. the display timings will be identical, but the transfer timings may not be (i.e., sdvob clocks and data may not be perfectly aligned with sdvoc clock and data as seen at the sdvo device(s)). since this uses just a single data stream, it uses a single pixel pipeline in the gmch. 13.5.3 multiple display configurations microsoft windows* 2000, windows* xp, and windows* vista operating systems provide support for multi-monitor display. since the gmch has several display ports available for its two pipes, it can support up to two different images on different display devices. timings and resolutions for these two images may be different. the gmch supports dual display clone, dual display twin, and extended desktop. dual display clone uses both display pipes to drive the same content, at the same resolution and color depth to two different displays. this configuration allows for different refresh rates on each display. dual display twin uses one of the display pipes to drive the same content, at the same resolution, color depth, and refres h rates to two different displays. extended desktop uses both display pipes to drive different content, at potentially different resolutions, refresh rates, and co lor depths to two different displays. this configuration allows for a larger windows de sktop by using both displays as a work surface. note: the gmch does not operate in parallel with an external pci express graphics device. the gmch can, however, work in co njunction with a pci graphics adapter. 13.5.3.1 high bandwidth digital content protection (hdcp) the gmch is the first desktop chipset with integr ated hdcp keys. hdcp protection is required to drive high definition content over the digital display. hdcp is supported on both the digital ports b and c, but not simultaneously. the gmch supports hdcp over hdmi, display port and dvi display technologies. hdcp key integration reduces the effort and resources of key handling and key buying at the customer end. datasheet 543 functional description 13.6 intel ? virtualization techno logy for i/o devices (intel ? 82q45 gmch only) 13.6.1 overview for the intel 4 series chipsets, the key inte l virtualization technology for i/o devices (device of virtualization) objectives are do main based isolation and virtualization. a domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. virtualization allows for the creation of one or more partitions on a single system. this could be multiple partitions in the same os or there can be multiple operating system instances running on the same system offering benefits such as system consolidation, legacy migration, activity partitioning, or security. currently, the gmch supports two partition approaches as shown in the eit usage model (see figure 15 ). 13.6.2 embedded it client usage model figure 15 shows two different host partitions. ? capability vm runs host os management . vm runs it/management applications. virtual partition hidden from the user. ? a vmm is introduced to virtualized bios and other system components to the os. ? dma remap engine exists in hardware for on-the-fly address translations. figure 15. example of eit usage model capability partition cos and apps virtual device management parition it/management apps io virtualization physical device driver virtual machine monitor (vmm) dma-remapping hardware io device 1 assigned to host os io device 2 assigned to service os functional description 544 datasheet 13.6.2.1 intel virtualization tech nology for i/o devices enables ? multiple containers (silos) or domains run on a single hardware platform, fully isolated from each other. dedicated hardware can be assigned to each container. address space remap prevents hardware from accessing space outside its memory allocation. ? flexible memory management by vmm. ? un-modified device drivers to run in both partitions. ? contain dma errors across partitions. ? allows enforcement of independent security policies for each partition. 13.6.2.2 hardware versus software virtualization ? though software-only approach for i/ o device management provides a few advantages like easier vm mobility across physical machines, this approach has some serious limitations. 13.6.2.3 hardware virtualization advantages ? hardware or device virtualization doesn?t cause any changes to guest os. ? no hardware functionality lost in virtual driver interface. ? vmm can be small since minimal drivers needed, thereby avoiding significant processor utilization overhead, and hence increases system performance. ? hardware approach provides more robust memory protection as described earlier. 13.6.3 concept of dma address remapping this section describes the hardware ar chitecture concepts of dma remapping. the dma-remapping architecture facilitates fl exible assignment of i/o devices to an arbitrary number of domains. each domain ha s a view of physical address space that may be different than the host physical address space. dma-remapping treats the address specified in dma requests as dma virtual addresses (dva). depending on the software usage model, the dma virtual address space may be the same as the guest- physical address (gpa) space of the domain to which the i/o device is assigned, or a purely virtual address space defined by software. in either case, dma-remapping provides the transformation of address in a dma request issued by an i/o device to its corresponding host-physical address (hpa). for simplicity, the rest of the document describes the input address to the dma- remapping hardware as gpa. figure 16 illustrates the i/o physical address translation. i/o devices 1 and 2 are assigned to domains 1 and 2 respectively. the software responsible for creating and managing the domains allocates system physical memory for both domains and sets up the dma a ddress translation function. gpa in dma requests initiated by devices 1 and 2 are translated to appropriate hpas by the dma remapping hardware. datasheet 545 functional description 13.7 intel ? trusted execution technology (intel ? txt) (intel ? 82q45 and 82q43 gmch only) trusted execution technology (txt) is a security initiative that involves the processor, chipset, and platform. trusted execution tec hnology requires the following support in the chipset: ? new fsb encodings for ltmw and ltmr cycles ? measured launch of a vmm, using a tpm ? protected path from the processor to th e tpm, which is enabled by the processor ? ranges of memory protected from dma accesses. figure 16. dma ad dress translation functional description 546 datasheet 13.8 intel ? management engine (me) subsystem the platform implements an intel management engine (intel me) subsystem to provide intel ? active management technology (intel amt) functionality. this me was implemented using a scaleable architecture. the me subsystem consists of a microcontroller, memory controller, and various i/o components spread across the (g)mch and ich i/o controller. me has a low pin count, low power private communication link - controller link (clink) - that connects the me-(g)mch and me-ich functional logic. the clink for the me subsystem is analogous to dmi for the host subsystem. the manageability engine is a low power execution engine that provides hardware for partitioned and/or secured firmware. the us age models for me are in the manageability of the platform (i.e., intel qst, inte l tpm, and asf functionality, alerting, communications with network in case of os absent state, etc.) 13.8.1 me host visibl e functional blocks the me subsystem contains various i/o and logic which is internal to me functionality. additionally, it also contains host visible pci functions making it a multi-function pci device. the following are the host visible functions heci (host manageability engi ne communication interface): heci provides an interface for host software and me firmware communication. it allows for communication between the host processor based driver and firmware that is running in the me. there are 2 heci functions inside the me subsystem with their independent register space. pt-io (proactive technology io): this block provides functionality for the core of intel amt in host operating system absent state. it exposes two functions to host software: ? ide-r (ide redirection): ide-r function ex poses a standard ide device to the host based driver. usage for this function is to allows the client machine with me enabled to transfer data back and forth between the client and the console which is on the network. typical usage model is remote boot. ? kt (keyboard text redirection): kt function exposes an uart register set to the me host. this allows the client to have a 2-way communication between the client with me enabled and the console over the ne twork. typical usage is to send text to a remote console and receive remote console keystrokes. datasheet 547 functional description 13.8.2 me power states me power states and host/me state combinations are described in the following tables. 13.8.3 host/me state transitions scenario 1: s5/mo ff (g3) to s0/m0 ? bios detects memory and initializes system memory controller ? me waits for bios message before moving from moff to m0 ? bios sends me information about the dimms, which me stores into flash scenario 2: s(x)/m1 to s0/m0 ? bios asks already running me to recover dimm timing parameters from flash ? bios initializes host memory controller ? bios notifies me that high performance memory is available and it transitions from m1 to m0 scenario 3: s(x)/moff to sx/m1 ? after initial boot (s5/moff to s0/m0), memory configuration is saved in flash ? wake event triggers switch to sx/m1 ? memory configuration loaded and bsel information supplied to clock chip ? transition takes place mstate description moff me off m1 me is running at slow speed, using its own memory controller which can access ch0 memory. m0 me is running at full speed using the host memory controller to access uma. table 37. host/me state combinations given host state all owable me states s0 m0, moff s3, s4, s5 m1, moff functional description 548 datasheet 13.9 thermal sensor there are several registers that need to be configured to support the (g) mch thermal sensor functionality and smi# generation. customers must enable the catastrophic trip point as protection for the (g) mch . if the catastrophic trip point is crossed, then the (g) mch will instantly turn off all clocks inside the device. customers may optionally enable the hot trip point to generate smi#. customers will be required to then write their own smi# handler in bios that will speed up the (g) mch (or system) fan to cool the part. 13.9.1 pci device 0, function 0 the smicmd register requires that a bit be set to generate an smi# when the hot trip point is crossed. the errsts register can be inspected for the smi alert. 13.9.2 gmchbar thermal sensor registers the digital thermometer configuration regist ers reside in the mchbar configuration space. address register symbol register name default value access c8?c9h errsts error status 0000h rwc/s, ro cc?cdh smicmd smi command 0000h ro, r/w address register symbol register name default value access cd8?cd8h tsc1 thermal sensor control 1 00h rw/l, r/w, rs/wc cd9?cd9h tsc2 thermal sensor control 2 00h ro, rw/l cda?cdah tss thermal sensor status 00h ro cdc?cdfh tsttp thermal sensor temperature trip point 00000000h ro, rw, r/w/l ce2?ce2h tco thermal calibrati on offset 00h rw/l/k, r/w/l ce4?ce4h therm1 hardware throttle control 00h rw/l, ro, r/w/l/k ce6?ce6h therm3 tco fuses 00h ro, rs/wc cea?cebh tis thermal interrupt status 0000h ro, r/wc cf1?cf1h tsmicmd thermal smi command 00h ro, r/w datasheet 549 functional description 13.10 power management the (g)mch has many permutations of possibly concurrently operating modes. obviously, care should be taken (hardware and software) to disable unused sections of the silicon when this can be done with sufficiently low performance impact. refer to the acpi specification, revision 3.0 for an overview of the system power states mentioned in this section. 13.10.1 main memory power management this section details the support provided by the (g)mch corresponding to the various processor/display/system acpi states. descriptions provided in this section should be used in section 13.10.3 . table 38. targeted memory state conditions mode memory state with internal graphics memory state with external graphics c0, c1, c2 dynamic memory rank power down based on idle conditions dynamic memory rank power down based on idle conditions c3, c4 dynamic memory rank power down based on idle conditions if graphics engine is idle, no display requests, and permitted display configuration, then enter self-refresh. otherwise use dynamic memory rank power down based on idle conditions dynamic memory rank power down based on idle conditions if there are no memo ry requests, then enter self-refresh . otherwise, use dynamic memory rank power down based on idle conditions s3 self refresh mode self refresh mode s4 memory power down (contents lost ) memory power down (contents lost) table 39. platform system states state description g0/s0 full on g1/s1 stop clock. clock to processor still ru nning. clock stopped to processor core. processor thread synchronization not required g1/s3-cold suspend to ram (str). context saved to memory (s3-hot is not supported by the (g)mch) g1/s4 suspend to disk (std). all power lost (except wakeup on ich) g2/s5 soft off. all power lost (except wakeup on ich). total reboot g3 hard off. all power (ac and battery) removed from system functional description 550 datasheet 13.10.2 interface power states supported table 40. processor power states state description c0 full on c1/c1e auto halt c2/c2e stop clock. clock to processor stil l running. clock stopped to processor core. processor thread synchronization required. c3 deep sleep. clock to processor stopped c4/c4e deeper sleep. same as c3 wi th reduced voltage on the processor table 41. internal graphics display device control state description d0 display active d1 low power state, low latenc y recovery, standby display d2 suspend display d3 power-off display table 42. pci express link states state description l0 full on ? active transfer state l1 lowest active power management - longer exit latency table 43. main memory states state description power up cke asserted. active mode pre-charge power down cke deasserted (not self-refresh) with all banks closed active power down cke deasserted (not se lf-refresh) with min. one bank active self-refresh cke deasserted using device self-refresh datasheet 551 functional description 13.10.3 chipset state combinations (g)mch supports the state combinations listed in the ta b l e 4 4 . table 44. g, s, and c state combinations global (g) state sleep (s) state processor (c) state processor state system clocks description g0 s0 c0 full on on full on g0 s0 c1 auto-halt on auto halt g0 s0 c2 stop grant on stop grant g1 s0 c3 deep sleep, clock to processor stopped on deep sleep g1 s0 c4 deeper sleep reduced voltage on the processor on deep sleep with processor voltage lowered. g1 s3 power-off ? off, except rtc suspend to ram g1 s4 power-off ? off, except rtc suspend to disk g2 s5 power-off ? off, except rtc soft off g3 na power-off ? power-off hard off table 45. interface activity to state mapping acpi state/ feature c0/c1/c2 c3/c4 s1 s3 s4, s5 dram on (with power saving features) self-refresh (with this power saving feature enabled) on (with power saving features) self-refresh for non-me channel. other channel is me state dependent depending on me state gtl control, data, address buffer sense amp disable no dynamic disabling of data bus sense amps, dynamic transmit clock gating no dynamic disabling of data bus sense amps, dynamic transmit clock gating no dynamic disabling of data bus sense amps, dynamic transmit clock gating on auto halt pci express state l0/l1 (aspm) l0/l1 (aspm) l0/l1 (aspm) power off power off dmi interface l0/l1 (aspm) l0/l1 (aspm) l0/l1 (aspm power off power off hpll running running running depending on me state depending on me state functional description 552 datasheet pci express pll running running running power off power off dpll a & b running when corresponding display pipe is enabled running when corresponding display pipe is enabled running when corresponding display pipe is enabled power off power off fsb, dmi, pci express rcomp running running running power off power off thermal sensor yes yes yes depending on me state depending on me state (g)mch core power on on on off off mem rcomp running running (bypass mode) running depending on me state depending on me state table 45. interface activity to state mapping acpi state/ feature c0/c1/c2 c3/c4 s1 s3 s4, s5 datasheet 553 functional description 13.11 clocking the (g)mch has a total of 5 plls providing many times that many internal clocks. the plls are: ? host pll ? generates the main core clocks in the host clock domain. can also be used to generate memory and internal graphics core clocks. uses the host clock (h_clkin) as a reference. ? memory i/o pll - optionally generates low jitter clocks for memory i/o interface, as opposed to from host pll. uses the host fsb differential clock (hpl_clkinp/ hpl_clkinn) as a reference. low jitter clock source from memory i/o pll is required for ddr667 and higher frequencies. ? pci express pll ? generates all pci express related clocks, including the direct media that connect to the ich. this pll uses the 100 mhz clock (exp_clknp/ exp2_clknp) as a reference. display pll a ? generates the internal clocks for display a. uses d_refclkin as a reference. ? display pll b ? generates the internal clocks for display b. also uses d_refclkin as a reference. ck505 is the clocking chip required for the platform. functional description 554 datasheet figure 17. platform clocking diagram pci down device 24 mhz intel ? ich10 osc 32.768 khz pci express 100 mhz sata 100 mhz pci slot pci 33 mhz sio lpc tpm lpc dmi pci 33 mhz pci 33 mhz pci 33 mhz pci 33 mhz ref 14 mhz ref 14 mhz usb 48 mhz drefclk 96 mhz diff pair memory slot0 slot1 slot2 slot3 xdp processor processor diff pair processor diff pair processor diff pair pci express pci express pci express slot pci 33 mhz pci0 pci1 pci2 pcif5 pci4 ref / fsc usb / fsa src0 / dot96 src2 / 2# src5 / 5# src4 / 4# src7/ 1# src6 / 6# src3 / 3# src8 / itp cpu1 / 1# cpu0 / 0# lan (boazman) pci express 100 mhz pci express 100 mhz pci express 100 mhz pci express 100 mhz pci express slot (g)mch intel high definition audio nc nc fsb pci 33 mhz pci3 25.000 mhz clocks pci0 and pci1 should be routed to the longest trace lengths on platforms that use pci0 and pci1 pci_stop#/src5 cpu_stop#/src#5 ck505 56 pin tssop datasheet 555 electrical characteristics 14 electrical characteristics this chapter provides the absolute maximu m ratings, current consumption, and dc characteristics. 14.1 absolute minimum and maximum ratings ta b l e 4 6 specifies the intel ? 4 series chipset absolute maximum and minimum ratings. within functional operatio n limits, functionality and long-term reliability can be expected. at conditions outside functional operatio n condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. if a device is returned to conditio ns within functional operation limits after having been subjected to conditions outs ide these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to condit ions exceeding the functional operation condition limits. at conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time its reliabilit y will be severely degraded or not function when returned to conditions within th e functional operating condition limits. although the (g)mch contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. table 46. absolute minimum and maximum ratings symbol parameter min max unit notes t storage storage temperature -55 150 c 1 (g)mch core vcc (intel 82p45, 82p43, 82q45, 82q43, 82b43, 82g41 (g)mch only) 1.1 v core supply voltage with respect to v ss -0.3 1.21 v vcc (intel ? 82g45, 82g43 gmch only) 1.125 v core supply voltage with respect to v ss -0.3 1.21 v host interface (800/1066/1333 mhz) vtt_fsb system bus input voltage with respect to vss -0.3 1.32 v vcca_hpll 1.1 v host pll analog supply voltage with respect to v ss -0.3 1.21 v system memory interface (ddr2 667/800 mhz, ddr3 800/1066 mhz) vcc_ddr 1.8 v ddr2 / 1.5 v ddr3 system memory supply voltage with respect to v ss -0.3 4.0 v electrical characteristics 556 datasheet 14.2 current consumption ta b l e 4 7 and ta b l e 4 8 show the current consumption for the (g)mch. i cc values are provided for the worst case i cc situations for each component of the (g)mch. ?i cc max current values are defined as the theoretical maximum instantaneous current consumed while operating at v cc_max , t jmax and executing the worst case instruction mix. ?i cc sustained current values are defined as the maximum current consumed under tdp workload while operating at v cc_max , t jmax and executing the worst case real application instruction mix. i cc sustained current values or maximum current values cannot occur simultaneously on all interfaces. vcc_ckddr 1.8 v ddr2 / 1.5 v ddr3 clock system memory supply voltage with respect to v ss -0.3 4.0 v vcca_mpll 1.1 v system memory pll analog supply voltage with respect to v ss -0.3 1.21 v pci express* / intel ? sdvo / dmi / hdmi / dvi /dp interface vcc_exp (intel 82p45, 82p43, 82q45, 82q43, 82b43, 82g41 (g)mch only) 1.1 v pci express* and dmi supply voltage with respect to v ss -0.3 1.21 v vcc_exp (intel 82g45, 82g43 (g)mch only) 1.125 v pci express* and dmi supply voltage with respect to v ss -0.3 1.21 v vcca_exp 1.5 v pci express* analog supply voltage with respect to v ss -0.3 1.65 v vccapll_exp 1.1 v pci express* pll analog supply voltage with respect to v ss -0.3 1.21 v r, g, b / crt dac display interface (8 bit) vcca_dac 3.3 v display dac analog supply voltage with respect to v ss -0.3 3.63 v vccdq_crt 1.5 v display dac quiet digital supply voltage with respect to v ss -0.3 1.65 v vcca_dplla 1.1 v display pll a analog supply voltage with respect to v ss -0.3 1.21 v vcca_dpllb 1.1 v display pll b analog supply voltage with respect to v ss -0.3 1.21 v controller link interface vcc_cl 1.1 v supply voltage with respect to v ss -0.3 1.21 v cmos interface vcc3_3 3.3 v cmos supply voltage with respect to v ss -0.3 3.63 v notes: 1. possible damage to the (g)mch may occu r if the (g)mch temperature exceeds 150 c. intel does not ensure functionality for parts that have exceeded temperatures ab ove 150 c due to specification violation. table 46. absolute minimum and maximum ratings symbol parameter min max unit notes datasheet 557 electrical characteristics ?i cc idle current values are defined as the current consumed during idle state while operating at nominal vcc and nominal temperature. table 47. current consumption in acpi s0 state for intel ? 82g45, 82g43, 82b43, 82g41 gmch, and 82p45, 82p43 mch components symbol parameter signal names i cc sustained i cc max unit notes gmch mch gmch mch i vcc 1.1 v core supply current (discrete graphics) vcc n/a 9.637 n/a 9.8402 a i vcc 1.125 v core supply current (integrated graphics) vcc 14.162 n/a 17.984 n/a a i vcc_ddr2 ddr2 system memory interface (1.8 v) supply current vcc_ddr 1.163 1.104 1.328 1.328 a i vcc_ckddr2 ddr2 system memory clock interface (1.8 v) supply current vcc_ckddr 0.323 0.323 0.373 0.373 a i vcc_ddr3 ddr3 system memory interface (1.5 v) supply current vcc_ddr 0.899 0.640 1.963 1.9629 a i vcc_ckddr3 ddr3 system memory clock interface (1.5 v) supply current vcc_ckddr 0.251 0.251 0.288 0.2881 a i vcc_exp 1.1 v pci express* / intel ? sdvo and dmi supply current vcc_exp n/a 3.082 n/a 3.0821 a 1 i vcc_exp 1.125 v pci express* / intel ? sdvo and dmi supply current vcc_exp 1.345 n/a 1.345 n/a a 1 i vcc_cl 1.1 v controller supply current vcc_cl 3.529 4.126 4.060 4.6667 a i vtt_fsb system bus supply current vtt_fsb 0.418 0.418 0.914 0.914 a i vcca_exp 1.5 v pci express* / intel ? sdvo and dmi analog supply current vcca_exp 0.006 0.006 0.006 0.006 a i vcca_dac 3.3 v display dac analog supply current vcca_dac 0.074 0.012 0.074 0.0116 a i vcc3_3 3.3 v cmos supply current vcc3_3 0.014 0.014 0.014 0.014 a i vccdq_crt 1.5 v display quiet digital supply current vccdq_crt 0 0 0 0 a electrical characteristics 558 datasheet i vccapll_exp 1.1 v pci express* / intel ? sdvo and dmi pll analog supply current vccapll_exp 0.02 0.02 0.02 0.0201 a i vcca_hpll 1.1 v host pll supply current vcca_hpll 0.031 0.031 0.031 0.0313 a i vcca_dplla 1.1 v display pll a supply current vcca_dplla 0.059 0.007 0.059 0.007 a i vcca_dpllb 1.1 v display pll b supply current vcca_dpllb 0.059 0.007 0.059 0.007 a i vcca_mpll 1.1 v system memory pll analog supply current vcca_mpll 0.083 0.083 0.083 0.083 a notes: 1. the difference in current is due to different number of lanes. for the intel 82p45 and 82p43 mch, x16 lane width. for the 82g 45, 82g43, 82g41, 82b43gmch, x1 lane width. table 48. current consumption in acpi s0 state for intel ? 82q45 and 82q43 components symbol parameter signal names i cc sustained i cc max i cc idle unit notes i vcc 1.1 v core supply current (integrated graphics) vcc 11.8 15.4 2.078 a i vcc_ddr2 ddr2 system memory interface (1.8 v) supply current vcc_ddr 1.163 1.328 0.204 a i vcc_ckddr2 ddr2 system memory clock interface (1.8 v) supply current vcc_ckddr 0.324 0.373 0.293 a i vcc_ddr3 ddr3 system memory interface (1.5 v) supply current vcc_ddr 0.879 1.571 0.130 a i vcc_ckddr3 ddr3 system memory clock interface (1.5 v) supply current vcc_ckddr 0.223 0.257 0.179 a i vcc_exp 1.1 v pci express* / intel ? sdvo and dmi supply current vcc_exp 1.345 1.345 0.196 a i vcc_cl 1.1 v controller supply current vcc_cl 2.491 3 1.822 a i vtt_fsb system bus supply current vtt_fsb 0.418 0.914 n/a a table 47. current consumption in acpi s0 state for intel ? 82g45, 82g43, 82b43, 82g41 gmch, and 82p45, 82p43 mch components symbol parameter signal names i cc sustained i cc max unit notes gmch mch gmch mch datasheet 559 electrical characteristics ta b l e 4 9 shows the maximum power consumptio n for the intel 82q45 gmch in the acpi s3, s4, and s5 states with intel active management technology support. platforms that use intel active manageme nt technology will keep dram memory powered in s4 and s5. current consumption used by the (g)mch will vary between the "idle" case and the "max" case, depending on activity on the intel management engine. for the majority of the time, the intel management engine will be in the "idle" state. it is unknown if commercial software manageme nt applications will be able to generate this level of power consumption i vcca_exp 1.5 v pci express* / intel ? sdvo and dmi analog supply current vcca_exp 0.006 0.006 n/a a i vcca_dac 3.3 v display dac analog supply current vcca_dac 0.074 0.074 n/a a i vcc3_3 3.3 v cmos supply current vcc3_3 0.014 0.014 n/a a i vccdq_crt 1.5 v display quiet digital supply current vccdq_crt 0 0 n/a a i vccapll_exp 1.1 v pci express* / intel ? sdvo and dmi pll analog supply current vccapll_e xp 0.02 0.02 n/a a i vcca_hpll 1.1 v host pll supply current vcca_hpll 0.031 0.031 n/a a i vcca_dplla 1.1 v display pll a supply current vcca_dpll a 0.059 0.059 n/a a i vcca_dpllb 1.1 v display pll b supply current vcca_dpll b 0.059 0.059 n/a a i vcca_mpll 1.1 v system memory pll analog supply current vcca_mpll 0.083 0.083 n/a a table 48. current consumption in acpi s0 state for intel ? 82q45 and 82q43 components symbol parameter signal names i cc sustained i cc max i cc idle unit notes table 49. current consumption in s3, s4, s5 with intel ? active management technology operation (intel ? 82q45 gmch only) symbol parameter signal names idle max unit notes i mch_cl 1.1 v supply current for (g)mch with intel amt vcc_cl 2.014 2.389 a i ddr2_platform ddr2 system memory interface (1.8 v) supply current in standby states with intel amt vcc_ddr, vcc_ckddr 0.17 0.19 a i ddr3_platform ddr3 system memory interface (1.5 v) supply current in standby states with intel amt vcc_ddr, vcc_ckddr 0.054 0.092 a electrical characteristics 560 datasheet 14.3 (g)mch buffer supply and dc characteristics 14.3.1 i/o buffer supply voltages the i/o buffer supply voltage is measured at the (g)mch package pins. the tolerances shown in ta b l e 5 0 are inclusive of all noise from dc up to 20 mhz. in the lab, the voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of 3 db/decade above 20 mhz under all operating conditions. ta b l e 5 0 indicates which supplies are connected directly to a voltage regulator or to a filtered voltage rail. for voltages that ar e connected to a filter, they should me measured at the input of the filter. if the recommended platform decoupling guidelines cannot be met, the system designer will have to make tradeoffs betwee n the voltage regulator output dc tolerance and the decoupling performance of the capaci tor network to stay within the voltage tolerances listed in ta b l e 5 0 . table 50. i/o buffer supply voltage symbol parameter min nom max unit notes vcc_ddr ddr2 i/o supply voltage 1.71 1.8 1.89 v ddr3 i/o supply voltage 1.425 1.5 1.575 v vcc_ckddr ddr2 clock supply voltage 1.71 1.8 1.89 v 3 ddr3 clock supply voltage 1.425 1.5 1.575 v vcc_exp (intel 82p45, 82p43, 82q45, 82q43, 82b43, 82g41 gmch) sdvo, pci express* supply voltage 1.045 1.1 1.155 v vcc_exp (intel 82g45, 82g43 gmch) sdvo, pci express* supply voltage 1.095 1.125 1.155 v vcca_exp sdvo, pci express* anal og supply voltage 1.425 1.5 1.575 v 3 vtt_fsb 1.2 v system bus input supply voltage 1.14 1.2 1.26 v vcc (intel 82p45, 82p43 mch, 82q45, 82q43, 82b43, 82g41 gmch) (g)mch core supply voltage 1.045 1.1 1.155 v vcc (intel 82g45, 82g43 gmch) gmch core supply voltage 1.095 1.125 1.155 v vcc_cl controller supply voltage 1.045 1.1 1.155 v vcc3_3 cmos supply voltage 3.135 3.3 3.465 v datasheet 561 electrical characteristics vcca_dac display dac analog supply voltage 3.135 3.3 3.465 v 1 vccdq_crt display quiet digital supply voltage 1.425 1.5 1.575 v 2 vccapll_exp, vccdppl_exp, vcca_dplla, vcca_dpllb, vcca_hpll, vccd_hpll, vcca_mpll various pll?s analog supply voltages 1.045 1.1 1.155 v 3, 4 notes: 1. vcca_dac voltage tolerance should only be measured when the dac is turned on and at a stable resolution setting. any noise on the dac during power on or display resolution changes do not impact the circuit. 2. the vccdq_crt can also operate at a nominal 1.8 v 5% input vo ltage. only the 1.5 v nominal vo ltage setting will be validated internally. 3. these rails are filtered from other voltage rails on the plat form and should be measured at the input of the filter. 4. the noise specifications for vcca_dplla, vcca_dpplb, vc ca_hpll, vccd_hpll and vcca_m pll are 50, 50, 70, 70 and 70 respectively in mvpp. table 50. i/o buffer supply voltage symbol parameter min nom max unit notes electrical characteristics 562 datasheet 14.3.2 general dc characteristics platform reference voltages at the top of ta b l e 5 1 are specified at dc only. v ref measurements should be made with respect to the supply voltage. table 51. dc characteristics symbol parameter min nom max unit notes reference voltages fsb_dvref fsb_accvref host data, address, and common clock signal reference voltages 0.635 x vtt_fsb ? 2% 0.635 x vtt_fsb 0.635 x vtt_fsb + 2% v fsb_swing host compensation reference voltage 0.25 x vtt_fsb ? 2% 0.25 x vtt_fsb 0.25 x vtt_fsb + 2% v cl_vref controller link reference voltage 0.3325 0.35 0.3675 v ddr_vref ddr2 reference voltage 0.85 0.9 0.95 v ddr_vref ddr3 reference voltage 0.70 0.75 0.80 v host interface v il_h host gtl+ input low voltage -0.072 0 (0.635 x vtt_fsb) ? 0.072 v v ih_h host gtl+ input high voltage (0.635 x vtt_fsb) + 0.072 vtt_fsb vtt_fsb + 0.072 v v ol_h host gtl+ output low voltage ?? (0.25 x vtt_fsb) + 0.072 v v oh_h host gtl+ output high voltage vtt_fsb ? 0.072 ?vtt_fsbv i ol_h host gtl+ output low current ?? vtt_fsbmax * (1 ? 0.25) / rtt min ma rtt min = 47.5 i leak_h host gtl+ input leakage current ??tbd a v ol < vpad< vtt_f sb c pad host gtl+ input capacitance 1.5 ? 2.5 pf c pckg host gtl+ input capacitance (common clock) tbd ? tbd pf ddr2 system memory interface v il(dc) ddr2 input low voltage ddr_vref ? 100 mv ddr_vref ? 100 mv ddr_vref ? 100 mv v v ih(dc) ddr2 input high voltage ddr_vref + 100 mv ddr_vref + 100 mv ddr_vref + 100 mv v v il(ac) ddr2 input low voltage ddr_vref ? 125 mv ddr_vref ? 125 mv ddr_vref ? 125 mv v v ih(ac) ddr2 input high voltage ddr_vref + 125 mv ddr_vref + 125 mv ddr_vref + 125 mv v v ol ddr2 output low voltage 0.6 0.64 0.67 v 1 datasheet 563 electrical characteristics v oh ddr2 output high voltage 1.45 1.54 1.62 v 1 i leak input leakage current <0.1 <0.1 <0.1 a 2 i leak input leakage current <0.1 <0.1 <0.1 a 3 c i/o dq/dqs/dqsb ddr2 input/ output pin capacitance 2.3 2.3 2.3 pf ddr3 system memory interface v il(dc) ddr3 input low voltage ddr_vref ? 100 mv ddr_vref ? 100 mv ddr_vref ? 100 mv v v ih(dc) ddr3 input high voltage ddr_vref + 100 mv ddr_vref + 100 mv ddr_vref + 100 mv v v il(ac) ddr3 input low voltage ddr_vref ? 125 mv ddr_vref ? 125 mv ddr_vref ? 125 mv v v ih(ac) ddr3 input high voltage ddr_vref + 125 mv ddr_vref + 125 mv ddr_vref + 125 mv v v ol ddr3 output low voltage 0.6 0.64 0.67 v 1 v oh ddr3 output high voltage 1.45 1.52 1.62 v 1 i leak input leakage current <0.1 <0.1 <0.1 a 2 i leak input leakage current <0.1 <0.1 <0.1 a 3 c i/o dq/dqs/dqsb ddr3 input/ output pin capacitance 2.3 2.3 2.3 pf 1.1 v pci express* interface 2.0 (includes pci express* / intel ? sdvo / dvi / hdmi /dp) v tx-diff p-p differential peak to peak output voltage 0.8 1.0 1.2 v 4 v tx_cm-acp ac peak common mode output voltage ??60mv z tx-diff-dc dc differential tx impedance 80 100 120 ? v rx-diff p-p differential peak to peak input voltage 0.175 ? 1.2 v 5 v rx_cm-acp ac peak common mode input voltage ?? 75@2.5 ghz 300@100 mhz mv hpd (hot plug detect) v il input low voltage ? ? 200 mv v ih input high voltage 600 ? mv input clocks v il input low voltage -0.30 0 ? v v ih input high voltage ? ? 1.15 v v cross(abs) absolute crossing voltage 0.300 ? 0.550 v 6, 7, 8 v cross(rel) range of crossing points ? ? 0.140 v c in input capacitance 1.0 ? 3.0 pf sdvo_ctrldata, sdvo_ctrlclk , ddpc_ctrldata, ddpc_ctrclk v il input low voltage ? ? 0.75 v v ih input high voltage 1.75 ? ? v table 51. dc characteristics symbol parameter min nom max unit notes electrical characteristics 564 datasheet i leak input leakage current ? ? 10 a c in input capacitance ? ? 10.0 pf i ol output low current (cmos outputs) ??7.8ma @ 50% swing i oh output high current (cmos outputs) -1 ? ? ma @ 50% swing v ol output low voltage (cmos outputs) ??0.4v v oh output high voltage (cmos outputs) 2.25 ? ? v crt_ddc_data, crt_ddc_clk v il input low voltage ? ? 0.3 * v ccp v v ih input high voltage 0.6 * v ccp ??v i leak input leakage current ? ? tbd a c in input capacitance ? ? 10.0 pf i ol output low current (cmos outputs) ???ma @ 50% swing i oh output high current (cmos outputs) ???ma @ 50% swing v ol output low voltage (cmos outputs) ? ? 0.4@3ma v v oh output high voltage (cmos outputs) ???v hda_bclk, hda_sdi v il input low voltage ? ? 0.4 * v ccp v v ih input high voltage 0.6 * v ccp ??v i leak input leakage current ? ? 10 a c in input capacitance ? ? 7.5 pf v ol output low voltage (cmos outputs) ? ? 0.10 * vcc v v oh output high voltage (cmos outputs) 0.9 * vcc ? ? v cl_data, cl_clk v il input low voltage ? vref ? 80mv ? v v ih input high voltage ? vref + 80mv ? v i leak input leakage current ? ? a c in input capacitance ? 5 ? pf i ol output low current (cmos outputs) ?~1?ma @v ol_ hi max table 51. dc characteristics symbol parameter min nom max unit notes datasheet 565 electrical characteristics i oh output high current (cmos outputs) 6.2 8 9.8 ma @v oh_ hi min v ol output low voltage (cmos outputs) ?0?v v oh output high voltage (cmos outputs) 0.62 0.8 0.98 v pwrok, cl_pwrok, rstin# v il input low voltage 1.05 1.081 1.122 v v ih input high voltage 1.93 2.011 2.093 v i leak input leakage current 50 75 120 a c in input capacitance 477.292 503.396 531.486 ff cl_rst# v il input low voltage vss ? vref ? 80 mv v v ih input high voltage vref + 80mv ? vcc v i leak input leakage current ? ? 20 a c in input capacitance ? ? 2.0 pf ich_syncb i ol output low current (cmos outputs) ??2.0ma @v ol_ hi max i oh output high current (cmos outputs) -2.0 ? ? ma @v oh_ hi min v ol output low voltage (cmos outputs) ? ? 0.33 v v oh output high voltage (cmos outputs) 2.97 ? ? v crt_hsync, crt_vsync i ol output low current (cmos outputs) ???ma @v ol_ hi max i oh output high current (cmos outputs) ???ma @v oh_ hi min v ol output low voltage (cmos outputs) 0 ? 0.5@ 8ma v v oh output high voltage (cmos outputs) 2.4 ? 8ma ? 3.6 v notes: 1. determined with 2x (g)mch buffer strength settings into a 50 to 0.5xvcc_ddr test load. 2. applies to pin to vcc or vss leakage current for the ddr_a_dq_63:0 and ddr_b_dq_63:0 signals. 3. applies to pin to pin leakage current between ddr_a_dq s_7:0, ddr_a_dqsb_7:0, ddr_b _dqs_7:0, and ddr_b_dqsb_7:0 signals. 4. specified at the measurement point into a timing and voltage compliance test load as shown in transmitter compliance eye diag ram of pci express* specification and meas ured over any 250 consecutive tx uls. 5. specified at the measurement point over any 250 consecutive uls. the test load shown in receiver compliance eye diagram of pc i express* spec should be used as the rx device when taking measurements. 6. crossing voltage defined as instan taneous voltage when rising edge of bclk0 equals falling edge of bclk1. 7. v havg is the statistical average of the vh measured by the oscilloscope. 8. the crossing point must meet the absolute and relative crossi ng point specifications simultan eously. refer to the appropriate processor datasheet for further information. table 51. dc characteristics symbol parameter min nom max unit notes electrical characteristics 566 datasheet 14.3.3 r, g, b / crt dac displa y dc characteristics (intel ? 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch only) 14.3.4 di/dt characteristics to decrease voltage regulator costs, design time and to improve voltage regulator efficiency, di/dt values can be used for these purposes. also, di/dt values can be used to understand how customer's voltage regulator (vr) feedback mechanism has to work to limit the noise within voltage tolerance specifications. for example, when a sudden current change (di/ dt) is seen by vr, it will not follow that demand, it will have some slow response. duri ng that time, its output voltage will tend to go low, if the response is not fast enough, they will violate voltage tolerance specifications. cost of vr is also a function of how fast the response time is, by having di/dt data, customers can hold dv in voltage tolerance specifications using minimum cost. two sets of di/dt values are provided: "at vr level: used to optimize vr "at package pin level: used to optimize motherboard edge capacitor table 52. r, g, b / crt dac display dc char acteristics: functional operating range (vcca_dac = 3.3 v 5%) parameter min typical max unit notes dac resolution ? 8 ? bits 1 notes: 1. measured at each r, g, b termination according to the vesa test procedure - evaluation of analog display graphics subsystems proposal (version 1, draf t 4, december 1, 2000). max luminance (full-scale) .665 .700 .770 v 1 , 2, 4 (white video level voltage) 2. max steady-state amplitude min luminance ? 0.000 ? v 1 , 3, 4 (black video level voltage) 3. min steady-state amplitude 4. defined for a double 75 ohm termination. lsb current 73.2 ? ua 4 ,5 5. set by external reference resistor value. integral linearity (inl) -1.0 ? +1.0 lsb 1 ,6 6. inl and dnl measured and calculated according to vesa video signal standards. differential linearity (dnl) -1.0 ? +1.0 lsb 1 , 6 video channel-channel voltage amplitude mismatch ?? 6% 7 7. max full-scale voltage difference among r, g, b outp uts (percentage of steady-state full-scale voltage). monotonicity ensured datasheet 567 electrical characteristics ta b l e 5 3 shows the simulated di/dt data at different level for main power rails. table 53. di/dt simulation data rail di/dt @ vr di/dt @ package pin vtt ~ 2ma/ns ~ 750 ma/ns vcc_ddr ~ 4ma/ns ~ 1.5 a/ns vcc ~ 2.8a/us ~ 6 a/us (vr design) ~ 4 a/100ns (edge cap) vcc_cl ~ 2.8a/us ~ 2 ma/us vcc_peg ~ 3.5ma/ns ~ 15 ma/ns vcc_dmi ~ 1ma/ns ~ 3.5 ma/ns electrical characteristics 568 datasheet datasheet 569 ballout and package specifications 15 ballout and package specifications this chapter details the (g)mch ba llout and package specifications. 15.1 ballout figure 18 , figure 19 , and figure 20 show the (g)mch ballout from a top of the package view. ta b l e 5 4 lists the ballout arranged alphabetically by signal name. note: notes for figure 18 , figure 19 , figure 20 , and ta b l e 5 4 . 1. balls that are listed as rsvd are reserved. 2. balls that are listed as nc are no connects. 3. analog display signals (crt_red, crt_redb, crt_green, crt_greenb, crt_blue, crt_blueb, crt_iref, crt_ hsync, crt_vsync, crt_ddc_clk, crt_ddc_data) and the sdvo_ctrlclk and sdvo_ctrldata signals are not used on the 82p45 and 82p42 mch. contact your intel field representative for proper termination of the corresponding balls. 4. for the 82q45, 82q43, 82b43, 82g45, 82g43, 82g41 gmch, the pci express and sdvo/hdmi signals are multiplexed. however, only the pci express signal name is included in the following ba llout figures and table. see section 2.8 for the signal name mapping. ballout and package specifications 570 datasheet figure 18. gmch ballout diagram (t op view left ? columns 45?31) 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 be rsvd nc vss vss ddr_b_ma _13 vcc_sm vss vcc_sm be bd nc vss vss ddr_b_o dt_3 ddr_b_cs b_3 ddr_b_cs b_1 vcc_sm ddr_b_o dt_0 ddr_b_w eb ddr_b_ra sb vcc_sm ddr_a_ma _4 ddr_a_ma _8 bd bc vss ddr_spu ddr_spd ddr_a_ma _0 ddr_b_o dt_1 ddr_b_ca sb ddr_a_ma _1 ddr_a_ma _3 bc bb ddr_vref ddr3_a_m a0 vcc_sm ddr_b_o dt_2 ddr_b_cs b_2 ddr_b_cs b_0 ddr_a_ma _2 ddr_a_ma _5 bb ba ddr_rpu vcc_sm ddr_a_ck b_0 ddr_a_ma _7 ba ay vss ddr_a_bs _1 ddr_rpd vcc_sm ddr_a_ck b_5 ddr_a_ck _0 ddr_b_ck b_2 ddr_b_ck _0 ddr_a_ma _6 ay aw nc ddr_a_ma _10 ddr_a_w eb ddr_b_d q_37 ddr_a_ck _5 ddr_b_ck _5 ddr_b_ck _2 ddr_b_ck b_0 ddr_b_ck b_1 aw av ddr_a_bs _0 vcc_sm ddr_a_ra sb ddr3_b_o dt3 ddr_b_d q_36 vss dd r_a_ck b_2 ddr_b_ck b_5 vss ddr_b_ck _1 av au ddr_a_cs b_2 ddr_a_cs b_0 ddr_a_ca sb ddr_b_d q_39 ddr_b_d q_38 ddr_b_d m_4 ddr_b_d q_33 ddr_a_ck _2 vss ddr_a_ck _3 ddr_b_ck b_3 au at vcc_sm ddr3_a_ web vss ddr_a_ck b_3 ddr_b_ck _3 at ar ddr_a_od t_2 ddr3_a_c sb1 ddr_a_od t_0 ddr_a_cs b_1 vss ddr_b_d qs_4 ddr_b_d qsb_4 ddr_b_d q_32 vss vss vss ar ap vss vcc_sm ddr_b_ck _4 ap an ddr_b_d q_45 ddr_b_d q_44 vss ddr_b_d q_35 vss ddr_b_d q_34 vss an am ddr_a_od t_1 ddr_a_cs b_3 ddr_a_ma _13 vcc_smcl k am al vss vss ddr_a_dq _36 ddr_a_dq _32 ddr_a_od t_3 ddr_b_d q_47 vss ddr_b_d m_5 ddr_b_d q_41 ddr_b_d q_40 ddr_b_d qsb_5 vcc_s mcl k vcc_smcl k al ak ddr_a_dq _37 ddr_a_dq _33 ddr_a_d m_4 ddr_b_d q_52 vss vss ddr_b_d q_46 ddr_b_d q_42 vss ddr_b_d qs_5 rsvd vcc_smcl k vcc_cl ak aj vss vss ddr_b_d q_53 vss ddr_b_d q_48 ddr_b_d q_49 vss ddr_b_d m_6 ddr_b_d q_43 rsvd vcc_cl vcc_cl aj ah ddr_a_dq _38 ddr_a_dq s_4 ddr_a_dq sb_4 ah ag vss ddr_a_dq _35 ddr_a_dq _34 ddr_a_dq _39 vcc_cl ag af ddr_a_dq _45 ddr_a_dq _40 ddr_a_dq _41 ddr_a_dq _44 vss ddr_b_d q_50 ddr_b_d qs_6 ddr_b_d qsb_6 vss ddr_b_d q_54 vss vcc_cl vcc_cl af ae ddr_a_d m_5 vss ddr_a_dq sb_5 vss ddr_b_d q_61 vss ddr_b_d q_51 ddr_b_d q_60 ddr_b_d q_55 vss vcc_cl vcc_cl vcc_cl ae ad ddr_a_dq _46 ddr_a_dq s_5 nc ddr_b_d q_56 vs s ddr_b_d q_57 ddr_b_d m_7 vss ddr_b_d qsb_7 vss vcc_cl vcc_cl vcc_cl ad ac vss ddr_a_dq _42 ddr_a_dq _43 ddr_a_dq _47 vcc_cl ac ab ddr_a_dq _53 ddr_a_dq _48 ddr_a_dq _52 ddr_b_d q_58 vss ddr_b_d q_63 ddr_b_d q_62 vss ddr_b_d qs_7 vss vcc_cl vcc_cl vcc_cl ab aa ddr_a_d m_6 vss ddr_a_dq _49 vss ddr_b_d q_59 vss fsb_ab_3 4 fsb_ab_3 5 fsb_ab_2 9 vss vcc_cl vcc_cl vcc_cl aa y ddr_a_dq _54 ddr_a_dq s_6 ddr_a_dq sb_6 ddr_a_dq _55 vss fsb_ab_3 3 fsb_ab_3 1 fsb_ab_2 7 vss fsb_ab_3 2 vcc_cl vcc_cl vcc_cl y wvss vss ddr_a_dq _50 ddr_a_dq _51 vcc_cl w v ddr_a_dq _60 ddr_a_dq _61 ddr_a_dq _56 v u ddr_a_dq _57 vss fsb_ab_2 5 vss fsb_ab_2 2 fsb_ab_3 0 vss fsb_ab_2 8 fsb_ab_2 4 vccd_h pl l nc rsvd u t ddr_a_dq s_7 ddr_a_dq sb_7 ddr_a_d m_7 vss fsb_adst bb_1 vss fsb_ab_2 3 fsb_ab_1 7 vss fsb_ab_2 6 vss vss vss t rvss ddr_a_dq _63 nc ddr_a_dq _62 ddr_a_dq _58 fsb_ab_2 1 vss fsb_ab_2 0 fsb_ab_1 8 fsb_ab_1 6 fsb_ab_1 9 rsvd rsvd r p ddr_a_dq _59 dprstpb slpb vss p n fsb_ab_1 4 fsb_ab_1 0 vss fsb_ab_1 2 vss fsb_ab_1 1 vss n m fsb_ab_1 5 vss fsb_db_2 5 m l fsb_rsb_ 1 fsb_ab_9 fsb_breq 0b fsb_trdy b vss fsb_ab_8 fsb_ab_4 fsb_ab_3 vss fsb_db_2 2 fsb_db_2 4 l kvss fsb_hitm b fsb_reqb _1 vss fsb_dstb pb_1 k jf s b _ b n r b fsb_drdy b fsb_adsb fsb_ab_1 3 fsb_adst bb_0 fsb_reqb _2 fsb_ab_5 vss fs b_db_1 7 fsb_db_2 1 fsb_dstb nb_1 j hfsb_hitb vss fsb_dbsy b fsb_lock b fsb_ab_7 vss fsb_bprib fsb_db_1 8 vss vss h g fsb_defe rb fsb_rsb_ 0 fsb_rsb_ 2 fsb_reqb _4 fsb_reqb _0 fsb_db_2 0 vss fsb_db_2 3 fsb_db_2 8 g f vss fsb_db_0 vss fsb_ab_6 fsb_db_9 fsb_db_1 9 fsb_db_5 0 fsb_dinv b_1 fsb_db_5 7 f ef s b _ d b _ 4 v s s fsb_db_1 6 vss e d fsb_db_2 fsb_db_6 vss fsb_db_1 2 fsb_db_1 4 fsb_db_5 3 fsb_dstb nb_3 fsb_db_5 4 d cvssfsb_db_1 fsb_reqb _3 fsb_db_3 fsb_dstb pb_0 fsb_db_1 3 fsb_db_5 1 fsb_dstb pb_3 c b nc vss fsb_db_5 fsb_db_7 fsb_dinv b_0 fsb_dstb nb_0 fsb_db_8 fsb_db_1 1 fsb_db_1 5 fsb_db_5 2 vss fsb_db_5 6 fsb_db_4 9 b a rsvd nc vss vss fsb_db_1 0 vss fsb_db_5 5 vss a 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 datasheet 571 ballout and package specifications figure 19. gmch ballout diagram (top view left ? columns 30?16) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 be vss vcc_sm vss vcc_sm vss vss ddr_b_ck e_2 be bd ddr_a_ma _9 vcc_sm ddr_a_ma _14 ddr_a_ck e_1 ddr_b_bs _0 vcc_sm ddr_b_ma _0 ddr_b_ma _3 ddr_b_ma _5 vcc_sm ddr_b_ma _9 ddr_b_ma _11 ddr_b_bs _2 vss ddr_a_dq _23 bd bc ddr_a_ma _11 ddr_a_bs _2 ddr_b_ma _10 ddr3_dra mrstb ddr_b_ma _6 ddr_b_ma _7 ddr_b_ck e_0 ddr_a_dq _18 bc bb ddr_a_ma _12 vss ddr_a_ck e_0 ddr_b_bs _1 vss ddr_b_ma _2 ddr_b_ma _1 ddr_b_ma _4 vss ddr_b_ma _8 ddr_b_ma _12 ddr_b_ck e_3 ddr_a_dq _19 bb ba ddr_a_ck e_2 vss ddr_b_ma _14 ba ay vss ddr_a_ck b_1 ddr_a_ck e_3 vss ddr_a_dq _27 ddr_a_dq _25 vss ddr_b_ck e_1 ddr_b_d q_16 vss ay aw vss ddr_a_ck _1 vss ddr_b_d q _28 vss vss ddr_a_dq _24 vss vss ddr_b_d q_21 aw av vss ddr_b_d q_27 ddr_b_d q_25 ddr_b_d m_3 ddr_a_dq _26 ddr_a_d m_3 vss ddr_b_d q_19 ddr_b_d q_17 vss av au vss ddr_b_d q_26 ddr_b_d qs_3 vss ddr_a_dq _31 vss ddr_a_dq _28 vss ddr_b_d m_2 ddr_b_d q_15 au at ddr_a_ck _4 vss ddr_b_d qsb_3 ddr_b_d q_24 vss ddr_a_dq sb_3 ddr_a_dq _29 ddr_b_d q_22 vss ddr_b_d q_11 at ar ddr_a_ck b_4 ddr_b_d q_31 vss ddr_b_d q_29 ddr_a_dq _30 ddr_a_dq s_3 ddr_b_d q_18 ddr_b_d qs_2 ddr_b_d qsb_2 vss ar ap ddr_b_ck b_4 vss ddr_b_d q_30 vss vss vss vss vss ddr_b_d q_20 ddr_b_d q_14 ap an rsvd rsvd vss vss vss vss vss ddr_b_d q_23 nc nc an am vcccml_d dr vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl am al vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_ cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl al ak vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_ cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl ak aj vcc_cl vcc_cl vcc_cl vss vcc vss vcc vss vcc vss vcc vcc vcc aj ah ah ag vcc_cl vcc vss vcc vss vcc vss vcc vss vcc vss vcc vcc ag af nc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc af ae nc vcc vcc vss vcc vss vcc vss vcc vss vcc vcc vcc ae ad nc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vcc ad ac nc vcc vcc vss vcc vss vcc vss vcc vss vcc vcc vcc ac ab vcc vcc vss vcc vss vcc vss vcc vss vcc vss vss vss ab aa vcc vcc vcc vss vcc vss vcc vss vcc vss vcc vss vss aa y vcc_cl vcc_cl vss vcc vss vcc vss vcc vss vcc vss vss vss y w nc vcc vcc vss vcc vss vcc vss vcc vss vcc vss vss w v v u rsvd vcc vcc vcc vcc vcc vcc vcc vcc vss vss vss vss u t vss vcc vcc vcc vcc vcc vcc vcc vcc vss vss vss vss t r vss vcc vcc vcc vcc vtt_fsb vtt_fsb vtt_fsb vtt_fsb vtt_fsb vss vss vss r p hpl_clkin n hpl_clkin p vss vss vtt_fsb vtt_fsb vtt_fsb vtt_fsb vss vss p n vss vss vss rsvd fsb_db_4 7 vtt_fsb vtt_fsb vtt_fsb xortest vss n m fsb_db_2 6 fsb_db_3 0 fsb_db_3 9 vss vss vtt_fsb vtt_fsb allztest rsvd rsvd m lvss fsb_db_3 7 vss fsb_db_3 5 fsb_db_4 5 vtt_fsb vtt_fsb vss itpm_enb vss l k fsb_db_2 9 vss fsb_db_3 6 fsb_dstb nb_2 vss vtt_fsb vtt_fsb vss vss rsvd k j fsb_db_2 7 fsb_db_3 2 fsb_db_3 8 fsb_dstb pb_2 fsb_db_4 6 vtt_fsb vtt_fsb rsvd cen rsvd j hvss fsb_db_3 4 fsb_db_4 0 vss fsb_db_4 4 vtt_fsb vtt_fsb vss exp_sm vss h g fsb_db_3 1 vss vss fsb_db_4 3 vss vtt_fsb vtt_fsb bscantes t vss bsel1 g fvss fsb_db_3 3 fsb_dinv b_2 fsb_db_4 1 fsb_db_4 2 vtt_fsb vtt_fsb dualx8_en able bsel0 vss f e fs b_db_6 2 vtt_fsb vcc3_3 e d fsb_dinv b_3 fsb_db_5 8 fsb_cpur stb vss vss vtt_fsb vtt_fsb vtt_fsb vss vcca_dpl la vcca_dac crt_gree n vss d c fsb_db_6 0 fsb_db_4 8 vtt_fsb vtt_fsb fsb_dvre f vcca_dpl lb crt_blue vss c b fsb_db_6 1 vss fsb_db_6 3 vss vtt_fsb vtt_fsb fsb_swin g fsb_accv ref vcca_hpl l vss vccdq_cr t vcca_dac crt_red vss vccapll_e xp b a fsb_db_5 9 vss vtt_fsb fsb_rcom p vcca_mpl l vss vcca_exp a 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ballout and package specifications 572 datasheet figure 20. gmch ballout diagram (t op view left ? columns 15?1) 1 51 41 31 21 11 0987654321 be vss ddr_a_d q_21 vss ddr_a_d q_13 ddr_a_d q_6 vss nc rsvd be bd ddr_a_d qs_2 ddr_a_d m_2 vss ddr_a_d q_10 ddr_a_d q_14 ddr_a_d m_1 vss ddr_a_d q_2 ddr_a_d q_7 ddr_a_d qsb_0 ddr_a_d q_1 vss nc bd bc ddr_a_d q_17 ddr_a_d q_20 ddr_a_d qsb_1 ddr_a_d q_12 ddr_a_d qs_0 ddr_a_d m_0 ddr_a_d q_0 vss bc bb ddr_a_d qsb_2 ddr_a_d q_16 ddr_a_d q_11 ddr_a_d qs_1 ddr_a_d q_8 ddr_a_d q_3 vss ddr_a_d q_4 bb ba ddr_a_d q_22 ddr_b_d q_2 vss ddr_a_d q_5 ba ay vss ddr_b_d q_8 ddr_a_d q_15 ddr_b_d q_7 ddr_a_d q_9 ddr_b_d m_0 cl_data cl_clk vss ay aw ddr_b_d q_10 ddr_b_d q_13 vss ddr_b_d qsb_0 ddr_b_d qs_0 ddr_b_d q_6 ddr_b_d q_1 vss cl_rstb aw av vss vss vss vss vss dd r_b_d q_0 vss hda_rstb vss hda_sdo av au ddr_b_d qsb_1 ddr_b_d q_12 ddr_b_d q_3 vss ddr_b_d q_5 ddr_b_d q_4 vss vss hda_bclk hda_sync hda_sdi au at ddr_b_d qs_1 vss vss vss vss at ar ddr_b_d m_1 vss vss vss vss vss jtag_tdi ddr3_dra m_pwrok pwrok vss vcc_hda ar ap ddr_b_d q_9 vcc_cl vcc_cl ap an cl_vref jtag_tck jtag_tdo jtag_tms cl_pwrok vss rstinb an am vcc_cl vcc_cl vcc_cl vcc_cl am al vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_ cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl vcc_cl al ak nc vcc_cl vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp ak aj vcc_cl vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp vcc_exp aj ah vss vss vss ah ag vcc_exp vss dmi_txn_ 3 vccavrm_ exp exp_rbia s ag af vcc_exp vcc_exp vss vss vss vss dmi_rxp_ 3 dmi_rxn_ 3 vss vss dmi_txp_ 3 vcc dmi_txn_ 2 af ae vcc_exp vcc_exp vss vss vss dmi_rxn_ 1 dmi_rxp_ 1 vss dmi_rxn_ 2 dmi_rxp_ 2 dmi_txn_ 1 dmi_txp_ 2 vss ae ad vcc_exp vcc_exp rsvd vss peg_rxn_ 15 peg_rxp_ 15 vss dmi_rxn_ 0 dmi_rxp_ 0 vss dmi_txp_ 1 vss dmi_txn_ 0 ad ac vcc_exp vss vcc dmi_txp_ 0 peg_txp_ 15 ac a b rsvd vcc_exp rsvd vss vss peg_rxp_ 13 peg_rxn_ 13 vss vss vss vss peg_rxp_ 14 peg_txn_ 15 ab aa vcc_exp vcc_exp vss vss vss peg_rxn_ 10 peg_rxp_ 10 vss peg_rxp_ 12 peg_rxn_ 12 peg_txp_ 14 peg_rxn_ 14 vss aa y vcc_exp vcc_exp vss vss vss vss vss exp_comp i exp_rcom po exp_icom po peg_txn_ 14 vss vss y w vcc_exp vss peg_txp_ 13 vss vss w v vcc peg_txn_ 13 peg_txn_ 12 v u vcc_exp vcc_exp vss vss vss peg_rxp_ 8 peg_rxn_ 8 vss peg_rxn_ 9 peg_rxp_ 9 peg_txp_ 12 vss u t rsvd rsvd vss vss vss vss vss vss vss vss vss vss peg_txp_ 11 t r rsvd rsvd vss vss peg_rxn_ 7 peg_rxp_ 7 vss peg_rxp_ 6 peg_rxn_ 6 vss peg_rxp_ 11 vss peg_txn_ 11 r pbsel2 peg_rxn_ 11 vcc peg_txp_ 10 p n vss vss peg_rxn_ 4 peg_rxp_ 4 vss peg_rxp_ 5 peg_rxn_ 5 n m cr t_ddc_ clk peg_txn_ 10 vss m l crt_ddc_ data rsvd rsvd vss vss vss peg_rxn_ 3 peg_rxp_ 3 vss vcc peg_txn_ 9 l k ich_sync b vss vss peg_txn_ 8 peg_txp_ 9 k jrsvd sdvo_ctr ldata ddpc_ctr lclk vss vss peg_rxn_ 2 peg_rxp_ 2 vss vss vss peg_txp_ 8 j h vss vss vss vss vss vss peg_rxp_ 1 vcc peg_txp_ 7 vss h grsvd sdvo_ctr lclk vss dpl_refs sclkinn dpl_refs sclkinp peg_rxn_ 0 peg_rxn_ 1 vss peg_txn_ 7 g f exp_slr crt_irtn ddpc_ctr ldata vcc vss peg_rxp_ 0 vss vss vss f e dpl_refc lkinp exp_clkn vss vss e d dpl_refc lkinn crt_hsyn c vss exp_clkp peg_txn_ 2 vss vss peg_txp_ 6 d c crt_vsyn c peg_txp_ 0 peg_txp_ 2 peg_txn_ 3 vss vss peg_txn_ 6 vss c bdac_iref nc vccdpll_ exp pe g_txn_ 0 vss peg_txn_ 1 peg_txp_ 3 peg_txp_ 4 peg_txn_ 4 peg_txn_ 5 peg_txp_ 5 rsvd b avss vss peg_txp_ 1 vss vss vss a 1 51 41 31 21 11 0987654321 ballout and package specifications datasheet 573 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] vtt_fsb a25 -66 -642.3 vtt_fsb b25 -66 -609.3 vtt_fsb b26 -99 -625.6 vtt_fsb c24 -33 -592.1 vtt_fsb c26 -99 -592.1 vtt_fsb d22 31 -560.6 vtt_fsb d23 0 -575.3 vtt_fsb d24 -31 -560.6 vtt_fsb e23 0 -547.7 vtt_fsb f21 70.5 -514.5 vtt_fsb f22 19.5 -514.5 vtt_fsb g21 70.5 -486.5 vtt_fsb g22 19.5 -486.5 vtt_fsb h21 70.5 -458.5 vtt_fsb h22 19.5 -458.5 vtt_fsb j21 70.5 -430.5 vtt_fsb j22 19.5 -430.5 vtt_fsb k21 70.5 -402.5 vtt_fsb k22 19.5 -402.5 vtt_fsb l21 70.5 -374.5 vtt_fsb l22 19.5 -374.5 vtt_fsb m21 70.5 -346.5 vtt_fsb m22 19.5 -346.5 vtt_fsb n20 121.5 -318.9 vtt_fsb n21 70.5 -318.9 vtt_fsb n22 19.5 -318.9 vtt_fsb p20 121.5 -290.9 vtt_fsb p21 70.5 -290.9 vtt_fsb p22 19.5 -290.9 vtt_fsb p24 -19.5 -290.9 vtt_fsb r20 109.2 -254.8 vtt_fsb r23 0 -254.8 vtt_fsb r24 -36.4 -254.8 vss b17 198 -609.3 vss a3 579.3 -642.3 vss a43 -579.3 -642.3 vss a6 527.9 -642.3 vss b44 -610.8 -610.8 vss bc1 642.3 579.3 vss bc45 -642.3 579.3 vss bd2 610.8 610.8 vss bd44 -610.8 610.8 vss be3 579.3 642.3 vss be43 -579.3 642.3 vss c1 642.3 -579.3 vss c45 -642.3 -579.3 vss f1 642.3 -527.9 vss a12 330 -642.3 vss a15 264 -642.3 vss a19 132 -642.3 vss a27 -132 -642.3 vss a31 -264 -642.3 vss a36 -396 -642.3 vss a40 -527.9 -642.3 vss aa1 642.3 -66 vss aa11 374.5 -70.5 vss aa12 346.5 -70.5 vss aa13 318.9 -70.5 vss aa20 109.2 -72.8 vss aa22 36.4 -72.8 vss aa24 -36.4 -72.8 vss aa26 -109.2 -72.8 vss aa34 -346.5 -70.5 vss aa38 -458.5 -70.5 vss aa40 -514.5 -70.5 vss aa44 -609.3 -66 vss aa8 458.5 -70.5 vss ab11 374.5 -19.5 vss ab12 346.5 -19.5 vss ab19 145.6 -36.4 vss ab21 72.8 -36.4 vss ab23 0 -36.4 vss ab25 -72.8 -36.4 vss ab27 -145.6 -36.4 vss ab34 -346.5 -19.5 vss ab36 -402.5 -19.5 vss ab39 -486.5 -19.5 vss ab4 560.6 -31 vss ab6 514.5 -19.5 vss ab7 486.5 -19.5 vss ab8 458.5 -19.5 vss ac20 109.2 0 vss ac22 36.4 0 vss ac24 -36.4 0 vss ac26 -109.2 0 vss ac45 -642.3 0 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 574 datasheet vss ac5 547.7 0 vss ad12 346.5 19.5 vss ad19 145.6 36.4 vss ad21 72.8 36.4 vss ad23 0 36.4 vss ad25 -72.8 36.4 vss ad27 -145.6 36.4 vss ad3 592.1 33 vss ad34 -346.5 19.5 vss ad36 -402.5 19.5 vss ad39 -486.5 19.5 vss ad6 514.5 19.5 vss ad9 430.5 19.5 vss ae1 642.3 66 vss ae11 374.5 70.5 vss ae20 109.2 72.8 vss ae22 36.4 72.8 vss ae24 -36.4 72.8 vss ae26 -109.2 72.8 vss ae34 -346.5 70.5 vss ae38 -458.5 70.5 vss ae40 -514.5 70.5 vss ae44 -609.3 66 vss ae8 458.5 70.5 vss af10 402.5 121.5 vss af11 374.5 121.5 vss af12 346.5 121.5 vss af13 318.9 121.5 vss af33 -318.9 121.5 vss af35 -374.5 121.5 vss af39 -486.5 121.5 vss af6 514.5 121.5 vss af7 486.5 121.5 vss ag19 145.6 145.6 vss ag21 72.8 145.6 vss ag23 0 145.6 vss ag25 -72.8 145.6 vss ag27 -145.6 145.6 vss ag45 -642.3 132 vss ag5 547.7 132 vss ah2 625.6 165 vss ah3 592.1 165 vss ah4 560.6 165 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] vss aj20 109.2 182 vss aj22 36.4 182 vss aj24 -36.4 182 vss aj26 -109.2 182 vss aj36 -402.5 172.5 vss aj39 -486.5 172.5 vss aj44 -609.3 198 vss aj45 -642.3 198 vss ak35 -374.5 223.5 vss ak38 -458.5 223.5 vss ak39 -486.5 223.5 vss al38 -458.5 274.5 vss al44 -608.8 264 vss al45 -642.3 264 vss an33 -321.4 321.4 vss an36 -402.5 321.5 vss an38 -458.5 321.5 vss an7 486.5 321.5 vss ap20 121.5 346.5 vss ap22 19.5 346.5 vss ap24 -19.5 346.5 vss ap29 -172.5 346.5 vss ap45 -642.3 330 vss ar10 401.3 369.5 vss ar11 357.9 357.9 vss ar16 223.5 374.5 vss ar26 -121.5 374.5 vss ar31 -274.5 374.5 vss ar33 -321.5 371.4 vss ar35 -357.9 357.9 vss ar39 -486.5 369.5 vss ar8 458.5 369.5 vss ar9 430.5 369.5 vss at1 642.3 396 vss at11 369.5 401.3 vss at13 321.5 402.5 vss at17 172.5 402.5 vss at2 608.8 396 vss at24 -19.5 402.5 vss at29 -172.5 402.5 ddr_a_ckb_3 at33 -321.5 402.5 vss at35 -369.5 401.3 vss au20 121.5 430.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 575 vss au22 19.5 430.5 vss au25 -70.5 430.5 vss au30 -223.5 430.5 vss au9 418 418 vss av13 321.5 458.5 vss av15 274.5 458.5 vss av16 223.5 458.5 vss av2 609.3 462 vss av21 70.5 458.5 vss av30 -223.5 458.5 vss av38 -462.5 462.5 vss av8 462.5 462.5 vss aw11 369.5 486.5 vss aw17 172.5 486.5 vss aw20 121.5 486.5 vss aw22 19.5 486.5 vss aw24 -19.5 486.5 vss aw26 -121.5 486.5 vss aw3 592 495 vss aw30 -223.5 486.5 vss ay1 642.3 527.9 vss ay16 223.5 514.5 vss ay21 70.5 514.5 vss ay25 -70.5 514.5 vss ay30 -223.5 514.5 vss ay45 -642.3 527.9 vss b21 66 -609.3 vss b27 -132 -608.8 vss b29 -198 -609.3 vss b34 -330 -609.3 vss ba23 0 547.7 vss ba5 544.9 544.9 vss bb21 64 559.1 vss bb25 -64 559.1 vss bb28 -165 560.6 vss bb6 523 576.3 vss bd12 330 609.3 vss bd17 198 609.3 vss bd8 462 609.3 vss be10 396 642.3 vss be15 264 642.3 vss be19 132 642.3 vss be21 66 642.3 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] vss be25 -66 642.3 vss be29 -198 642.3 vss be34 -330 642.3 vss be40 -527.9 642.3 ddr_a_dq_6 be6 527.9 642.3 vss c3 578.3 -578.3 vss c5 551 -589.9 peg_txn_3 c7 495 -592 vss d11 363 -560.6 vss d16 231 -560.6 vss d21 64 -559.1 vss d25 -64 -559.1 vss d26 -99 -560.6 vss d39 -492 -560.6 vss d6 523 -576.3 vss d7 492 -560.6 peg_txn_2 d8 460.5 -559.1 vss e3 589.9 -551 vss e31 -264 -547.7 vss e41 -544.9 -544.9 vss e5 544.9 -544.9 vss f16 223.5 -514.5 vss f2 609 -525.8 vss f30 -223.5 -514.5 vss f4 576.3 -523 vss f42 -576.3 -523 vss f45 -642.3 -527.9 vss f8 465.5 -526.9 vss g11 369.5 -486.5 vss g17 172.5 -486.5 vss g24 -19.5 -486.5 vss g26 -121.5 -486.5 vss g29 -172.5 -486.5 vss g3 592 -495 vss g35 -369.5 -486.5 vss h1 642.3 -463.2 vss h11 369.5 -458.5 vss h13 321.5 -458.5 vss h15 274.5 -458.5 vss h16 223.5 -458.5 vss h20 121.5 -458.5 vss h25 -70.5 -458.5 vss h30 -223.5 -458.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 576 datasheet vss h31 -274.5 -458.5 vss h33 -321.5 -458.5 vss h38 -462.5 -462.5 vss h44 -609.3 -462 vss h7 497.4 -463 vss h8 462.5 -462.5 vss h9 417.5 -458.5 vss j3 592.1 -429 vss j37 -418 -418 vss j4 564.5 -429 vss j5 539.1 -439.8 vss j8 458.5 -417.5 vss j9 418 -418 vss k13 321.5 -402.5 vss k17 172.5 -402.5 vss k20 121.5 -402.5 vss k24 -19.5 -402.5 vss k29 -172.5 -402.5 vss k33 -321.5 -402.5 vss k45 -642.3 -396 vss l10 401.3 -369.5 vss l16 223.5 -374.5 vss l20 121.5 -374.5 vss l26 -121.5 -374.5 vss l30 -223.5 -374.5 vss l35 -357.9 -357.9 vss l39 -486.5 -369.5 vss l4 560.6 -363 vss l8 458.5 -369.5 vss l9 430.5 -369.5 vss m1 642.3 -330 vss m24 -19.5 -346.5 vss m25 -70.5 -346.5 vss m44 -609.3 -330 vss n11 371.4 -321.5 vss n13 321.4 -321.4 vss n26 -121.5 -318.9 vss n29 -172.5 -318.9 vss n33 -321.4 -321.4 vss n36 -402.5 -321.5 vss n38 -458.5 -321.5 vss n8 458.5 -321.5 vss p25 -70.5 -290.9 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] vss p26 -121.5 -290.9 vss r11 374.5 -274.5 vss r12 346.5 -274.5 vss r2 608.8 -264 vss r38 -458.5 -274.5 vss r45 -642.3 -264 vss r5 547.7 -264 vss r8 458.5 -274.5 vss t10 402.5 -223.5 vss t11 374.5 -223.5 vss t12 346.5 -223.5 vss t13 318.9 -223.5 vss t3 592.1 -231 vss t35 -374.5 -223.5 vss t38 -458.5 -223.5 vss t4 560.6 -231 vss t40 -514.5 -223.5 vss t6 514.5 -223.5 vss t7 486.5 -223.5 vss t8 458.5 -223.5 vss t9 430.5 -223.5 vss u1 642.3 -198 vss u11 374.5 -172.5 vss u12 346.5 -172.5 vss u13 318.9 -172.5 vss u36 -402.5 -172.5 vss u39 -486.5 -172.5 vss u44 -609.3 -198 vss u8 458.5 -172.5 vss w1 642.3 -132 vss w2 608.8 -132 vss w20 109.2 -145.6 vss w22 36.4 -145.6 vss w24 -36.4 -145.6 vss w26 -109.2 -145.6 vss w45 -642.3 -132 vss w5 547.7 -132 vss y10 402.5 -121.5 vss y11 374.5 -121.5 vss y12 346.5 -121.5 vss y13 318.9 -121.5 vss y19 145.6 -109.2 vss y2 625.6 -99 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 577 vss y21 72.8 -109.2 vss y23 0 -109.2 vss y25 -72.8 -109.2 vss y27 -145.6 -109.2 vss y3 592.1 -99 vss y35 -374.5 -121.5 vss y39 -486.5 -121.5 vss y9 430.5 -121.5 vcc_cl aa31 -254.8 -72.8 vcc_cl ab31 -254.8 -36.4 vcc_cl ac31 -254.8 0 vcc_cl ad31 -254.8 36.4 vcc_cl ae31 -254.8 72.8 vcc_cl af31 -254.8 109.2 vcc_cl ag30 -218.4 145.6 vcc_cl ag31 -254.8 145.6 vcc_cl aj30 -218.4 182 vcc_cl aj31 -254.8 182 vcc_cl ak16 218.4 218.4 vcc_cl ak17 182 218.4 vcc_cl ak19 145.6 218.4 vcc_cl ak20 109.2 218.4 vcc_cl ak21 72.8 218.4 vcc_cl ak22 36.4 218.4 vcc_cl ak23 0 218.4 vcc_cl ak24 -36.4 218.4 vcc_cl ak25 -72.8 218.4 vcc_cl ak26 -109.2 218.4 vcc_cl ak27 -145.6 218.4 vcc_cl ak29 -182 218.4 vcc_cl ak30 -218.4 218.4 vcc_cl al1 642.3 264 vcc_cl al10 402.5 274.5 vcc_cl al11 374.5 274.5 vcc_cl al12 346.5 274.5 vcc_cl al14 290.5 269.3 vcc_cl al15 254.8 254.8 vcc_cl al16 218.4 254.8 vcc_cl al17 182 254.8 vcc_cl al19 145.6 254.8 vcc_cl al2 608.8 264 vcc_cl al20 109.2 254.8 vcc_cl al21 72.8 254.8 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] vcc_cl al22 36.4 254.8 vcc_cl al23 0 254.8 vcc_cl al24 -36.4 254.8 vcc_cl al25 -72.8 254.8 vcc_cl al26 -109.2 254.8 vcc_cl al27 -145.6 254.8 vcc_cl al29 -182 254.8 vcc_cl al4 575.3 264 vcc_cl al5 547.7 264 vcc_cl al6 514.5 274.5 vcc_cl al7 486.5 274.5 vcc_cl al8 458.5 274.5 vcc_cl al9 430.5 274.5 vcc_cl am2 625.6 297 vcc_cl am3 592.1 297 vcc_cl am4 560.6 297 vcc_cl ap1 642.3 330 vcc_cl ap2 609.3 330 vcc_cl w31 -254.8 -145.6 vcc_cl y31 -254.8 -109.2 vcc_cl y29 -182 -109.2 vcc_cl y30 -218.4 -109.2 vccdq_crt b20 99 -625.6 vccdpll_exp b12 330 -609.3 vccd_hpll u33 -318.9 -172.5 vcccml_ddr am30 -223.5 290.9 vcc_smclk ak32 -290.9 223.5 vcc_smclk al31 -254.8 254.8 vcc_smclk al32 -290.5 269.3 vcc_smclk am31 -269.3 290.5 vccavrm_exp ag2 608.8 132 vccapll_exp b16 231 -625.6 vcc_cl aj27 -145.6 182 vcc_cl aj29 -182 182 vcca_exp a17 198 -642.3 vcca_mpll a21 66 -642.3 vcca_hpll b22 33 -625.6 vcc_cl aa32 -290.9 -70.5 vcc_cl aa33 -318.9 -70.5 vcc_cl ab32 -290.9 -19.5 vcc_cl ab33 -318.9 -19.5 vcc_cl ad32 -290.9 19.5 vcc_cl ad33 -318.9 19.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 578 datasheet vcc_cl ae32 -290.9 70.5 vcc_cl ae33 -318.9 70.5 vcc_cl af32 -290.9 121.5 vcc_cl aj32 -290.9 172.5 vcc_cl ak31 -254.8 218.4 vcc_cl al30 -218.4 254.8 vcc_cl am15 269.3 290.5 vcc_cl am16 223.5 290.9 vcc_cl am17 172.5 290.9 vcc_cl am20 121.5 290.9 vcc_cl am21 70.5 290.9 vcc_cl am22 19.5 290.9 vcc_cl am24 -19.5 290.9 vcc_cl am25 -70.5 290.9 vcc_cl am26 -121.5 290.9 vcc_cl am29 -172.5 290.9 vcc_cl y32 -290.9 -121.5 vcc_cl y33 -318.9 -121.5 vcca_dac b19 132 -608.8 vcca_dac d19 132 -575.3 vcca_dpllb c20 99 -592.1 vcca_dplla d20 99 -560.6 vcc_exp aa14 290.9 -70.5 vcc_exp aa15 254.8 -72.8 vcc_exp ab14 290.9 -19.5 vcc_exp ac15 254.8 0 vcc ac4 575.3 0 vcc_exp ad14 290.9 19.5 vcc_exp ad15 254.8 36.4 vcc_exp ae14 290.9 70.5 vcc_exp ae15 254.8 72.8 vcc_exp af14 290.9 121.5 vcc_exp af15 254.8 109.2 vcc af3 592.1 99 vcc_exp ag15 254.8 145.6 vcc_exp aj10 402.5 172.5 vcc_exp aj11 374.5 172.5 vcc_exp aj12 346.5 172.5 vcc_exp aj13 318.9 172.5 vcc_exp aj14 290.9 172.5 vcc_exp aj6 514.5 172.5 vcc_exp aj7 486.5 172.5 vcc_exp aj8 458.5 172.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] vcc_exp aj9 430.5 172.5 vcc_exp ak10 402.5 223.5 vcc_exp ak11 374.5 223.5 vcc_exp ak12 346.5 223.5 vcc_exp ak13 318.9 223.5 vcc_exp ak6 514.5 223.5 vcc_exp ak7 486.5 223.5 vcc_exp ak8 458.5 223.5 vcc_exp ak9 430.5 223.5 vcc f9 417.5 -520.5 vcc h4 559.1 -460.5 vcc l3 592.1 -363 vcc p3 592.1 -297 vcc_exp u14 290.9 -172.5 vcc_exp u15 254.8 -182 vcc v4 560.6 -165 vcc_exp w15 254.8 -145.6 vcc_exp y14 290.9 -121.5 vcc_exp y15 254.8 -109.2 vcc_cl aj15 254.8 182 vcc_cl ak14 290.9 223.5 vcc3_3 e19 132 -547.7 vcc_exp aj1 642.3 198 vcc_exp aj2 609.3 198 vcc_exp ak2 625.6 231 vcc_exp ak3 592.1 231 vcc_exp ak4 560.6 231 vcc_sm ap44 -609.3 330 vcc_sm at45 -642.3 396 vcc_sm av44 -609.3 462 vcc_sm ay40 -525.3 525.3 vcc_sm ba41 -544.9 544.9 vcc_sm bb39 -492 560.6 vcc_sm bd21 66 609.3 vcc_sm bd25 -66 609.3 vcc_sm bd29 -198 609.3 vcc_sm bd34 -330 609.3 vcc_sm bd38 -462 609.3 vcc_sm be23 0 642.3 vcc_sm be27 -132 642.3 vcc_sm be31 -264 642.3 vcc_sm be36 -396 642.3 vcc_hda ar2 625.6 363 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 579 vss aa16 218.4 -72.8 vss aa17 182 -72.8 vcc aa19 145.6 -72.8 vcc aa21 72.8 -72.8 vcc aa23 0 -72.8 vcc aa25 -72.8 -72.8 vcc aa27 -145.6 -72.8 vcc aa29 -182 -72.8 vcc aa30 -218.4 -72.8 vss ab16 218.4 -36.4 vss ab17 182 -36.4 vcc ab20 109.2 -36.4 vcc ab22 36.4 -36.4 vcc ab24 -36.4 -36.4 vcc ab26 -109.2 -36.4 vcc ab29 -182 -36.4 vcc ab30 -218.4 -36.4 vcc ac16 218.4 0 vcc ac17 182 0 vcc ac19 145.6 0 vcc ac21 72.8 0 vcc ac23 0 0 vcc ac25 -72.8 0 vcc ac27 -145.6 0 vcc ac29 -182 0 vcc ad16 218.4 36.4 vcc ad17 182 36.4 vcc ad20 109.2 36.4 vcc ad22 36.4 36.4 vcc ad24 -36.4 36.4 vcc ad26 -109.2 36.4 vcc ad29 -182 36.4 vcc ae16 218.4 72.8 vcc ae17 182 72.8 vcc ae19 145.6 72.8 vcc ae21 72.8 72.8 vcc ae23 0 72.8 vcc ae25 -72.8 72.8 vcc ae27 -145.6 72.8 vcc ae29 -182 72.8 vcc af16 218.4 109.2 vcc af17 182 109.2 vcc af19 145.6 109.2 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] vcc af20 109.2 109.2 vcc af21 72.8 109.2 vcc af22 36.4 109.2 vcc af23 0 109.2 vcc af24 -36.4 109.2 vcc af25 -72.8 109.2 vcc af26 -109.2 109.2 vcc af27 -145.6 109.2 vcc af29 -182 109.2 vcc ag16 218.4 145.6 vcc ag17 182 145.6 vcc ag20 109.2 145.6 vcc ag22 36.4 145.6 vcc ag24 -36.4 145.6 vcc ag26 -109.2 145.6 vcc ag29 -182 145.6 vcc aj16 218.4 182 vcc aj17 182 182 vcc aj19 145.6 182 vcc aj21 72.8 182 vcc aj23 0 182 vcc aj25 -72.8 182 vss n16 223.5 -318.9 vss p16 223.5 -290.9 vss p17 172.5 -290.9 vss r16 218.4 -254.8 vss r17 182 -254.8 vss r19 145.6 -254.8 vcc r25 -72.8 -254.8 vcc r26 -109.2 -254.8 vcc r27 -145.6 -254.8 vcc r29 -182 -254.8 vss r30 -218.4 -254.8 vss t16 218.4 -218.4 vss t17 182 -218.4 vss t19 145.6 -218.4 vss t20 109.2 -218.4 vcc t21 72.8 -218.4 vcc t24 -36.4 -218.4 vcc t25 -72.8 -218.4 vcc t26 -109.2 -218.4 vcc t27 -145.6 -218.4 vcc t29 -182 -218.4 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 580 datasheet vss t30 -218.4 -218.4 vss u16 218.4 -182 vss u17 182 -182 vss u19 145.6 -182 vss u20 109.2 -182 vcc u21 72.8 -182 vcc u22 36.4 -182 vcc u23 0 -182 vcc u24 -36.4 -182 vcc u25 -72.8 -182 vcc u26 -109.2 -182 vcc u27 -145.6 -182 vcc u29 -182 -182 vss w16 218.4 -145.6 vss w17 182 -145.6 vcc w19 145.6 -145.6 vcc w21 72.8 -145.6 vcc w23 0 -145.6 vcc w25 -72.8 -145.6 vcc w27 -145.6 -145.6 vcc w29 -182 -145.6 nc w30 -218.4 -145.6 vss y16 218.4 -109.2 vss y17 182 -109.2 vcc y20 109.2 -109.2 vcc y22 36.4 -109.2 vcc y24 -36.4 -109.2 vcc y26 -109.2 -109.2 nc b14 297 -625.6 nc ak15 254.8 218.4 nc ae30 -218.4 72.8 nc af30 -218.4 109.2 nc ac30 -218.4 0 nc ad30 -218.4 36.4 sdvo_ctrldata j13 321.5 -430.5 sdvo_ctrlclk g13 321.5 -486.5 rsvd a45 -642.3 -642.3 rsvd b2 610.8 -610.8 rsvd be1 642.3 642.3 rsvd be45 -642.3 642.3 rstinb an6 520.5 321.5 pwrok ar4 560.6 363 slpb p42 -560.6 -297 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] rsvd l13 321.5 -371.4 dprstpb p43 -592.1 -297 rsvd l11 357.9 -357.9 peg_txp_9 k1 642.3 -396 peg_txp_8 j2 625.6 -429 peg_txp_7 h2 609.3 -462 peg_txp_6 d2 624 -553.6 peg_txp_5 b3 579.6 -605.9 peg_txp_4 b7 497.9 -623.9 vss a8 463.2 -642.3 peg_txn_1 b9 429 -625.6 peg_txp_15 ac1 642.3 0 peg_txp_14 aa4 559.1 -64 peg_txp_13 w4 575.3 -132 peg_txp_12 u2 609.3 -198 peg_txp_11 t2 625.6 -231 peg_txp_10 p2 625.6 -297 peg_txp_1 a10 396 -642.3 peg_txp_0 c11 363 -592.1 peg_txn_9 l2 625.6 -363 peg_txn_8 k2 608.8 -396 peg_txn_7 g2 623.9 -497.9 peg_txn_6 c2 605.9 -579.6 peg_txn_5 b4 553.6 -624 peg_txn_4 b6 525.8 -609 peg_txp_3 b8 462 -609.3 peg_txp_2 c9 429 -592.1 peg_txn_15 ab2 625.6 -33 peg_txn_14 y4 560.6 -99 peg_txn_13 v3 592.1 -165 peg_txn_12 v2 625.6 -165 peg_txn_11 r1 642.3 -264 peg_txn_10 m2 609.3 -330 vss b10 396 -608.8 peg_txn_0 b11 363 -625.6 peg_rxp_9 u6 514.5 -172.5 peg_rxp_8 u10 402.5 -172.5 peg_rxp_7 r9 430.5 -274.5 peg_rxp_6 r7 486.5 -274.5 peg_rxp_5 n7 486.5 -321.5 peg_rxp_4 n9 430.5 -321.5 peg_rxp_3 l6 520.5 -369.5 peg_rxp_2 j6 520.5 -417.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 581 peg_rxp_15 ad10 402.5 19.5 peg_rxp_14 ab3 592.1 -33 peg_rxp_13 ab10 402.5 -19.5 peg_rxp_12 aa7 486.5 -70.5 peg_rxp_11 r4 575.3 -264 peg_rxp_10 aa9 430.5 -70.5 peg_rxp_1 h6 526.9 -465.5 peg_rxp_0 f6 525.3 -525.3 peg_rxn_9 u7 486.5 -172.5 peg_rxn_8 u9 430.5 -172.5 peg_rxn_7 r10 402.5 -274.5 peg_rxn_6 r6 514.5 -274.5 peg_rxn_5 n6 520.5 -321.5 peg_rxn_4 n10 402.5 -321.5 peg_rxn_3 l7 486.5 -369.5 peg_rxn_2 j7 486.5 -417.5 peg_rxn_15 ad11 374.5 19.5 peg_rxn_14 aa2 609.3 -66 peg_rxn_13 ab9 430.5 -19.5 peg_rxn_12 aa6 514.5 -70.5 peg_rxn_11 p4 560.6 -297 peg_rxn_10 aa10 402.5 -70.5 peg_rxn_1 g4 560.6 -492 peg_rxn_0 g7 505.7 -505.7 itpm_enb l17 172.5 -374.5 exp_sm h17 172.5 -458.5 rsvd g15 274.5 -486.5 exp_slr f15 274.5 -514.5 rsvd k16 223.5 -402.5 xortest n17 172.5 -318.9 allztest m20 121.5 -346.5 bsel2 p15 269.3 -290.5 dualx8_enable f20 121.5 -514.5 rsvd j20 121.5 -430.5 rsvd j15 274.5 -430.5 rsvd m16 223.5 -346.5 rsvd j16 223.5 -430.5 bscantest g20 121.5 -486.5 cen j17 172.5 -430.5 rsvd m17 172.5 -346.5 bsel1 g16 223.5 -486.5 bsel0 f17 172.5 -514.5 nc a44 -610.8 -642.3 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] nc bd1 642.3 610.8 nc bd45 -642.3 610.8 nc be2 610.8 642.3 nc be44 -610.8 642.3 ddr_a_dqs_5 ad43 -592.1 33 nc an16 223.5 318.9 vss an26 -121.5 318.9 vss ap21 70.5 346.5 vss ap25 -70.5 346.5 vss ar13 321.5 371.4 vss ar3 592.1 363 vss au5 539.1 439.8 vss au6 520.5 417.5 vss av11 369.5 458.5 ddr_b_ckb_5 av35 -369.5 458.5 vss av6 526.9 465.5 vss av9 417.5 458.5 nc aw44 -623.9 497.9 vss bd43 -579.6 605.9 vss k11 369.5 -401.3 vss n30 -223.5 -318.9 vss p31 -269.3 -290.5 nc r42 -575.3 -264 vss t31 -254.8 -218.4 vss t32 -290.9 -223.5 vss t33 -318.9 -223.5 nc u32 -290.9 -172.5 vss w44 -608.8 -132 cl_vref an13 321.4 321.4 cl_rstb aw2 623.9 497.9 cl_data ay4 576.3 523 cl_clk ay2 609 525.8 cl_pwrok an8 458.5 321.5 nc b45 -642.3 -610.8 ich_syncb k15 274.5 -402.5 vtt_fsb r22 36.4 -254.8 vtt_fsb r21 72.8 -254.8 vss an22 19.5 318.9 vss an21 70.5 318.9 vcc t23 0 -218.4 vcc t22 36.4 -218.4 vss ae13 318.9 70.5 vss ae12 346.5 70.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 582 vss an24 -19.5 318.9 vss an25 -70.5 318.9 jtag_tms an9 430.5 321.5 jtag_tdo an10 402.5 321.5 jtag_tdi ar7 486.5 369.5 jtag_tck an11 371.4 321.5 rsvd u30 -218.4 -182 rsvd u31 -254.8 -182 rsvd r31 -254.8 -254.8 rsvd r32 -290.5 -269.3 hpl_clkinp p29 -172.5 -290.9 hpl_clkinn p30 -223.5 -290.9 fsb_trdyb l40 -520.5 -369.5 fsb_swing b24 -33 -625.6 fsb_rsb_2 g42 -560.6 -492 fsb_rsb_1 l44 -625.6 -363 fsb_rsb_0 g43 -592 -495 fsb_reqb_4 g39 -505.7 -505.7 fsb_reqb_3 c43 -578.3 -578.3 fsb_reqb_2 j39 -486.5 -417.5 fsb_reqb_1 k35 -369.5 -401.3 fsb_reqb_0 g38 -463 -497.4 fsb_rcomp a23 0 -642.3 rsvd n25 -70.5 -318.9 fsb_lockb h40 -526.9 -465.5 fsb_hitmb k44 -608.8 -396 fsb_hitb h45 -642.3 -463.2 fsb_dvref c22 33 -592.1 fsb_dstbpb_3 c32 -297 -592.1 fsb_dstbpb_2 j25 -70.5 -430.5 fsb_dstbpb_1 k31 -274.5 -402.5 fsb_dstbpb_0 c39 -495 -592 fsb_dstbnb_3 d32 -297 -560.6 fsb_dstbnb_2 k25 -70.5 -402.5 fsb_dstbnb_1 j31 -274.5 -430.5 fsb_dstbnb_0 b39 -497.9 -623.9 fsb_drdyb j43 -592.1 -429 fsb_dinvb_3 d30 -231 -560.6 fsb_dinvb_2 f26 -121.5 -514.5 fsb_dinvb_1 f33 -321.5 -520.5 fsb_dinvb_0 b40 -525.8 -609 fsb_deferb g44 -623.9 -497.9 fsb_dbsyb h42 -559.1 -460.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] fsb_db_9 f38 -465.5 -526.9 fsb_db_8 b38 -462 -609.3 fsb_db_7 b42 -553.6 -624 fsb_db_63 b28 -165 -625.6 fsb_db_62 e27 -132 -547.7 fsb_db_61 b30 -231 -625.6 fsb_db_60 c30 -231 -592.1 fsb_db_6 d40 -523 -576.3 fsb_db_59 a29 -198 -642.3 fsb_db_58 d28 -165 -560.6 fsb_db_57 f31 -274.5 -514.5 fsb_db_56 b32 -297 -625.6 fsb_db_55 a34 -330 -642.3 fsb_db_54 d31 -264 -575.3 fsb_db_53 d35 -363 -560.6 fsb_db_52 b35 -363 -625.6 fsb_db_51 c35 -363 -592.1 fsb_db_50 f35 -369.5 -520.5 fsb_db_5 b43 -579.6 -605.9 fsb_db_49 b31 -264 -608.8 fsb_db_48 c28 -165 -592.1 fsb_db_47 n24 -19.5 -318.9 fsb_db_46 j24 -19.5 -430.5 fsb_db_45 l24 -19.5 -374.5 fsb_db_44 h24 -19.5 -458.5 fsb_db_43 g25 -70.5 -486.5 fsb_db_42 f24 -19.5 -514.5 fsb_db_41 f25 -70.5 -514.5 fsb_db_40 h26 -121.5 -458.5 fsb_db_4 e43 -589.9 -551 fsb_db_39 m26 -121.5 -346.5 fsb_db_38 j26 -121.5 -430.5 fsb_db_37 l29 -172.5 -374.5 fsb_db_36 k26 -121.5 -402.5 fsb_db_35 l25 -70.5 -374.5 fsb_db_34 h29 -172.5 -458.5 fsb_db_33 f29 -172.5 -514.5 fsb_db_32 j29 -172.5 -430.5 fsb_db_31 g30 -223.5 -486.5 fsb_db_30 m29 -172.5 -346.5 fsb_db_3 c41 -551 -589.9 fsb_db_29 k30 -223.5 -402.5 fsb_db_28 g31 -274.5 -486.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 583 fsb_db_27 j30 -223.5 -430.5 fsb_db_26 m30 -223.5 -346.5 fsb_db_25 m31 -274.5 -346.5 fsb_db_24 l31 -274.5 -374.5 fsb_db_23 g33 -321.5 -486.5 fsb_db_22 l33 -321.5 -371.4 fsb_db_21 j33 -321.5 -430.5 fsb_db_20 g37 -417.5 -486.5 fsb_db_2 d44 -624 -553.6 fsb_db_19 f37 -417.5 -520.5 fsb_db_18 h35 -369.5 -458.5 fsb_db_17 j35 -369.5 -430.5 fsb_db_16 e37 -439.8 -539.1 fsb_db_15 b36 -396 -608.8 fsb_db_14 d37 -429 -564.5 fsb_db_13 c37 -429 -592.1 fsb_db_12 d38 -460.5 -559.1 fsb_db_11 b37 -429 -625.6 fsb_db_10 a38 -463.2 -642.3 fsb_db_1 c44 -605.9 -579.6 fsb_db_0 f44 -609 -525.8 fsb_cpurstb d27 -132 -575.3 fsb_breq0b l42 -560.6 -363 fsb_bprib h37 -417.5 -458.5 fsb_bnrb j44 -625.6 -429 fsb_adstbb_1 t39 -486.5 -223.5 fsb_adstbb_0 j40 -520.5 -417.5 fsb_adsb j42 -564.5 -429 fsb_accvref b23 0 -608.8 fsb_ab_9 l43 -592.1 -363 fsb_ab_8 l38 -458.5 -369.5 fsb_ab_7 h39 -497.4 -463 fsb_ab_6 f40 -525.3 -525.3 fsb_ab_5 j38 -458.5 -417.5 fsb_ab_4 l37 -430.5 -369.5 fsb_ab_35 aa36 -402.5 -70.5 fsb_ab_34 aa37 -430.5 -70.5 fsb_ab_33 y38 -458.5 -121.5 fsb_ab_32 y34 -346.5 -121.5 fsb_ab_31 y37 -430.5 -121.5 fsb_ab_30 u37 -430.5 -172.5 fsb_ab_3 l36 -401.3 -369.5 fsb_ab_29 aa35 -374.5 -70.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] fsb_ab_28 u35 -374.5 -172.5 fsb_ab_27 y36 -402.5 -121.5 fsb_ab_26 t34 -346.5 -223.5 fsb_ab_25 u40 -514.5 -172.5 fsb_ab_24 u34 -346.5 -172.5 fsb_ab_23 t37 -430.5 -223.5 fsb_ab_22 u38 -458.5 -172.5 fsb_ab_21 r39 -486.5 -274.5 fsb_ab_20 r37 -430.5 -274.5 fsb_ab_19 r34 -346.5 -274.5 fsb_ab_18 r36 -402.5 -274.5 fsb_ab_17 t36 -402.5 -223.5 fsb_ab_16 r35 -374.5 -274.5 fsb_ab_15 m45 -642.3 -330 fsb_ab_14 n40 -520.5 -321.5 fsb_ab_13 j41 -539.1 -439.8 fsb_ab_12 n37 -430.5 -321.5 fsb_ab_11 n35 -371.4 -321.5 fsb_ab_10 n39 -486.5 -321.5 rsvd ab13 318.9 -19.5 rsvd ad13 318.9 19.5 exp_rcompo y7 486.5 -121.5 exp_rbias ag1 642.3 132 rsvd ab15 254.8 -36.4 exp_icompo y6 514.5 -121.5 exp_compi y8 458.5 -121.5 exp_clkp d9 429 -564.5 exp_clkn e9 439.8 -539.1 nc an17 172.5 318.9 dpl_refssclkinp g8 463 -497.4 dpl_refssclkinn g9 417.5 -486.5 dpl_refclkinp e15 264 -547.7 dpl_refclkinn d15 264 -575.3 rsvd t14 290.9 -223.5 rsvd t15 254.8 -218.4 rsvd r14 290.5 -269.3 rsvd r15 254.8 -254.8 dmi_txp_3 af4 560.6 99 dmi_txp_2 ae2 609.3 66 dmi_txp_1 ad4 560.6 31 dmi_txp_0 ac2 608.8 0 dmi_txn_3 ag4 575.3 132 dmi_txn_2 af2 625.6 99 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 584 datasheet dmi_txn_1 ae4 559.1 64 dmi_txn_0 ad2 625.6 33 dmi_rxp_3 af9 430.5 121.5 dmi_rxp_2 ae6 514.5 70.5 dmi_rxp_1 ae9 430.5 70.5 dmi_rxp_0 ad7 486.5 19.5 dmi_rxn_3 af8 458.5 121.5 dmi_rxn_2 ae7 486.5 70.5 dmi_rxn_1 ae10 402.5 70.5 dmi_rxn_0 ad8 458.5 19.5 ddr3_dramrstb bc24 -33 592.1 ddr3_dram_pw rok ar6 520.5 369.5 ddr3_b_odt3 av40 -526.9 465.5 ddr3_a_web at44 -608.8 396 ddr3_a_ma0 bb40 -523 576.3 ddr3_a_csb1 ar43 -592.1 363 ddr_vref bb44 -624 553.6 ddr_spu bc44 -605.9 579.6 ddr_spd bc43 -578.3 578.3 ddr_rpu ba43 -589.9 551 ddr_rpd ay42 -576.3 523 rsvd ak33 -318.9 223.5 rsvd aj33 -318.9 172.5 ddr_b_web bd36 -396 608.8 ddr_b_rasb bd35 -363 625.6 ddr_b_odt_3 bd42 -553.6 624 ddr_b_odt_2 bb38 -460.5 559.1 ddr_b_odt_1 bc39 -495 592 ddr_b_odt_0 bd37 -429 625.6 ddr_b_ma_9 bd20 99 625.6 ddr_b_ma_8 bb20 99 560.6 ddr_b_ma_7 bc20 99 592.1 ddr_b_ma_6 bc22 33 592.1 ddr_b_ma_5 bd22 33 625.6 ddr_b_ma_4 bb22 31 560.6 ddr_b_ma_3 bd23 0 608.8 ddr_b_ma_2 bb24 -31 560.6 ddr_b_ma_14 ba19 132 547.7 ddr_b_ma_13 be38 -463.2 642.3 ddr_b_ma_12 bb19 132 575.3 ddr_b_ma_11 bd19 132 608.8 ddr_b_ma_10 bc26 -99 592.1 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ddr_b_ma_1 bb23 0 575.3 ddr_b_ma_0 bd24 -33 625.6 ddr_b_dqsb_7 ad35 -374.5 19.5 ddr_b_dqsb_6 af36 -402.5 121.5 ddr_b_dqsb_5 al34 -346.5 274.5 ddr_b_dqsb_4 ar37 -430.5 369.5 ddr_b_dqsb_3 at26 -121.5 402.5 ddr_b_dqsb_2 ar17 172.5 374.5 ddr_b_dqsb_1 au 15 274.5 430.5 ddr_b_dqsb_0 aw9 417.5 486.5 ddr_b_dqs_7 ab35 -374.5 -19.5 ddr_b_dqs_6 af37 -430.5 121.5 ddr_b_dqs_5 ak34 -346.5 223.5 ddr_b_dqs_4 ar38 -458.5 369.5 ddr_b_dqs_3 au26 -121.5 430.5 ddr_b_dqs_2 ar20 121.5 374.5 ddr_b_dqs_1 at15 274.5 402.5 ddr_b_dqs_0 aw8 463 497.4 ddr_b_dq_9 ap15 274.5 346.5 ddr_b_dq_8 ay13 321.5 520.5 ddr_b_dq_7 ay9 417.5 520.5 ddr_b_dq_63 ab38 -458.5 -19.5 ddr_b_dq_62 ab37 -430.5 -19.5 ddr_b_dq_61 ae39 -486.5 70.5 ddr_b_dq_60 ae36 -402.5 70.5 ddr_b_dq_6 aw7 505.7 505.7 ddr_b_dq_59 aa39 -486.5 -70.5 ddr_b_dq_58 ab40 -514.5 -19.5 ddr_b_dq_57 ad38 -458.5 19.5 ddr_b_dq_56 ad40 -514.5 19.5 ddr_b_dq_55 ae35 -374.5 70.5 ddr_b_dq_54 af34 -346.5 121.5 ddr_b_dq_53 aj40 -514.5 172.5 ddr_b_dq_52 ak40 -514.5 223.5 ddr_b_dq_51 ae37 -430.5 70.5 ddr_b_dq_50 af38 -458.5 121.5 ddr_b_dq_5 au8 458.5 417.5 ddr_b_dq_49 aj37 -430.5 172.5 ddr_b_dq_48 aj38 -458.5 172.5 ddr_b_dq_47 al39 -486.5 274.5 ddr_b_dq_46 ak37 -430.5 223.5 ddr_b_dq_45 an40 -520.5 321.5 ddr_b_dq_44 an39 -486.5 321.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 585 ddr_b_dq_43 aj34 -346.5 172.5 ddr_b_dq_42 ak36 -402.5 223.5 ddr_b_dq_41 al36 -402.5 274.5 ddr_b_dq_40 al35 -374.5 274.5 ddr_b_dq_4 au7 486.5 417.5 ddr_b_dq_39 au41 -539.1 439.8 ddr_b_dq_38 au40 -520.5 417.5 ddr_b_dq_37 aw39 -505.7 505.7 ddr_b_dq_36 av39 -497.4 463 ddr_b_dq_35 an37 -430.5 321.5 ddr_b_dq_34 an35 -371.4 321.5 ddr_b_dq_33 au38 -458.5 417.5 ddr_b_dq_32 ar36 -401.3 369.5 ddr_b_dq_31 ar29 -172.5 374.5 ddr_b_dq_30 ap26 -121.5 346.5 ddr_b_dq_3 au11 369.5 430.5 ddr_b_dq_29 ar25 -70.5 374.5 ddr_b_dq_28 aw25 -70.5 486.5 ddr_b_dq_27 av29 -172.5 458.5 ddr_b_dq_26 au29 -172.5 430.5 ddr_b_dq_25 av26 -121.5 458.5 ddr_b_dq_24 at25 -70.5 402.5 ddr_b_dq_23 an20 121.5 318.9 ddr_b_dq_22 at20 121.5 402.5 ddr_b_dq_21 aw16 223.5 486.5 ddr_b_dq_20 ap17 172.5 346.5 ddr_b_dq_2 ba9 439.8 539.1 ddr_b_dq_19 av20 121.5 458.5 ddr_b_dq_18 ar21 70.5 374.5 ddr_b_dq_17 av17 172.5 458.5 ddr_b_dq_16 ay17 172.5 514.5 ddr_b_dq_15 au16 223.5 430.5 ddr_b_dq_14 ap16 223.5 346.5 ddr_b_dq_13 aw13 321.5 486.5 ddr_b_dq_12 au13 321.5 430.5 ddr_b_dq_11 at16 223.5 402.5 ddr_b_dq_10 aw15 274.5 486.5 ddr_b_dq_1 aw4 560.6 492 ddr_b_dq_0 av7 497.4 463 ddr_b_dm_7 ad37 -430.5 19.5 ddr_b_dm_6 aj35 -374.5 172.5 ddr_b_dm_5 al37 -430.5 274.5 ddr_b_dm_4 au39 -486.5 417.5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ddr_b_dm_3 av25 -70.5 458.5 ddr_b_dm_2 au17 172.5 430.5 ddr_b_dm_1 ar15 274.5 374.5 ddr_b_dm_0 ay6 525.3 525.3 ddr_b_csb_3 bd40 -525.8 609 ddr_b_csb_2 bb37 -429 564.5 ddr_b_csb_1 bd39 -497.9 623.9 ddr_b_csb_0 bb35 -363 560.6 ddr_b_cke_3 bb18 165 560.6 ddr_b_cke_2 be17 198 642.3 ddr_b_cke_1 ay20 121.5 514.5 ddr_b_cke_0 bc18 165 592.1 vss au35 -369.5 430.5 ddr_b_ckb_4 ap30 -223.5 346.5 ddr_b_ckb_3 au31 -274.5 430.5 ddr_b_ckb_2 ay35 -369.5 520.5 ddr_b_ckb_1 aw31 -274.5 486.5 ddr_b_ckb_0 aw33 -321.5 486.5 ddr_b_ck_5 aw37 -417.5 486.5 ddr_b_ck_4 ap31 -274.5 346.5 ddr_b_ck_3 at31 -274.5 402.5 ddr_b_ck_2 aw35 -369.5 486.5 ddr_b_ck_1 av31 -274.5 458.5 ddr_b_ck_0 ay33 -321.5 520.5 ddr_b_casb bc37 -429 592.1 ddr_b_bs_2 bd18 165 625.6 ddr_b_bs_1 bb26 -99 560.6 ddr_b_bs_0 bd26 -99 625.6 rsvd an30 -223.5 318.9 rsvd an29 -172.5 318.9 ddr_a_web aw42 -560.6 492 ddr_a_rasb av42 -559.1 460.5 ddr_a_odt_3 al40 -514.5 274.5 ddr_a_odt_2 ar44 -625.6 363 ddr_a_odt_1 am44 -625.6 297 ddr_a_odt_0 ar42 -560.6 363 ddr_a_ma_9 bd30 -231 625.6 ddr_a_ma_8 bd31 -264 608.8 ddr_a_ma_7 ba31 -264 547.7 ddr_a_ma_6 ay31 -274.5 514.5 ddr_a_ma_5 bb31 -264 575.3 ddr_a_ma_4 bd32 -297 625.6 ddr_a_ma_3 bc32 -297 592.1 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 586 datasheet ddr_a_ma_2 bb32 -297 560.6 ddr_a_ma_14 bd28 -165 625.6 ddr_a_ma_13 am42 -560.6 297 ddr_a_ma_12 bb30 -231 560.6 ddr_a_ma_11 bc30 -231 592.1 ddr_a_ma_10 aw43 -592 495 ddr_a_ma_1 bc35 -363 592.1 ddr_a_ma_0 bc41 -551 589.9 ddr_a_dqsb_7 t43 -592.1 -231 ddr_a_dqsb_6 y42 -560.6 -99 ddr_a_dqsb_5 ae42 -559.1 64 ddr_a_dqsb_4 ah42 -560.6 165 ddr_a_dqsb_3 at22 19.5 402.5 ddr_a_dqsb_2 bb15 264 575.3 ddr_a_dqs_1 bb9 429 564.5 ddr_a_dqsb_0 bd4 553.6 624 ddr_a_dqs_7 t44 -625.6 -231 ddr_a_dqs_6 y43 -592.1 -99 nc ad42 -560.6 31 ddr_a_dqs_4 ah43 -592.1 165 ddr_a_dqs_3 ar22 19.5 374.5 ddr_a_dqs_2 bd15 264 608.8 ddr_a_dq_14 bd10 396 608.8 ddr_a_dqs_0 bc5 551 589.9 ddr_a_dm_1 bd9 429 625.6 ddr_a_dq_9 ay8 465.5 526.9 ddr_a_dq_2 bd7 497.9 623.9 ddr_a_dq_63 r44 -608.8 -264 ddr_a_dq_62 r41 -547.7 -264 ddr_a_dq_61 v43 -592.1 -165 ddr_a_dq_60 v44 -625.6 -165 ddr_a_dq_7 bd6 525.8 609 ddr_a_dq_59 p44 -625.6 -297 ddr_a_dq_58 r40 -514.5 -274.5 ddr_a_dq_57 u45 -642.3 -198 ddr_a_dq_56 v42 -560.6 -165 ddr_a_dq_55 y40 -514.5 -121.5 ddr_a_dq_54 y44 -625.6 -99 ddr_a_dq_53 ab44 -625.6 -33 ddr_a_dq_52 ab42 -560.6 -31 ddr_a_dq_51 w41 -547.7 -132 ddr_a_dq_50 w42 -575.3 -132 ddr_a_dq_5 ba3 589.9 551 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ddr_a_dq_49 aa42 -559.1 -64 ddr_a_dq_48 ab43 -592.1 -33 ddr_a_dq_47 ac41 -547.7 0 ddr_a_dq_46 ad44 -625.6 33 ddr_a_dq_45 af44 -625.6 99 ddr_a_dq_44 af40 -514.5 121.5 ddr_a_dq_43 ac42 -575.3 0 ddr_a_dq_42 ac44 -608.8 0 ddr_a_dq_41 af42 -560.6 99 ddr_a_dq_40 af43 -592.1 99 ddr_a_dq_4 bb2 624 553.6 ddr_a_dq_39 ag41 -547.7 132 ddr_a_dq_38 ah44 -625.6 165 ddr_a_dq_37 ak44 -625.6 231 ddr_a_dq_36 al42 -575.3 264 ddr_a_dq_35 ag44 -608.8 132 ddr_a_dq_34 ag42 -575.3 132 ddr_a_dq_33 ak43 -592.1 231 ddr_a_dq_32 al41 -547.7 264 ddr_a_dq_31 au24 -19.5 430.5 ddr_a_dq_30 ar24 -19.5 374.5 ddr_a_dq_12 bc7 495 592 ddr_a_dq_29 at21 70.5 402.5 ddr_a_dq_28 au21 70.5 430.5 ddr_a_dq_27 ay24 -19.5 514.5 ddr_a_dq_26 av24 -19.5 458.5 ddr_a_dq_25 ay22 19.5 514.5 ddr_a_dq_24 aw21 70.5 486.5 ddr_a_dq_23 bd16 231 625.6 ddr_a_dq_22 ba15 264 547.7 ddr_a_dq_16 bb14 297 560.6 ddr_a_dq_21 be12 330 642.3 ddr_a_dq_3 bb7 492 560.6 ddr_a_dq_19 bb16 231 560.6 ddr_a_dq_18 bc16 231 592.1 ddr_a_dm_2 bd14 297 625.6 ddr_a_dq_17 bc14 297 592.1 ddr_a_dq_10 bd11 363 625.6 ddr_a_dq_15 ay11 369.5 520.5 ddr_a_dq_8 bb8 460.5 559.1 ddr_a_dq_13 be8 463.2 642.3 ddr_a_dq_20 bc11 363 592.1 ddr_a_dq_11 bb11 363 560.6 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 587 ddr_a_dq_1 bd3 579.6 605.9 ddr_a_dq_0 bc2 605.9 579.6 ddr_a_dm_7 t42 -560.6 -231 ddr_a_dm_6 aa45 -642.3 -66 ddr_a_dm_5 ae45 -642.3 66 ddr_a_dm_4 ak42 -560.6 231 ddr_a_dm_3 av22 19.5 458.5 vss ay15 274.5 514.5 ddr_a_dqsb_1 bc9 429 592.1 ddr_a_dm_0 bc3 578.3 578.3 ddr_a_csb_3 am43 -592.1 297 ddr_a_csb_2 au44 -625.6 429 ddr_a_csb_1 ar40 -520.5 369.5 ddr_a_csb_0 au43 -592.1 429 ddr_a_cke_3 ay26 -121.5 514.5 ddr_a_cke_2 ba27 -132 547.7 ddr_a_cke_1 bd27 -132 608.8 ddr_a_cke_0 bb27 -132 575.3 ddr_a_ckb_5 ay38 -465.5 526.9 ddr_a_ckb_4 ar30 -223.5 374.5 ddr_a_ck_3 au33 -321.5 430.5 ddr_a_ckb_2 av3 7 -417.5 458.5 ddr_a_ckb_1 ay29 -172.5 514.5 ddr_a_ckb_0 ba37 -439.8 539.1 ddr_a_ck_5 aw38 -463 497.4 ddr_a_ck_4 at30 -223.5 402.5 vss av33 -321.5 458.5 ddr_a_ck_2 au37 -418 418 ddr_a_ck_1 aw29 -172.5 486.5 ddr_a_ck_0 ay37 -417.5 520.5 ddr_a_casb au42 -564.5 429 ddr_a_bs_2 bc28 -165 592.1 ddr_a_bs_1 ay44 -609 525.8 ddr_a_bs_0 av45 -642.3 463.2 ddpc_ctrldata f11 369.5 -520.5 ddpc_ctrlclk j11 369.5 -430.5 vss c16 231 -592.1 dac_iref b15 264 -608.8 crt_vsync c14 297 -592.1 crt_red b18 165 -625.6 crt_irtn f13 321.5 -520.5 crt_hsync d14 297 -560.6 crt_green d18 165 -560.6 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] crt_ddc_data l15 274.5 -374.5 crt_ddc_clk m15 274.5 -346.5 crt_blue c18 165 -592.1 hda_sync au3 592.1 429 hda_sdo av1 642.3 463.2 hda_sdi au2 625.6 429 hda_rstb av4 559.1 460.5 hda_bclk au4 564.5 429 ?a1 ?a11 ?a13 ?a14 ?a16 ?a18 ?a2 ?a20 ?a22 ?a24 ?a26 ?a28 ?a30 ?a32 ?a33 ?a35 ?a37 ?a39 ?a4 ?a41 ?a42 ?a5 ?a7 ?a9 ? aa18 ? aa28 ? aa3 ? aa41 ? aa43 ? aa5 ?ab1 ?ab18 ?ab28 ?ab41 ?ab45 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 588 datasheet ?a b 5 ?a c 1 0 ?a c 1 1 ?a c 1 2 ?a c 1 3 ?a c 1 4 ?a c 1 8 ?a c 2 8 ?a c 3 ?a c 3 2 ?a c 3 3 ?a c 3 4 ?a c 3 5 ?a c 3 6 ?a c 3 7 ?a c 3 8 ?a c 3 9 ?a c 4 0 ?a c 4 3 ?a c 6 ?a c 7 ?a c 8 ?a c 9 ?a d 1 ?a d 1 8 ?a d 2 8 ?a d 4 1 ?a d 4 5 ?a d 5 ?a e 1 8 ?a e 2 8 ?a e 3 ?a e 4 1 ?a e 4 3 ?a e 5 ?a f 1 ?a f 1 8 ?a f 2 8 ?a f 4 1 ?a f 4 5 ?a f 5 ?a g 1 0 ?a g 1 1 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?a g 1 2 ?a g 1 3 ?a g 1 4 ?a g 1 8 ?a g 2 8 ?a g 3 ?a g 3 2 ?a g 3 3 ?a g 3 4 ?a g 3 5 ?a g 3 6 ?a g 3 7 ?a g 3 8 ?a g 3 9 ?a g 4 0 ?a g 4 3 ?a g 6 ?a g 7 ?a g 8 ?a g 9 ?a h 1 ?a h 1 0 ?a h 1 1 ?a h 1 2 ?a h 1 3 ?a h 1 4 ?a h 1 5 ?a h 1 6 ?a h 1 7 ?a h 1 8 ?a h 1 9 ?a h 2 0 ?a h 2 1 ?a h 2 2 ?a h 2 3 ?a h 2 4 ?a h 2 5 ?a h 2 6 ?a h 2 7 ?a h 2 8 ?a h 2 9 ?a h 3 0 ?a h 3 1 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 589 ?a h 3 2 ?a h 3 3 ?a h 3 4 ?a h 3 5 ?a h 3 6 ?a h 3 7 ?a h 3 8 ?a h 3 9 ?a h 4 0 ?a h 4 1 ?a h 4 5 ?a h 5 ?a h 6 ?a h 7 ?a h 8 ?a h 9 ?a j 1 8 ?a j 2 8 ?a j 3 ?a j 4 ?a j 4 1 ?a j 4 2 ?a j 4 3 ?a j 5 ?a k 1 ?a k 1 8 ?a k 2 8 ?a k 4 1 ?a k 4 5 ?a k 5 ?a l 1 3 ?a l 1 8 ?a l 2 8 ?a l 3 ?a l 3 3 ?a l 4 3 ?a m 1 ?a m 1 0 ?a m 1 1 ?a m 1 2 ?a m 1 3 ?a m 1 4 ?a m 1 8 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?a m 1 9 ?a m 2 3 ?a m 2 7 ?a m 2 8 ?a m 3 2 ?a m 3 3 ?a m 3 4 ?a m 3 5 ?a m 3 6 ?a m 3 7 ?a m 3 8 ?a m 3 9 ?a m 4 0 ?a m 4 1 ?a m 4 5 ?a m 5 ?a m 6 ?a m 7 ?a m 8 ?a m 9 ?a n 1 ?a n 1 2 ?a n 1 4 ?a n 1 5 ?a n 1 8 ?a n 1 9 ?a n 2 ?a n 2 3 ?a n 2 7 ?a n 2 8 ?a n 3 ?a n 3 1 ?a n 3 2 ?a n 3 4 ?a n 4 ?a n 4 1 ?a n 4 2 ?a n 4 3 ?a n 4 4 ?a n 4 5 ?a n 5 ?a p 1 0 ?a p 1 1 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 590 datasheet ?a p 1 2 ?a p 1 3 ?a p 1 4 ?a p 1 8 ?a p 1 9 ?a p 2 3 ?a p 2 7 ?a p 2 8 ?a p 3 ?a p 3 2 ?a p 3 3 ?a p 3 4 ?a p 3 5 ?a p 3 6 ?a p 3 7 ?a p 3 8 ?a p 3 9 ?a p 4 ?a p 4 0 ?a p 4 1 ?a p 4 2 ?a p 4 3 ?a p 5 ?a p 6 ?a p 7 ?a p 8 ?a p 9 ?a r 1 ?a r 1 2 ?a r 1 4 ?a r 1 8 ?a r 1 9 ?a r 2 3 ?a r 2 7 ?a r 2 8 ?a r 3 2 ?a r 3 4 ?a r 4 1 ?a r 4 5 ?a r 5 ?a t 1 0 ?a t 1 2 ?a t 1 4 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?a t 1 8 ?a t 1 9 ?a t 2 3 ?a t 2 7 ?a t 2 8 ?a t 3 ?a t 3 2 ?a t 3 4 ?a t 3 6 ?a t 3 7 ?a t 3 8 ?a t 3 9 ?a t 4 ?a t 4 0 ?a t 4 1 ?a t 4 2 ?a t 4 3 ?a t 5 ?a t 6 ?a t 7 ?a t 8 ?a t 9 ?a u 1 ?a u 1 0 ?a u 1 2 ?a u 1 4 ?a u 1 8 ?a u 1 9 ?a u 2 3 ?a u 2 7 ?a u 2 8 ?a u 3 2 ?a u 3 4 ?a u 3 6 ?a u 4 5 ?a v 1 0 ?a v 1 2 ?a v 1 4 ?a v 1 8 ?a v 1 9 ?a v 2 3 ?a v 2 7 ?a v 2 8 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 591 ?a v 3 ?a v 3 2 ?a v 3 4 ?a v 3 6 ?a v 4 1 ?a v 4 3 ?a v 5 ?a w 1 ?a w 1 0 ?a w 1 2 ?a w 1 4 ?a w 1 8 ?a w 1 9 ?a w 2 3 ?a w 2 7 ?a w 2 8 ?a w 3 2 ?a w 3 4 ?a w 3 6 ?a w 4 0 ?a w 4 1 ?a w 4 5 ?a w 5 ?a w 6 ?a y 1 0 ?a y 1 2 ?a y 1 4 ?a y 1 8 ?a y 1 9 ?a y 2 3 ?a y 2 7 ?a y 2 8 ?a y 3 ?a y 3 2 ?a y 3 4 ?a y 3 6 ?a y 3 9 ?a y 4 1 ?a y 4 3 ?a y 5 ?a y 7 ?b 1 ?b 1 3 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?b 3 3 ?b 4 1 ?b 5 ?b a 1 ?b a 1 0 ?b a 1 1 ?b a 1 2 ?b a 1 3 ?b a 1 4 ?b a 1 6 ?b a 1 7 ?b a 1 8 ?b a 2 ?b a 2 0 ?b a 2 1 ?b a 2 2 ?b a 2 4 ?b a 2 5 ?b a 2 6 ?b a 2 8 ?b a 2 9 ?b a 3 0 ?b a 3 2 ?b a 3 3 ?b a 3 4 ?b a 3 5 ?b a 3 6 ?b a 3 8 ?b a 3 9 ?b a 4 ?b a 4 0 ?b a 4 2 ?b a 4 4 ?b a 4 5 ?b a 6 ?b a 7 ?b a 8 ?b b 1 ? bb10 ? bb12 ? bb13 ? bb17 ? bb29 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 592 datasheet ?b b 3 ?b b 3 3 ?b b 3 4 ?b b 3 6 ?b b 4 ?b b 4 1 ?b b 4 2 ?b b 4 3 ?b b 4 5 ?b b 5 ?b c 1 0 ?b c 1 2 ?b c 1 3 ?b c 1 5 ?b c 1 7 ?b c 1 9 ?b c 2 1 ?b c 2 3 ?b c 2 5 ?b c 2 7 ?b c 2 9 ?b c 3 1 ?b c 3 3 ?b c 3 4 ?b c 3 6 ?b c 3 8 ?b c 4 ?b c 4 0 ?b c 4 2 ?b c 6 ?b c 8 ?b d 1 3 ?b d 3 3 ?b d 4 1 ?b d 5 ?b e 1 1 ?b e 1 3 ?b e 1 4 ?b e 1 6 ?b e 1 8 ?b e 2 0 ?b e 2 2 ?b e 2 4 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?b e 2 6 ?b e 2 8 ?b e 3 0 ?b e 3 2 ?b e 3 3 ?b e 3 5 ?b e 3 7 ?b e 3 9 ?b e 4 ?b e 4 1 ?b e 4 2 ?b e 5 ?b e 7 ?b e 9 ?c 1 0 ?c 1 2 ?c 1 3 ?c 1 5 ?c 1 7 ?c 1 9 ?c 2 1 ?c 2 3 ?c 2 5 ?c 2 7 ?c 2 9 ?c 3 1 ?c 3 3 ?c 3 4 ?c 3 6 ?c 3 8 ?c 4 ?c 4 0 ?c 4 2 ?c 6 ?c 8 ?d 1 ?d 1 0 ?d 1 2 ?d 1 3 ?d 1 7 ?d 2 9 ?d 3 ?d 3 3 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 593 ?d 3 4 ?d 3 6 ?d 4 ?d 4 1 ?d 4 2 ?d 4 3 ?d 4 5 ?d 5 ?e 1 ?e 1 0 ?e 1 1 ?e 1 2 ?e 1 3 ?e 1 4 ?e 1 6 ?e 1 7 ?e 1 8 ?e 2 ?e 2 0 ?e 2 1 ?e 2 2 ?e 2 4 ?e 2 5 ?e 2 6 ?e 2 8 ?e 2 9 ?e 3 0 ?e 3 2 ?e 3 3 ?e 3 4 ?e 3 5 ?e 3 6 ?e 3 8 ?e 3 9 ?e 4 ?e 4 0 ?e 4 2 ?e 4 4 ?e 4 5 ?e 6 ?e 7 ?e 8 ?f 1 0 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?f 1 2 ?f 1 4 ?f 1 8 ?f 1 9 ?f 2 3 ?f 2 7 ?f 2 8 ?f 3 ?f 3 2 ?f 3 4 ?f 3 6 ?f 3 9 ?f 4 1 ?f 4 3 ?f 5 ?f 7 ?g 1 ?g 1 0 ?g 1 2 ?g 1 4 ?g 1 8 ?g 1 9 ?g 2 3 ?g 2 7 ?g 2 8 ?g 3 2 ?g 3 4 ?g 3 6 ?g 4 0 ?g 4 1 ?g 4 5 ?g 5 ?g 6 ?h 1 0 ?h 1 2 ?h 1 4 ?h 1 8 ?h 1 9 ?h 2 3 ?h 2 7 ?h 2 8 ?h 3 ?h 3 2 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 594 datasheet ?h 3 4 ?h 3 6 ?h 4 1 ?h 4 3 ?h 5 ?j 1 ?j 1 0 ?j 1 2 ?j 1 4 ?j 1 8 ?j 1 9 ?j 2 3 ?j 2 7 ?j 2 8 ?j 3 2 ?j 3 4 ?j 3 6 ?j 4 5 ?k 1 0 ?k 1 2 ?k 1 4 ?k 1 8 ?k 1 9 ?k 2 3 ?k 2 7 ?k 2 8 ?k 3 ?k 3 2 ?k 3 4 ?k 3 6 ?k 3 7 ?k 3 8 ?k 3 9 ?k 4 ?k 4 0 ?k 4 1 ?k 4 2 ?k 4 3 ?k 5 ?k 6 ?k 7 ?k 8 ?k 9 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?l 1 ?l 1 2 ?l 1 4 ?l 1 8 ?l 1 9 ?l 2 3 ?l 2 7 ?l 2 8 ?l 3 2 ?l 3 4 ?l 4 1 ?l 4 5 ?l 5 ?m 1 0 ?m 1 1 ?m 1 2 ?m 1 3 ?m 1 4 ?m 1 8 ?m 1 9 ?m 2 3 ?m 2 7 ?m 2 8 ?m 3 ?m 3 2 ?m 3 3 ?m 3 4 ?m 3 5 ?m 3 6 ?m 3 7 ?m 3 8 ?m 3 9 ?m 4 ?m 4 0 ?m 4 1 ?m 4 2 ?m 4 3 ?m 5 ?m 6 ?m 7 ?m 8 ?m 9 ?n 1 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications datasheet 595 ?n 1 2 ?n 1 4 ?n 1 5 ?n 1 8 ?n 1 9 ?n 2 ?n 2 3 ?n 2 7 ?n 2 8 ?n 3 ?n 3 1 ?n 3 2 ?n 3 4 ?n 4 ?n 4 1 ?n 4 2 ?n 4 3 ?n 4 4 ?n 4 5 ?n 5 ?p 1 ?p 1 0 ?p 1 1 ?p 1 2 ?p 1 3 ?p 1 4 ?p 1 8 ?p 1 9 ?p 2 3 ?p 2 7 ?p 2 8 ?p 3 2 ?p 3 3 ?p 3 4 ?p 3 5 ?p 3 6 ?p 3 7 ?p 3 8 ?p 3 9 ?p 4 0 ?p 4 1 ?p 4 5 ?p 5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?p 6 ?p 7 ?p 8 ?p 9 ?r 1 3 ?r 1 8 ?r 2 8 ?r 3 ?r 3 3 ?r 4 3 ?t 1 ?t 1 8 ?t 2 8 ?t 4 1 ?t 4 5 ?t 5 ?u 1 8 ?u 2 8 ?u 3 ?u 4 ?u 4 1 ?u 4 2 ?u 4 3 ?u 5 ?v 1 ?v 1 0 ?v 1 1 ?v 1 2 ?v 1 3 ?v 1 4 ?v 1 5 ?v 1 6 ?v 1 7 ?v 1 8 ?v 1 9 ?v 2 0 ?v 2 1 ?v 2 2 ?v 2 3 ?v 2 4 ?v 2 5 ?v 2 6 ?v 2 7 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ballout and package specifications 596 datasheet ?v 2 8 ?v 2 9 ?v 3 0 ?v 3 1 ?v 3 2 ?v 3 3 ?v 3 4 ?v 3 5 ?v 3 6 ?v 3 7 ?v 3 8 ?v 3 9 ?v 4 0 ?v 4 1 ?v 4 5 ?v 5 ?v 6 ?v 7 ?v 8 ?v 9 ?w 1 0 ?w 1 1 ?w 1 2 ?w 1 3 ?w 1 4 ?w 1 8 ?w 2 8 ?w 3 ?w 3 2 ?w 3 3 ?w 3 4 ?w 3 5 ?w 3 6 ?w 3 7 ?w 3 8 ?w 3 9 ?w 4 0 ?w 4 3 ?w 6 ?w 7 ?w 8 ?w 9 ?y 1 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] ?y 1 8 ?y 2 8 ?y 4 1 ?y 4 5 ?y 5 table 54. gmch ballout arranged by signal name signal names ball # x[mils] y[mils] datasheet 597 ballout and package specifications 15.2 package specifications the (g)mch is available in a 34 mm [1.34 in] x 34 mm [1.34 in] flip chip ball grid array (fc-bga) package with 1254 solder balls (see figure 21 ). refer to the intel ? 4 series chipset family thermal and mechanical design guide for details. figure 21. (g)mch package drawing ballout and package specifications 598 datasheet datasheet 599 testability 16 testability in the (g)mch, testability for automated test equipment (ate) board level testing has been implemented as both jtag boundary scan and xor chains. 16.1 jtag boundary scan the (g)mch adds boundary scan ability compatible with the ieee 1149.1-2001 standard (test access port and boundary-scan architecture) specification. refer to the above mentioned specification for functionality. see figure 22 for test mode entry. the bscantest pin serves as a boundary-scan test strap. assertion of this strap (low) is required to disable glitch-masking logic; otherwise, boundary-scan control signals to device pin are blocked. the ddr3_dram_pwrok pin must be high for the ddr3_dramrstb pin boundary-scan data to become valid. note that this signal is only used on platforms where ddr3 is enabled. on ddr2 platforms, if ddr3_dram_pwrok is held low, then the boundary- scan data on the ddr3_dramrstb pin will be invalid. figure 22. jtag boundary scan test mode initialization cycles bscantest ddpc_ctrldata sdvo_ctrldata ddr3_dram_pwrok cl_pwrok pwrok cl_rstb rstinb hpl_clkinp exp_clkp hpl_clkinn exp_clkn = 3 cycles jtag_tck jtag_tms clock running or stopped = 0 s = 1 s = 3 s clock running or stopped (clock frequency not critical) = 1 s = 1 cycle = 1 s = 5 cycles drive straps low (values not important here) testability 600 datasheet the cl_pwrok pin provides hardware reset to the tap, so it must be driven low at power up to ensure clean reset to the tap. this pin must be driven high to indicate that power is valid, which also allows the tap to come out of reset. cl_rstb must be high for the specified time , for fuses to be loaded and valid before pwrok is asserted. the pwrok pin must be driven high in order to indicate that power is valid. it also latches the bscantest strap. the rstinb pin must be initially active (low) then de-asserted (high) so that the i/o buffers will operate correctly. clocking of the hpl_clkinn/p and exp_clkn/p pins is required to initialize internal registers including those that set default buffer compensation values. clock frequency is not critical due to pll bypass mode fo rced when bscantest strap is asserted. the jtag_tms pin should be held high before asserting mepwrok (cl_pwrok), and held high for at least 5 jtag_tck cycles to ensure that the tap exits the test-logic- reset state at the expected time once tms goes low. note that jtag_tms has an internal pullup. 16.1.1 tap instructions and opcodes the tap controller supports the jtag instructions as listed in ta b l e 5 5 . the instruction register length is 4 bits. 16.1.2 tap interface and timings. the (g)mch uses 4 dedicated pins to access the test access port (tap), and the port timings are shown in figure 23 . table 55. supported tap instructions opcode (binary) instruction selected test data register tdr length 0000b extest boundary-scan 485 0001b sample/ preload (sampre) boundary-scan 485 0011b idcode device identification (value: 0x04105013) 32 0100b clamp bypass 1 0101b extest_toggle boundary-scan 485 0110b highz bypass 1 1111b bypass bypass 1 others reserved datasheet 601 testability table 56. jtag pins pin direction description jtag_tck input test clock pin for jtag tap controller and test logic jtag_tms input with weak pullup jtag test mode select pin. sample d by the tap on the rising edge of tck to control the operation of the tap state machine. it is recommended that tms is held high when (cl_pwrok) is driven from low-to-high, to ensure dete rministic operation of the test logic. jtag_tdi input with weak pullup jtag test data input pin, sample d on the rising edge of tck to provide serial test instructions and data. jtag_tdo output jtag test data output pin. in inactive drive state except when instructions or data are being sh ifted. tdo changes on the falling edge of tck. during shifting, td o drives actively high and low. figure 23. jtag test mode initialization cycles tck tms tdi td o t jc t jc h t jsu t jh t jc o t jc o t jvz t jcl table 57. jtag signal timings symbol parameter min max unit notes t jc jtag tck clock period 25 ? ns 40 mhz t jcl jtag tck clock low time 0.4 * t jc ?ns t jch jtag tck clock high time 0.4 * t jc ?ns t jsu setup of tms and tdi before tck rising 11 ? ns t jh tms and tdi hold after tck rising 5 ? ns t jco tck falling to tdo output valid ? 7 ns t jvz tck falling to tdo output high-impedance ? 9 ns testability 602 datasheet 16.2 xor test mode initialization an xor-tree is a chain of xor gates each with one input pin connected to it, which allows for pad to ball to trace connection testing. the xor testing methodology is to boot the part using straps to enter xor mode (a description of the boot process follows). once in xor mode, all of the pins of an xor chain are driven to logic 1. this action will force the output of that xor chain to either a 1 if the number of the pins making up the chain is even or a 0 if the number of the pins making up the chain is odd. once a valid output is detected on the xor chain output, a walking 0 pattern is moved from one end of the chain to the other. every time the walking 0 is applied to a pin on the chain, the output will toggle. if the output does not toggle, there is a disconnect somewhere between die, package, and boar d and the system can be considered a failure. figure 24 shows the wave forms to be able to boot the (g)mch into xor mode. the straps that need to be controlled during this boot process are bsel[2:0], sdvo_ctrldata, exp_en, exp_slr, and xortest. all strap values must be driven before pwrok asserts. bsel0 must be a 1. bsel[2:1] need to be defined values, but logic value in any order will work. xortest must be driven to 0. figure 24. xor test mode initialization cycles pwrok rstin# strap pins hclkp/gclkp hclkn/gclkn xor inputs xor output cl_pwrok x cl_rst# datasheet 603 testability if sdvo is present in the design, sdvo_ctr ldata must be pulled to logic 1. depending on if static lane reversal is used and if the sdvo/pcie coexistence is selected, exp_slr and exp_en must be pulled in a valid manner. 16.2.1 xor chain definition for the (g)mch xor chain definitions, contact your intel field representative. testability 604 datasheet |
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