? 1. general description the dac1617d1g0 is a high-speed 16-bit dual channel digital-to-analog converter (dac) with selectable ? 2, ? 4 and ? 8 interpolation filters. th e device is optimized for multi-carrier and broadband wireless transmitters at sample rates of up to 1 gsps. supplied from a 3.3 v and a 1.8 v source, the dac1617d1g0 integrates a differential scalable output current up to 34 ma. the serial peripheral interface (spi) pr ovides full control of the dac1617d1g0. the dac1617d1g0 integrates a low voltage differential signaling (lvds) double data rate (ddr) receiver interf ace, with an on-chip 100 ? termination. the lvds ddr interface accepts a multiplex input data stream such as interleaved or folded. an internal lvds input auto-calibration ensures the ro bustness and stabilit y of the interface. digital on-chip modulation converts the complex i and q inputs from baseband to if. a 40-bit numerically controlled oscillator (nco) sets the mixe r frequency. high resolution internal gain, phase and offset control provide outsta nding image and local oscillator (lo) signal rejection at the system analog modulator output. an inverse (sin x) / x function ensures a cont rolled flatness 0.5 db for high bandwidths at the dac output. multiple device synchronization allows synchronization of the outputs of multiple dac devices. mds guarantees a maximum skew of one output clock period between several devices. the dac1617d1g0 includes a very low noise capacitor-free integrated phase-locked loop (pll) multiplier which generates a dac clock rate from the lvds clock rate. the dac1617d1g0 is available in an hvqfn72 package (10 mm ? 10 mm). 2. features and benefits dac1617d1g0 dual 16-bit dac, lvds interface, up to 1 gsps, x2, x4 and x8 interpolating rev. 03 ? 2 july 2012 preliminary data sheet ? dual-channel 16-bit resolution ? synchronization of multiple dac devices ? 1 gsps maximum update rate ? 3-wire or 4-wire mode spi interface ? selectable ? 2, ? 4 and ? 8 interpolation filters ? differential scalable output current from 8.1 ma to 34 ma ? very low noise capacitor-free integrated phase-locked loop (pll) ? external analog offset control (10-bit auxiliary dacs)
dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 2 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 3. applications ? wireless infrastructure: lte, wimax, gsm, cdma, wcdma, td-scdma ? communications: lmds/mmds, point-to-point ? direct digital synthesis (dds) ? broadband wireless systems ? digital radio links ? instrumentation ? automated test equipment (ate) 4. ordering information ? embedded numerically controlled oscillator (nco) with 40-bit programmable frequency ? high resolution internal digital gain and offset control to support high performance iq-modulator image rejection ? embedded complex(i/q) digital if modulator ? internal phase correction ? 1.8 v and 3.3 v power supplies ? inverse (sin x) / x function ? lvds ddr compatible input interface with on-chip 100 ? terminations ? power-down mode and sleep mode; 5-bit nco low-power mode ? lvds ddr input clock up to 370 mhz ? on-chip 1.25 v reference ? lvds or lvpecl compatible dac clock ? industrial temperature range ? 40 ? c to +85 ? c ? interleaved or folded i and q data input mode ? 72 pins small form factor hvqfn package table 1. ordering information type number package name description version DAC1617D1G0HN hvqfn72 plastic thermal enhanced very thin quad flat package; no leads; 72 terminals; body 10 ? 10 ? 0.85 mm sot813-3
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 3 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 5. block diagram fig 1. block diagram d d d , 2 8 7 % 3 , 2 8 7 % 1 , 2 8 7 $ 3 , 2 8 7 $ 1 $ 8 ; $ 3 $ 8 ; $ 1 v l q f r v 2 ) ) 6 ( 7 & |