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hm5221605 series 2 m lvttl interface sdram (64-kword 16-bit 2-bank) 66 mhz / 58 mhz / 50 mhz ade-203-199c (z) rev. 3.0 nov. 1997 description all inputs and outputs are referred to the rising edge of the clock input. the hm5221605 is offered in 2 banks for improved performance. features 3.3v power supply clock frequency: 50 mhz/58 mhz/66 mhz (max) lvttl interface single pulsed ras 2 banks can operates simultaneously and independently burst read/write operation and burst read/single write operation capability programmable burst length: 1/2/4/8/full page (256) programmable burst sequence: ? sequential ? interleave full page burst length capability ? sequential burst ? burst stop capability programmable cas latency: 1/2/3 byte control by dqmu and dqml 512 refresh cycles: 8 ms 2 variations of refresh ? auto refresh ? self refresh
hm5221605 series 2 ordering information type no. frequency package hm5221605tt-15 HM5221605TT-17 hm5221605tt-20 66 mhz 57 mhz 50 mhz 400-mil 50-pin plastic tsop ii (ttp-50da) pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v cc i/o0 i/o1 v ss q i/o2 i/o3 v cc q i/o4 i/o5 v ss q i/o6 i/o7 v cc q dqml we cas ras cs a9 a8 a0 a1 a2 a3 v cc hm5221605tt series (top view) v ss i/o15 i/o14 v ss q i/o13 i/o12 v cc q i/o11 i/o10 v ss q i/o9 i/o8 v cc q nc dqmu clk cke nc nc nc a7 a6 a5 a4 v ss
hm5221605 series 3 pin description pin name function a0 to a9 address input row address a0 to a6, a8 column address a0 to a7 bank select address a9 i/o0 to i/o15 data-input/output cs chip select ras row address strobe command cas column address strobe command we write enable command dqmu dqml upper byte input/output mask lower byte input/output mask clk clock input cke clock enable v cc power for internal circuit v ss ground for internal circuit v cc q power for i/o circuit v ss q ground for i/o circuit nc no connection
hm5221605 series 4 block diagram column address counter column address buffer row address buffer refresh counter a0 ?a9 a0 ?a6, a8, a9 i/o0 ?i/o15 input buffer output buffer control logic & timing generator row decoder row decoder sense amplifier & i/o bus column decoder sense amplifier & i/o bus column decoder memory array memory array clk cke cs ras cas we dqml a0 ?a7 bank 0 bank 1 dqmu 256 row x 256 column x 16 bit 256 row x 256 column x 16 bit
hm5221605 series 5 pin functions clk (input pin): clk is the master clock input to this pin. the other input signals are referred at clk rising edge. cs (input pin): when cs is low, the command input cycle becomes valid. when cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. ras , cas , and we (input pins): although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a8 (input pins): row address (ax0 to ax6, ax8) is determined by a0 to ax6, a8 level at the bank active command cycle clk rising edge. column address (ay0 to ay7) is determined by a0 to a7 level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a8 defines the precharge mode. when a8 = high at the precharge command cycle, both banks are precharged. but when a8 = low at the precharge command cycle, only the bank that is selected by a9 (bs) is precharged. a9 (input pin): a9 is a bank select signal (bs). the memory array of the hm5221605 is divided into bank 0 and bank 1, both which contain 256 row 256 column 16 bits. if a9 is low, bank 0 is selected, and if a9 is high, bank 1 is selected. cke (input pin): this pin determines whether or not the next clk is valid. if cke is high, the next clk rising edge is valid. if cke is low, the next clk rising edge is invalid. this pin is used for power- down and clock suspend modes. dqmu/dqml (input pins): dqmu controls upper byte and dqml controls lower byte input/output buffers. read operation: if dqmu/dqml is high, the output buffer becomes high-z. if the dqmu/dqml is low, the output buffer becomes low-z. write operation: if dqmu/dqml is high, the previous data is held (the new data is not written). if dqmu/dqml is low, the data is written. i/o0 to i/o15 (i/o pins): data is input to and output from these pins. these pins are the same as those of a conventional dram. v cc and v cc q (power supply pins): 3.3 v is applied. (v cc is for the internal circuit and v cc q is for the output buffer.) v ss and v ss q (power supply pins): ground is connected. (v ss is for the internal circuit and v ss q is for the output buffer.)
hm5221605 series 6 command operation command truth table the synchronous dram recognizes the following commands specified by the cs , ras , cas , we and address pins. function symbol cke n - 1 n cs ras cas we a9 a8 a0 to a7 ignore command desl h h no operation nop h lhhh burst stop in full page bst h lhhl column address and read command read h lhlhvlv read with auto-precharge read a h lhlhvhv column address and write command writ h l hl lvlv write with auto-precharge writ a h lhllvhv row address strobe and bank active actv h llhhvvv precharge select bank pre h l lhlvl precharge all bank pall h llhl h refresh ref/self h v l l l h mode register set mrs h llllvvv note: h: v ih . l: v il . : v ih or v il . v: valid address input ignore command [desl]: when this command is set ( cs is high), the synchronous dram ignore command input at the clock. however, the internal status is held. no operation [nop]: this command is not an execution command. however, the internal operations continue. burst stop in full-page [bst]: this command stops a full-page burst operation (burst length = full-page (256)), and is illegal otherwise. full page burst continues until this command is input. when data input/output is completed for a full-page of data (256), it automatically returns to the start address, and input/output is performed repeatedly. column address strobe and read command [read]: this command starts a read operation. in addition, the start address of burst read is determined by the column address (ay0 to ay7) and the bank select address (bs). after the read operation, the output buffer becomes high-z. read with auto precharge [read a]: this command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. when the burst length is full-page (256), this command is illegal.
hm5221605 series 7 column address strobe and write command [writ]: this command starts a write operation. when the burst write mode is selected, the column address (ay0 to ay7) and the bank select address (a9) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address (ay0 to ay7) and the bank select address (a9). write with auto precharge [writ a]: this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. when the burst length is full-page (256), this command is illegal. row address strobe and bank activate [actv]: this command activates the bank that is selected by a9 (bs) and determines the row address (ax0 to ax6, ax8). when a9 is low, bank 0 is activated. when a9 is high, bank 1 is activated. precharge selected bank [pre]: this command starts precharge operation for the bank selected by a9. if a9 is low, bank 0 is selected. if a9 is high, bank 1 is selected. precharge all banks [pall]: this command starts a precharge operation for all banks. refresh [ref/self]: this command starts the refresh operation. there are two types of refresh operation, the one is auto refresh, and the other is self refresh. for details, refer to the cke truth table section. mode register set [mrs]: synchronous dram has a mode register that defines how it operates. the mode register is specified by the address pins (a0 to a9) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. dqm truth table function symbol cke n - 1 n dqmu dqml upper byte write enable/output enable enbu h l lower byte write enable/output enable enbl h l upper byte write inhibit/output disable masku h h lower byte write inhibit/output disable maskl h h note: h: v ih . l: v il . : v ih or v il . the hm5221605 series can mask input/output data by means of dqmu and dqml. dqmu masks the upper byte and dqml masks the lower byte. during reading, the output buffer is set to low-z by setting dqmu/dqml to low, enabling data output. on the other hand, when dqmu/dqml is set to high, the output buffer becomes high-z, disabling data output. during writing, data is written by setting dqmu/dqml to low. when dqmu/dqml is set to high, the previous data is held (the new data is not written). desired data can be masked during burst read or burst
hm5221605 series 8 write by setting dqmu/dqml. for details, refer to the dqm control section of the hm5221605 operating instructions. cke truth table current state function cke n - 1 n cs ras cas we address active clock suspend mode entry h l h any clock suspend l l clock suspend clock suspend mode exit l h l h h h lhh idle auto-refresh command ref h h l l l h idle self-refresh entry self h l l l l h idle power down entry h l l h h h hlh self refresh self refresh exit selfx l h l h h h lhh power down power down exit l h l h h h lhh note: h: v ih . l: v il . : v ih or v il . clock suspend mode entry: the synchronous dram enters clock suspend mode from active mode by setting cke to low. the clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend: this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read a suspend: the data being output is held (and continues to be output). write suspend and writ a suspend: in this mode, external signals are not accepted. however, the internal state is held. clock suspend: during clock suspend mode, keep the ckl to low. clock suspend mode exit: the synchronous dram exits from clock suspend mode by setting cke to high during the clock suspend state. i dle: in this state, all banks are not selected, and completed precharge operation. auto refresh command [ref]: when this command is input from the idle state, the synchronous dram starts auto-refresh operation. (the auto-refresh is the same as the cbr refresh of conventional drams.) during the auto-refresh operation, refresh address and bank select address are generated inside the synchronous dram. for every auto-refresh cycle, the internal address counter is updated. accordingly, 512 times are required to refresh the entire memory. before executing the auto-refresh
hm5221605 series 9 command, all the banks must be in the idle state. in addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto refresh. self refresh entry [self]: when this command is input during the idle state, the synchronous dram starts self refresh operation. after the execution of this command, self refresh continues while cke is low. since self refresh is performed internally and automatically, external refresh operations are unnecessary. power down mode entry: when this command is executed during the idle state, the synchronous dram enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. self refresh exit: when this command is executed during self refresh mode, the synchronous dram can exit from self refresh mode. after exiting from self refresh mode, the synchronous dram enters the idle state. power down exit: when this command is executed at the power down mode, the synchronous dram can exit from power down mode. after exiting from power down mode, the synchronous dram enters the idle state.
hm5221605 series 10 function truth table the following table shows the operations that are performed when each command is issued in each mode of the synchronous dram. current state cs ras cas we address command operation precharge h desl enter idle after t rp l hhh nop enter idle after t rp l hhl bst illegal l h l h ba, ca, a8 read/read a illegal l h l l ba, ca, a8 writ/writ a illegal l l h h ba, ra actv illegal l l h l ba, a8 pre, pall illegal lllh ref, self illegal llll mode mrs illegal idle h desl nop l hhh nop nop l hhl bst nop l h l h ba, ca, a8 read/read a illegal l h l l ba, ca, a8 writ/writ a illegal l l h h ba, ra actv bank and row active l l h l ba, a8 pre, pall nop lllh ref, self refresh llll mode mrs mode register set
hm5221605 series 11 current state cs ras cas we address command operation row active h desl nop l hhh nop nop l hhl bst nop l h l h ba, ca, a8 read/read a begin read l h l l ba, ca, a8 writ/writ a begin write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a8 pre, pall precharge lllh ref, self illegal llll mode mrs illegal read h desl continue burst to end l hhh nop continue burst to end l hhl bst burst stop to full page l h l h ba, ca, a8 read/read a continue burst read to cas latency and new read l h l l ba, ca, a8 writ/writ a term burst read/start write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a8 pre, pall term burst read and precharge lllh ref, self illegal llll mode mrs illegal read with auto h x desl continue burst to end and precharge precharge l h h h nop continue burst to end and precharge l hhl bst illegal l h l h ba, ca, a8 read/read a illegal l h l l ba, ca, a8 writ/writ a illegal l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a8 pre, pall illegal lllh ref, self illegal llll mode mrs illegal
hm5221605 series 12 current state cs ras cas we address command operation write h desl continue burst to end l hhh nop continue burst to end l hhl bst burst stop on full page l h l h ba, ca, a8 read/read a term burst and new read l h l l ba, ca, a8 writ/writ a term burst and new write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a8 pre, pall term burst write and precharge* 2 lllh ref, self illegal llll mode mrs illegal write with auto h desl continue burst to end and precharge precharge l h h h nop continue burst to end and precharge l hhl bst illegal l h l h ba, ca, a8 read/read a illegal l h l l ba, ca, a8 writ/writ a illegal l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a8 pre, pall illegal lllh ref, self illegal llll mode mrs illegal refresh h desl enter idle after t rc (auto refresh) l h h h nop enter idle after t rc l hhl bst enter idle after t rc l h l h ba, ca, a8 read/read a illegal l h l l ba, ca, a8 writ/writ a illegal l l h h ba, ra actv illegal l l h l ba, a8 pre, pall illegal lllh ref, self illegal llll mode mrs illegal notes 1. h: v ih . l: v il . : v ih or v il . the other combinations are inhibit. 2. an interval of t rwl is required between the final valid data input and the precharge command. 3. if t rrd is not satisfied, this operation is illegal.
hm5221605 series 13 from [precharge] to [desl], [nop] or [bst]: when these commands are executed, the synchronous dram enters the idle state after t rp has elapsed from the completion of precharge. from [idle] to [desl], [nop], [bst], [pre] or [pall]: these commands result in no operation. to [actv]: the bank specified by the address pins and the row address is activated. to [ref], [self]: the synchronous dram enters refresh mode (auto refresh or self refresh). to [mrs]: the synchronous dram enters the mode register set cycle. from [row active] to [desl], [nop] or [bst]: these commands result in no operation. to [read], [read a]: a read operation starts. (however, an interval of t rcd is required.) to [writ], [writ a]: a write operation starts. (however, an interval of t rcd is required.) to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands set the synchronous dram to precharge mode. (however, an interval of t ras is required.) from [read] to [desl], [nop]: these commands continue read operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: data output by the previous read command continues to be output. after cas latency, the data output resulting from the next command will start. to [writ], [writ a]: these commands stop a burst read, and start a write cycle. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop a burst read, and the synchronous dram enters precharge mode.
hm5221605 series 14 from [read with auto-precharge] to [desl], [nop]: these commands continue read operations until the burst operation is completed, and the synchronous dram then enters precharge mode. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from [write] to [desl], [nop]: these commands continue write operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: these commands stop a burst and start a read cycle. to [writ], [writ a]: these commands stop a burst and start the next write cycle. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop burst write and the synchronous dram then enters precharge mode. from [write with auto precharge] to [desl], [nop]: these commands continue write operations until the burst is completed, and the synchronous dram enters precharge mode. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from [refresh] to [desl], [nop], [bst]: after an auto refresh cycle (after t rc ), the synchronous dram automatically enters the idle state.
hm5221605 series 15 simplified state diagram precharge write suspend read suspend row active idle idle power down auto refresh self refresh mode register set power on writea writea suspend reada reada suspend active clock suspend sr entry sr exit mrs refresh cke cke_ active write read write with ap read with ap power applied cke cke_ cke cke_ cke cke_ cke cke_ cke cke_ precharge ap read write write with ap read with read with ap write with ap precharge precharge precharge bst (on full page) bst (on full page) *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
hm5221605 series 16 mode register configuration the mode register is set by the input to the address pins (a0 to a9) during mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. a9 and a8: (opcode): the synchronous dram has two types of write modes. one is the burst write mode, and the other is the single write mode. these bits specify write mode. burst read and burst write: burst write is performed for the specified burst length starting from the column address specified in the write cycle. burst read and single write: data is only written to the column address specified during the write cycle, regardless of the burst length. a7: keep this bit low at the mode register set cycle. a6, a5, a4: (lmode): these pins specify the cas latency. a3: (bt): a burst type is specified. when full-page burst is performed, only "sequential" can be selected. a2, a1, a0: (bl): these pins specify the burst length.
hm5221605 series 17 a2 a1 a0 burst length 00 0 1 00 1 2 01 0 4 01 1 8 1 1 1 f.p. bt = 0 bt = 1 10 0 r 11 0 r 1 2 4 8 r r r a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 00 0 r 00 1 1 01 0 2 01 1 3 1 r r is reserved (inhibit) a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 opcode 0 lmode bt bl a9 0 0r write mode a8 0 1 burst read and burst write 1 burst read and single write 0 1r 1 10 1 r r f.p. = full page (256) = 0 or 1 burst sequence a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequence 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequence starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequence starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
hm5221605 series 18 operation of hm5221605 series read/write operations bank active: before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (actv) command. either bank 0 or bank 1 is activated according to the status of the a9 pin, and the row address (ax0 to ax6, ax8) is activated by the a0 to a8 pins at the bank active command cycle. an interval of t rcd is required between the bank active command input and the following read/write command input. read operation: a read operation starts when a read command is input. output buffer becomes low-z in the ( cas latency - 1) cycle after read command set. hm5221605 series can perform a burst read operation. the burst length can be set to 1,2,4,8 or full-page (256). the start address for a burst read is specified by the column address (ay0 to ay7) and the bank select address (a9) at the read command set cycle. in a read operation, data output starts after the number of cycles specified by the cas latency. the cas latency can be set to 1, 2, 3. when the burst length is 1, 2, 4 or 8, the dout buffer automatically becomes high-z at the next cycle after the successive burst-length data has been output. when the burst length is full-page (256), data is repeatedly output until the burst stop command is input. the cas latency and burst length must be specified at the mode register. cas latency read clk command dout actv row column out 0 out 1 out 2 out 3 address cl = 1 cl = 2 cl = 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 t rcd cl: cas latency burst length = 4
hm5221605 series 19 burst length read clk command dout actv row column out 0 out 6 out 7 out 8 address out 0 out 1 out 4 out 5 out 0 out 1 out 2 out 3 bl = 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 6 out 7 out 4 out 5 out 255 out 0 out 1 bl = 2 bl = 4 bl = 8 bl = full page (256) t rcd bl: burst length cas latency = 2 write operation: burst write or single write mode is selected by the opcode (a9, a8) of the mode register. 1. burst write: a burst write operation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same cycle as a write command set. (the latency of data input is 0.) the burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. the write start address is specified by the column address (ay0 to ay7) and the bank select address (a9) at the write command set cycle. burst write writ clk command din actv row column in 0 in 6 in 7 in 8 address in 1 in 4 in 5 in 3 bl = 1 in 6 in 7 in 4 in 5 in 255 in 0 in 1 bl = 2 bl = 4 bl = 8 bl = full page (256) t rcd in 0 in 0 in 0 in 0 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 cas latency = 1, 2, 3
hm5221605 series 20 2. single write: a single write operation is enabled by setting opcode (a9, a8) to (1, 0). in a single write operation, data is only written to the column address (ay0 to ay7) and the bank select address (a9) specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0). single write write clk command din active row column in 0 address t rcd cas latency = 1, 2, 3 burst length = 1, 2, 4, 8, full page
hm5221605 series 21 auto precharge read with auto precharge: in this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval defined by l apr is required before execution of the next command. cas latency precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output 1 same cycle as the final data is output clk read cl=1 command out0 out1 out2 dout l apr out3 actv read out0 out1 read out0 out2 out3 actv out2 out1 l apr l apr cl=2 command cl=3 command dout dout actv out3 note: internal auto-precharge starts at the timing indicated by " ". at clk = 33 mhz (i apr changes depending on the operating frequency.
hm5221605 series 22 write with auto precharge: in this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval of l apw is required between the final valid data input and input of the next command. burst write (burst length = 4) clk command i/o (input) writ l in0 in1 in2 apw actv in3 single write clk command i/o (input) l apw writ actv in full-page burst stop burst stop command during burst read: the burst stop (bst) command is used to stop data output during a full-page burst. the bst command sets the output buffer to high-z and stops the full-page burst read. the timing from command input to the last data changes depending on the cas latency setting. when the cas latency is 3, the data becomes invalid two cycles after the bst command. in addition, the bst command is valid only during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8. cas latency bst to valid data bst to high impedance 10 1 21 2 32 3
hm5221605 series 23 cas latency = 1, burst length = full page clk command i/o (output) out out out out l bsr 0 cycle l bsh 1 cycle bst out cas latency = 2, burst length = full page l = 1 cycle bsr clk command i/o (output) out out out out l = 2 cycle bsh bst out out cas latency = 3, burst length = full page l = 2 cycle bsr clk command i/o (output) out out out out l = 3 cycle bsh bst out out out
hm5221605 series 24 burst stop command at burst write: the burst stop command (bst command) is used to stop data input during a full-page burst write. data is still written in the same cycle as the bst command, but no data is written in subsequent cycles. in addition, the bst command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8. and an interval of t rwl is required between the bst command and the next precharge command. burst length = full page t clk command i/o (input) in rwl in in l = 1 cycle bsw pre/pall bst
hm5221605 series 25 command intervals read command to read command interval 1. same bank, same row address: when another read command is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (same row address in same bank) clk command dout out b3 address (a0-a8) out b1 out b2 bs(a9) actv row column a read read column b out a0 out b0 bank0 active column =a read column =b read column =a dout column =b dout cas latency = 3 burst length = 4 bank0 2. same bank, different row address : when the row address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command.
hm5221605 series 26 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (different bank) clk command dout out b3 address (a0-a8) out b1 out b2 bs(a9) actv row 0 row 1 actv read column a out a0 out b0 bank0 active bank1 active bank0 read bank1 read read column b bank0 dout bank1 dout cas latency = 3 burst length = 4 write command to write command interval 1. same bank, same row address: when another write command is executed at the same row address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. in the case of burst writes, the second write command has priority. write to write command interval (same row address in same bank) clk command din in b3 address (a0-a8) in b1 in b2 bs(a9) actv row writ writ column b in a0 in b0 bank0 active column =a write column =b write burst write mode burst length = 4 bank0 column a 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. in the case of burst write, the second write command has priority.
hm5221605 series 27 write to write command interval (different bank) clk command din in b3 address (a0-a8) in b1 in b2 bs(a9) actv row 0 row 1 actv writ column a in a0 in b0 bank0 active bank1 active bank0 write bank1 write writ column b burst write mode burst length = 4 read command to write command interval 1. same bank, same row address: when the write command is executed at the same row address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. however, dqmu/dqml must be set high so that the output buffer becomes high-z before data input. read to write command interval (1) clk command dout in b2 in b3 read writ in b0 in b1 high-z din cl=1 cl=2 cl=3 dqmu /dqml burst length = 4 burst write
hm5221605 series 28 read to write command interval (2) clk command dout read writ dqmu /dqml cl=1 cl=2 cl=3 din high-z high-z high-z 2 clock 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command or a bank-active command. 3. different bank: when the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. however, dqml/dqmu must be set high so that the output buffer becomes high-z before data input.
hm5221605 series 29 write command to read command interval 1. same bank, same row address: when the read command is executed at the same row address of the same bank as the preceding write command, the write command can be performed after an interval of no less than 1 cycle. however, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. write to read command interval (1) clk command din writ read in a0 out b1 out b2 out b3 out b0 dout column=a write column=b read column=b dout cas latency dqmu/dqml burst write mode cas latency = 1 burst length = 4 bank0 write to read command interval (2) clk command din writ read in a0 out b1 out b2 out b3 out b0 dout column=a write column=b read column=b dout cas latency in a1 dqmu/dqml burst write mode cas latency = 1 burst length = 4 bank0
hm5221605 series 30 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. however, in the case of a burst write, data will continue to be written until one cycle before the read command is executed (as in the case of the same bank and the same address). read command to precharge command interval (same bank): when the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. however, since the output buffer then becomes high-z after the cycles defined by l hzp , there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. to read all data by burst read, the cycles defined by l ep must be assured as an interval from the final data output to precharge command execution. read to precharge command interval (same bank): to output all data cas latency = 1, burst length = 4 clk out a0 out a1 out a2 command dout read pre/pall out a3 cl=1 l = 0 cycle ep cas latency = 2, burst length = 4 clk command dout read pre/pall out a0 out a1 out a2 out a3 cl=2 l = -1 cycle ep
hm5221605 series 31 cas latency = 3, burst length = 4 clk command dout read pre/pall out a0 out a1 out a2 out a3 cl=3 l = -2 cycle ep read to precharge command interval (same bank): to stop output data cas latency = 1, burst length = 2, 4, 8 clk out a0 command dout read pre/pall l hzp =1 high-z cas latency = 2, burst length = 2, 4, 8 clk command dout read pre/pall out a0 l hzp =2 high-z cas latency = 3, burst length = 2, 4, 8 clk command dout read pre/pall out a0 l hzp =3 high-z
hm5221605 series 32 write command to precharge command interval (same bank): when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. however, if the burst write operation is unfinished, the input data must be masked by means of dqmu and dqml for assurance of the cycle defined by t rwl . write to precharge command interval (same bank) burst length = 4 (to stop write operation) clk command din writ pre/pall t rwl dqmu/dqml clk in a0 in a1 command din writ pre/pall t rwl dqmu/dqml burst length = 4 (to write all data) clk in a0 in a1 in a2 command din writ pre/pall in a3 t rwl dqmu/dqml
hm5221605 series 33 bank active command interval 1. same bank: the interval between the two bank-active commands must be no less than t rc . bank active to bank active for same bank clk command address (a0-a8) bs (a9) bank 0 active actv row actv row bank 0 active t rc 2. in the case of different bank-active commands: the interval between the two bank-active commands must be no less than t rrd . bank active to bank active for different bank clk command address (a0-a8) bs (a9) bank 0 active bank 1 active actv row:0 actv row:1 t rrd
hm5221605 series 34 mode register set to bank-active command interval: the interval between setting the mode register and executing a bank-active command must be no less than t rsa . clk command address (a0-a9) mode register set bank active mrs actv t rsa bs & row code
hm5221605 series 35 dqm control the dqmu and dqml mask the lower and upper bytes of the i/o data, respectively. the timing of dqmu/dqml is different during reading and writing. reading: when data is read, the output buffer can be controlled by dqmu/dqml. by setting dqmu/dqml to low, the output buffer becomes low-z, enabling data output. by setting dqmu/dqml to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal reading operations continue. the latency of dqmu/dqml during reading is 2. clk i/o (output) out 0 out 1 l = 2 latency out 3 dod dqmu /dqml high-z writing: input data can be masked by dqmu/dqml. by setting dqmu/dqml to low, data can be written. in addition, when dqmu/dqml is set to high, the corresponding data is not written, and the previous data is held. the latency of dqmu/dqml during writing is 0. clk i/o (input) in 0 in 1 l = 0 latency in 3 did dqmu /dqml
hm5221605 series 36 refresh auto refresh: all the banks must be precharged before executing an auto refresh command. since the auto refresh command updates the interval counter every time it is executed and determines the banks and the row addresses to be refreshed, external address specification is not required. the refresh cycle is 512 cycles/8 ms. (512 cycles are required to refresh all the row addresses.) the output buffer becomes high- z after auto refresh start. in addition, since a precharge has been completed by an internal operation after the auto refresh, an additional precharge operation by the precharge command is not required. self refresh: after executing a self refresh command, the self refresh operation continues while cke is held low. during self refresh operation, all row addresses are refreshed by the internal refresh timer. a self refresh is terminated by a self refresh exit command. after the self refresh, since it is impossible to determine the address of the last row to be refreshed, an auto refresh should immediately be performed for all addresses (512 cycles). others power down mode: the synchronous dram enters power down mode when cke goes low in the idle state. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the synchronous dram exits from the power down mode, and command input is enabled from the next cycle. in this mode, internal refresh is not performed. clock suspend mode: by driving cke to low during a bank-active or read/write operation, the synchronous dram enters clock suspend mode. during clock suspend mode, external input signals are ignored and the internal state is maintained. when cke is driven high, the synchronous dram terminates clock suspend mode, and command input is enabled from the next cycle. for details, refer to the "cke truth table". power up sequence: hm5221605 series has two types of power up sequence. hitachi recommends that the dqmu/dqml and the cke are set to high to ensure output to be in the high impedance and to prevent from bus contention. 1. during power up sequence, the dqmu/dqml and the cke must be set to high. when 100 m s has past after power on, all banks must be precharged using the precharge command. after t rp delay, set the mode register. and after t rsa delay, execute two or more cycles of auto refresh operation as dummy, an interval of t rc is required between two auto refresh commands. 2. during power up sequence, the dqmu/dqml and the cke must be set to high. when 200 m s has past after power on, all banks must be precharged using the precharge command. after t rp delay, set 8 or more auto refresh commands. and set the mode register set command to initialize the mode register.
hm5221605 series 37 absolute maximum ratings parameter symbol value unit notes voltage on any pin relative to v ss v t C1.0 to +5.5 v 1, 2 supply voltage relative to v ss v cc C1.0 to +4.6 v 2 short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c notes: 1. v ih (max) = 5.75 v for pulse width 5 ns. 2. respect to v ss . recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min max unit notes supply voltage v cc , v cc q 3.0 3.6 v 1 v ss , v ss q0 0 v input high voltage v ih 2.0 5.5 v 1, 2 input low voltage v il C0.3 0.8 v 1, 3 notes: 1. all voltage referred to v ss 2. v ih (max) = 5.75 v for pulse width 5 ns 3. v il (min) = C1.0 v for pulse width 5 ns
hm5221605 series 38 dc characteristics (ta = 0 to 70 c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) hm5221605 -15 -17 -20 parameter symbol min max min max min max unit test conditions notes operating current i cc1 85 75 70 ma burst length = 1 t rc = min 1, 2, 4 standby current i cc2 3 3 3 ma cke = v il , t ck = min 5 (bank disable) 2 2 2 ma cke = v il clk = v il or v ih fixed 6 33 30 26 ma cke = v ih , nop command, t ck = min 3 active standby current (bank active) i cc3 7 7 7 ma cke = v il , t ck = min, i/o = high-z 1, 2 34 31 26 ma cke = v ih , nop command t ck = min, i/o = high-z 1, 2, 3 burst operating current (cl = 1) i cc4 656050mat ck = min, bl = 4 1, 2, 4 (cl = 2) i cc4 100 95 80 ma (cl = 3) i cc4 105 95 85 ma refresh current i cc5 706560mat rc = min self refresh current i cc6 2 2 2 mav ih 3 v cc C 0.2 v il 0.2 v 7 input leakage current i li C10 10 C10 10 C10 10 m a0 vin v cc output leakage current i lo C10 10 C10 10 C10 10 m a0 vout v cc i/o = disable output high voltage v oh 2.4 2.4 2.4 v i oh = C2 ma output low voltage v ol 0.4 0.4 0.4 v i ol = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signal transition is once per two clk cycles. 4. input signal transition is once per one clk cycle. 5. after power down mode set, clk operating current. 6. after power down mode set, no clk operating current. 7. after self refresh mode set, self refresh current.
hm5221605 series 39 capacitance (ta = 25 c, v cc , v cc q = 3.3 v 0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1, 3 input capacitance (signals) c i2 5 pf 1, 3 output capacitance (i/o) c o 7 pf 1, 2, 3 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. dqmu/dqml = v ih to disable dout. 3. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to 70 c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) hm5221605 -15 -17 -20 parameter symbol min max min max min max unit notes system clock cycle time (cl = 1) t ck 30 34 40 ns 1 (cl = 2,3) t ck 15 17 20 ns clk high pulse width t ckh 4.578ns1 clk low pulse width t ckl 4.578ns1 access time from clk (cl = 1) t ac 30 34 38 ns 1, 2 (cl = 2) t ac 15 16.5 18 ns (cl = 3) t ac 13 15.5 18 ns read command to data valid time (cl = 1) t ack 30 34 38 ns 1, 2 (cl = 2) t ack 30 33.5 38 ns (cl = 3) t ack 43 49.5 58 ns data-out hold time (cl = 1) t oh 4 4 4 ns 1, 2 (cl = 2, 3) t oh 2 22 ns clk to data-out low impedance t lz 0 0 0 ns 1, 2 clk to data-out high impedance (cl = 1) t hz 415417419ns1, 3 (cl = 2, 3) t hz 210212214ns
hm5221605 series 40 ac characteristics (ta = 0 to 70 c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) (cont.) hm5221605 -15 -17 -20 parameter symbol min max min max min max unit notes data-in setup time t ds 4 44 ns1 data in hold time t dh 2 22 ns1 address setup time t as 4 44 ns1 address hold time t ah 2 22 ns1 cke setup time t ces 4 4 4 ns 1, 4 cke setup time for cke function exit t cesp 13 15 17 ns 1, 5 cke hold time t ceh 2 22 ns1 cke hold time for cke function exit t cehp 17 19 22 ns 1, 6 command ( cs , ras , cas , we , dqm) setup time t cs 4 44 ns1 command ( cs , ras , cas , we , dqm) hold time t ch 2 22 ns1 ref/active to ref/active command period t rc 110 120 130 ns 1 active to precharge command period t ras 70 10000 75 10000 80 10000 ns 1 active to precharge on full page mode t rasc 80000 80000 80000 ns 1 active command to column command (same bank) t rcd 30 34 40 ns 1 precharge to active command period t rp 30 34 40 ns 1 the last data-in to precharge lead time t rwl 30 34 40 ns 1 active (a) to active (b) command period t rrd 30 34 40 ns 1 register set to active command t rsa 30 34 40 ns 1 transition time (rise to fall) t t 15 15 15 ns refresh period t ref 8 8 8 ms notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.40 v. 2. access time is measured at 1.40 v. load condition is c l = 50 pf with current source. 3. t hz (max) defines the time at which the outputs achieves 200 mv. load condition is c l = 5 pf with current source. 4. t ces define cke setup time to clk rising edge except power down exit command and active clock suspend exit command. 5. t cesp define cke setup time to clk rising edge for power down exit command and active clock suspend exit command. 6. t cehp define clk rising edge to cke hold time for self refresh exit command, power down exit command and active clock suspend exit command.
hm5221605 series 41 test conditions input and output timing reference levels: 1.4 v input waveform and output load: see following figures. t t 2.8 v v ss input 80% 20% t t 500 w +1.4 v i/o cl output relationship between frequency and minimum latency hm5221605 parameter -15 -17 -20 frequency (mhz) t ck (ns) symbol 66 15 33 30 58 17 29 34 50 20 25 40 note active command to column command (same bank) t rcd 21 21 21 1 active command to active command (same bank) t rc 74 74 63 1, = [t ras + t rp ] active command to precharge command (same bank) t ras 53 53 42 1 precharge command to active command (same bank) t rp 21 21 21 1 last data input to precharge command (same bank) t rwl 21 21 21 1 active command to active command (different bank) t rrd 21 21 21 1 last data in to active command (auto precharge, same bank) l apw 42 42 42 = [t rwl + t rp ] self refresh exit to command input l sec 84 84 74 precharge command to high impedance ( cas latency = 1) l hzp 1 1 1 ( cas latency = 2) l hzp 22 22 22 ( cas latency = 3) l hzp 33 33 33 last data out to active command (auto precharge, same bank) ( cas latency = 1) l apr 2 1 1 = [t rp ] ( cas latency = 2,3) l apr 21 10 10 = [t rp ] C 1
hm5221605 series 42 hm5221605 parameter -15 -17 -20 frequency (mhz) t ck (ns) symbol 66 15 33 30 58 17 29 34 50 20 25 40 note last data out to precharge (early precharge) ( cas latency = 1) l ep 0 0 0 ( cas latency = 2) l ep C1 C1 C1 C1 C1 C1 ( cas latency = 3) l ep C2 C2 C2 C2 C2 C2 column command to column command l ccd 11 11 11 write command to data in latency l wcd 00 00 00 dqm to data in l did 00 00 00 dqm to data out l dod 22 22 22 cke to clk disable l cle 11 11 11 register set to active command t rsa 21 21 21 cs to command disable l cdd 00 00 00 power down exit to command input l pec 11 11 11 burst stop to output valid data hold ( cas latency = 1) l bsr 0 0 0 ( cas latency = 2) l bsr 11 11 11 ( cas latency = 3) l bsr 22 22 22 burst stop to output high impedance ( cas latency = 1) l bsh 1 1 1 ( cas latency = 2) l bsh 22 22 22 ( cas latency = 3) l bsh 33 33 33 burst stop to write data ignore l bsw 11 11 11 note: 1. t rcd to t rrd are recommended value.
hm5221605 series 43 timing waveforms read cycle bank 0 active bank 0 read bank 0 precharge clk cke cs t ras t rcd t ch t cs ras cas we a9 a8 address dqmu/l i/o(input) i/o(output) t ch t cs t ckh t t ck t ac t ac ckl t ack t ac t oh t oh t hz t oh t rp t rc burst length = 4 bank0 access = v or v t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ac t lz v ih ih il
hm5221605 series 44 write cycle clk cke cs t ras t rcd ras cas we a9 a8 address dqmu/l i/o(input) i/o(output) t ch t cs t ckh t t ck t dh t dh ckl t dh t dh t ds t ds t ds t ds t rp t rc t rwl bank 0 write t ch t cs bank 0 active bank 0 precharge t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ah t as t ah t as t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as v ih burst length = 4 bank0 access = v or v ih il
hm5221605 series 45 mode register set cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clk cke cs ras cas we a9(bs) address dqmu/l i/o(input) i/o(output) high-z b b+3 b b?1 b?2 b?3 t valid c: b rsa code t rcd t rp precharge if needed mode register set bank 1 active bank 1 read r: b c: b output mask v ih t rcd = 3 cas latency = 3 burst length = 4 = v or v ih il read cycle/write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 cke ras cs cas we address dqmu/l i/o (input) i/o (output) clk a9(bs) r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 bank 0 active bank 0 read bank 1 active bank 1 read bank 1 read bank 1 read bank 0 precharge bank 1 precharge bank 0 active bank 0 write bank 1 active bank 1 write bank 1 write bank 1 write bank 0 precharge bank 1 precharge cke ras cs cas we address dqmu/l i/o (input) i/o (output) a9(bs) high-z high-z v ih v ih read cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il write cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il
hm5221605 series 46 read/single write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:a' r:a c:a c:a a a a a bank 0 active bank 0 read bank 1 active bank 0 write bank 0 precharge bank 1 precharge bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 1 active c:a bank 0 read a a+1 a+2 a+3 bank 0 write bank 0 write cke ras cs cas we address dqmu/l i/o (input) i/o (output) clk a9(bs) cke ras cs cas we address dqmu/l i/o (input) i/o (output) a9(bs) c:b bc a+1 a+3 a+1 a+2 a+3 c:c v ih v ih read/single write ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il
hm5221605 series 47 read/burst write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:a' r:a c:a c:a a a+1 a+2 a+3 a+1 a a+1 a+2 a+3 bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 1 active cke ras cs cas we address dqmu/l i/o (input) i/o (output) clk a9(bs) cke ras cs cas we address dqmu/l i/o (input) i/o (output) a9(bs) a+1 a+2 a+3 a a+3 a bank 0 active bank 0 read bank 1 active clock suspend bank 0 write bank 0 precharge bank 1 precharge v ih read/burst write ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il
hm5221605 series 48 full page read/write cycle high-z 0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 r:a c:a r:b a-2 a-1 a a+1 a+2 r:a c:a r:b high-z a a+1 a+2 a+3 a+1 a+2 a+3 a+4 a+5 a+6 bank 0 active bank 0 read bank 1 active burst stop bank 1 precharge bank 0 active bank 0 write bank 1 active burst stop bank 1 precharge a a+1 a+2 a+3 a+3 a+4 a+6 a+5 cke ras cs cas we address dqmu/l i/o (input) i/o (output) clk a9(bs) cke ras cs cas we address dqmu/l i/o (input) i/o (output) a9(bs) a+4 v ih v ih a+5 read cycle ras - cas delay = 3 cas latency = 3 burst length = full page = v or v ih il write cycle ras - cas delay = 3 cas latency = 3 burst length = full page = v or v ih il auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clk cke cs cas we a9(bs) address dqmu/l i/o(input) i/o(output) high-z rp precharge if needed auto refresh active bank 0 t rc t rc t auto refresh read bank 0 r:a c:a a8=1 ras a a+1 v ih refresh cycle and read cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il
hm5221605 series 49 self refresh cycle clk cke cs ras cas we a9(bs) address dqmu/l i/o(input) i/o(output) precharge command if needed self refresh entry command auto refresh self refresh exit ignore command or no operation cke low a8=1 rc t rp t high-z self refresh cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il clock suspend mode 0123 4 5 6 7 8 9 1011121314151617181920 a a+1 a+2 a+3 b b+1 b+2 r:a c:a r:b c:b a a+1 a+2 b b+1 b+2 b+3 bank0 active active clock suspend start active clock supend end bank0 read bank1 active read suspend start read suspend end bank0 precharge bank1 read earliest bank1 precharge bank0 write bank0 active active clock suspend start active clock suspend end bank1 active write suspend start write suspend end bank1 write bank0 precharge earliest bank1 precharge b+3 cke ras cs cas we address dqmu/l i/o (input) i/o (output) clk a9(bs) cke ras cs cas we address dqmu/l i/o (input) i/o (output) a9(bs) a+3 high-z high-z t cesp t ceh t ces r:a c:a r:b c:b read cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il write cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il
hm5221605 series 50 power down mode clk cke cs ras cas we a9(bs) address dqmu/l i/o (input) i/o (output) precharge command if needed power down entry active bank 0 power down mode exit cke low r: a a8=1 rp t high-z power down cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il
hm5221605 series 51 power up sequence (1) 78910 16 17 18 11 12 13 14 15 auto refresh * bank active if needed rc t rc t auto refresh * valid 0 123456 clk cke cs ras cas we address dqmu/l i/o t valid rsa code t rp all banks precharge mode register set v ih v ih 19 high-z note: set 2 or more auto refresh commands. = v or v ih il power up sequence (2) 78910 16 17 18 11 12 13 14 15 auto refresh * bank active if needed rc t rc t auto refresh * valid 0 123456 clk cke cs ras cas we address dqmu/l i/o t valid rsa t rp all banks precharge mode register set v ih v ih 19 high-z code note: set 8 or more auto refresh commands. = v or v ih il
hm5221605 series 52 package dimensions hm5221605tt series (ttp-50da) 0.13 m 0.10 0.80 50 26 125 20.95 21.35 max 0.30 0.10 1.20 max 10.16 0.13 0.05 11.76 0.20 0.50 0.10 0 ?5 0.94 max 0.17 0.05 0.80 hitachi code jedec eiaj weight (reference value) ttp-50da ? ? 0.51 g 0.25 0.05 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
hm5221605 series 53 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm5221605 series 54 revision record rev. date contents of modification drawn by approved by 0.0 nov. 18, 1993 initial issue s. ishikawa t. kizaki 0.1 sep. 22, 1994 clock frequency: 50/57/66 mhz to 50/58/66 mhz pin functions: change of description simplified state diagram change of order and simplified state diagram addition of note command operation: addition of description dqm truth table and cke truth table: change of description function truth table: addition of note2,3 and description mode register configuration: change of description change of order for burst sequence operation of hm5221605 series: change of description and figures dc characteristics: addition of note2, 3, 4, 5, 6 and 7 i cc1 max: 80/70/65 ma to 85/75/70ma i cc2 max: 25/22/20 ma to 33/30/26ma i cc3 max: 30/26/23 ma to 34/31/26 ma i cc4 (cl = 1)max: 55/50/45 ma to 65/60/50 ma i cc4 (cl = 2)max: 100/90/80 ma to 100/95/80 ma capacitance: addition of note3 ac characteristics: deletion of note4 and 5 relationship between frequency and minimum latency t rc : 8/5/7/4/6/3 to 8/5/7/4/7/4 l sec : 8/5/7/4/6/3 to 8/4/7/4/7/4 addition of l ep (cl = 3): -2/-2/-2/-2/-2/-2 addition of note 1 change of timing waveforms addition of power up sequence change of name for mode register write cycle to mode register set cycle change of name for read/write cycle to read/burst write cycle change of package type: ttp-50d to ttp-50da m.sakamoto t. kizaki 1.0 jun. 20, 1995 operation of hm5221605 series addition of figure for read to write command interval(2) change of description for power-up sequence absolute maximum ratings: addition of note2 relationship between frequency and minimum latency t rc : 8/5/7/4/7/4 to 8/5/8/4/7/4 l sec : 8/5/7/4/7/4 to 8/4/8/4/7/4 addition of l bsr (cl = 3): 2/2/2/2/2/2 timing waveforms addition of power up sequence (2) m.sakamoto t. kizaki
hm5221605 series 55 revision record (cont) rev. date contents of modification drawn by approved by 2.0 nov. 14, 1996 change of format ac characteristics t ckh min: 6/7/8 ns to 4.5/7/8 ns t ckl min: 6/7/8 ns to 4.5/7/8 ns t rp min: 34/34/40 ns to 30/34/40 ns addition of t cehp min 17/19/22 ns addition of notes5, 6 change of note4 relationship between frequency and minimum latency t rc : 8/5/8/4/7/4 to 7/4/7/4/6/3 t rp : 3/2/2/1/2/1 to 2/1/2/1/2/1 l apw : 5/3/4/2/4/2 to 4/2/4/2/4/2 deletion of note2: cl = cas latency m.sakamoto t. kizaki 3.0 nov. 1997 change of subtitle

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