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1 12-bit, 555ksps sar adc isl267452 the isl267452 is a 12-bit, 555ksps sampling sar-type adc featuring excellent linearity over supply and temperature variations, and is drop-in compatible with the ad7452. the robust, fully-differential input offers high impedance to minimize errors due to leakage currents, and the specified measurement accuracy is maintained with inpu t signals up to the supply rails. the reference accepts inputs from 0.1v to 2.2v for 3v operation and 0.1v to 3.5v for 5v operation, which provides design flexibility in a wide variety of applications. the isl267452 also features up to 8kv human body model esd survivability. the serial digital interface is spi compatible and is easily interfaced to all popular fpgas and microcontrollers. power dissipation is 7mw at a sampling rate of 555ksps, and just 5w between conversions utilizing auto power-down mode (with a 5v supply), making the isl267452 an excellent solution for remote industrial sensors and battery-powered instruments. the isl267452 is available in an 8 ld sot-23 package, and is specified for operation over the industrial temperature range (-40c to +85c). features ? drop-in compatible with ad7452 ? differential input (span = 2vref) ? simple spi-compatible serial digital interface ? guaranteed no missing codes ? 555khz sampling rate ? 3v or 5v operation ?low operating current - 1.25ma at 555ksps with 3v supplies - 1.70ma at 555ksps with 5v supplies ? power-down current between conversions: 1a ? excellent differential non-linearity ? low thd: -83db (typ) ? pb-free (rohs compliant) ? available in sot-23 package applications ? remote data acquisition ? battery operated systems ? industrial process control ? energy measurement ? data acquisition systems ? pressure sensors ? flow controllers figure 1. block diagram figure 2. differential linearity error vs code serial interface vdd vref gnd vin+ vin ? sclk sdata cs dac dac sar logic vref -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 code dnl (lsb) july 26, 2012 fn8255.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl267452 2 fn8255.0 july 26, 2012 typical connection diagram pin configuration isl267452 (8 ld sot-23) top view vref vin+ vin? gnd vdd sclk sdata cs vref p-p + +3v/5v supply p/c vref serial interface 10f 0.1f vref p-p 0.1f vref 8 7 6 5 1 2 3 4 vin+ vin ? gnd vdd sclk sdata cs pin descriptions isl267452 description pin name pin number vdd 8 supply voltage, +2.7v to 5.25v. sclk 7 serial clock input. controls digital i/o timing and clocks the conversion. sdata 6 digital conversion output. cs 5 chip select input. controls the start of a conversion. gnd 4 ground vin? 3 negative analog input. vin+ 2 positive analog input. vref 1 reference voltage.
isl267452 3 fn8255.0 july 26, 2012 ordering information part number (notes 1, 2, 3) part marking vdd range (v) temp range (c) package tape & reel (pb-free) pkg. dwg. # isl267452ihz-t 7452 (note 4) 2.7 to 5.25 -40 to +85 8 ld sot-23 p8.064 ISL267452IHZ-T7A 7452 (note 4) 2.7 to 5.25 -40 to +85 8 ld sot-23 p8.064 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materials and nipdau plate -e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free sold ering operations. intersil pb-fr ee products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl267452 . for more information on msl please see techbrief tb363 . 4. the part marking is located on the bottom of the part.
isl267452 4 fn8255.0 july 26, 2012 table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 adc transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 voltage reference input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 short cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 signal-to-(noise + distortion) ratio (sinad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 total harmonic distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 peak harmonic or spurious noise (sfdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 intermodulation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 aperture delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 aperture jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 full power bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 common-mode rejection ratio (cmrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 integral nonlinearity (inl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 differential nonlinearity (dnl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 zero-code error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 positive gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 negative gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 track and hold acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power supply rejection ratio (psrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 p8.064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
isl267452 5 fn8255.0 july 26, 2012 absolute maximum rating s thermal information any pin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v analog input to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to vdd+0.3v digital i/o to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to vdd+0.3v digital input voltage to gnd . . . . . . . . . . . . . . . . . . . . . . .-0.3v to vdd+0.3v maximum current in to any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 8kv machine model (tested per jesd22-a115b) . . . . . . . . . . . . . . . . . 400v charged device model (tested per jesd22-c101e). . . . . . . . . . . . 1.5kv latch up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld sot-23 package (notes 5, 6). . . . . . . . 135 99 operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for jc , the ?case temp? location is taken at the package top center. electrical specifications vdd = +3.0v to +3.6v, f sclk = 10mhz, f s = 555ksps, vref = 2.0v; vdd = +4.75v to +5.25v, f sclk =10mhz, f s = 555ksps, vref = 2.5v; v cm = vref, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions isl267452 units min (note 7) typ max (note 7) dynamic performance sinad signal-to (noise + distortion) ratio f in = 100khz vdd = +4.75v to +5.25v 70.0 71.4 db f in = 100khz vdd = +3.0v to +3.6v 68.5 70.5 db thd total harmonic distortion f in = 100khz vdd = +4.75v to +5.25v -84 -76 db f in = 100khz vdd = +3.0v to +3.6v -84 -74 db sfdr spurious free dynamic range f in = 100khz vdd = +4.75v to +5.25v -87 -76 db f in = 100khz vdd = +3.0v to +3.6v -85 -74 db imd intermodulation distortion 2nd and 3rd order, f in = 90khz, 110khz -95 db tpd aperture delay 1ns tpd aperture jitter 15 ps 3db full power bandwidth @ ?3db 15 mhz dc accuracy nresolution 12 bits inl integral nonlinearity -1 0.4 1 lsb dnl differential nonlinea rity guaranteed no missed codes to 12 bits -0.95 0.3 0.95 lsb offset zero-code error zero volt differential input -6 0.2 6 lsb gain positive gain error vref input range -2 0.1 2 lsb negative gain error -2 0.1 2 lsb analog input (note 8) |ain| full-scale input span 2 x vref vin+ - vin? v vin+, vin? absolute input voltage range v cm = vref vin+ v cm vref/2 v vin? v cm vref/2 v
isl267452 6 fn8255.0 july 26, 2012 i leak input dc leakage current -1 1 a c vin input capacitance track/hold mode 13/5 pf reference input vref vref input voltage range vdd = 3v (1% tolerance for specified performance) 2.0 v vdd = 5v (1% tolerance for specified performance) 2.5 v i leak dc leakage current -1 1 a c vref vref input capacitance track/hold mode 21/18.5 pf logic inputs v ih input high voltage 2.4 v v il input low voltage 0.8 v i leak input leakage current -1 1 a c in input capacitance 10 pf logic outputs v oh output high voltage i source = 200a vdd - 0.3 v v ol output low voltage i sink = 200a 0.4 v i oz floating-state output current -1 1 a c out floating-state output capacitance 10 pf output coding two?s complement conversion rate t conv conversion time f sclk = 10mhz 1.6 s t acq acquisition time 200 ns f max throughput rate 555 ksps power requirements vdd positive supply voltage range 2.7 3.6 v 4.75 5.25 v i dd positive supply input current static 1 a dynamic 3v 1250 a 5v 1700 a power dissipation static mode vdd = 3v 3 w vdd = 5v 5 w dynamic vdd = 3v, f smpl =555ksps 3.75 mw vdd = 5v, f smpl =555ksps 8.5 mw notes: 7. compliance to datasheet limits is assured by one or more methods: produc tion test, characterization and/or design. 8. the absolute voltage applied to each analog input must be between gnd and vdd to guarantee datasheet performance. electrical specifications vdd = +3.0v to +3.6v, f sclk = 10mhz, f s = 555ksps, vref = 2.0v; vdd = +4.75v to +5.25v, f sclk =10mhz, f s = 555ksps, vref = 2.5v; v cm = vref, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions isl267452 units min (note 7) typ max (note 7)
isl267452 7 fn8255.0 july 26, 2012 timing specifications limits established by characterizati on and are not production tested. v dd = 3.0v to 3.6v, f sclk =10mhz, f s = 555ksps, v ref = 2.0v; v dd = 4.75v to 5.25v, f sclk =10mhz, f s = 555ksps, v ref =2.5v; v cm = v ref unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 7) typ max (note 7) units f sclk clock frequency 0.01 10 mhz t sclk clock period 100 ns t acq acquisition time 200 ns t conv conversion time 1.6 s t csw cs pulse width 10 ns t css cs falling edge to s clk falling edge setup time 10 ns t cdv cs falling edge to sdata valid 20 ns t clkdv sclk falling edge to sdata valid 40 ns t sdh sclk falling edge to sdata hold 10 ns t sw sclk pulse width 0.4 x t sclk ns t disable sclk falling edge to sdata disable time (note 9) extrapolated back to true bus relinquish 10 35 ns t quiet quiet time before sample 60 ns note: 9. during characterization, t disable is measured from the rele ase point with a 10pf load (see figure 4) and the equivalent timing using the ad7452 loading (25pf) is calculated. figure 3. serial interface timing diagram sclk sdata 12 3 4 5 16 15 14 t csw t cdv t css t conv 13 00 0 0 msb d0 d1 d2 t quiet t sw t clkdv cs hi-z t acq figure 4. equivalent load circuit output pin c l 10pf vdd 2.85k r l
isl267452 8 fn8255.0 july 26, 2012 typical performance characteristics figure 5. isl267452 sinad vs analog input frequency for various supply voltages figure 6. isl267452 dynamic performance with vdd = 3v figure 7. isl267452 dynamic performance with vdd = 5v figure 8. cmrr vs frequency for vdd = 5v figure 9. typical dnl for the isl267452 for vdd = 5v figure 10. psrr vs supply ripple frequency without supply decoupling 55 60 65 70 75 10 100 1k input frequency (khz) sinad (dbc) 2.7v 3.6v 4.75v 5.25v -160 -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 frequency (khz) amplitude (dbfs) 277.5 8192 point fft f sample = 555ksps f in = 92.5khz sinad = 70.9db thd = 82.9db sfdr = 86.6db -160 -140 -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 frequency (khz) amplitude (dbfs) 277.5 8192 point fft f sample = 555ksps f in = 92.5khz sinad = 71.7db thd = 85db sfdr = 86.2db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10k 100k 1k 10k frequency (hz) cmrr (db) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 code dnl (lsb) -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 600 700 800 900 1000 frequency (khz) 250mv p-p sine wave on vdd no decoupling on vdd psrr (db)
isl267452 9 fn8255.0 july 26, 2012 figure 11. typical inl for the isl267452 for vdd = 5v fi gure 12. change in dnl vs vref for the isl267452 for vdd = 5v figure 13. change in inl vs vref for the isl267452 for vdd = 3v figure 14. change in dnl vs vref for the isl267452 for vdd = 3v figure 15. change in offset error vs reference voltage for vdd = 5v and 3v for the isl267452 figure 16. change in inl vs vref for the isl267452 for vdd = 5v typical performance characteristics (continued) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 code inl (lsb) -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 vref (v) dnl (lsb) neg dnl pos dnl -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 inl (lsb) vref (v) neg inl pos inl -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 vref (v) dnl (lsb) neg dnl pos dnl -2 -1 0 1 2 3 4 5 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 zero code error (lsb) vref (v) 3v 5v -5 -4 -3 -2 -1 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 inl (lsb) vref (v) neg inl pos inl
isl267452 10 fn8255.0 july 26, 2012 functional description the isl267452 is based on a succ essive approximation register (sar) architecture utilizing capacitive charge redistribution digital to analog converters (dacs). figure 19 shows a simplified representation of the converter. during the acquisition phase (acq) the differential input is stored on the sampling capacitors (cs). the comparator is in a balanced state since the switch across its inputs is closed. the si gnal is fully acquired after t acq has elapsed, and the switches then transition to the conversion phase (conv) so the stored voltage may be converted to digital format. the comparator will become unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltag e is not exactly at mid-scale). the comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the msb. the sar logic then forces the capacitive dacs to adjust up or down by one quarter of full-scale by switching in binarily weighted capacitors. again, the comparator output reflects whether the stored voltage is above or below the new value, setting the value of the next lowest bit. this proc ess repeats until all 12 bits have been resolved. an external clock must be applied to the sclk pin to generate a conversion result. the allowable frequency range for sclk is 10khz to 10mhz (555ksps). serial output data is transmitted on the falling edge of sclk. the receiving device (fpga, dsp or microcontroller) may latch the data on the rising edge of sclk to maximize set-up and hold times. a stable, low-noise reference voltage must be applied to the vref pin to set the full-scale input range and common-mode voltage. see ?voltage reference input? on page 11 for more details. adc transfer function the output coding for the isl267452 is twos complement. the first code transition occurs at successive lsb values (i.e., 1 lsb, 2 lsb, and so on). the lsb size of the isl267452 is 2*vref/4096. the ideal transfer characteristic of the isl267452 is shown in figure 20. figure 17. change in enob vs reference voltage for vdd = 5v and 3v for the isl267452 figure 18. histogram of 10,000 conversions of a dc input for the isl267452 with vdd = 5v typical performance characteristics (continued) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 enob (bits) vref (v) 5v 3v 0 10k 20k 30k 40k 50k 60k 70k 2044 2045 2046 2047 2048 2049 2050 code 65,516 codes 10 codes 10 codes hits figure 19. sar adc architectural block diagram vin + vin ? vref acq conv acq acq conv conv dac dac sar logic c s c s figure 20. ideal transf er characteristics 1lsb = 2?vref/4096 100...000 100...001 100...010 111...111 000...000 000...001 011...110 011...111 adc code analog input vin+ ? (vin?) ? vref + ?lsb +vref ? 1?lsb 0v +vref ? 1lsb
isl267452 11 fn8255.0 july 26, 2012 analog input the isl267452 features a fully differential input with a nominal full-scale range equal to twice the applied vref voltage. each input swings vref v p-p , 180 out-of-phase from one another for a total differential input of 2*vref (refer to figure 21). differential signaling offers seve ral benefits over a single-ended input, such as: ? doubling of the full-scale input range (and therefore the dynamic range) ? improved even order harmonic distortion ? better noise immunity due to common mode rejection figure 22 shows the relationship between the reference voltage and the full-scale input range for two different values of vref. note that there is a trade-off between vref and the allowable common mode input voltage (vcm). the full-scale input range is proportional to vref; therefore the vcm range must be limited for larger values of vref in order to keep the absolute maximum and minimum voltages on the vin+ and vin? pins within specification. figures 23 and 24 illustrate this relationship for 5v and 3v operation, respectively. the dashed lines show the theoretical vcm range based solely on keeping the vin+ and vin? pins within the supply rails. additional restrictions are imposed due to the required headroom of the input circuitry, resulting in practical limits shown by the shaded area. voltage reference input an external low-noise reference volt age must be applied to the vref pin to set the full-scale input range of the converter. the reference input accepts voltages ranging from 0.1v to 2.2v for 3v operation and 0.1v to 3.5v for 5v operation. the device is specified with a reference voltage of 2.5v for 5v operation and 2.0v for 3v operation. figures 26 and 27 illustrate possible voltage reference options for the isl267452. figure 26 uses the precision isl21090 voltage reference, which exhibits exceptionally low drift and low noise. the isl21090 must use a power supply greater than 4.7v. the vref input pin of the isl267452 uses very low current, so the decoupling capacitor can be small (0.1f). figure 27 illustrates the isl21010 voltage reference being used with the isl267452. the isl21010 series voltage references have higher noise and drift than the isl26090 devices, but they consume very low operating current and are excellent for battery-powered applications. figure 21. differential input signaling figure 22. relationship between vref and full-scale range isl267452 v cm vref p-p vref p-p vin + vin ? 3.0 5.0 2.0 1.0 4.0 vi n+ vi n? vcm 2.0v p-p vref = 2v 3.0 5.0 2.0 1.0 4.0 vi n+ vi n? vcm 2.5v p-p vref = 2. 5v t v t v figure 23. relationship between vref and vcm for vdd = 5v figure 24. relationship between vref and vcm for vdd = 3v 3.0 5.0 2.0 1.0 4.0 vref vcm 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3.25v 1.75v 4.25v 1.5 2.0 1.0 0.5 vref vcm 0.25 0.50 0.75 1.00 2.5 2.00 1.25 1.50 1.75 2.5 1.0v 2.0v
isl267452 12 fn8255.0 july 26, 2012 converter operation the isl267452 is designed to minimize power consumption by only powering up the sar compar ator during conversion time. when the converter is in track mode (its sample capacitors are tracking the input signal) the sa r comparator is powered down. the state of the converter is dictated by the logic state of cs . when cs is high, the sar comparator is powered down while the sampling capacitor array is tracking the input. when cs transitions low, the capacitor array immediately captures the analog signal that is being tracked. after cs is taken low, the sclk pin is toggled 16 times. for the first 3 clocks, the comparator is powered up and auto-zeroed, then the sar decision process is begun. this process uses 12 sclk cycles. each sar decision is presented to the sdata output on the next clock cycle after the sar decision is performed. the sar process (12 bits) is completed on sclk cycl e 15. at this point in time, the sar comparator is powered down and the capacitor array is placed back into track mode. th e last sar comparator decision is output from sdata on the 16th sclk cycle. when the last data bit is output from sdata, the output switches to a logic 0 until cs is taken high, at which time, the sdata output enters a high-z state. figure 28 on page 13 illustra tes the system timing for the isl267452. figure 25. power consumption vs throughput rate 0.01 0.1 1 10 100 0 50 100 150 200 250 300 350 throughput (ksps) power (mw) vdd = 3v vdd = 5v figure 26. precision voltage reference for +5v supply 1 2 3 4 8 7 6 5 dnc v in comp gnd dnc dnc v out trim 0.1f vdd 0.1f 2.5v vref 0.1f bulk + 5v isl21090 isl267452 figure 27. voltage reference for +3.0v to +3.6v, or for +5v supply vdd 0.1f vref 0.1f bulk + +3.0v to +3.6v isl21010 gnd v in v out 1 2 3 0.1f 1.25, 2.048 or 2.5v or +5v isl267452
isl267452 13 fn8255.0 july 26, 2012 power-on reset when power is first applied, th e isl267452 performs a power-on reset that requires approximately 2.5ms to execute. after this is complete, a single dummy conversion must be executed (by taking cs low) in order to initialize the switched capacitor track and hold. the dummy conversion cycle will take 1.6s with an 10mhz sclk. once the dummy cycle is complete, the adc mode will be determined by the state of cs . regular conversions can be started immediately after this dummy cycle is completed and time has been allowed for proper acquisition. acquisition time to achieve the maximum sample rate (555ksps) in the isl267452 device, the maximum acqu isition time is 200ns. for slower conversion rates, or fo r conversions performed using a slower sclk value than 10mhz, the minimum acquisition time is 200ns. this minimum acquisition time also applies to all the devices if short cycling is utilized. short cycling in cases where a lower resolution conversion is acceptable, cs can be pulled high before all sclk falling edges have elapsed. this is referred to as short cyclin g, and it can be used to further optimize power dissipation. in this mode, a lower resolution result will be output, but the ad c will enter static mode sooner and exhibit a lower average po wer consumption than if the complete conversion cycle were carried out. the minimum acquisition time (t acq ) requirement of 200ns must be met for the next conversion to be valid. application hints grounding and layout the printed circuit board that ho uses the isl267452 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes since it gives the best shielding. digital and an alog ground planes should be joined in only one place, and th e connection should be a star ground point established as close to the gnd pin on the isl267452 as possible. avoid running digital lines under the device, as this will couple noise onto the die. the analog ground plane should be allowed to run under the isl267452 to avoid noise coupling. the power supply lines to the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and anal og signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. figure 28. isl267452 system timing
isl267452 14 fn8255.0 july 26, 2012 terminology signal-to-(noise + distortion) ratio (sinad) this is the measured ratio of sign al-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more le vels, the smaller the quantization noise. the theoretical signal-to-(n oise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by equation 1: thus, for a 12-bit converter, this is 74db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the isl267452, it is defined as equation 2: where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise (sfdr) peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental (also referred to as spurious free dynamic range (sfdr)). normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m and n = 0, 1, 2 or 3. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb ) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ?2fb). the isl267452 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and th ird order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample-to-sample variation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input. common-mode rejection ratio (cmrr) the common-mode rejection ratio is defined as the ratio of the power in the adc output at full-scal e frequency, f, to the power of a 250mv p-p sine wave applied to the common-mode voltage of vin+ and vin? of frequency fs: pf is the power at the frequency f in the adc output; pfs is the power at frequency fs in the adc output. integral nonlinearity (inl) this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero-code error this is the deviation of the midscale code transition (111...111 to 000...000) from the ideal vin+ ? vin? (i.e., 0 lsb). positive gain error this is the deviation of the last code transition (011...110 to 011...111) from the ideal vin+ ? vin? (i.e., +ref ? 1 lsb), after the zero code error has been adjusted out. negative gain error this is the deviation of the first code transition (100...000 to 100...001) from the ideal vin+ ? vi n? (i.e., ? ref + 1 lsb), after the zero code error has been adjusted out. track and hold acquisition time the track and hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to adc vdd supply of frequency f s . the frequency of this input varies from 1khz to 1mhz. pf is the power at frequency f in the adc output; pfs is the power at frequency f s in the adc output. signal-to-(noise + distortion) 6.02 n 1.76 + () db = (eq. 1) (eq. 2) thd db () 20 v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 ++++ v 1 2 ----------------------------------------------------------------------- - log = (eq. 3) cmrr db () 10 pfl pfs ? () log = (eq. 4) psrr db () 10 pf pfs ? () log =
isl267452 15 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8255.0 july 26, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl267452 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 26, 2012 fn8255.0 initial release.
isl267452 16 fn8255.0 july 26, 2012 small outline transistor plastic packages (sot23-8) d e 1 e c l e b c l a2 a a1 c l 0.20 (0.008) m 0.10 (0.004) c c -c- seating plane 1234 5 6 87 e1 c l c view c view c l r1 r 4x 1 4x 1 gauge plane l1 seating l2 c plane c base metal with c1 b1 plating b p8.064 8 lead small outline transistor plastic package symbol inches millimeters notes min max min max a 0.036 0.057 0.90 1.45 - a1 0.000 0.0059 0.00 0.15 - a2 0.036 0.051 0.90 1.30 - b 0.009 0.015 0.22 0.38 - b1 0.009 0.013 0.22 0.33 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 d 0.111 0.118 2.80 3.00 3 e 0.103 0.118 2.60 3.00 - e1 0.060 0.067 1.50 1.70 3 e 0.0256 ref 0.65 ref - e1 0.0768 ref 1.95 ref - l 0.014 0.022 0.35 0.55 4 l1 0.024 ref. 0.60 ref. l2 0.010 ref. 0.25 ref. n8 85 r 0.004 - 0.10 - r1 0.004 0.010 0.10 0.25 0 o 8 o 0 o 8 o - rev. 2 9/03 notes: 1. dimensioning and tolerance per asme y14.5m-1994. 2. package conforms to eiaj sc-74 and jedec mo178ba. 3. dimensions d and e1 are exclusive of mold flash, protrusions, or gate burrs. 4. footlength l measured at reference to gauge plane. 5. ?n? is the number of terminal positions. 6. these dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. controlling dimension: millimeter. converted inch dimensions are for reference only

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