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femtoclocks? crystal-to-hcsl clock generator ics841608i idt ? / ics ? hcsl clock generator 1 ics841608aki rev. a june 18, 2008 g eneral d escription the ics841608i is an optimized pcie and srio clock generator and member of the hiperclocks? family of high-performance clock solutions from idt. the device uses a 25mhz parallel crystal to generate 100mhz and 125mhz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. the device has excellent phase jitter (<1ps rms) suitable for clock components requiring precise and low-jitter pcie or srio or both clock signals. designed for telecom, networking and industrial applications, the ics841608i can also drive the high-speed srio and pcie serdes clock inputs of communication processors, dsps, switches and bridges. f eatures ? eight hcsl outputs: configurable for pcie (100mhz) and srio (125mhz) clock signals ? selectable crystal oscillator interface, 25mhz, 18pf parallel resonant crystal or lvcmos/lvttl single-ended reference clock input ? supports the following output frequencies: 100mhz or 125mhz ? vco: 500mhz ? pll bypass and output enable ? pci express (2.5gb/s) and gen 2 (5 gb/s) jitter compliant ? rms phase jitter @125mhz, using a 25mhz crystal (1.875mhz ? 20mhz): 0.37ps (typical) ? full 3.3v power supply mode ? -40c to 85c ambient operating temperature ? available in both standard and (rohs 5) lead-free (rohs 6) packages hiperclocks? ic s b lock d iagram p in a ssignment 0 1 1 0 m = 20 n 4 5 (default) osc femtoclock pll vco = 500mhz xtal_in xtal_out ref_sel fsel mr/noe iref bypass ref_in pulldown pulldown pulldown pulldown pulldown q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 xtal_in xtal_out mr/noe v dd q0 nq0 q1 nq1 nq4 q4 v dd nq3 q3 nq2 q2 gnd fsel iref bypass v dda ref_sel ref_in v dd gnd v dd nq7 q7 nq6 q6 gnd nq5 q5 ics841608i 32-lead vfqfn 5mm x 5mm x 0.925mm package body k package top view
idt ? / ics ? hcsl clock generator 2 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 1 , n i _ l a t x t u o _ l a t x t u p n i , t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i n i _ l a t x 3e o n / r mt u p n in w o d l l u p e h t , h g i h c i g o l n e h w . e l b a n e t u p t u o w o l e v i t c a . t e s e r r e t s a m h g i h e v i t c a . ) z - i h ( e c n a d e p m i h g i h n i e r a s t u p t u o e h t d n a t e s e r e r a s r e d i v i d l a n r e t n i . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . c 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . n o i t c n u f s u o n o r h c n y s a , 4 1 , 4 1 3 , 4 2 v d d r e w o p. s n i p y l p p u s e r o c 6 , 50 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 8 , 71 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 2 3 , 9 1 , 9d n gr e w o p. d n u o r g y l p p u s r e w o p 1 1 , 0 12 q n , 2 qt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 3 1 , 2 13 q n , 3 qt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 6 1 , 5 14 q n , 4 qt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 15 q n , 5 qt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 1 2 , 0 26 q n , 6 qt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 3 2 , 2 27 q n , 7 qt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 5 2l e s ft u p n in w o d l l u p . a 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f t u p t u o 6 2f e r it u p t u o r o t s i s e r n o i s i c e r p d e x i f l a n r e t x e n a . t u p t u o r o t s i s e r e c n e r e f e r t n e r r u c l s c h 5 7 4 ( r o f d e s u t n e r r u c e c n e r e f e r a s e d i v o r p d n u o r g o t n i p s i h t m o r f ) . s t u p t u o k c o l c x q n / x q e d o m - t n e r r u c l a i t n e r e f f i d 7 2s s a p y bt u p n in w o d l l u p . n o i t c n u f s u o n o r h c n y s a . n o i t a r e p o s s a p y b l l p / n o i t a r e p o l l p s t c e l e s . b 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8 2v a d d r e w o p. n i p y l p p u s g o l a n a 9 2l e s _ f e rt u p n in w o d l l u p . d 3 e l b a t e e s . e c r u o s e c n e r e f e r t u p n i e h t s t c e l e s . t c e l e s e c n e r e f e r . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 3n i _ f e rt u p n in w o d l l u p. t u p n i k c o l c e c n e r e f e r l l p l t t v l / s o m c v l : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r t able 3d. ref_sel f unction t able t able 3c. mr/noe f unction t able t able 3b. bypass f unction t able t u p n i l e s _ f e re c n e r e f e r t u p n i 0) t l u a f e d ( l a t x 1n i _ f e r t u p n i e o n / r mn o i t c n u f 0) t l u a f e d ( d e l b a n e s t u p t u o 1) e c n a d e p m i - h g i h ( d e l b a s i d s t u p t u o , t e s e r e c i v e d t able 3a. fsel f unction t able (f ref = 25mh z ) t u p n is t u p t u o l e s fn 7 : 0 q n / 7 : 0 q 05 ) t l u a f e d ( e i c p ) z h m 0 0 1 ( 5 / o c v 14 o i r s ) z h m 5 2 1 ( 4 / o c v t u p n i s s a p y bn o i t a r u g i f n o c l l p 0) t l u a f e d ( d e l b a n e l l p 1f ( d e s s a p y b l l p t u o f = f e r ) n
idt ? / ics ? hcsl clock generator 3 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 37c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v5%, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i , l e s _ f e r , n i _ f e r , e o n / r m , s s a p y b l e s f v d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i , l e s _ f e r , n i _ f e r , e o n / r m , s s a p y b l e s f v d d v , v 5 6 4 . 3 = n i v 0 =5 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 5 1 . 0 ?3 . 3v d d v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 7 8a m i a d d t n e r r u c y l p p u s g o l a n a 5 1a m
idt ? / ics ? hcsl clock generator 4 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator t able 6. ac c haracteristics , v dd = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 5 / o c v0 0 1z h m 4 / o c v5 2 1z h m t ) ? ( t i j1 e t o n ; ) m o d n a r ( r e t t i j e s a h p s m r ) z h m 0 2 - z h m 5 7 8 . 1 ( , z h m 0 0 19 3 . 0s p ) z h m 0 2 - z h m 5 7 8 . 1 ( , z h m 5 2 17 3 . 0s p t j 2 e t o n ; k a e p - o t - k a e p r e t t i j e s a h p , ) z h m 0 5 ? z h m 2 . 1 ( , z h m 0 0 1 0 1 6 t u p n i l a t s y r c z h m 5 2 , s e l p m a s 6 3 . 4 2s p , ) z h m 5 . 2 6 ? z h m 2 . 1 ( , z h m 5 2 1 0 1 6 t u p n i l a t s y r c z h m 5 2 , s e l p m a s 6 7 . 3 2s p t s m r _ f h _ k l c f e r 3 e t o n ; s m r r e t t i j e s a h p 0 1 , z h m 0 0 1 6 , s e l p m a s t u p n i l a t s y r c z h m 5 2 4 4 . 2 s p s m r 0 1 , z h m 5 2 1 6 , s e l p m a s t u p n i l a t s y r c z h m 5 2 7 3 . 2 s p s m r t ) c c ( t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y c 0 5s p t ) o ( k s5 , 4 e t o n ; w e k s t u p t u o 5 0 1s p e g d e e s i r e t a r 7 , 6 e t o n ; e t a r e g d e g n i s i r 6 . 04s n / v e t a r e g d e l l a f7 , 6 e t o n ; e t a r e g d e g n i l l a f 6 . 04s n / v v b r 8 , 6 e t o n ; e g a t l o v k c a b g n i r 0 0 1 -0 0 1v m v x a m 0 1 , 9 e t o n ; e g a t l o v t u p t u o . x a m e t u l o s b a 0 5 1 1v m v n i m 1 1 , 9 e t o n ; e g a t l o v t u p t u o . n i m e t u l o s b a 0 0 3 -v m v s s o r c ; e g a t l o v g n i s s o r c e t u l o s b a 3 1 , 2 1 , 9 e t o n 0 5 20 5 5v m v s s o r c v f o n o i t a i r a v l a t o t s s o r c ; s e g d e l l a r e v o 4 1 , 2 1 , 9 e t o n 0 4 1v m c d o5 1 , 6 e t o n ; e l c y c y t u d t u p t u o 8 42 5% t e l b a t s 8 , 6 e t o n ; t u p t u o k c o l c e l b a t s p u - r e w o p 0 0 5s p t l e m i t k c o l l l p 0 9s m . z h m 5 2 1 d n a z h m 0 0 1 t a n e k a t e r a s n o i t a c i f i c e p s l l a : e t o n . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n , e t o n n o i t a c i l p p a t d i e e s . n o i t c n u f r e f s n a r t m e t s y s g n i y l p p a r e t f a r e t t i j s m r : 2 e t o n . s t n e m e r i u q e r k c o l c e c n e r e f e r s s e r p x e i c p m u m i x a m . k a e p - o t - k a e p s p 6 8 s i s s e r p x e i c p r o f t i m i l . z h m 6 1 - 5 d n a z h m 6 1 - 8 e r a 2 n e g e i c p r o f 2 h d n a 1 h r o f s e i c n e u q e r f e l o p e h t . n o i t c n u f r e f s n a r t m e t s y s g n i y l p p a r e t f a r e t t i j s m r : 3 e t o n , e t o n n o i t a c i l p p a t d i e e s . s t n e m e r i u q e r k c o l c e c n e r e f e r s s e r p x e i c p . s m r s p 1 . 3 s i 2 n o i t a r e n e g s s e r p x e i c p r o f t i m i l m u m i x a m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 5 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . m r o f e v a w l a i t n e r e f f i d m o r f n e k a t t n e m e r u s a e m : 6 e t o n . ) x q n s u n i m x q m o r f d e v i r e d ( m r o f e v a w l a i t n e r e f f i d e h t n o v m 0 5 1 + o t v m 0 5 1 - m o r f t n e m e r u s a e m : 7 e t o n e h t n o d e r e t n e c s i w o d n i w t n e m e r u s a e m v m 0 0 3 e h t . e m i t l l a f d n a e s i r r o f n o i g e r t n e m e r u s a e m e h t h g u o r h t c i n o t o n o m e b t s u m l a n g i s e h t . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . g n i s s o r c o r e z l a i t n e r e f f i d t : 8 e t o n e l b a t s s i t i e r o f e b s e g d e g n i l l a f / g n i s i r r e t f a e g a t l o v l a i t n e r e f f i d v m 0 5 1 m u m i n i m a n i a t n i a m t s u m k c o l c l a i t n e r e f f i d e h t e m i t e h t s i v e h t o t n i k c a b p o r d o t d e w o l l a b r . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . e g n a r l a i t n e r e f f i d 0 0 1 . m r o f e v a w d e d n e e l g n i s m o r f n e k a t t n e m e r u s a e m : 9 e t o n . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o o h s r e v o g n i d u l c n i e g a t l o v s u o e n a t n a t s n i m u m i x a m e h t s a d e n i f e d : 0 1 e t o n . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o o h s r e d n u g n i d u l c n i e g a t l o v s u o e n a t n a t s n i m u m i n i m e h t s a d e n i f e d : 1 1 e t o n . x q n f o e g d e g n i l l a f e h t s l a u q e x q f o e g d e g n i s i r e h t f o e u l a v e g a t l o v s u o e n a t n a t s n i e h t e r e h w t n i o p g n i s s o r c t a d e r u s a e m : 2 1 e t o n . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . g n i s s o r c s i e g d e h c i h w f o s s e l d r a g e r , t s e h g i h e h t o t t n i o p g n i s s o r c t s e w o l e h t m o r f n o i t a i r a v l a t o t e h t o t s r e f e r : 3 1 e t o n . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t n e m e r u s a e m s i h t r o f s t n i o p g n i s s o r c l l a o t s r e f e r v e h t n i e c n a i r a v d e w o l l a m u m i x a m e h t s i s i h t . x q n g n i l l a f d n a x q g n i s i r f o e g a t l o v g n i s s o r c l l a f o n o i t a i r a v l a t o t e h t s a d e n i f e d : 4 1 e t o n s s o r c . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . m e t s y s r a l u c i t r a p y n a r o f . % 0 5 e b t s u m e l c y c y t u d t u p n i : 5 1 e t o n
idt ? / ics ? hcsl clock generator 5 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator t ypical p hase n oise at 100mh z 100mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.39ps (typical) o ffset f requency (h z ) n oise p ower dbc hz ? ? ? 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.37ps (typical) o ffset f requency (h z ) n oise p ower dbc hz t ypical p hase n oise at 125mh z filter raw phase noise data phase noise result by adding filter to raw data ? ? ? filter raw phase noise data phase noise result by adding filter to raw data
idt ? / ics ? hcsl clock generator 6 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator p arameter m easurement i nformation o utput s kew 3.3v hcsl o utput l oad ac t est c ircuit 3.3v hcsl o utput l oad ac t est c ircuit rms p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t sk(o) qy qx nqy nqx d ifferential m easurement p oints for r ise /f all t ime 475 measurement point 33 100 100 33 measurement point 49.9 49.9 hcsl gnd 2pf 2pf 0v iref 3.3v5% v dd 3.3v5%, v dda d ifferential m easurement p oints for r ingback q - nq -150mv +150mv 0.0v fall edge rate rise edge rate t st able t stable v rb v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v this load condition is used for i dd , t sk(o), and t jit measurements. 475 50 50 hcsl gnd 0v scope iref 3.3v5% v dd 3.3v5%, v dda
idt ? / ics ? hcsl clock generator 7 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator p arameter m easurement i nformation , continued d ifferential m esurement p oints for d uty c ycle p eriod s ingle -e nded m easurement p oints for a bsolute c ross p oint /s wing s ingle -e nded m easurement p oints for d elta c ross p oint nq q v cross_max = 550mv v cross_min = 250mv v max = 1.15v v min = -0.30v q nq v cross_delta = 140mv clock period (differential) positive duty cycle (differential) negative duty cycle (differential) q - nq 0.0v c omposite pcie t ransfer f unction 20 -20 -40 -60 -80 -100 0 10 4 10 5 10 6 10 7 10 8 -3db 1.2mhz -3db 21.9mhz frequency (hz) mag (db) h3(s) * (h1(s) ? h2(s))
idt ? / ics ? hcsl clock generator 8 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the ics841608i provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional10 resistor along with a 10f bypass capacitor be connected to the v dda pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd f igure 2. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p at h in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 2. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadfame base pac kage, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
idt ? / ics ? hcsl clock generator 9 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac couple capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by remov- ing r1 and making r2 50 . f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface xta l _i n xta l _o u t vcc r2 ro r1 zo = 50 rs vcc .1uf v dd v dd zo = ro + rs c rystal i nput i nterface the ics841608i has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 4 below f igure 4. c rystal i npu t i nterface were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. c1 27p x1 18pf parallel crystal c2 27p xtal_out xtal_in
idt ? / ics ? hcsl clock generator 10 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator f igure 5. ics841608i s chematic e xample s chematic e xample figure 5 shows an example of ics841608i application schematic. in this example, the device is operated at v dd = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 = 27pf and c2 = 27pf are recommended for frequency accuracy. for different board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. two examples of hcsl terminations are shown in this schematic. the decoupling capacitors should be located as close as possible to the power pin. i nputs : c rystal i nputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. ref_in i nput for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the ref_in to ground. lvcmos c ontrol p ins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : hcsl o utput s all unused hcsl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. c3 0.1u + - r8 50 vd d x1 25mhz tl4 zo = 50 vd d set logic input to '0' rd2 1k tl3 zo = 50 to logic input pins c1 27pf u1 ics841608i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 xta l _i n xta l _o u t mr/noe vdd q0 nq0 q1 nq1 gnd q2 nq2 q3 nq3 vdd q4 nq4 q5 nq5 gnd q6 nq6 q7 nq7 vdd gn d vdd ref_in ref_sel vd da bypass iref fsel + - r6 50 mr / noe fsel recommended for pci express point-to-point connection vdd=3.3v vdd set logic input to '1' ref_sel r4 33 vdd rd1 not install r1 10 r7 50 vdd vd d vd da c2 27pf (u1:6) ru1 1k logic control input examples (u1:14) vdd tl2 zo = 50 to logic input pins vdd c7 .1uf vd d tl1 zo = 50 18pf vdd r3 33 (u1:31) r5 50 bypass recommended for pci express add-in card vd d ru2 not install c6 .1uf c8 .1uf c4 10u c5 0.1u hcsl termination (u1:24) r2 475 vdd
idt ? / ics ? hcsl clock generator 11 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator r ecommended t ermination figure 6a is the recommended termination for applications which require the receiver and driver to be on a separate pcb. all traces should be 50 impedance. f igure 6a. r ecommended t ermination figure 6b is the recommended termination for applications which require a point to point connection and contain the driver f igure 6b. r ecommended t ermination and receiver on the same pcb. all traces should all be 50 impedance. 0.7v differential hcsl clock driver 0.7v differential hcsl clock driver 0.7v differential hcsl add-in card
idt ? / ics ? hcsl clock generator 12 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics841608i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics841608i is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (87ma + 15ma) = 353.43mw ? power (outputs) max = 44.5mw/loaded output pair if all outputs are loaded, the total power is 8 * 44.5mw = 356mw total power _max (3.465v, with all outputs switching) = 353.43mw + 356mw =709.43 mw 2. junction temperature. junction temperature, tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 37c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.709w * 37c/w = 111.2c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 32-p in vfqfn, f orced c onvection ja vs. air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
idt ? / ics ? hcsl clock generator 13 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 7. hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. the highest power dissipation occurs when v dd is high. power = (v dd_high ? v out ) * i out, since v out = i out * r l = (v dd_high ? i out * r l ) * i out = (3.465v ? 17ma * 50 ) * 17ma total power dissipation per output pair = 44.5mw f igure 7. hcsl d river c ircuit and t ermination v dd v out r l 50 ic ? i out = 17ma r ref = 475 1%
idt ? / ics ? hcsl clock generator 14 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator r eliability i nformation t ransistor c ount the transistor count for ics841608i is: 2785 t able 8. ja vs . a ir f low t able for 32 l ead vfqfn ja vs. air flow (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
idt ? / ics ? hcsl clock generator 15 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator p ackage o utline - k s uffix for 32 l ead vfqfn t able 9. p ackage d imensions reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s 2 - d h h v m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 8 . 0- -0 0 . 1 1 a 0- -5 0 . 0 3 a . f e r 5 2 . 0 b 8 1 . 05 2 . 00 3 . 0 n d 8 n e 8 d c i s a b 0 0 . 5 2 d 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 0 . 5 2 e 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 5 . 0 l 0 3 . 00 4 . 00 5 . 0 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this draw- ing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8 below.
idt ? / ics ? hcsl clock generator 16 ics841608aki rev. a june 18, 2008 ics841608i femtoclocks? crystal-to-hcsl clock generator t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i k a 8 0 6 1 4 8i a 8 0 6 1 4 8 s c in f q f v d a e l 2 3y a r tc 5 8 o t c 0 4 - t i k a 8 0 6 1 4 8i a 8 0 6 1 4 8 s c in f q f v d a e l 2 3l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i k a 8 0 6 1 4 8l i a 8 0 6 1 4 s c in f q f v " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l i k a 8 0 6 1 4 8l i a 8 0 6 1 4 s c in f q f v " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics841608i femtoclocks? crystal-to-hcsl clock generator innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product spe cifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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