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slls585 ? november 2003 1 post office box 655303 ? dallas, texas 75265 1 to 1.6 gigabits per second (gbps) serializer/deserializer (tlk2201b) 1.2 to 1.6 gigabits per second (gbps) serializer/deserializer (tlk2201bi) low power consumption <200 mw at 1.25 gbps lvpecl compatible differential i/o on high speed interface single monolithic pll design support for 10 bit interface or reduced interface 5 bit ddr (double data rate) clocking receiver differential input thresholds 200 mv minimum industrial temperature range from ?40 c to 85 c (tlk2201bi) ieee 802.3 gigabit ethernet compliant advanced 0.25 m cmos technology no external filter capacitors required comprehensive suite of built-in testability ieee 1149.1 jtag support 2.5-v supply voltage for lowest power operation 3.3-v tolerant on lvttl inputs hot plug protection 64-pin vqfp with thermally enhanced package (powerpad ? ) 17 18 19 jtdi sync/pass gnd rd0 rd1 rd2 vdd rd3 rd4 rd5 rd6 vdd rd7 rd8 rd9 gnd 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gnd td0 td1 td2 vdd td3 td4 td5 td6 vdd td7 td8 td9 gnd modesel prbsen 21 22 23 24 vdd rxp 63 62 61 60 59 64 58 txp txn vdda vdda gnda vdda jtrst n los jtdo enable vdd loopen vdd gnd refclk vdd syncen gnd 56 55 54 57 25 26 27 28 29 53 52 testen vdda rxn 51 50 49 30 31 32 rbc1 rbc0 r bcmode gnda jtms tck gndp ll vdd vddpll description the tlk2201b and tlk2201bi gigabit ethernet transceivers provide for ultrahigh-speed full-duplex point-to-point data transmissions. these devices are based on the timing requirements of the 10-bit interface specification by the ieee 802.3 gigabit ethernet specification. the tlk2201b supports data rates from 1.0 gbps through 1.6 gbps and the tlk2201bi supports data rates from 1.2 gbps through 1.6 gbps. copyright ? 2003, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. powerpad is a trademark of texas instruments.
slls585 ? november 2003 2 post office box 655303 ? dallas, texas 75265 description (continued) the primary application of these devices is to provide building blocks for point-to-point baseband data transmission o ver controlled impedance media of 50 ? or 75 ? . the transmission media can be printed-circuit board traces, copper cables or fiber-optical media. the ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. the tlk2201b and tlk2201bi perform the data serialization, deserialization, and clock extraction functions for a physical layer interface device. the transceiver operates at 1.25 gbps (typical), providing up to 1 gbps of data bandwidth over a copper or optical media interface. the tlk2201b and tlk2201bi support both the defined 10-bit interface (tbi) and a reduced 5-bit interface utilizing double data rate (ddr) clocking. in the tbi mode the serializer/deserializer (serdes) accepts 10-bit wide 8b/10b parallel encoded data bytes. the parallel data bytes are serialized and transmitted differentially at pecl compatible voltage levels. the serdes extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. in the ddr mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and falling edge of the reference clock. the data is clocked most significant bit first, (bits 0 ? 4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5 ? 9 of the 8b/10b encoded data) are clocked on the falling edge of the clock. the tlk2201b and tlk2201bi provide a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (prbs) generation and verification. an ieee 1149.1 jtag port is also supported. the tlk2201b and tlk2201bi are housed in a high performance, thermally enhanced, 64-pin vqfp powerpad package. use of the powerpad package does not require any special considerations except to note that the powerpad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. it is recommended that the tlk2201b and tlk2201bi powerpads be soldered to the thermal land on the board. the tlk2201b is characterized for operation from 0 c to 70 c. the tlk2201bi is characterized for operation from ?40 c to 85 c. the tlk2201b and tlk2201bi use a 2.5-v supply. the i/o section is 3.3-v compatible. with the 2.5-v supply the chipset is very power-efficient, dissipating less than 200 mw typical power when operating at 1.25 gbps. the tlk2201b and tlk2201bi are designed to be hot plug capable. a power-on reset causes rbc0, rbc1, the parallel output signal terminals, txp, and txn to be held in high-impedance state. differences between tlk2201b, tlk2201bi, and tnete2201 the tlk2201b and tlk2201bi are the functional equivalent of the tnete2201. there are several dif ferences between the devices as noted below. refer to figure 12 in the application information section for an example of a typical application circuit. the v cc is 2.5 v for the tlk2201b and tlk2201bi vs 3.3 v for tnete2201. the pll filter capacitors on pins 16, 17, 48, and 49 of the tnete2201 are no longer required. the tlk2201b and tlk2201bi uses these pins to provide added test capabilities. the capacitors, if present, do not affect the operation of the device. no pulldown resistors are required on the txp/txn outputs.
slls585 ? november 2003 3 post office box 655303 ? dallas, texas 75265 block diagram 2:1 mux prbs generator 10 bit registers td(0?9) prbsen loopen parallel to serial phase generator clock refclk control logic modesel enable testen interpolator and clock extraction prbs verification serial to parallel and comma detect clock rbc1 rbc0 sync/pass rd(0?9) syncen rbcmode jtag control register jtms jtrstn jtdi tck jtdo 2:1 mux 2:1 mux clock data txp txn rxp rxn los detailed description data transmission these devices support both the defined 10-bit interface (tbi) and a reduced 5-bit interface utilizing ddr clocking. when modesel is low, the tbi mode is selected. when modesel is high, the ddr mode is selected. in the tbi mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data, td0?td9) on the rising edge of refclk. the refclk is also used by the serializer, which multiplies the clock by a factor of 10, providing a signal that is fed to the shift register. the 8b/10b encoded data is transmitted sequentially bit 0 through 9 over the differential high-speed i/o channel. in the ddr mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins td0?td4. in this mode data is aligned to both the rising and falling edges of refclk. the data is then formed into a 10-bit wide word and sent to the serializer. the rising edge refclk clocks in bit 0?4, and the falling edge of refclk clocks in bits 5?9. ( bit 0 is the first bit transmitted).
slls585 ? november 2003 4 post office box 655303 ? dallas, texas 75265 detailed description (continued) transmission latency data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit 9. the minimum latency in tbi mode is 19 bit times. the maximum latency in tbi mode is 20 bit times. the minimum latency in ddr mode is 29 bit times, and maximum latency in ddr mode is 30 bit times. 10 bit code txp, txn td(0?9) refclk t d(tx latency) 10 bit code b9 figure 1. transmitter latency full rate mode data reception the receiver portion deserializes the differential serial data. the serial data is retimed based on an interpolated clock generated from the reference clock. the serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with receive byte clocks (rbc0, rbc1). receiver clock select mode there are two modes of operation for the parallel busses. 1)the 10-bit (tbi) mode and 2) 5-bit (ddr) mode. when in tbi mode, there are two user-selectable clock modes that are controlled by the rbcmode terminal. 1) full-rate clock on rbc0 and 2) half-rate clocks on rbc0 and rbc1. when in the ddr mode, only a full-rate clock is available on rbc0; refer to table 1. table 1. mode selection modesel rbcmode mode frequency (tlk2201b) frequency (tlk2201bi) 0 0 tbi half-rate 100?125 mhz 120?125 mhz 0 1 tbi full-rate 100?160 mhz 120?160 mhz 1 0 ddr 100?125 mhz 120?125 mhz 1 1 ddr 100?125 mhz 120?125 mhz in the half-rate mode, two receive byte clocks (rbc0 and rbc1) are 180 degrees out of phase and operate at one-half the data rate. the clocks are generated by dividing down the recovered clock. the received data is output with respect to the two receive byte clocks (rbc0, rbc1) allowing a protocol device to clock the parallel bytes using the rbc0 and rbc1 rising edges. the outputs to the protocol device, byte 0 of the received data valid on the rising edge of rbc1. refer to the timing diagram shown in figure 2.
slls585 ? november 2003 5 post office box 655303 ? dallas, texas 75265 receiver clock select mode (continued) t d(s) t d(s) t d(h) t d(h) k28.5 dxx.x dxx.x dxx.x k28.5 dxx.x rbc0 rbc1 sync rd(0?9) figure 2. synchronous timing characteristics waveforms (tbi half-rate mode) in the normal-rate mode, only rbc0 is used and operates at full data rate (i.e., 1.25 gbps data rate produces a 125 mhz clock). the received data is output with respect to the rising edge of rbc0. rbc1 is low in this mode. refer to the timing diagram shown in figure 3. t d(h) t d(s) k28.5 dxx.x dxx.x dxx.x k28.5 dxx.x rbc0 sync rd(0?9) figure 3. synchronous timing characteristics waveforms (tbi full-rate mode) in the double data rate mode, the receiver presents the data on both the rising and falling edges of rbc0. rbc1 is low impedance. the data is clocked bit-0 first, and aligned to the rising edge of rbc0. refer to the timing diagram shown in figure 4. k28.5 dxx.x t d(s) t d(h) t d(s) t d(h) k28.5 dxx.x dxx.x dxx.x dxx.x dxx.x k28.5 k28.5 dxx.x bits 0?4 bits 5?9 rbc0 sync rd(0?4) figure 4. synchronous timing characteristics waveforms (ddr mode) the receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. the received serial data rate (rxp and rxn) is at the same baud rate as the transmitted data stream, 0.02% (200 ppm) for proper operation (see page 11).
slls585 ? november 2003 6 post office box 655303 ? dallas, texas 75265 receiver word alignment these devices use the ieee 802.3 gigabit ethernet defined 10-bit k28.5 character (comma character) word alignment scheme. the following sections explain how this scheme works and how it realigns itself. comma character on expected boundary these devices provide 10-bit k28.5 character recognition and word alignment. the 10-bit word alignment is enabled by forcing the syncen terminal high. this enables the function that examines and compares serial input data to the seven bit synchronization pattern. the k28.5 character is defined by the 8-bit/10-bit coding scheme as a pattern consisting of 00 1111 1010 (a negative number beginning with disparity) with the 7 msbs (001 1111), referred to as the comma character. the k28.5 character was implemented specifically for aligning data words. as long as the k28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly aligned and data realignment is not required. figure 2 shows the timing characteristics of rbc0, rbc1, sync and rd0?rd9 while synchronized. (note: the k28.5 character is valid on the rising edge of rbc1). comma character not on expected boundary if synchronization is enabled and a k28.5 character straddles the expected 10-bit word boundary, then word realignment is necessary. realignment or shifting the 10-bit word boundary truncates the character following the misaligned k28.5, but the following k28.5 and all subsequent data is aligned properly as shown in figure 5. the rbc0 and rbc1 pulse widths are stretched or stalled in their current state during realignment. with this design the maximum stretch that occurs is 20 bit times. this occurs during a worst case scenario when the k28.5 is aligned to the falling edge of rbc1 instead of the rising edge. figure 5 shows the timing characteristics of the data realignment. dxx.x k28.5 dxx.x dxx.x k28.5 k28.5 dxx.x dxx.x dxx.x dxx.x dxx.x k28.5 dxx.x dxx.x k28.5 k28.5 dxx.x dxx.x 31 bit times max receive path latency worst case misaligned k28.5 misalignment corrected input data rbc0 rbc1 rd(0?9) sync corrupt data 30 bit times (max) figure 5. word realignment timing characteristics waveforms systems that do not require framed data may disable byte alignment by tying syncen low. when a sync character is detected, the sync signal is brought high and is aligned with the k28.5 character. the duration of the sync pulse is equal to the duration of the data when in tbi mode. when in ddr mode the sync pulse is present for the entire rbc0 period.
slls585 ? november 2003 7 post office box 655303 ? dallas, texas 75265 data reception latency the serial to parallel data latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with rd0 received as first bit. the minimum latency in tbi mode is 21 bit times and the maximum latency is 31 bit times. the minimum latency in ddr mode is 27 bit times and maximum latency is 34 bit times. data reception latency (continued) 10 bit code rxp, rxn rd(0?9) rbc0 10 bit code t d(rx latency) figure 6. receiver latency ? tbi normal mode shown loss of signal detection these devices have a loss of signal (los) detection circuit for conditions where the incoming signal no longer has sufficient voltage level to keep the clock recovery circuit in lock. the los is intended to be an indication of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of signal coding health. under a prbs serial input pattern, los is high for signal amplitudes greater than 150 mv. the los is low for all amplitudes below 50 mv. between 50 mv and 150 mv, los is undetermined. testability the loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. the enable function allows for all circuitry to be disabled so that an iddq test can be performed. the prbs function also allows for a bist( built-in self test). the terminal setting, testen high, enables the test mode. the terminal testen has an internal pulldown resistor, so it defaults to normal operation. the testen is only used for factory testing, and is not intended for the end-user. loopback testing the transceiver can provide a self-test function by enabling (loopen to high level) the internal loopback path. enabling this function causes serial transmitted data to be routed internally to the receiver. the parallel data output can be compared to the parallel input data for functional verification. (the external differential output is held in a high-impedance state during the loopback testing.) enable function when held low, enable disables all quiescent power in both the analog and digital circuitry. this allows an ultralow-power idle state when the link is not active.
slls585 ? november 2003 8 post office box 655303 ? dallas, texas 75265 prbs function these devices have a built-in 2 7 ?1 prbs function. when the prbsen control bit is set high, the prbs test is enabled. a prbs is generated and fed into the 10-bit parallel transmitter input bus. data from the normal parallel input source is ignored during prbs test mode. the prbs pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. the output can be sent to a (bert) bit error rate tester or to the receiver of another tlk2201b or tlk2201bi. since the prbs is not really random and is really a predetermined sequence of ones and zeros, the data can be captured and checked for errors by a bert. these devices also have a built-in bert function on the receiver side that is enabled by prbsen. it can receive a prbs pattern and check for errors, and then reports the errors by forcing the sync/p ass terminal low. when prbs is enabled, rbcmode and modesel are ignored. the device operates in tbi mode with a full-rate clock on rbc0. the prbs testing supports two modes (normal and latched), which are controlled by the syncen input. when syncen is low, the result of the prbs bit error rate test is passed to the sync/pass terminal. when syncen is high the result of the prbs verification is latched on the sync/pass output (i.e., a single failure forces sync/pass to remain low). terminal functions terminal i/o description name no. i/o description signal txp txn 62 61 pecl o differential output transmit. txp and txn are differential serial outputs that interface to a copper or an optical i/f module. txp and txn are put in a high-impedance state when loopen is high and are active when loopen is low. rxp rxn 54 52 pecl i differential input receive. rxp and rxn together are the differential serial input interface from a copper or an optical i/f module. refclk 22 i reference clock. refclk is an external input clock that synchronizes the receiver and transmitter interface (100 mhz to 160 mhz). the transmitter uses this clock to register the input data (td0?td9) for serialization. in the tbi mode that data is registered on the rising edge of refclk. in the ddr mode, the data is registered on both the rising and falling edges of refclk with the most significant bits aligned to the rising edge of refclk. td0?td9 2?4, 6?9, 11?13 i transmit data. when in the tbi mode (modesel = low) these inputs carry 10-bit parallel data output from a protocol device to the transceiver for serialization and transmission. this 10-bit parallel data is clocked into the transceiver on the rising edge of refclk and transmitted as a serial stream with td0 sent as the first bit. when in the ddr mode (modesel = high) only td0?td4 are valid. the 5-bit parallel data is clocked into the transceiver on the rising and falling edge of refclk and transmitted as a serial stream with td0 sent as the first bit. rd0?rd9 45, 44, 43, 41, 40, 39, 38, 36, 35, 34 o receive data. when in tbi mode (modesel = low) these outputs carry 10-bit parallel data output from the transceiver to the protocol layer. the data is referenced to terminals rbc0 and rbc1, depending on the receive clock mode selected. rd0 is the first bit received. when in the ddr mode (modesel = high) only rd0?rd4 are valid. rd5?rd9 are held low. the 5-bit parallel data is clocked out of the transceiver on the rising edge of rbc0. rbc0 rbc1 31 30 o receive byte clock. rbc0 and rbc1 are recovered clocks used for synchronizing the 10-bit output data on rd0?rd9. the operation of these clocks is dependent upon the receive clock mode selected. in the half-rate mode, the 10-bit output data words are valid on the rising edges of rbc0 and rbc1. these clocks are adjusted to half-word boundaries in conjunction with synchronous detect. the clocks are always expanded during data realignment and never slivered or truncated. rbc0 registers bytes 1 and 3 of received data. rbc1 registers bytes 0 and 2 of received data. in the normal rate mode, only rbc0 is valid and operates at 1/10 the serial data rate. data is aligned to the rising edge. in the ddr mode, only rbc0 is valid and operates at 1/10 the serial data rate. data is aligned to both the rising and falling edges.
slls585 ? november 2003 9 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal i/o description name no. i/o description signal (continued) rbcmode 32 i p/d ? receive clock mode select. when rbcmode and modesel are low, half-rate clocks are output on rbc0 and rbc1. when modesel is low and rbcmode is high, a full baud-rate clock is output on rbc0 and rbc1 is held low . when modesel is high, rbcmode is ignored and a full baud-rate clock is output on rbc0 and rbc1 is held low. syncen 24 i p/u ? synchronous function enable. when syncen is high, the internal synchronization function is activated. when this function is activated, the transceiver detects the k28.5 comma character (001 1111 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. when syncen is low, serial input data is unframed in rd0 ? rd9. sync/pass 47 o synchronous detect. the sync output is asserted high upon detection of the comma pattern in the serial data path. sync pulses are output only when syncen is activated (asserted high). in prbs test mode (prbsen=high), sync/pass outputs the status of the prbs test results (high=pass). los 26 o loss of signal. indicates a loss of signal on the high-speed differential inputs rxp and rxn. if magnitude of rxp?rxn > 150 mv, los = 1, valid input signal if magnitude of rxp?rxn < 150 mv and > 50 mv, los is undefined if magnitude of rxp?rxn < 50 mv, los = 0, loss of signal modesel 15 i p/d ? mode select. this terminal selects between the 10-bit interface and a reduced 5-bit ddr interface. when low the 10-bit interface (tbi) is selected. when pulled high, the 5-bit ddr mode is selected. the default mode is the tbi. test loopen 19 i p/d ? loop enable. when loopen is high (active), the internal loop-back path is activated. the transmitted serial data is directly routed to the inputs of the receiv er. this provides a self-test capability in conjunction with the protocol device. the txp and txn outputs are held in a high-impedance state during the loop-back test. loopen is held low during standard operational state with external serial outputs and inputs active. tck 49 i test clock. ieee1149.1 (jtag) jtdi 48 i p/u ? test data input. ieee1149.1 (jtag) jtdo 27 o test data output. ieee1149.1 (jtag) jtrstn 56 i p/u ? reset signal. ieee1149.1 (jtag) jtms 55 i p/u ? test mode select. ieee1149.1 (jtag) enable 28 i p/u ? when this terminal is low, the device is disabled for iddq testing. rd0 ? rd9, rbcn, txp, and txn are high impedance. the pullup and pulldown resistors on any input are disabled. when enable is high, the device operates normally. prbsen 16 i p/d ? prbs enable. when prbsen is high, the prbs generation circuitry is enabled. the prbs verification circuit in the receive side is also enabled. a prbs signal can be fed to the receive inputs and checked for errors, that are reported by the sync/pass terminal indicating low. testen 17 i p/d ? manufacturing test terminal power vdd 5, 10, 20, 23, 29, 37, 42, 50, 63 supply digital logic power. provides power for all digital circuitry and digital i/o buffers. vdda 53, 57, 59, 60 supply analog power. vdda provides power for the high-speed analog circuits, receiver, and transmitter vddpll 18 supply pll power. provides power for the pll circuitry. this terminal requires additional filtering. ? p/d = internal pulldown ? p/u = internal pullup
slls585 ? november 2003 10 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal i/o description name no. i/o description ground gnda 51,58 ground analog ground. gnda provides a ground for the high-speed analog circuits, rx and tx. gnd 1, 14, 21, 25, 33, 46 ground digital logic ground. provides a ground for the logic circuits and digital i/o buffers. gndpll 64 ground pll ground. provides a ground for the pll circuitry. absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? supply voltage, v dd (see note 1) ?0.3 v to 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range at ttl terminals, v i ?0.5 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range at any other terminal ?0.3 v to v dd +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electrostatic discharge cdm: 1 kv, hbm:2 kv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . characterized free-air operating temperature range 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . characterized free-air operating temperature range: tlk2201b 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . tlk2201bi ?40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values, except differential i/o bus voltages, are with respect to network ground terminal. dissipation rating table package t a 25 c power rating operating factor ? above t a = 25 c t a = 70 c power rating rcp64 5.25 w 46.58 mw/ c 2.89 w rcp64 ? 3.17 w 23.70 mw/ c 1.74 w rcp64 # 2.01 w 13.19 mw/ c 1.11 w ? this is the inverse of the traditional junction-to-ambient thermal resistance (r ja ). 2 oz. trace and copper pad with solder. ? 2 oz. trace and copper pad without solder. # standard jedec high-k board note: for more information, refer to ti application note powerpad thermally enhanced package, ti literature number slma002. thermal characteristics parameter test condition min typ max unit board-mounted, no air flow, high conductivity ti recommended test board, chip soldered or greased to thermal land 21.47 r ja junction-to-free-air thermal resistance board-mounted, no air flow, high conductivity ti recommended test board with thermal land but no solder or grease thermal connection to thermal land 42.20 c/w board-mounted, no air flow, jedec test board 75.83 board-mounted, no air flow, high conductivity ti recommended test board, chip soldered or greased to thermal land 0.38 r jc junction-to-case-thermal resistance board-mounted, no air flow, high conductivity ti recommended test board with thermal land but no solder or grease thermal connection to thermal land 0.38 c/w board-mounted, no air flow, jedec test board 7.8
slls585 ? november 2003 11 post office box 655303 ? dallas, texas 75265 recommended operating conditions min nom max unit supply voltage, v dd, v dd(a) 2.3 2.5 2.7 v total supply current i dd, i dd(a) frequency = 1.25 gbps, prbs pattern 80 ma total supply current i dd, i dd(a) frequency = 1.6 gbps, worst case pattern ? 111 ma total power dissipation p d frequency = 1.25 gbps prbs pattern 200 mw total power dissipation p d frequency = 1.6 gbps worst case pattern ? 310 mw total shutdown current i dd, i dd(a) enable = 0, vdda , vdd = 2.7 v 50 a startup lock time, pll v dd, v dd(a) = 2.5 v, en to pll acquire 500 s operating free-air temperature, t a tlk2201b 0 70 c operating free-air temperature, t a tlk2201bi ?40 85 c ? worst case pattern is a pattern that creates a maximum transition density on the serial transceiver. tlk2201b reference clock (refclk) timing requirements over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit frequency minimum data rate typ?0.01% 100 typ?0.01% mhz frequency maximum data rate typ?0.01% 160 typ?0.01% mhz accuracy ?100 100 ppm duty cycle 40% 50% 60% jitter random plus deterministic 40 ps tlk2201bi reference clock (refclk) timing requirements over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit frequency minimum data rate typ?0.01% 120 typ?0.01% mhz frequency maximum data rate typ?0.01% 160 typ?0.01% mhz accuracy ?100 100 ppm duty cycle 40% 50% 60% jitter random plus deterministic 40 ps ttl electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ?400 a v dd ?0.2 2.3 v v ol low-level output voltage i ol = 1 ma gnd 0.25 0.5 v v ih high-level input voltage 1.7 3.6 v v il low-level input voltage 0.8 v i ih input high current v dd = 2.3 v, v in = 2.0 v 40 a i il input low current v dd = 2.3 v, v in = 0.4 v ?40 a c in 4 pf
slls585 ? november 2003 12 post office box 655303 ? dallas, texas 75265 transmitter/receiver characteristics parameter test conditions min typ max unit vod = |txd?txn| rt = 50 ? 600 850 1100 mv vod = |txd?txn| rt = 75 ? 800 1050 1200 mv v (cm) transmit common mode voltage range rt = 50 ? 1000 1250 1400 mv v (cm) transmit common mode voltage range rt = 75 ? 1000 1250 1400 mv receiver input voltage requirement, vid = |rxp ? rxn| 200 1600 mv receiver common mode voltage range, (rxp + rxn)/2 1000 1250 2250 mv i lkg(r) receiver input leakage current ?350 350 a c i receiver input capacitance 2 pf t (tj) serial data total jitter (peak-to-peak) differential output jitter, random + deterministic, prbs pattern, r = 125 mhz 0.24 ui t (dj) serial data deterministic jitter (peak-to-peak) differential output jitter, prbs pattern, r = 125 mhz 0.12 ui t r , t f differential signal rise, fall time (20% to 80%) r l = 50 ? , c l = 5 pf, see figures 7 and 8 100 250 ps serial data jitter tolerance minimum required eye opening, (per ieee-802.3 specification) differential input jitter, random + deterministic, r = 125 mhz 0.25 ui receiver data acquisition lock time from powerup 500 s data relock time from loss of synchronization 1024 bit times t d(tx latency) tx latency tbi modes see figure 1 19 20 ui t d(tx latency) tx latency ddr mode 29 30 ui t d(rx latency) rx latency tbi modes see figure 6 21 31 ui t d(rx latency) rx latency ddr mode 27 34 ui 80% 50% 20% t r t r t f t f 80% 50% 20% v v v v 80% 20% 0 v 1v ?1v tx+ tx? vod figure 7. differential and common-mode output voltage definitions c l 5 pf c l 5 pf 50 ? 50 ? figure 8. transmitter test setup t r t f clock 80% 50% 20% t r t f 2 v 0.8 v data 1.4 v figure 9. ttl data i/o valid levels for ac measurement
slls585 ? november 2003 13 post office box 655303 ? dallas, texas 75265 lvttl output switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t r(rbc) clock rise time 0.3 1.5 ns t f(rbc) clock fall time 80% to 20% output voltage, c = 5 pf (see figure 9) 0.3 1.5 ns t r data rise time 80% to 20% output voltage, c = 5 pf (see figure 9) 0.3 1.5 ns t f data fall time 0.3 1.5 ns t su(d1) data setup time (rd0..rd9), data valid prior to rbc0 rising tbi normal mode (see figure 3) 2.5 ns t h(d1) data hold time (rd0..rd9), data valid after rbc0 rising tbi normal mode (see figure 3) 2 ns t su(d2) data setup time (rd0..rd4) ddr mode, r = 125 mhz (see figure 4) 2 ns t h(d2) data hold time (rd0..rd4) ddr mode, r = 125 mhz (see figure 4) 0.8 ns t su(d3) data setup time (rd0..rd9) tbi half-rate mode, r = 125 mhz (see figure 2) 2.5 ns t h(d3) data hold time (rd0..rd9) tbi half-rate mode, r = 125 mhz (see figure 2) 1.5 ns transmitter timing requirements over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t su(d4) data setup time (td0..td9) tbi modes 1.6 ns t h(d4) data hold time (td0..td9) tbi modes 0.8 ns t su(d5) data setup time (td0..td9) ddr modes 0.7 ns t h(d5) data hold time (td0..td9) ddr modes 0.5 ns t r , t f td[0,9] data rise and fall time see figure 9 2 ns available options package t a plastic quad flat pack (rcp) 0 c to 70 c tlk2201brcp ?40 c to 85 c tlk2201bircp
slls585 ? november 2003 14 post office box 655303 ? dallas, texas 75265 application information 8b/10b transmission code the pcs maps gmii signals into ten-bit code groups and vice versa, using an 8b/10b block coding scheme. the pcs uses the transmission code to improve the transmission characteristics of information to be transferred across the link. the encoding defined by the transmission code ensures that sufficient transitions are present in the phy bit stream to make clock recovery possible in the receiver. such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. the 8b/10b transmission code specified for use has a high transition density, is run length limited, and is dc-balanced. the transition density of the 8b/10b symbols ranges from 3 to 8 transitions per symbol. the definition of the 8b/10b transmission code is specified in ieee 802.3 gigabit ethernet and ansi x3.230-1994 (fc?ph), clause 11. 8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. the bit notation of a,b,c,d,e,f,g,h for an unencoded information octet is used in the description of the 8b/10b transmission code-groups, where a is the lsb. each valid code group has been given a name using the following convention: /dx.y/ for the 256 valid data code-groups and /kx.y/ for the special control code-groups, where y is the decimal value of bits edcba and x is the decimal value of bits hgf (noted as k). thus, an octet value of fe representing a code-group value of k30.7 would be represented in bit notation as 111 11110.
slls585 ? november 2003 15 post office box 655303 ? dallas, texas 75265 application information _ + vdd gnd 5 k ? 7.5 k ? rxp rxn gnd 5 k ? 7.5 k ? vdd z o z o z o z o txp txn transmitter media receiver figure 10. high-speed i/o directly-coupled mode _ + vdd gnd 5 k ? 7.5 k ? rxp rxn gnd 5 k ? 7.5 k ? vdd z o z o z o z o txp txn transmitter media receiver figure 11. high-speed i/o ac-coupled mode
slls585 ? november 2003 16 post office box 655303 ? dallas, texas 75265 application information gnd gnda testen td0?td9 refclk prbsen 17 22 16 syncen 24 sync/pass 47 10 10 rd0?rd9 2 rbc0?rbc1 enable 28 tck 49 jtms 55 jtdi 48 jtrstn 56 jtdo 27 los 26 rbcmode 32 loopen 19 modesel 15 host protocol device jtag controller vdd vdda 2.5 v vddpll gndpll 5 ? at 100 mhz 2.5 v 64 18 62 controlled impedance transmission line txp 61 controlled impedance transmission line txn 54 controlled impedance transmission line rxp 52 controlled impedance transmission line rxn r t r t 50 ? 50 ? tlk2201b tlk2201bi 0.01 f figure 12. typical application circuit (ac mode) designing with powerpad the tlk2201b and tlk2201bi are housed in a high performance, thermally enhanced, 64-pin vqfp (rcp64) powerpad package. use of the powerpad package does not require any special considerations except to note that the powerpad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. therefore, if not implementing powerpad pcb features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed powerpad of connection etches or vias under the package. it is strongly recommended that the powerpad be soldered to the thermal land. the recommended convention, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. although the actual size of the exposed die pad may vary, the minimum size required for the keepout area for the 64-pin pfp powerpad package is 8 mm 8 mm.
slls585 ? november 2003 17 post office box 655303 ? dallas, texas 75265 application information designing with powerpad (continued) it is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the powerpad package. the thermal land varies in size depending on the powerpad package being used, the pcb construction, and the amount of heat that needs to be removed. in addition, the thermal land may or may not contain numerous thermal vias depending on pcb construction. other requirements for thermal lands and thermal vias are detailed in the ti application note powerpad thermally enhanced package application report , ti literature number slma002, available via the ti web pages beginning at url: http://www.ti.com . figure 13. example of a thermal land for the tlk2201b, this thermal land must be grounded to the low-impedance ground plane of the device. this improves not only thermal performance but also the electrical grounding of the device. it is also recommended that the device ground pin landing pads be connected directly to the grounded thermal land. the land size must be as large as possible without shorting device signal pins. the thermal land may be soldered to the exposed powerpad using standard reflow soldering techniques. while the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low-impedance ground plane for the device. more information may be obtained from the ti application note phy layout , ti literature number slla020.
slls585 ? november 2003 18 post office box 655303 ? dallas, texas 75265 mechanical data rcp (s-pqfp-g64) powerpad ? plastic quad flatpack 0,08 m 0,08 0,50 0,25 (see note d) thermal pad gage plane 0,13 nom 0 ? 7 0,75 0,45 0,15 0,05 seating plane 4147711/a 10/98 0,27 33 0,17 16 sq 48 9,80 1 10,20 7,50 typ 49 64 sq 0,85 0,75 11,80 12,20 1,00 max 17 32 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. the package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. this pad is electrically and thermally connected to the backside of the die and possibly selected leads. e. falls within jedec ms-026 powerpad is a trademark of texas instruments.
slls585 ? november 2003 19 post office box 655303 ? dallas, texas 75265 thermal pad mechanical data pptd037 rcp (s?pqfp?g64) powerpad plastic quad flatpack
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tlk2201bircp active hvqfp rcp 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr TLK2201BIRCPG4 active hvqfp rcp 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tlk2201bircpr active hvqfp rcp 64 1000 none cu nipdau level-3-235c-168 hr tlk2201brcp active hvqfp rcp 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tlk2201brcpr active hvqfp rcp 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 4-feb-2005 addendum-page 1
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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