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user?s manual pd789101a pd789101a(a1) pd789121a pd789121a(a1) pd789102a pd789102a(a1) pd789122a pd789122a(a1) pd789104a pd789104a(a1) pd789124a pd789124a(a1) pd789111a pd789111a(a1) pd789131a pd789131a(a1) pd789112a pd789112a(a1) pd789132a pd789132a(a1) pd789114a pd789114a(a1) pd789134a pd789134a(a1) pd78f9116a pd78f9116b(a1) pd78f9136a pd78f9136b(a1) pd78f9116b pd789101a(a2) pd78f9136b pd789121a(a2) pd789101a(a) pd789102a(a2) pd789121a(a) pd789122a(a2) pd789102a(a) pd789104a(a2) pd789122a(a) pd789124a(a2) pd789104a(a) pd789111a(a2) pd789124a(a) pd789131a(a2) pd789111a(a) pd789112a(a2) pd789131a(a) pd789132a(a2) pd789112a(a) pd789114a(a2) pd789132a(a) pd789134a(a2) pd789114a(a) pd789134a(a) pd78f9116b(a) pd78f9136b(a) 2000, 2003 printed in japan document no. u14643ej3v0ud00 (3rd edition) date published march 2005 ns cp(k)
user?s manual u14643ej3v0ud 2 [memo]
user?s manual u14643ej3v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
user?s manual u14643ej3v0ud 4 eeprom and fip are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc.
user?s manual u14643ej3v0ud 5 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of march, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u14643ej3v0ud 6 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
user?s manual u14643ej3v0ud 7 introduction target readers this manual is intended for users who wish to understand the functions of the pd789104a, 789114a, 789124a, 789134a subseries and to design and develop application systems and programs usi ng these microcontrollers. the target devices are shown as follows: ? pd789104a subseries: pd789101a, 789102a, 789104a, 789101a(a), 789102a(a), 789104a(a), 789101a(a1), 789102a(a1), 789104a(a1), 789101a(a2), 789102a(a2), 789104a(a2) ? pd789114a subseries: pd789111a, 789112a, 789114a, 78f9116a, 78f9116b, 789111a(a), 789112a(a), 789114a (a), 78f9116b(a), 789111a(a1), 789112a(a1), 789114a(a1), 78f9116b(a1), 789111a(a2), 789112a(a2), 789114a(a2) ? pd789124a subseries: pd789121a, 789122a, 789124a, 789121a(a), 789122a(a), 789124a(a), 789121a(a1), 789122a(a1), 789124a(a1), 789121a(a2), 789122a(a2), 789124a(a2) ? pd789134a subseries: pd789131a, 789132a, 789134a, 78f9136a, 78f9136b, 789131a(a), 789132a(a), 789134a (a), 78f9136b(a), 789131a(a1), 789132a(a1), 789134a(a1), 78f9136b(a1), 789131a(a2), 789132a(a2), 789134a(a2) the pd789104a/114a/124a/134a subser ies is a generic term for all the target devices in this manual. generic names in this document indicate the following products. [standard quality grade products] pd789101a, 789102a, 789104a, 789111a, 789112a, 789114a, 78f9116a, 78f9116b, 789121a, 789122a, 789124a, 789131a, 789132a, 789134a, 78f9136a, 78f9136b [(a) products] pd789101a(a), 789102a(a), 789104a(a ), 789111a(a), 789112a(a), 789114a(a), 78f9116b(a), 789121a(a), 789122a(a), 789124a(a), 789131a(a), 789132a(a), 789134a(a), 78f 9136b(a) [(a1) products] pd789101a(a1), 789102a(a1), 789104a(a1), 789111a(a1), 789112a(a1), 789114a(a1), 78f9116b(a1), 789121a(a1), 789122a(a1), 789124a(a1), 789131a(a1), 789132a(a1), 789134a(a1), 78f 9136b(a1) [(a2) products] pd789101a(a2), 789102a(a2), 789104a(a2), 789111a(a2), 789112a(a2), 789114a(a2), 789121a(a2), 789122a(a2), 789124a(a2), 789131a(a2), 789132a(a2), 789134a(a2)
user?s manual u14643ej3v0ud 8 [mask rom products] pd789101a, 789102a, 789104a, 789111a, 789112a, 789114a, 789121a, 789122a, 789124a, 789131a, 789132a, 789134a, 789101a(a), 789102a(a), 789104a(a), 789111a(a), 789112a(a), 789114a(a), 789121a(a), 789122a(a), 789124a(a), 789131a(a), 789132a(a), 789134a(a), 789101a(a1), 789102a(a1), 789104a(a1), 789111a(a1), 789112a(a1), 789114a(a1), 789121a(a1), 789122a(a1), 789124a(a1), 789131a(a1), 789132a(a1), 789134a(a1), 789101a(a2), 789102a(a2), 789104a(a2), 789111a(a2), 789112a(a2), 789114a(a2), 789121a(a2), 789122a(a2), 789124a(a2), 789131a(a2), 789132a(a2), 789134a(a2) [flash memory products] pd78f9116a, 78f9116b, 78f9116b (a), 78f9116b(a1), 78f9136a, 78f9136b, 78f9136b (a), 78f9136b(a1) the oscillation frequency of the system clock is regarded as f x for ceramic/crystal oscillation ( pd789104a and 789114a subseries), and regarded as f cc for an rc oscillation ( pd789124a and 789134a subseries). purpose this manual is intended to give users an understanding of the functi ons described in the organization below. organization the pd789104a, 789114a, 789124a, 789134a subseries user?s manual is divided into two parts: this manual and instructions (common to the 78k/0s series). pd789104a, 789114a, 789124a, 789134a subseries user?s manual (this manual) 78k/0s series instructions user?s manual ? pin functions ? internal block functions ? interrupts ? other internal peripheral functions ? electrical specifications ? cpu function ? instruction set ? instruction description
user?s manual u14643ej3v0ud 9 how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. ? when using this manual as a manual for the pd789101a(a), 789102a(a), 789104a(a), 789111a(a), 789112a(a), 789114a (a), 78f9116b(a), 789121a(a), 789122a(a), 789124a(a), 789131a(a), 789132a (a), 789134a(a), 78f9136b(a), 789101a(a1), 789102a(a1), 789104a(a1), 789111a(a1), 789112a(a1), 789114a(a1), 78f9116b(a1), 789121a(a1), 789122a(a1), 789124a(a1), 789131a(a1), 789132a(a1), 789134a(a1), 78f9136b(a1), 789101a(a2), 789102a(a2), 789104a(a2), 789111a(a2), 789112a(a2), 789114a(a2), 789121a(a2), 789122a(a2), 789124a(a2), 789131a(a2), 789132a(a2), and 789134a(a2) only the quality grade, s upply voltage, operating ambient temperature, minimum instruction execution time, and electric al specifications differ from the pd789101a, 789102a, 789104a, 789111a, 789112a, 789114a, 78f9116b, 789121a, 789122a, 789124a, 789131a, 789132a, 789134a, and 78f9136b (refer to 1.10 differences between standard qu ality grade products and (a), (a1), (a2) products , 2.9 differences between sta ndard quality grade products and (a), (a1), (a2) products ). for the (a), (a1), and (a2) products, read the part numbers in chapter 3 to chapter 20 as follows. pd789101a pd789101a(a), 789101a(a1), 789101a(a2) pd789102a pd789102a(a), 789102a(a1), 789102a(a2) pd789104a pd789104a(a), 789104a(a1), 789104a(a2) pd789111a pd789111a(a), 789111a(a1), 789111a(a2) pd789112a pd789112a(a), 789112a(a1), 789112a(a2) pd789114a pd789114a(a), 789114a(a1), 789114a(a2) pd78f9116b pd78f9116b(a), 78f9116b(a1) pd789121a pd789121a(a), 789121a(a1), 789121a(a2) pd789122a pd789122a(a), 789122a(a1), 789122a(a2) pd789124a pd789124a(a), 789124a(a1), 789124a(a2) pd789131a pd789131a(a), 789131a(a1), 789131a(a2) pd789132a pd789132a(a), 789132a(a1), 789132a(a2) pd789134a pd789134a(a), 789134a(a1), 789134a(a2) pd78f9136b pd78f9136b(a), 78f9136b(a1) ? to understand the overall functions in general read this manual in the order of the contents . ? how to interpret register formats the name of a bit whose number is in angle brackets (<>) is reserved in the assembler and is defined as an sfr variable by the #pragma sfr directive for the c compiler. ? to learn the detailed functions of a register whose register name is known refer to appendix c register index . ? to learn the details of the instru ction functions of the 78k/0s series refer to 78k/0s series instructions user ? s manual (u11047e) . ? to know the electrical specifications of the pd789104a/114a/124a/134a subseries refer to chapter 21 to chapter 31 electrical specifications . caution the application examples in this manual are created for ?standard? quality grade products for general electric equi pment. when using the application examples in this manual for purposes whic h require ?special? quality grades, thoroughly examine the quality grade of each part and circuit actually used.
user?s manual u14643ej3v0ud 10 conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789104a, 789114a, 789124a, 789134a subseries user?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to developmen t software tools (user?s manuals) document name document no. operation u16656e language u14877e ra78k0s assembler package structured assembly language u11623e operation u16654e cc78k0s c compiler language u14872e operation u16768e sm78k series ver. 2.52 system simulator external part user open in terface specification u15802e id78k0s-ns ver. 2.52 integrated debugger operation u16584e pm plus ver.5.10 u16569e documents related to development hardware tools (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789136-ns-em1 emulation board u14363e caution the related documen ts listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u14643ej3v0ud 11 documents related to flash memory writing document name document no. pg-fp3 flash memory progr ammer user's manual u13502e pg-fp4 flash memory progr ammer user's manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webs ite (http://www.necel.com/pkg/en/mount/index.html). caution the related documen ts listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u14643ej3v0ud 12 contents chapter 1 general ( pd789104a, 789114a subseries) ........................................................ 24 1.1 expanded-specification products and conventiona l-specification products ...................... 24 1.2 features....................................................................................................................... .................. 25 1.3 applications ................................................................................................................... ............... 25 1.4 ordering information........................................................................................................... ......... 26 1.5 quality grade .................................................................................................................. .............. 27 1.6 pin configuration (top view) ................................................................................................... ... 28 1.7 78k/0s series lineup ........................................................................................................... ........ 30 1.8 block diagram.................................................................................................................. ............. 33 1.9 outline of functions........................................................................................................... .......... 34 1.10 differences between standard quality grade pr oducts and (a), (a1), (a2) products ......... 36 chapter 2 general ( pd789124a, 789134a subseries) ........................................................ 37 2.1 features....................................................................................................................... .................. 37 2.2 applications ................................................................................................................... ............... 37 2.3 ordering information........................................................................................................... ......... 38 2.4 quality grade .................................................................................................................. .............. 39 2.5 pin configuration (top view) ................................................................................................... ... 40 2.6 78k/0s series lineup ........................................................................................................... ........ 42 2.7 block diagram.................................................................................................................. ............. 45 2.8 outline of functions........................................................................................................... .......... 46 2.9 differences between standard quality grade pr oducts and (a), (a1), (a2) products ......... 48 chapter 3 pin functio ns .................................................................................................... ........... 49 3.1 pin function list.............................................................................................................. ............. 49 3.2 description of pin functions................................................................................................... .... 51 3.2.1 p00 to p03 (port 0) ............................................................................................................ .................51 3.2.2 p10, p11 (port 1) .............................................................................................................. ..................51 3.2.3 p20 to p25 (port 2) ............................................................................................................ .................51 3.2.4 p50 to p53 (port 5) ............................................................................................................ .................52 3.2.5 p60 to p63 (port 6) ............................................................................................................ .................52 3.2.6 reset .......................................................................................................................... ......................52 3.2.7 x1, x2 ( pd789104a, 789114a s ubserie s) .......................................................................................52 3.2.8 cl1, cl2 ( pd789124a, 789134a s ubserie s) ...................................................................................52 3.2.9 av dd .............................................................................................................................. .....................52 3.2.10 av ss .............................................................................................................................. .....................52 3.2.11 v dd ............................................................................................................................. ........................52 3.2.12 v ss ............................................................................................................................. ........................52 3.2.13 v pp ( pd78f9116a, 78f9116b, 78f9136a , 78f9136b only).............................................................53 3.2.14 ic0 (pin no.20) (mask rom versi ons onl y)....................................................................................... ..53 3.2.15 ic0 (pins no. 10 and no .21) ..................................................................................................... ...........53 3.3 pin i/o circuits and recommended connection of u nused pins ........................................... 54 chapter 4 cpu archi tecture ................................................................................................. ..... 56 4.1 memory space ................................................................................................................... ........... 56
user?s manual u14643ej3v0ud 13 4.1.1 internal program memory space .................................................................................................. .......60 4.1.2 internal data memory (inter nal high-speed ra m) spac e.....................................................................61 4.1.3 special-function regi ster (sfr ) area........................................................................................... ........61 4.1.4 data memory addre ssing ......................................................................................................... ...........61 4.2 processor registers ............................................................................................................ .........65 4.2.1 control r egister s .............................................................................................................. ...................65 4.2.2 general-purpose regist ers ...................................................................................................... ............67 4.2.3 special-function r egisters (sfrs) .............................................................................................. .........68 4.3 instruction address addressing ................... .............................................................................. 71 4.3.1 relative addressi ng ............................................................................................................ ................71 4.3.2 immediate addressi ng........................................................................................................... ..............72 4.3.3 table indirect addre ssing ...................................................................................................... ..............73 4.3.4 register addressi ng ............................................................................................................ ................73 4.4 operand address addressing .......................................... ........................................................... 74 4.4.1 direct addr essi ng.............................................................................................................. ..................74 4.4.2 short direct addre ssing ........................................................................................................ ...............75 4.4.3 special-function regist er (sfr) addressi ng ..................................................................................... ...76 4.4.4 register addressi ng ............................................................................................................ ................77 4.4.5 register indire ct addre ssing ................................................................................................... ............78 4.4.6 based addr essi ng ............................................................................................................... ................79 4.4.7 stack addr essi ng ............................................................................................................... .................79 chapter 5 port f unctions................................................................................................... .........80 5.1 functions of ports............................................................................................................. ............80 5.2 port configuration.............................................................. ............................................... ............82 5.2.1 port 0 ......................................................................................................................... .........................82 5.2.2 port 1 ......................................................................................................................... .........................83 5.2.3 port 2 ......................................................................................................................... .........................84 5.2.4 port 5 ......................................................................................................................... .........................88 5.2.5 port 6 ......................................................................................................................... .........................89 5.3 port function control registers..... ........................................................................................... ..90 5.4 operation of port functions ......................................... ........................................................... ....93 5.4.1 writing to i/o port............................................................................................................ ....................93 5.4.2 reading from i/o port .......................................................................................................... ...............93 5.4.3 arithmetic operat ion of i/o port ............................................................................................... ............94 chapter 6 clock generator ( pd789104a, 789114a subseries) ......... ...........................95 6.1 function of clock generator.................................................................................................... ....95 6.2 configuration of clock generator .. ............................................................................................. 95 6.3 register controlling clock generator ............................ ............................................................96 6.4 system clock oscillator ........................................................................................................ .......97 6.4.1 system clock oscilla tor ........................................................................................................ ...............97 6.4.2 divi der ........................................................................................................................ ........................99 6.5 operation of clock generator....................................... ............................................................ .100 6.6 changing setting of cpu clock.................................................................................................1 01 6.6.1 time required for s witching cp u clock .......................................................................................... ...101 6.6.2 switching cp u cloc k............................................................................................................ .............101
user?s manual u14643ej3v0ud 14 chapter 7 clock generator ( pd789124a, 789134a subseries) ................................. 102 7.1 function of clock generator .................................................................................................... . 102 7.2 configuration of clock generator . ........................................................................................... 102 7.3 register controlling clock generator............................ .......................................................... 103 7.4 system clock oscillator ........................................................................................................ .... 104 7.4.1 system clock oscilla tor........................................................................................................ ..............104 7.4.2 examples of incorrect resonator connecti on ..................................................................................... 105 7.4.3 divi der........................................................................................................................ .......................106 7.5 operation of clock generator ................................................................................................... 107 7.6 changing setting of cpu clock ................................................................................................ 10 8 7.6.1 time required for s witching cp u clock .......................................................................................... ...108 7.6.2 switching cp u cloc k ............................................................................................................ .............109 chapter 8 16-bit time r 20 ................................................................................................. ........... 110 8.1 16-bit timer 20 functions...................................................................................................... .... 110 8.2 16-bit timer 20 configuration .................................................................................................. . 111 8.3 registers controlling 16-bit timer 20 .............................. ........................................................ 113 8.4 16-bit timer 20 operation...................................................................................................... .... 116 8.4.1 operation as ti mer inte rrupt ................................................................................................... ...........116 8.4.2 operation as timer output ...................................................................................................... ............118 8.4.3 capture oper ation .............................................................................................................. ...............119 8.4.4 16-bit timer c ounter 20 readout ................................................................................................ .........120 8.5 notes on using 16-bit timer 20 ................................................................................................ 1 21 8.5.1 restrictions on rewriting 16- bit compare r egister 20 .........................................................................12 1 chapter 9 8-bit timer/event counter 80 ............... .............................................................. 123 9.1 functions of 8-bit timer/event counter 80 ..................... ........................................................ 123 9.2 8-bit timer/event counter 80 confi guration ........................................................................... 124 9.3 registers controlling 8-bit timer/event counter 80 .... .......................................................... 126 9.4 operation of 8-bit timer/event c ounter 80.............................................................................. 128 9.4.1 operation as in terval timer .................................................................................................... ............128 9.4.2 operation as exter nal event count er ............................................................................................ .....130 9.4.3 operation as s quare-wave output ................................................................................................ .....131 9.4.4 operation as pwm output ........................................................................................................ .........133 9.5 notes on using 8-bit timer/event counter 80 ................ ........................................................ 134 chapter 10 watchdog timer .................................................................................................. ... 136 10.1 functions of watchdog timer................................................................................................... 1 36 10.2 configuration of watchdog timer .. .......................................................................................... 137 10.3 watchdog timer control registers ... ....................................................................................... 138 10.4 operation of watchdog ti mer ................................................................................................... 1 40 10.4.1 operation as watchdog ti mer .................................................................................................... ........140 10.4.2 operation as in terval timer .................................................................................................... ............141 chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) .. ......................... 142 11.1 8-bit a/d converter func tions .................................................................................................. 142 11.2 8-bit a/d converter configuration.................................. .......................................................... 14 2 11.3 registers controlling 8-bit a/d converter ...................... ........................................................ 144
user?s manual u14643ej3v0ud 15 11.4 8-bit a/d converter operation ...................................... ............................................................ .146 11.4.1 basic operation of 8- bit a/d c onverter ......................................................................................... .....146 11.4.2 input voltage and c onversion result ............................................................................................ ......147 11.4.3 operation mode of 8- bit a/d c onverter .......................................................................................... ...149 11.5 notes on using 8-bit a/d converter ............................... ..........................................................150 chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries).. ........................154 12.1 10-bit a/d converter functions........................................ ......................................................... 154 12.2 10-bit a/d converter configuration ................................ ..........................................................154 12.3 registers controlling 10-bit a/d converter ................ .............................................................156 12.4 10-bit a/d converter operation ....................................... .......................................................... 158 12.4.1 basic operation of 10- bit a/d c onverter ........................................................................................ ....158 12.4.2 input voltage and c onversion result ............................................................................................ ......159 12.4.3 operation mode of 10- bit a/d c onverter ......................................................................................... ..161 12.5 notes on using 10-bit a/d converter ............................. ..........................................................162 chapter 13 serial interface 20 ............................... ............................................................. ...166 13.1 functions of serial interface 20.................................... ........................................................... ..166 13.2 serial interface 20 configuration.... .......................................................................................... .166 13.3 serial interface 20 control registers ........................................................................................17 0 13.4 operation of serial interface 20 .................................... ........................................................... ..178 13.4.1 operation stop m ode ............................................................................................................ ............178 13.4.2 asynchronous serial inte rface (uart) mode ....................................................................................17 9 13.4.3 3-wire serial i/o mode......................................................................................................... ..............192 chapter 14 multiplier ....................................................................................................... ............202 14.1 multiplier function ............................................................................................................ ..........202 14.2 multiplier configuratio n....................................................................................................... .......202 14.3 multiplier control register .......................................... .......................................................... .....204 14.4 multiplier operation ........................................................................................................... .........205 chapter 15 interrupt functions ................................... .......................................................... 206 15.1 interrupt function types .................................................. ..................................................... .....206 15.2 interrupt sources and configuration .... ....................................................................................207 15.3 interrupt function control registers .... ....................................................................................209 15.4 interrupt servicing operation ...... ............................................................................................ ..214 15.4.1 non-maskable interrupt request acknowledgment operatio n ............................................................214 15.4.2 maskable interrupt request a cknowledgment operatio n....................................................................216 15.4.3 multiple interr upt serv icing ................................................................................................... .............218 15.4.4 interrupt r equest hol d......................................................................................................... ...............220 chapter 16 standby function...................................... .......................................................... ...221 16.1 standby function and configuration.... ....................................................................................221 16.1.1 standby f uncti on ............................................................................................................... ................221 16.1.2 standby function control register ( pd789104a, 789114a s ubserie s).............................................222 16.2 operation of standby function ............. ....................................................................................2 23 16.2.1 halt mode...................................................................................................................... .................223 16.2.2 stop mode ...................................................................................................................... ................226
user?s manual u14643ej3v0ud 16 chapter 17 reset function .................................................................................................. ..... 229 chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b ......... ........................................... 233 18.1 flash memory characteristics .............................................. .................................................... 2 34 18.1.1 programming environm ent........................................................................................................ ........234 18.1.2 communicati on m ode ............................................................................................................. ..........235 18.1.3 on-board pin proce ssing ........................................................................................................ ...........240 18.1.4 connection when using flash memory writ ing adapt er ...................................................................... 243 chapter 19 mask option (mask rom version). ................................................................. 247 chapter 20 instruction set ................................................................................................. ..... 248 20.1 operation...................................................................................................................... ............... 248 20.1.1 operand identifiers and description met hods .................................................................................... 248 20.1.2 description of ?oper ation? column .............................................................................................. .......249 20.1.3 description of ?flag operation? column......................................................................................... ......249 20.2 operation list ................................................................................................................. ............ 250 20.3 instructions listed by addressing type.................................................................................. 255 chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (expanded-specification products)............. .................................................. 258 chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products)...................................................... 271 chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2) ) .................................. 283 chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) ............................ 294 chapter 25 electrical specifications ( pd78f9116b(a1)) ............................................. 307 chapter 26 electrical specifications ( pd78f9116a) .................................................... 318 chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) ........... ......................................... 330 chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2) ) .................................. 341 chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) ............................ 352 chapter 30 electrical specifications ( pd78f9136b(a1)) ............................................. 364 chapter 31 electrical specifications ( pd78f9136a) .................................................... 375 chapter 32 characteristics curves (reference values) ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) ........... ......................................... 387
user?s manual u14643ej3v0ud 17 chapter 33 characteristics curves (reference values) ( pd78910xa(a1), 78911xa(a1), 78910xa(a 2), 78911xa(a2))...................................390 chapter 34 example of rc os cillator frequency characteristics (reference values) ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a), 78f9136a) ...................................................................................................................... .393 chapter 35 example of rc osci llator frequency characteristics (reference values) ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2))...................................................... ............................................................. 395 chapter 36 package drawing ...................................... ........................................................... ..397 chapter 37 recommended soldering conditions .. .........................................................398 appendix a development tools ............................................................................................... 401 a.1 software package............................................................................................................... .........403 a.2 language processing software........................................... ......................................................40 3 a.3 control software ............................................................................................................... ..........404 a.4 flash memory writing tools ..................................................................................................... .404 a.5 debugging tools (hardware) ..................................................................................................... 405 a.6 debugging tools (software) ............................................. ........................................................ .406 appendix b notes on target system design....................................................................407 appendix c register index .................................................................................................. ........409 c.1 register name index (alphabetical order)................ ...............................................................409 c.2 register symbol index (alphabetical order)............. ...............................................................411 appendix d revision history ................................................................................................ ......413 d.1 major revisions in this edition................................................................................................ .413 d.2 revision history up to previous edition......................... ..........................................................414
user?s manual u14643ej3v0ud 18 list of figures (1/4) figure no. title page 3-1 pin i/o circuits........................................................................................................... ...................................55 4-1 memory map ( pd789101a, 789111a, 789121a , 789131a) .......................................................................56 4-2 memory map ( pd789102a, 789112a, 789122a , 789132a) .......................................................................57 4-3 memory map ( pd789104a, 789114a, 789124a , 789134a) .......................................................................58 4-4 memory map ( pd78f9116a, 78f9116b, 78f 9136a, 78f9136b ) ..............................................................59 4-5 data memory addressing ( pd789101a, 789111a, 789121a , 789131a) ....................................................61 4-6 data memory addressing ( pd789102a, 789112a, 789122a , 789132a) ....................................................62 4-7 data memory addressing ( pd789104a, 789114a, 789124a , 789134a) ....................................................63 4-8 data memory addressing ( pd78f9116a, 78f9116b, 78f 9136a, 78f9136b ) ...........................................64 4-9 program counter configur ation.............................................................................................. ......................65 4-10 program status wo rd confi guratio n......................................................................................... ....................65 4-11 stack pointer configur ation ............................................................................................... ...........................66 4-12 data to be sav ed to sta ck memory.......................................................................................... ....................66 4-13 data to be restor ed from sta ck memory ..................................................................................... ................66 4-14 general-purpose regi ster confi guratio n.................................................................................... ..................67 5-1 port types ................................................................................................................. ...................................80 5-2 block diagram of p00 to p03................................................................................................ ........................82 5-3 block diagram of p10 and p1 1............................................................................................... ......................83 5-4 block diagr am of p20....................................................................................................... ............................84 5-5 block diagr am of p21....................................................................................................... ............................85 5-6 block diagram of p22, p23, and p2 5 ......................................................................................... ..................86 5-7 block diagr am of p24....................................................................................................... ............................87 5-8 block diagram of p50 to p53................................................................................................ ........................88 5-9 block diagram of p60 to p63................................................................................................ ........................89 5-10 port mode r egister format ................................................................................................. .........................91 5-11 format of pull-up resist or option r egister 0 .............................................................................. .................91 5-12 format of pull-up resist or option r egister b2............................................................................. ................92 6-1 block diagram of clock g enerat or ........................................................................................... ....................95 6-2 format of processor clock control regist er ................................................................................. ...............96 6-3 external circuit of system clock oscilla tor................................................................................ ...................97 6-4 examples of incorre ct resonator connec tion ................................................................................ .............98 6-5 switchi ng cpu clock ........................................................................................................ ..........................101 7-1 block diagram of clock g enerat or ........................................................................................... ..................102 7-2 format of processor clock control regist er ................................................................................. .............103 7-3 external circuit of system clock oscilla tor................................................................................ .................104 7-4 examples of incorre ct resonator connec tion ................................................................................ ...........105 7-5 switchi ng cpu clock ........................................................................................................ ..........................109 8-1 block diagram of 16-bit ti mer 20........................................................................................... ....................111
user?s manual u14643ej3v0ud 19 list of figures (2/4) figure no. title page 8-2 format of 16-bit timer mode control r egister 20............................................................................ ..........114 8-3 format of port mode regist er 2 ............................................................................................. ....................115 8-4 settings of 16-bit timer mode control regi ster 20 at timer inte rrupt oper ation .......................................116 8-5 timing of timer in terrupt o peratio n ........................................................................................ ...................117 8-6 settings of 16-bit timer mode control r egister 20 for timer ou tput oper ation .........................................118 8-7 timer out put ti ming........................................................................................................ ...........................118 8-8 settings of 16-bit timer mode control register 20 for capt ure operat ion.................................................119 8-9 capture operation timing (both e dges of cpt20 pin are specif ied) ........................................................119 8-10 16-bit timer count er 20 readout timing .................................................................................... ...............120 9-1 block diagram of 8-bi t timer/event counter 80.............................................................................. ...........125 9-2 format of 8-bit timer mode control r egister 80............................................................................. ...........126 9-3 format of port mode regist er 2 ............................................................................................. ....................127 9-4 interval timer operation timing ............................................................................................ .....................129 9-5 external event counter operation timing (with rising edge specif ied) ....................................................130 9-6 square-wave output timing .................................................................................................. ....................132 9-7 pwm out put ti ming .......................................................................................................... .........................133 9-8 start timing of 8-bit time r count er........................................................................................ ....................134 9-9 external event count er operati on timi ng .................................................................................... ..............134 9-10 timing after writing compar e register duri ng pwm ou tput ................................................................... ..135 10-1 block diagram of watchdog timer........................................................................................... ..................137 10-2 format of timer clock select regi ster 2................................................................................... .................138 10-3 format of watchdog timer mode regist er .................................................................................... ............139 11-1 block diagram of 8-bit a/d c onverter ...................................................................................... ..................142 11-2 format of a/d conver ter mode regi ster 0 ................................................................................... ..............144 11-3 format of analog input channel specification register 0 ................................................................... .......145 11-4 basic operation of 8-bit a/d c onverter.................................................................................... ..................147 11-5 relationship between analog input voltage and a/d conv ersion re sult ...................................................148 11-6 software-start ed a/d conv ersion ........................................................................................... ...................149 11-7 how to reduce current c onsumption in standby mode ......................................................................... ...150 11-8 conversion result readout timing (when c onversion result is undefined va lue) ..................................151 11-9 conversion result readout timing (when conversion result is normal va lue) .......................................151 11-10 analog input pin treat ment............................................................................................... .........................151 11-11 a/d conversion end interr upt request gener ation ti ming ................................................................... .....152 11-12 av dd pin tr eatm ent ................................................................................................................. ..................153 12-1 block diagram of 10-bit a/d c onverter ..................................................................................... .................154 12-2 format of a/d conver ter mode regi ster 0 ................................................................................... ..............156 12-3 format of analog input channel specification register 0 ................................................................... .......157 12-4 basic operation of 10-bit a/d c onverter................................................................................... .................159 12-5 relationship between analog input voltage and a/d conv ersion re sult ...................................................160
user?s manual u14643ej3v0ud 20 list of figures (3/4) figure no. title page 12-6 software-start ed a/d conv ersion........................................................................................... ....................161 12-7 how to reduce current c onsumption in standby mode ......................................................................... ...162 12-8 conversion result readout timing (when c onversion result is undefined va lue) ..................................163 12-9 conversion result readout timing (when conversion result is normal va lue) .......................................163 12-10 analog input pin treat ment ............................................................................................... .........................163 12-11 a/d conversion end interr upt request gener ation ti ming ................................................................... .....164 12-12 av dd pin tr eatm ent................................................................................................................. ...................165 13-1 block diagram of serial inte rface 20 ...................................................................................... ....................167 13-2 baud rate generat or block diagr am ......................................................................................... ................168 13-3 format of serial oper ating mode r egister 20 ............................................................................... .............171 13-4 format of asynchronous serial interface mode register 20 .................................................................. ....172 13-5 format of asynchronous serial interface status regist er 20 ................................................................ .....174 13-6 format of baud rate gener ator control register 20 ......................................................................... ........175 13-7 asynchronous serial interfac e transmit/receive data format ................................................................ ..185 13-8 asynchronous serial interface trans mission completion in terrupt ti ming .................................................187 13-9 asynchronous serial interface rec eption completion in terrupt ti ming......................................................1 88 13-10 receive e rror ti ming..................................................................................................... .............................189 13-11 3-wire serial i/o mode timing ............................................................................................ .......................195 14-1 block diagram of mult iplier ............................................................................................... ..........................203 14-2 format of multiplier control regi ster 0 ................................................................................... ....................204 14-3 multiplier o peration timing............................................................................................... ..........................205 15-1 basic configuration of interrupt function................................................................................. ...................208 15-2 format of interrupt request flag regist er ................................................................................. ................210 15-3 format of interrupt mask flag regist er .................................................................................... ..................211 15-4 format of external in terrupt mode r egister 0.............................................................................. ...............212 15-5 program status wo rd confi guratio n......................................................................................... ..................213 15-6 flowchart from non-maskable interrupt request generation to acknowl edgment .....................................215 15-7 timing of non-maskable in terrupt request acknowl edgment ................................................................... .215 15-8 acknowledging non-mask able interrupt reques t .............................................................................. .........215 15-9 interrupt acknowledgm ent program algorit hm ................................................................................ ...........217 15-10 interrupt request acknowledgment timing (example of mov a,r) ............................................................2 18 15-11 interrupt request acknowledgment timing (when interrupt request flag is generated at last clock during instru ction exec ution) ..........................218 15-12 example of multiple interrupt servic ing .................................................................................. ....................219 16-1 format of oscillation stabiliz ation time sele ct regi ster .................................................................. ..........222 16-2 releasing halt mode by in terrupt .......................................................................................... ..................224 16-3 releasing halt mode by r eset i nput ........................................................................................ .............225 16-4 releasing stop mode by in terrupt.......................................................................................... ..................227 16-5 releasing stop mode by r eset i nput ........................................................................................ ............228
user?s manual u14643ej3v0ud 21 list of figures (4/4) figure no. title page 17-1 block diagram of reset f uncti on ........................................................................................... ....................229 17-2 reset timing by reset input ............................................................................................... ....................230 17-3 reset timing by over flow in wa tchdog ti mer ................................................................................ ...........230 17-4 reset timing by reset input in stop mode .................................................................................. .........230 18-1 environment for writing program to fl ash me mory........................................................................... .........234 18-2 communication mode selection format ....................................................................................... .............236 18-3 example of connection with dedicated flas h progra mmer .................................................................... ..237 18-4 v pp pin connecti on exam ple........................................................................................................ ..............240 18-5 signal conflict (input pi n of serial interf ace) ........................................................................... ...................241 18-6 abnormal operati on of other device ........................................................................................ .................241 18-7 signal conflic t (reset pin) ............................................................................................... ........................242 18-8 example of flash memory writ ing adapter connection when using 3-wire serial i/o mode (sio-ch0) ...243 18-9 example of flash memory writ ing adapter connection when using 3-wire serial i/o mode (sio-ch1) ...244 18-10 example of flash memory writing a dapter connection when us ing uart mode ....................................245 18-11 example of flash memory writing adapt er connection when using pseudo 3-wire mode ......................246 a-1 developm ent t ools .......................................................................................................... ..........................402 b-1 distance between in-circuit emulator and conv ersion a dapter ................................................................ 407 b-2 connection condition of tar get system (n p-h44gb- tq) ........................................................................ .408
user?s manual u14643ej3v0ud 22 list of tables (1/2) table no. title page 1-1 differences between expanded-specification pr oducts and conventional-spec ification products..............24 1-2 differences between standard quality grade products and (a), (a1) , (a2) pr oducts..................................36 2-1 differences between standard quality grade products and (a), (a1) , (a2) pr oducts..................................48 3-1 types of pin i/o circuits and re commended connection of unused pins ...................................................54 4-1 internal rom capac ity ...................................................................................................... ...........................60 4-2 vector table ............................................................................................................... ..................................60 4-3 special-function register list ............................................................................................ .........................69 5-1 port functi ons ............................................................................................................. .................................81 5-2 configurat ion of port...................................................................................................... ...............................82 5-3 port mode register and output latch settings when using al ternate f unctions ........................................90 6-1 configuration of clock g enerat or ........................................................................................... ......................95 6-2 maximum time required for switchi ng cpu clock.............................................................................. ......101 7-1 configuration of clock g enerat or ........................................................................................... ....................102 7-2 maximum time required for switchi ng cpu clock.............................................................................. ......108 8-1 configuration of 16-bit ti mer 20........................................................................................... ......................111 8-2 interval time of 16-bit timer 20 ........................................................................................... ......................116 8-3 settings of capture edge................................................................................................... .........................119 9-1 interval time of 8-bi t timer/event counter 80.............................................................................. ..............123 9-2 square-wave output range of 8-bit timer/event counter 80 ................................................................... 124 9-3 8-bit timer/event c ounter 80 conf igurat ion ................................................................................. ..............124 9-4 interval time of 8-bit timer/event counter 80 (at f x = 5.0 mhz, 10.0 mhz operat ion) ..............................128 9-5 interval time of 8-bit timer/event counter 80 (at f cc = 4.0 mhz o perati on).............................................. 128 9-6 square-wave output range of 8- bit timer/event counter 80 (at f x = 5.0 mhz, 10.0 mhz operation) ......131 9-7 square-wave output range of 8- bit timer/event counter 80 (at f cc = 4.0 mhz o perati on) ..................... 131 10-1 program loop detection time of wa tchdog ti mer............................................................................. ........136 10-2 interv al time............................................................................................................. ..................................136 10-3 configuration of watchdog timer ........................................................................................... ....................137 10-4 program loop detection time of wa tchdog ti mer............................................................................. ........140 10-5 interval time of interval timer ........................................................................................... .........................141 11-1 configuration of 8-bit a/d c onverter ...................................................................................... ....................142 12-1 configuration of 10-bit a/d c onverter ..................................................................................... ...................154
user?s manual u14643ej3v0ud 23 list of tables (2/2) table no. title page 13-1 configuration of serial inte rface 20 ...................................................................................... ......................166 13-2 serial interface 20 operating m ode setti ngs............................................................................... ...............173 13-3 example of relationship be tween system clock and baud ra te ..............................................................17 6 13-4 relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h).......177 13-5 example of relationship be tween system clock and baud ra te ..............................................................18 4 13-6 relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h).......184 13-7 receive e rror c auses ...................................................................................................... ..........................189 15-1 interrupt source list ..................................................................................................... ..............................207 15-2 flags corresponding to interrupt r equest si gnals.......................................................................... ...........209 15-3 time from generation of maskabl e interrupt request to serv icing ........................................................... .216 16-1 halt mode o perating status ................................................................................................ ....................223 16-2 operation after re lease of ha lt mode...................................................................................... ...............225 16-3 stop mode o perating status................................................................................................ ....................226 16-4 operation after re lease of st op mode ...................................................................................... ..............228 17-1 hardware stat us after reset .............................................................................................. .......................231 18-1 differences between flash me mory and mask ro m versi ons ..................................................................23 3 18-2 communication mode list ( pd78f9116a, 78f 9136a) .............................................................................235 18-3 communication mode list ( pd78f9116b, 78f 9136b) .............................................................................235 18-4 pin connec tion li st ....................................................................................................... .............................239 19-1 selection of ma sk option fo r pins ......................................................................................... .....................247 20-1 operand identifiers and descripti on met hods ............................................................................... .............248 37-1 surface mounting type soldering c onditions ............................................................................... ............398
user?s manual u14643ej3v0ud 24 chapter 1 general ( pd789104a, 789114a subseries) 1.1 expanded-specification products and conventional-specification products the expanded-specification products and the conventional-s pecification products indicate the following products. expanded-specification produc ts......... products other than rank note 1 k ? mask rom products ordered on or later than december 1, 2001 (excluding (a1) and (a2) products note 2 ) ? flash memory products shipped on or later than january 1, 2002 (excluding (a1), (a2) products note 2 and the pd78f9116a) conventional-s pecification pr oducts .....rank note 1 k products ? products other than above notes 1. the rank is indicated by the letter at the 5th digit from the left in t he lot number in the package marking. lot number 2. for (a1) and (a2) products, refer to 1.10 differences betw een standard quality grade products and (a), (a1), (a2) products . the operating frequency specification differs between the expanded-specification products and the conventional- specification products as shown in table 1-1. table 1-1. differences between expanded-specification products and conventional-specification products guaranteed operating speed (operating frequency) supply voltage (v dd ) conventional-specification products expanded-specification products 4.5 to 5.5 v 5 mhz (0.4 s) 10 mhz (0.2 s) 3.0 to 5.5 v 5 mhz (0.4 s) 6 mhz (0.33 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) remark the figures in parentheses indicate the minimum instruction execution time. year code week code rank
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 25 1.2 features ? rom and ram capacities item part number program memory data memory (internal high-speed ram) pd789101a, 789111a, 789101a(a), 789111a(a), 789101a(a1), 789111a(a1), 789101a(a2), 789111a(a2) 2 kb pd789102a, 789112a, 789102a(a), 789112a(a), 789102a(a1), 789112a(a1), 789102a(a2), 789112a(a2) 4 kb pd789104a, 789114a, 789104a(a), 789114a(a), 789104a(a1), 789114a(a1), 789104a(a2), 789114a(a2) mask rom 8 kb pd78f9116a, 78f9116b, 78f9116b(a), 78f9116b(a1) flash memory 16 kb 256 bytes ? system clock: crystal/ceramic oscillation ? minimum instruction execution times switchable between high speed (0.2 s) and low speed (0.8 s) (system clock: 10.0 mhz note ) ? 20 i/o ports ? serial interface: 1 channel 3-wire serial i/o mode/uart mode selectable ? 8-bit resolution a/d converter: 4 channels ( pd789104a subseries) ? 10-bit resolution a/d converter: 4 channels ( pd789114a subseries) ? 3 timers ? 16-bit timer: 1 channel ? 8-bit timer/event counter: 1 channel ? watchdog timer: 1 channel ? multiplier: 8 bits 8 bits = 16 bits ? vectored interrupt sources: 10 ? supply voltage ? v dd = 1.8 to 5.5 v ( pd78910xa, 78911xa, 78910xa(a), 78911x a(a), 78f9116a, 78f9116b, 78f9116b(a)) ? v dd = 4.5 to 5.5 v ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2), 78f9116b(a1)) ? operating ambient temperature ? t a = ? 40 to + 85 c ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a), 78f9116a, 78f9116b, 78f9116b(a)) ? t a = ? 40 to +105 c ( pd78f9116b(a1)) ? t a = ? 40 to +110 c ( pd78910xa(a1), 78911xa(a1)) ? t a = ? 40 to +125 c ( pd78910xa(a2), 78911xa(a2)) note when v dd = 4.5 to 5.5 v and for expanded-specification products only 1.3 applications vacuum cleaners, washing machines, re frigerators, battery chargers, etc.
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 26 1.4 ordering information part number package internal rom pd789101amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789102amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789104amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789111amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789112amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789114amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9116amc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f9116bmc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd789101amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789102amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789104amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789111amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789112amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789114amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9116amc-5a4-a 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f9116bmc-5a4-a 30-pin plastic ssop (7.62 mm (300)) flash memory pd789101amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789102amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789104amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789111amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789112amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789114amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9116bmc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd789101amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789102amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789104amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789111amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789112amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789114amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9116bmc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd789101amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789102amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789104amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789111amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789112amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789114amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom remarks 1. indicates rom code suffix. 2. products with additional order code ?-a? are lead-free products.
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 27 1.5 quality grade part number package quality grade pd789101amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789102amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789104amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789111amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789112amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789114amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f9116amc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f9116bmc-5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789101amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789102amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789104amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789111amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789112amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789114amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd78f9116amc-5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd78f9116bmc-5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789101amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789102amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789104amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789111amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789112amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789114amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f9116bmc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd789101amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789102amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789104amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789111amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789112amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789114amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f9116bmc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd789101amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789102amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789104amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789111amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789112amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789114amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special remarks 1. indicates rom code suffix. 2. products with additional order code ?-a? are lead-free products. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 28 1.6 pin configuration (top view) ? 30-pin plastic ssop (7.62 mm (300)) pd789101amc- -5a4 pd789102amc- -5a4 pd789104amc- -5a4 pd789111amc- -5a4 pd789112amc- -5a4 pd789114amc- -5a4 pd78f9116amc-5a4 pd78f9116bmc-5a4 pd789101amc- -5a4-a pd789102amc- -5a4-a pd789104amc- -5a4-a pd789111amc- -5a4-a pd789112amc- -5a4-a pd789114amc- -5a4-a pd78f9116amc-5a4-a pd78f9116bmc-5a4-a pd789101amc(a)- -5a4 pd789102amc(a)- -5a4 pd789104amc(a)- -5a4 pd789111amc(a)- -5a4 pd789112amc(a)- -5a4 pd789114amc(a)- -5a4 pd78f9116bmc(a)-5a4 pd789101amc(a1)- -5a4 pd789102amc(a1)- -5a4 pd789104amc(a1)- -5a4 pd789111amc(a1)- -5a4 pd789112amc(a1)- -5a4 pd789114amc(a1)- -5a4 pd78f9116bmc(a1)-5a4 pd789101amc(a2)- -5a4 pd789102amc(a2)- -5a4 pd789104amc(a2)- -5a4 pd789111amc(a2)- -5a4 pd789112amc(a2)- -5a4 pd789114amc(a2)- -5a4 p23/intp0/cpt20/ss20 p24/intp1/to80/to20 p25/intp2/ti80 av dd p60/ani0 p61/ani1 p62/ani2 p63/ani3 av ss p50 ic0 p51 p52 p53 p00 28 27 26 30 29 25 24 23 22 21 20 19 18 16 p22/si20/r x d20 p21/so20/t x d20 p20/sck20/asck20 p11 p10 v dd v ss x1 x2 ic0 (v pp ) ic0 reset p03 p02 p01 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 cautions 1. connect the ic0 (interna lly connected) pin directly to the v ss pin. 2. connect the av dd pin to the v dd pin. 3. connect the av ss pin to the v ss pin. remark the pin connection in parentheses is intended for the pd78f9116a, 78f9116b, 78f9116b(a), and 78f9116b(a1).
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 29 ani0 to ani3: analog input rxd20: receive data asck20: asynchronous serial input sck20: serial clock av dd : analog power supply si20: serial input av ss : analog ground so20: serial output cpt20: capture trigger input ss20: chip select input ic0: internally connected ti80: timer input intp0 to intp2: external interrupt input to20, to80: timer output p00 to p03: port 0 txd20: transmit data p10, p11: port 1 v dd : power supply p20 to p25: port 2 v pp : programming power supply p50 to p53: port 5 v ss : ground p60 to p63: port 6 x1, x2: crystal 1, 2 reset: reset
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 30 1.7 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 52-pin 52-pin sio and resistance division type lcd (24 4) 8-bit a/d and on-chip voltage booster type lcd (23 4) pd789327 pd789467 pd789446 pd789436 pd789426 pd789306 pd789316 pd789426 with enhanced a/d converter (10 bits) pd789446 with enhanced a/d converter (10 bits) sio, 8-bit a/d, and on-chip voltage booster type lcd (15 4) sio, 8-bit a/d, and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 sio and on-chip voltage booster type lcd (24 4) 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin pd789407a pd789456 lcd drive 80-pin pd789417a pd789407a with enhanced a/d converter (10 bits) sio, 10-bit a/d converter, and on-chip voltage booster type lcd (28 4) 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 80-pin pd789479 pd789489 pd789881 64-pin uart and resistance division type lcd (26 4) products under development products in mass production small-scale package, general-purpose applications 78k/0s series on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock 44-pin small-scale package, general-purpose applications and a/d converter 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 pd789104a pd789114a pd789167 with enhanced a/d converter (10 bits) pd789104a with enhanced timer pd789124a with enhanced a/d converter (10 bits) rc oscillation version of the pd789104a pd789104a with enhanced a/d converter (10 bits) pd789026 with added 8-bit a/d converter and multiplier pd789177y pd789167y y subseries products support smb. 88-pin pd789830 pd789835b 144-pin uart and dot lcd (40 16) uart, 8-bit a/d, and dot lcd (total display output pins: 96) 42-/44-pin 44-pin pd789074 30-pin pd789026 with enhanced timer 30-pin pd789074 with enhanced timer and increased rom, ram capacity pd789088 pd789046 pd789026 usb 44-pin pd789800 for pc keyboard and on-chip usb function inverter control 44-pin pd789842 on-chip inverter controller and uart vfd drive 52-pin pd789871 on-chip vfd controller (total display output pins: 25) keyless entry 20-pin pd789860 pd789861 20-pin on-chip poc and key return circuit rc oscillation version of the pd789860 on-chip bus controller 30-pin pd789850a on-chip can controller meter control pd789052 20-pin pd789860 without eeprom, poc, and lvi pd789062 20-pin rc oscillation version of the pd789052 pd789862 30-pin pd789860 with enhanced timer, added sio, and increased rom, ram capacity 44-pin pd789852 pd789850a with enhanced functions such as timer and a/d converter sensor 20-pin pd789863 on-chip analog macro for sensor 20-pin rc oscillation version of the pd789864 pd789864 remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 31 the major functional differences betwe en the subseries are listed below. series for general-purpose applications and lcd drive timer v dd function subseries name rom capacity 8-bit 16-bit watc h wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks pd789046 16 kb 1 ch pd789026 4 kb to 16 kb 1 ch 34 pd789088 16 kb to 32 kb 3 ch pd789074 2 kb to 8 kb 1 ch 1 ch 1 ch (uart: 1 ch) 24 ? pd789062 rc oscillation version small-scale package, general- purpose applications pd789052 4 kb 2 ch ? ? 1 ch ? ? ? 14 1.8 v ? pd789177 ? 8 ch pd789167 16 kb to 24 kb 3 ch 1 ch 8 ch ? 31 ? pd789134a ? 4 ch pd789124a 4 ch ? rc oscillation version pd789114a ? 4 ch small-scale package, general- purpose applications and a/d converter pd789104a 2 kb to 8 kb 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835b 24 kb to 60 kb 6 ch ? 3 ch 37 1.8 v note pd789830 24 kb 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789489 32 kb to 48 kb ? 8 ch pd789479 24 kb to 48 kb 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 kb to 24 kb 3 ch 7 ch ? 43 pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 kb to 16 kb 6 ch 1 ch (uart: 1 ch) 40 ? pd789316 rc oscillation version pd789306 8 kb to 16 kb 1 ch ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 kb to 24 kb 2 ch ? 1 ch 1 ch ? ? 1 ch 21 1.8 v ? note flash memory version: 3.0 v
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 32 series for assp timer v dd function subseries name rom capacity 8-bit 16-bit watc h wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks usb pd789800 8 kb 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 kb to 16 kb 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? pd789852 24 kb to 32 kb 3 ch ? 8 ch 3 ch (uart: 2 ch) 31 on-chip bus controller pd789850a 16 kb 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 rc oscillation version, on- chip eeprom pd789860 4 kb 2 ch ? ? 14 keyless entry pd789862 16 kb 1 ch 2 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v on-chip eeprom pd789864 on-chip eeprom sensor pd789863 4 kb 1 ch note 2 ? 1 ch ? 4 ch ? 5 1.9 v rc oscillation version, on- chip eeprom vfd drive pd789871 4 kb to 8 kb 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 kb 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 3 ? notes 1. 10-bit timer: 1 channel 2. 12-bit timer: 1 channel 3. flash memory version: 3.0 v
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 33 1.8 block diagram 78k/0s cpu core rom (flash memory) ram v dd v ss ic0 (v pp ) ti80/intp2/p25 8-bit timer/ event counter 80 to80/to20 /intp1/p24 p00 to p03 port 0 p10, p11 port 1 p20 to p25 port 2 p50 to p53 port 5 p60 to p63 port 6 system control to20/to80 /intp1/p24 cpt20/intp0 /ss20/p23 16-bit timer 20 watchdog timer serial interface 20 sck20/asck20 /p20 si20/rxd20/p22 so20/txd20/p21 ss20/intp0 /cpt20/p23 a/d converter ani0/p60 to ani3/p63 av dd av ss reset x1 x2 interrupt control intp0/cpt20 /p23/ss20 intp1/to80 /to20/p24 intp2/ti80/p25 remarks 1. the size of the internal rom varies depending on the product. 2. items in parentheses apply to the pd78f9116a, 78f9116b, 78f9116b(a), and 78f9116b(a1).
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 34 1.9 outline of functions item pd789101a, 789111a, 789101a(a), 789111a(a), 789101a(a1), 789111a(a1), 789101a(a2), 789111a(a2) pd789102a, 789112a, 789102a(a), 789112a(a), 789102a(a1), 789112a(a1), 789102a(a2), 789112a(a2) pd789104a, 789114a, 789104a(a), 789114a(a), 789104a(a1), 789114a(a1), 789104a(a2), 789114a(a2) pd78f9116a, 78f9116b, 78f9116b(a), 78f9116b(a1) mask rom flash memory rom 2 kb 4 kb 8 kb 16 kb internal memory high-speed ram 256 bytes system clock crystal/ceramic oscillation minimum instruction execution time expanded-specification products of the pd78910xa, 78910xa(a), 78911xa, 78911xa(a), 78f9116b, 78f9116b(a) ? 0.2 s/0.8 s (@ system clock: 10.0 mhz operation, v dd = 4.5 to 5.5 v) other ? 0.4 s/1.6 s (@ system clock: 5.0 mhz operation) general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulations (such as set, reset, and test) multiplier 8 bits 8 bits = 16 bits i/o ports total: 20 ? cmos input: 4 ? cmos i/o: 12 ? n-ch open-drain: 4 a/d converter 8-bit resolution 4 channels ( pd789104a subseries) 10-bit resolution 4 channels ( pd789114a subseries) serial interface 3-wire serial i/o mode/uart mode selectable: 1 channel timer 16-bit timer: 1 channel 8-bit timer/event counter: 1 channel watchdog timer: 1 channel timer outputs one output maskable internal: 6, external: 3 vectored interrupts non-maskable internal: 1 supply voltage v dd = 1.8 to 5.5 v ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a), 78f9116a, 78f9116b, 78f9116b(a)) v dd = 4.5 to 5.5 v ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2), 78f9116b(a1)) operating ambient temperature t a = ? 40 to +85 c ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a), 78f9116a, 78f9116b, 78f9116b(a)) t a = ? 40 to +105 c ( pd78f9116b(a1)) t a = ? 40 to +110 c ( pd78910xa(a1), 78911xa(a1)) t a = ? 40 to +125 c ( pd78910xa(a2), 78911xa(a2)) package 30-pin plastic ssop (7.62 mm (300))
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 35 an outline of the timers is shown below. 16-bit timer 20 8-bit timer/event counter 80 watchdog timer interval timer ? 1 channel 1 channel note operating mode external event timer ? 1 channel ? timer output 1 output 1 output ? pwm output ? 1 output ? square-wave output ? 1 output ? capture 1 input ? ? function interrupt sources 1 1 1 note the watchdog timer provides a watchdog timer function and an interval timer function, but only one of the two functions can be used at a time.
chapter 1 general ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 36 1.10 differences between sta ndard quality grade products and (a), (a1), (a2) products the standard quality grade products and the (a), (a1), and (a2) products refer to the following products. [standard quality grade products]... pd789101a, 789102a, 789104a, 789111a, 789112a, 789114a, 78f9116a, 78f9116b [(a) products] .... pd789101a(a), 789102a(a), 789104a(a), 789111a(a ), 789112a(a), 789114a(a), 78f9116b(a) [(a1) products] .... pd789101a(a1), 789102a(a1), 789104a(a1), 789 111a(a1), 789112a(a1), 789114a(a1), 78f9116b(a1) [(a2) products] .... pd789101a(a2), 789102a(a2), 789104a(a2), 789 111a(a2), 789112a(a2), 789114a(a2) the differences between the standard qua lity grade products and the (a), (a 1), and (a2) products are shown in table 1-2. table 1-2. differences between standard qua lity grade products and (a), (a1), (a2) products products item standard quality grade products (a) products (a1) products (a2) products quality grade standard special supply voltage v dd = 1.8 to 5.5 v v dd = 4.5 to 5.5 v operating ambient temperature t a = ? 40 to +85 c ? pd78f9116b(a1) t a = ? 40 to +105 c ? other than pd78f9116b(a1) t a = ? 40 to +110 c t a = ? 40 to +125 c minimum instruction execution time expanded-specification products note : 0.2 s (@ 10.0 mhz operation) conventional-specification products note : 0.4 s (@ 5.0 mhz operation) 0.4 s (@ 5.0 mhz operation) electrical specifications refer to the relevant electrical specifications chapter. note refer to 1.1 expanded-specification products and conventional-specification products .
user?s manual u14643ej3v0ud 37 chapter 2 general ( pd789124a, 789134a subseries) caution all pd789124a, 789134a subseries products are conventional-specification products. no expanded-specification products are available in the pd789124a, 789134a subseries. 2.1 features ? rom and ram capacities item part number program memory data memory (internal high-speed ram) pd789121a, 789131a, 789121a(a), 789131a(a), 789121a(a1), 789131a(a1), 789121a(a2), 789131a(a2) 2 kb pd789122a, 789132a, 789122a(a), 789132a(a), 789122a(a1), 789132a(a1), 789122a(a2), 789132a(a2) 4 kb pd789124a, 789134a, 789124a(a), 789134a(a), 789124a(a1), 789134a(a1), 789124a(a2), 789134a(a2) mask rom 8 kb pd78f9136a, 78f9136b, 78f9136b(a), 78f9136b(a1) flash memory 16 kb 256 bytes ? system clock: rc oscillation ? minimum instruction execution times switchable between high speed (0.5 s) and low speed (2.0 s) (system clock: 4.0 mhz) ? 20 i/o ports ? serial interface: 1 channel 3-wire serial i/o mode/uart mode selectable ? 8-bit resolution a/d converter: 4 channels ( pd789124a subseries) ? 10-bit resolution a/d converter: 4 channels ( pd789134a subseries) ? 3 timers ? 16-bit timer: 1 channel ? 8-bit timer/event counter: 1 channel ? watchdog timer: 1 channel ? multiplier: 8 bits 8 bits = 16 bits ? vectored interrupt sources: 10 ? supply voltage ? v dd = 1.8 to 5.5 v ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a), 78f9136a, 78f9136b, 78f9136b(a) ) ? v dd = 4.5 to 5.5 v ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2), 78f9136b(a1) ) ? operating ambient temperature ? t a = ? 40 to + 85 c ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a), 78f9136a, 78f9136b, 78f9136b(a) ) ? t a = ? 40 to +105 c ( pd78f9136b(a1) ) ? t a = ? 40 to +110 c ( pd78912xa(a1), 78913xa(a1) ) ? t a = ? 40 to +125 c ( pd78912xa(a2), 78913xa(a2) ) 2.2 applications vacuum cleaners, washing machines, re frigerators, battery chargers, etc.
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 38 2.3 ordering information part number package internal rom pd789121amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789122amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789124amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789131amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789132amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789134amc- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9136amc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f9136bmc-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd789121amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789122amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789124amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789131amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789132amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd789134amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9136amc-5a4-a 30-pin plastic ssop (7.62 mm (300)) flash memory pd78f9136bmc-5a4-a 30-pin plastic ssop (7.62 mm (300)) flash memory pd789121amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789122amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789124amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789131amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789132amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789134amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9136bmc(a)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd789121amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789122amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789124amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789131amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789132amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789134amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd78f9136bmc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) flash memory pd789121amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789122amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789124amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789131amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789132amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom pd789134amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) mask rom remarks 1. indicates rom code suffix. 2. products with additional order code ?-a? are lead-free products.
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 39 2.4 quality grade part number package quality grade pd789121amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789122amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789124amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789131amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789132amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd789134amc- -5a4 30-pin plastic ssop (7.62 mm (300)) standard pd78f9136amc-5a4 30-pin plasti c ssop (7.62 mm (300)) standard pd78f9136bmc-5a4 30-pin plasti c ssop (7.62 mm (300)) standard pd789121amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789122amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789124amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789131amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789132amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd789134amc- -5a4-a 30-pin plastic ssop (7.62 mm (300)) standard pd78f9136amc-5a4-a 30-pin plas tic ssop (7.62 mm (300)) standard pd78f9136bmc-5a4-a 30-pin plas tic ssop (7.62 mm (300)) standard pd789121amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789122amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789124amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789131amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789132amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789134amc(a)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f9136bmc(a)-5a4 30-pin plasti c ssop (7.62 mm (300)) special pd789121amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789122amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789124amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789131amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789132amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789134amc(a1)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd78f9136bmc(a1)-5a4 30-pin plastic ssop (7.62 mm (300)) special pd789121amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789122amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789124amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789131amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789132amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special pd789134amc(a2)- -5a4 30-pin plastic ssop (7.62 mm (300)) special remarks 1. indicates rom code suffix. 2. products with additional order code ?-a? are lead-free products. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 40 2.5 pin configuration (top view) ? 30-pin plastic ssop (7.62 mm (300)) pd789121amc- -5a4 pd789122amc- -5a4 pd789124amc- -5a4 pd789131amc- -5a4 pd789132amc- -5a4 pd789134amc- -5a4 pd78f9136amc-5a4 pd78f9136bmc-5a4 pd789121amc- -5a4-a pd789122amc- -5a4-a pd789124amc- -5a4-a pd789131amc- -5a4-a pd789132amc- -5a4-a pd789134amc- -5a4-a pd78f9136amc-5a4-a pd78f9136bmc-5a4-a pd789121amc(a)- -5a4 pd789122amc(a)- -5a4 pd789124amc(a)- -5a4 pd789131amc(a)- -5a4 pd789132amc(a)- -5a4 pd789134amc(a)- -5a4 pd78f9136bmc(a)-5a4 pd789121amc(a1)- -5a4 pd789122amc(a1)- -5a4 pd789124amc(a1)- -5a4 pd789131amc(a1)- -5a4 pd789132amc(a1)- -5a4 pd789134amc(a1)- -5a4 pd78f9136bmc(a1)-5a4 pd789121amc(a2)- -5a4 pd789122amc(a2)- -5a4 pd789124amc(a2)- -5a4 pd789131amc(a2)- -5a4 pd789132amc(a2)- -5a4 pd789134amc(a2)- -5a4 p23/intp0/cpt20/ss20 p24/intp1/to80/to20 p25/intp2/ti80 av dd p60/ani0 p61/ani1 p62/ani2 p63/ani3 av ss p50 ic0 p51 p52 p53 p00 28 27 26 30 29 25 24 23 22 21 20 19 18 16 p22/si20/r x d20 p21/so20/t x d20 p20/sck20/asck20 p11 p10 v dd v ss cl1 cl2 ic0 (v pp ) ic0 reset p03 p02 p01 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 cautions 1. connect the ic0 (interna lly connected) pin directly to the v ss pin. 2. connect the av dd pin to the v dd pin. 3. connect the av ss pin to the v ss pin. remark the pin connection in parentheses is intended for the pd78f9136a, 78f9136b, 78f9136b(a), and 78f9136b(a1).
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 41 ani0 to ani3: analog input reset: reset asck20: asynchronous serial input rxd20: receive data av dd : analog power supply sck20: serial clock av ss : analog ground si20: serial input cl1, cl2: rc oscillator so20: serial output cpt20: capture trigger input ss20: chip select input ic0: internally connected ti80: timer input intp0 to intp2: external interrupt input to20, to80: timer output p00 to p03: port 0 txd20: transmit data p10, p11: port 1 v dd : power supply p20 to p25: port 2 v pp : programming power supply p50 to p53: port 5 v ss : ground p60 to p63: port 6
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 42 2.6 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 52-pin 52-pin sio and resistance division type lcd (24 4) 8-bit a/d and on-chip voltage booster type lcd (23 4) pd789327 pd789467 pd789446 pd789436 pd789426 pd789306 pd789316 pd789426 with enhanced a/d converter (10 bits) pd789446 with enhanced a/d converter (10 bits) sio, 8-bit a/d, and on-chip voltage booster type lcd (15 4) sio, 8-bit a/d, and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 sio and on-chip voltage booster type lcd (24 4) 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin pd789407a pd789456 lcd drive 80-pin pd789417a pd789407a with enhanced a/d converter (10 bits) sio, 10-bit a/d converter, and on-chip voltage booster type lcd (28 4) 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 80-pin pd789479 pd789489 pd789881 64-pin uart and resistance division type lcd (26 4) products under development products in mass production small-scale package, general-purpose applications 78k/0s series on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock 44-pin small-scale package, general-purpose applications and a/d converter 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 pd789104a pd789114a pd789167 with enhanced a/d converter (10 bits) pd789104a with enhanced timer pd789124a with enhanced a/d converter (10 bits) rc oscillation version of the pd789104a pd789104a with enhanced a/d converter (10 bits) pd789026 with added 8-bit a/d converter and multiplier pd789177y pd789167y y subseries products support smb. 88-pin pd789830 pd789835b 144-pin uart and dot lcd (40 16) uart, 8-bit a/d, and dot lcd (total display output pins: 96) 42-/44-pin 44-pin pd789074 30-pin pd789026 with enhanced timer 30-pin pd789074 with enhanced timer and increased rom, ram capacity pd789088 pd789046 pd789026 usb 44-pin pd789800 for pc keyboard and on-chip usb function inverter control 44-pin pd789842 on-chip inverter controller and uart vfd drive 52-pin pd789871 on-chip vfd controller (total display output pins: 25) keyless entry 20-pin pd789860 pd789861 20-pin on-chip poc and key return circuit rc oscillation version of the pd789860 on-chip bus controller 30-pin pd789850a on-chip can controller meter control pd789052 20-pin pd789860 without eeprom, poc, and lvi pd789062 20-pin rc oscillation version of the pd789052 pd789862 30-pin pd789860 with enhanced timer, added sio, and increased rom, ram capacity 44-pin pd789852 pd789850a with enhanced functions such as timer and a/d converter sensor 20-pin pd789863 on-chip analog macro for sensor 20-pin rc oscillation version of the pd789864 pd789864 remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 43 the major functional differences betwe en the subseries are listed below. series for general-purpose applications and lcd drive timer v dd function subseries name rom capacity 8-bit 16-bit watc h wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks pd789046 16 kb 1 ch pd789026 4 kb to 16 kb 1 ch 34 pd789088 16 kb to 32 kb 3 ch pd789074 2 kb to 8 kb 1 ch 1 ch 1 ch (uart: 1 ch) 24 ? pd789062 rc oscillation version small-scale package, general- purpose applications pd789052 4 kb 2 ch ? ? 1 ch ? ? ? 14 1.8 v ? pd789177 ? 8 ch pd789167 16 kb to 24 kb 3 ch 1 ch 8 ch ? 31 ? pd789134a ? 4 ch pd789124a 4 ch ? rc oscillation version pd789114a ? 4 ch small-scale package, general- purpose applications and a/d converter pd789104a 2 kb to 8 kb 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835b 24 kb to 60 kb 6 ch ? 3 ch 37 1.8 v note pd789830 24 kb 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789489 32 kb to 48 kb ? 8 ch pd789479 24 kb to 48 kb 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 kb to 24 kb 3 ch 7 ch ? 43 pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 kb to 16 kb 6 ch 1 ch (uart: 1 ch) 40 ? pd789316 rc oscillation version pd789306 8 kb to 16 kb 1 ch ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 kb to 24 kb 2 ch ? 1 ch 1 ch ? ? 1 ch 21 1.8 v ? note flash memory version: 3.0 v
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 44 series for assp timer v dd function subseries name rom capacity 8-bit 16-bit watc h wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks usb pd789800 8 kb 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 kb to 16 kb 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? pd789852 24 kb to 32 kb 3 ch ? 8 ch 3 ch (uart: 2 ch) 31 on-chip bus controller pd789850a 16 kb 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 rc oscillation version, on- chip eeprom pd789860 4 kb 2 ch ? ? 14 keyless entry pd789862 16 kb 1 ch 2 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v on-chip eeprom pd789864 on-chip eeprom sensor pd789863 4 kb 1 ch note 2 ? 1 ch ? 4 ch ? 5 1.9 v rc oscillation version, on- chip eeprom vfd drive pd789871 4 kb to 8 kb 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 kb 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 3 ? notes 1. 10-bit timer: 1 channel 2. 12-bit timer: 1 channel 3. flash memory version: 3.0 v
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 45 2.7 block diagram 78k/0s cpu core rom (flash memory) ram ti80/intp2/p25 8-bit timer/ event counter 80 to80/to20 /intp1/p24 p00 to p03 port 0 p10, p11 port 1 p20 to p25 port 2 p50 to p53 port 5 p60 to p63 port 6 system control to20/to80 /intp1/p24 cpt20/intp0 /ss20/p23 watchdog timer serial interface 20 sck20/asck20 /p20 si20/rxd20/p22 so20/txd20/p21 ss20/intp0 /cpt20/p23 a/d converter ani0/p60 to ani3/p63 av dd av ss reset cl1 cl2 interrupt control intp0/cpt20 /p23/ss20 intp1/to80 /to20/p24 intp2/ti80/p25 v dd v ss ic0 (v pp ) 16-bit timer 20 remarks 1. the size of the internal rom varies depending on the product. 2. items in parentheses apply to the pd78f9136a, 78f9136b, 78f9136b(a), 78f9136b(a1).
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 46 2.8 outline of functions item pd789121a, 789131a, 789121a(a), 789131a(a), 789121a(a1), 789131a(a1), 789121a(a2), 789131a(a2) pd789122a, 789132a, 789122a(a), 789132a(a), 789122a(a1), 789132a(a1), 789122a(a2), 789132a(a2) pd789124a, 789134a, 789124a(a), 789134a(a), 789124a(a1), 789134a(a1), 789124a(a2), 789134a(a2) pd78f9136a, 78f9136b, 78f9136b(a), 78f9136b(a1) mask rom flash memory rom 2 kb 4 kb 8 kb 16 kb internal memory high-speed ram 256 bytes system clock rc oscillation minimum instruction execution time 0.5/2.0 s (@ system clock: 4.0 mhz operation) general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulations (such as set, reset, and test) multiplier 8 bits 8 bits = 16 bits i/o ports total: 20 ? cmos input: 4 ? cmos i/o: 12 ? n-ch open-drain: 4 a/d converter 8-bit resolution 4 channels ( pd789124a subseries) 10-bit resolution 4 channels ( pd789134a subseries) serial interface 3-wire serial i/o mode/uart mode selectable: 1 channel timer 16-bit timer: 1 channel 8-bit timer/event counter: 1 channel watchdog timer: 1 channel timer outputs one output maskable internal: 6, external: 3 vectored interrupts non-maskable internal: 1 supply voltage v dd = 1.8 to 5.5 v ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a), 78f9136a, 78f9136b, 78f9136b(a)) v dd = 4.5 to 5.5 v ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2), 78f9136b(a1)) operating ambient temperature t a = ? 40 to +85 c ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a), 78f9136a, 78f9136b, 78f9136b(a)) t a = ? 40 to +105 c ( pd78f9136b(a1)) t a = ? 40 to +110 c ( pd78912xa(a1), 78913xa(a1)) t a = ? 40 to +125 c ( pd78912xa(a2), 78913xa(a2)) package 30-pin plastic ssop (7.62 mm (300))
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 47 an outline of the timers is shown below. 16-bit timer 20 8-bit timer/event counter 80 watchdog timer interval timer ? 1 channel 1 channel note operating mode external event timer ? 1 channel ? timer output 1 output 1 output ? pwm output ? 1 output ? square-wave output ? 1 output ? capture 1 input ? ? function interrupt sources 1 1 1 note the watchdog timer provides a watchdog timer function and an interval timer function, but only one of the two functions can be used at a time.
chapter 2 general ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 48 2.9 differences between standa rd quality grade products and (a), (a1), (a2) products the standard quality grade products and the (a), (a1), and (a2) products refer to the following products. [standard quality grade products]... pd789121a, 789122a, 789124a, 789131a, 789132a, 789134a, 78f9136a, 78f9136b [(a) products] .... pd789121a(a), 789122a(a), 789124a(a), 789131a(a ), 789132a(a), 789134a(a) , 78f9136b(a) [(a1) products] .... pd789121a(a1), 789122a(a1), 789124a(a1), 789131a(a1), 789132a(a1), 789134a(a1), 78f9136b(a1) [(a2) products] .... pd789121a(a2), 789122a(a2), 789124a(a2), 789131a(a2), 789132a(a2), 789134a(a2) the differences between the standard qua lity grade products and the (a), (a 1), and (a2) products are shown in table 2-1. table 2-1. differences between standard qua lity grade products and (a), (a1), (a2) products products item standard quality grade products (a) products (a1) products (a2) products quality grade standard special supply voltage v dd = 1.8 to 5.5 v v dd = 4.5 to 5.5 v operating ambient temperature t a = ? 40 to +85 c ? pd78f9136b(a1) t a = ? 40 to +105 c ? other than pd78f9136b(a1) t a = ? 40 to +110 c t a = ? 40 to +125 c electrical specifications refer to the relevant electrical specifications chapter.
user?s manual u14643ej3v0ud 49 chapter 3 pin functions 3.1 pin function list (1) port pins pin name i/o function after reset alternate function p00 to p03 i/o port 0 4-bit i/o port input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). input ? p10, p11 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). input ? p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 intp0/cpt20/ss20 p24 intp1/to80/to20 p25 i/o port 2 6-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by pull-up resistor option register b2 (pub2). input intp2/ti80 p50 to p53 i/o port 5 4-bit n-channel open-drain i/o port input/output can be specified in 1-bit units. for a mask rom version, use of an on-chip pull-up resistor can be specified by a mask option. input ? p60 to p63 input port 6 4-bit input-only port input ani0 to ani3
chapter 3 pin functions user?s manual u14643ej3v0ud 50 (2) non-port pins pin name i/o function after reset alternate function intp0 p23/cpt20/ss20 intp1 p24/to80/to20 intp2 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. input p25/ti80 si20 input serial data input to serial interface input p22/rxd20 so20 output serial data output from serial interface input p21/txd20 sck20 i/o serial clock i/o for se rial interface input p20/asck20 asck20 input serial clock input to asynch ronous serial interface input p20/sck20 ss20 input chip select input to serial interface input p23/cpt20/intp0 rxd20 input serial data input to asynchronous serial interface input p22/si20 txd20 output serial data output from asynchronous serial interface input p21/so20 ti80 input external count clock input to 8-bit timer/event counter 80 input p25/intp2 to80 output 8-bit timer/event counter 80 output input p24/intp1/to20 to20 output 16-bit timer 20 output input p24/intp1/to80 cpt20 input capture edge input input p23/intp0/ss20 ani0 to ani3 input a/d converter analog input input p60 to p63 av ss ? a/d converter ground potential ? ? av dd ? a/d converter analog power supply ? ? x1 input ? ? x2 ? connecting ceramic resonator/cr ystal resonator for system clock oscillation ( pd789104a, 789114a subseries) ? ? cl1 input ? ? cl2 ? connecting resistor (r) and capa citor (c) for system clock oscillation ( pd789124a and 789134a subseries) ? ? reset input system reset input input ? v dd ? positive power supply ? ? v ss ? ground potential ? ? ic0 ? internally connected. directly connect to the v ss pin. ? ? v pp ? sets flash memory programming mode. applies a high voltage when a program is written or verified. ? ?
chapter 3 pin functions user?s manual u14643ej3v0ud 51 3.2 description of pin functions 3.2.1 p00 to p03 (port 0) these pins constitute a 4-bit i/o port and can be set in inpu t or output port mode in 1-bit units by using port mode register 0 (pm0). when these pins are used as an input por t, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (pu0). 3.2.2 p10, p11 (port 1) these pins constitute a 2-bit i/o port and can be set in inpu t or output port mode in 1-bit units by using port mode register 1 (pm1). when these pins are used as an input por t, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (pu0). 3.2.3 p20 to p25 (port 2) these pins constitute a 6-bit i/o port. in addition, they function as timer i/o, external interrupt inputs, and serial interface data and clock i/o. port 2 can be specified in the following operation modes in 1-bit units. (1) port mode in this mode, p20 to p25 function as a 6-bit i/o port. po rt 2 can be specifi ed as input or output mode in 1-bit units by using port mode register 2 (pm2). use of an on- chip pull-up resistor can be specified in 1-bit units by using pull-up resistor option register b2 (pub2), regar dless of the setting of port mode register 2 (pm2). (2) control mode in this mode, p20 to p25 function as timer i/o, external interrupt input, clock i/o of the serial interface and the data i/o. (a) ti80 this is the external clock input pin for 8-bit timer/event counter 80. (b) to20, to80 to20 is the output pin of 16-bit timer 20. to80 is the output pin of 8-bit timer/event counter 80. (c) cpt20 this is the input pin of the capture edge. (d) intp0 to intp2 these are external interrupt input pins for which the valid edge (rising edge, falling edge, and both rising and falling edges) can be specified. (e) si20, so20 these are the serial data i/o pins of the serial interface. (f) sck20 these are the serial clock i/o pins of the serial interface. (g) ss20 this is the chip select input pin of the serial interface.
chapter 3 pin functions user?s manual u14643ej3v0ud 52 (h) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface. (i) asck20 this is the serial clock input pin of the asynchronous serial interface. caution when using these pins as serial interface pins, the i/o mode and output latch must be set according to the function to be used. for deta ils of the setting, refer to table 13-2 serial interface 20 operating mode settings. 3.2.4 p50 to p53 (port 5) these pins constitute a 4-bit n-ch open-drain i/o port and can be specified in input or output mode in 1-bit units by using port mode register 5 (tm5). for a mask rom version, use of an on-chip pull-up resistor can be specified by a mask option. 3.2.5 p60 to p63 (port 6) these pins constitute a 4-bit input-only port. in addition to general-purpose input ports, these pins function as the a/d converter input pins. (1) port mode in the port mode, these pins function as a 4-bit input-only port. (2) control mode in the control mode, the pins of port 6 can be us ed as a/d converter analog inputs (ani0 to ani3). 3.2.6 reset this pin inputs an active-low system reset signal. 3.2.7 x1, x2 ( pd789104a, 789114a subseries) these pins are used to connect a ceramic resonator /crystal resonator for system clock oscillation. to supply an external clock, input the clock to x1 and input the inverted signal to x2. 3.2.8 cl1, cl2 ( pd789124a, 789134a subseries) these are resistor (r) and capacitor (c) con nection pins for system clock oscillation. 3.2.9 av dd this is the analog power supply pin of the a/d conver ter. always use the same potential as that of the v dd pin even when the a/d converter is not used. 3.2.10 av ss this is the ground potential pin of the a/d converter. always use the same potential as that of the v ss pin even when the a/d converter is not used. 3.2.11 v dd this is the positive power supply pin. 3.2.12 v ss this is the ground pin.
chapter 3 pin functions user?s manual u14643ej3v0ud 53 3.2.13 v pp ( pd78f9116a, 78f9116b, 78f9136a, 78f9136b only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. connect this pin in either of the following ways. ? independently connect to a 10 k ? pull-down resistor. ? by using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode or to v ss in the normal operation mode. if the wiring between the v pp and v ss pins is long or external noise is superimposed on the v pp pin, the user program may malfunction. 3.2.14 ic0 (pin no.20) (mask rom versions only) the ic0 (internally connected) pin (no. 20) (refer to 1.6 pin configuration (top view) , 2.5 pin configuration (top view) ) is used to set the pd789104a/114a/124a/134a subseries in th e test mode before shipment. in the normal operation mode, connect this pin directly to the v ss pin with as short a wiring length as possible. if a potential difference is generated between the ic0 pin and v ss pin due to a long wiring length between the ic0 pin and v ss pin or external noise superimposed on the ic0 pin, the user program may malfunction. connect the ic0 pin directly to the v ss pin. v ss ic0 (pin no.20) keep short 3.2.15 ic0 (pins no.10 and no.21) the ic0 pins (no.10 and no.21) (refer to 1.6 pin configuration (top view) , 2.5 pin configuration (top view) are internally connected. connect the ic0 pins directly to v ss .
chapter 3 pin functions user?s manual u14643ej3v0ud 54 3.3 pin i/o circuits and recomme nded connection of unused pins the i/o circuit type for each pin and the recommended connection of pins are shown in table 3-1. for the i/o circuit configuration of each type, refer to figure 3-1 . table 3-1. types of pin i/o circuits and recommended connection of unused pins pin name i/o circuit type i/o re commended connection of unused pins p00 to p03 p10, p11 5-a p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 input: independently connect these pins to v dd or v ss via a resistor. output: leave open p23/intp0/cpt20/ss20 p24/intp1/to80/to20 p25/intp2/ti80 8-a input: independently connect these pins to v ss via a resistor. output: leave open p50 to p53 (mask rom version) 13-w p50 to p53 ( pd78f9116a, 78f9116b, 78f9136a, 78f9136b) 13-v i/o input: directly connect these pins to v ss . output: leave these pins open at low-level output after setting the port output latch to 0. p60/ani0 to p63/ani3 9-c input directly connect to v dd or v ss . av dd directly connect to v dd . av ss ? ? directly connect to v ss . reset 2 input ? ic0 directly connect to v ss . v pp ? ? independently connect 10 k ? pull-down resistor to this pin or connect this pin directly to v ss .
chapter 3 pin functions user?s manual u14643ej3v0ud 55 figure 3-1. pin i/o circuits schmitt-triggered input with hysteresis characteristics type 2 in type 5-a pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch type 13-v v ss v ss type 8-a pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss type 9-c in comparator + ? v ref (threshold voltage) av ss p-ch n-ch input enable output data output disable in/out v dd n-ch input enable pull-up resistor (mask option) type 13-w v ss output data output disable in/out n-ch middle-voltage input buffer middle-voltage input buffer input enable
user?s manual u14643ej3v0ud 56 chapter 4 cpu architecture 4.1 memory space the pd789104a/114a/124a/134a subseries can access 64 kb of memory space. figures 4-1 to 4-4 show the memory maps. figure 4-1. memory map ( pd789101a, 789111a, 789121a, 789131a) ffffh ff00h feffh fe00h fdffh 0800h 07ffh 0000h 07ffh 0000h 0080h 007fh 0040h 003fh 0016h 0015h data memory space program memory space special-function registers 256 8 bits internal high-speed ram 256 8 bits reserved internal rom 2,048 8 bits program area callt table area program area vector table area
chapter 4 cpu architecture user?s manual u14643ej3v0ud 57 figure 4-2. memory map ( pd789102a, 789112a, 789122a, 789132a) ffffh ff00h feffh fe00h fdffh 1000h 0fffh 0000h 0fffh 0000h 0080h 007fh 0040h 003fh 0016h 0015h data memory space program memory space special-function registers 256 8 bits internal high-speed ram 256 8 bits reserved internal rom 4,096 8 bits program area callt table area program area vector table area
chapter 4 cpu architecture user?s manual u14643ej3v0ud 58 figure 4-3. memory map ( pd789104a, 789114a, 789124a, 789134a) ffffh ff00h feffh fe00h fdffh 2000h 1fffh 0000h 1fffh 0000h 0080h 007fh 0040h 003fh 0016h 0015h data memory space program memory space special-function registers 256 8 bits internal high-speed ram 256 8 bits reserved internal rom 8,192 8 bits program area callt table area program area vector table area
chapter 4 cpu architecture user?s manual u14643ej3v0ud 59 figure 4-4. memory map ( pd78f9116a, 78f9116b, 78f9136a, 78f9136b) ffffh ff00h feffh fe00h fdffh 4000h 3fffh 0000h 3fffh 0000h 0080h 007fh 0040h 003fh 0016h 0015h data memory space program memory space special-function registers 256 8 bits internal high-speed ram 256 8 bits reserved flash memory 16,384 8 bits program area callt table area program area vector table area
chapter 4 cpu architecture user?s manual u14643ej3v0ud 60 4.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the pd789104a/114a/124a/134a subseries provides the follo wing internal roms (or flash memory) containing the following capacities. table 4-1. internal rom capacity internal rom part number structure capacity pd789101a, 789111a, 789121a, 789131a 2,048 8 bits pd789102a, 789112a, 789122a, 789132a 4,096 8 bits pd789104a, 789114a, 789124a, 789134a mask rom 8,192 8 bits pd78f9116a, 78f9116b, 78f9136a, 78f9136b flash memory 16,384 8 bits the following areas are allocated to the internal program memory space. (1) vector table area the 22-byte area of addresses 0000h to 0015h is reserved as a vector table area. this area stores program start addresses to be used when branching by reset input or interrupt request generation. of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. table 4-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 000ch intsr20/intcsi20 0004h intwdt 000eh intst20 0006h intp0 0010h inttm80 0008h intp1 0012h inttm20 000ah intp2 0014h intad0 (2) callt instruction table area the subroutine entry address of a 1- byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh.
chapter 4 cpu architecture user?s manual u14643ej3v0ud 61 4.1.2 internal data memory (internal high-speed ram) space the pd789104a/114a/124a/134a subseries provi des a 256-byte internal high-speed ram. the internal high-speed ram can also be used as a stack memory. 4.1.3 special-function register (sfr) area special-function registers (sfrs) of on-chip peripheral hard ware are allocated to th e area of ff00h to ffffh (refer to table 4-3 ). 4.1.4 data memory addressing the pd789104a/114a/124a/134a subseries provides a vari ety of addressing modes which take account of memory manipulability, etc. especially at addresses corresponding to data memory area (fe00h to feffh), particular addressing modes can be used to meet the functi ons of the special-function registers (sfrs) and general- purpose registers. figures 4-5 to 4-8 show the data memory addressing modes. figure 4-5. data memory addressing ( pd789101a, 789111a, 789121a, 789131a) ffffh 0800h 07ffh 0000h ff00h feffh ff20h ff1fh fe20h fe1fh fe00h fdffh special-function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits reserved internal rom 2,048 8 bits sfr addressing short direct addressing direct addressing register indirect addressing based addressing
chapter 4 cpu architecture user?s manual u14643ej3v0ud 62 figure 4-6. data memory addressing ( pd789102a, 789112a, 789122a, 789132a) ffffh 1000h 0fffh 0000h ff00h feffh ff20h ff1fh fe20h fe1fh fe00h fdffh special-function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits reserved internal rom 4,096 8 bits sfr addressing short direct addressing direct addressing register indirect addressing based addressing
chapter 4 cpu architecture user?s manual u14643ej3v0ud 63 figure 4-7. data memory addressing ( pd789104a, 789114a, 789124a, 789134a) ffffh 2000h 1fffh 0000h fe00h fdffh ff00h feffh ff20h ff1fh fe20h fe1fh special-function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits reserved internal rom 8,192 8 bits sfr addressing short direct addressing direct addressing register indirect addressing based addressing
chapter 4 cpu architecture user?s manual u14643ej3v0ud 64 figure 4-8. data memory addressing ( pd78f9116a, 78f9116b, 78f9136a, 78f9136b) ffffh 4000h 3fffh 0000h fe00h fdffh ff00h feffh ff20h ff1fh fe20h fe1fh special-function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits reserved flash memory 16,384 8 bits sfr addressing short direct addressing direct addressing register indirect addressing based addressing
chapter 4 cpu architecture user?s manual u14643ej3v0ud 65 4.2 processor registers the pd789104a/114a/124a/134a subseries provides the following on-chip processor registers. 4.2.1 control registers the control registers contain special functions to control the program seq uence statuses and stack memory. the program counter, program status word, an d stack pointer are control registers. (1) program counter (pc) the program counter is a 16-bit regist er that holds the address information of the next program to be executed. in normal operation, the pc is automat ically incremented according to the nu mber of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data or register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 4-9. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically st acked upon interrupt request generation or push psw instruction execution and are automat ically restored upon execution of the reti and pop psw instructions. reset input sets the psw to 02h. figure 4-10. program status word configuration 70 ie z 0 ac 0 0 1 cy psw (a) interrupt enable flag (ie) this flag controls interrupt request acknowledgment operations of cpu. when ie = 0, the ie flag is set to the interrupt disa bled (di) status. all interrupt requests except non- maskable interrupts are disabled. when ie = 1, the ie flag is set to the interrupt enabl ed (ei) status and interrupt request acknowledgment is controlled by the interrupt mask flag for each interrupt source. this flag is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (d) carry flag (cy) this flag stores overflow and underflow upon add/subtra ct instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
chapter 4 cpu architecture user?s manual u14643ej3v0ud 66 (3) stack pointer (sp) this is a 16-bit register used to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 4-11. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of a wr ite (save) to the stack memory and is incremented after a read (restore) from the stack memory. each stack operation saves/restores dat a as shown in figures 4-12 and 4-13. caution since reset input makes th e sp contents undefined, be sure to initialize the sp before instruction execution. figure 4-12. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 register pair higher figure 4-13. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower ret instruction pop rp instruction sp pc7 to pc0 register pair higher sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
chapter 4 cpu architecture user?s manual u14643ej3v0ud 67 4.2.2 general-purpose registers the general-purpose registers cons ist of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and in addit ion, two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). they can be described in terms of functional names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 4-14. general-purpose register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) functional names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 4 cpu architecture user?s manual u14643ej3v0ud 68 4.2.3 special-function registers (sfrs) unlike general-purpose registers, special-function register s have their own functions and are allocated to the 256- byte area ff00h to ffffh. special-function registers can be mani pulated, like general-purpose register s, with operation, transfer, and bit manipulation instructions. the bit units in which one regi ster can be manipulated (1, 8, and 16) differ depending on the special-function register type. each bit unit for manipulation can be specified as follows. ? 1-bit manipulation a symbol reserved by the assembler is described as the opera nd (sfr.bit) of a 1-bit manipulation instruction. this manipulation can also be specified with an address. ? 8-bit manipulation a symbol reserved by the assembler is described as the op erand (sfr) of an 8-bit manipulation instruction. this manipulation can also be specified with an address. ? 16-bit manipulation a symbol reserved by the assembler is described as the operand of a 16-bit manipulation instruction. when specifying an address, describe an even address. table 4-3 lists the special-function registers. the m eanings of the symbols in this table are as follows. ? symbol indicates the addresses of the implem ented special-function register. the symbols shown in this column are the reserved words of the assembler, and have already been defined as an sfr variable by #pragma sfr directive for the c compiler. therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. ? r/w indicates whether the special-function regi ster in question can be read or written. r/w: read/write r: read only w: write only ? bit units for manipulation indicates the bit units (1, 8, and 16) in which the s pecial-function register in question can be manipulated. ? after reset indicates the status of the special-functi on register when the reset signal is input.
chapter 4 cpu architecture user?s manual u14643ej3v0ud 69 table 4-3. special-function register list (1/2) bit units for manipulation address special-function regi ster (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ? ff01h port 1 p1 ? ff02h port 2 p2 ? ff05h port 5 p5 r/w ? ff06h port 6 p6 ? 00h ff10h mul0l ff11h 16-bit multiplication result storage register 0 mul0h mul0 ? note 1 note 2 ff14h ff15h a/d conversion result register note 3 adcr0 r ? note 2 undefined ff16h cr20l ff17h 16-bit compare register 20 cr20h cr20 w ? note 1 note 2 ffffh ff18h tm20l ff19h 16-bit timer counter 20 tm20h tm20 ? note 1 note 2 0000h ff1ah tcp20l ff1bh 16-bit capture register 20 tcp20h tcp20 r ? note 1 note 2 undefined ff20h port mode register 0 pm0 ? ff21h port mode register 1 pm1 ? ff22h port mode register 2 pm2 ? ff25h port mode register 5 pm5 ? ffh ff32h pull-up resistor option register b2 pub2 ? ff42h time clock select register 2 tcl2 ? ? ff48h 16-bit timer mode control register 20 tmc20 r/w ? ff50h 8-bit compare register 80 cr80 w ? ? 00h ff51h 8-bit timer counter 80 tm80 r ? ? undefined ff53h 8-bit timer mode control register 80 tmc80 r/w ? 00h notes 1. although these registers are usually accessed in 16-bit units, they can also be accessed in 8-bit units. access these registers in 8-bit units by means of direct addressing. 2. these registers can be accessed in 16-bit un its only by means of short direct addressing. 3. when this register is used for an 8-bit a/d converter ( pd789104a and 789124a subseries), it can be accessed only in 8-bit units. at this time, the regist er address is ff15h. when this register is used for a 10-bit a/d converter ( pd789114a and 789134a subseries), it can be accessed only in 16-bit units. when using the pd78f9116a and 78f9116b as the fl ash memory versions of the pd789101a, 789102a, or 789104a, or when using the pd78f9136a and 78f9136b as the flash memory versions of the pd789121a, 789122a, or 789124a, this register can be accessed in 8-bit units. however, only the object file assembled with the pd789101a, 789102a, or 789104a, or object file assembled with the pd789121a, 789122a, or 789124a can be used.
chapter 4 cpu architecture user?s manual u14643ej3v0ud 70 table 4-3. special-function register list (2/2) bit units for manipulation address special-function regi ster (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff70h asynchronous serial interface mode register 20 asim20 r/w ? ff71h asynchronous serial interface status register 20 asis20 r ? ff72h serial operating mode register 20 csim20 ? ff73h baud rate generator control register 20 brgc20 r/w ? ? 00h transmit shift register 20 txs20 w ? ? ffh ff74h receive buffer register 20 rxb20 sio20 r ? ? undefined ff80h a/d converter mode register 0 adm0 ? ff84h analog input channel specification register 0 ads0 r/w ? 00h ffd0h multiplication data register a0 mra0 ? ffd1h multiplication data register b0 mrb0 w ? undefined ffd2h multiplier control register 0 mulc0 ? ffe0h interrupt request flag register 0 if0 ? ffe1h interrupt request flag register 1 if1 ? 00h ffe4h interrupt mask flag register 0 mk0 ? ffe5h interrupt mask flag register 1 mk1 ? ffh ffech external interrupt mode register 0 intm0 ? ? fff7h pull-up resistor option register 0 pu0 ? fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time select register note osts ? ? 04h fffbh processor clock control register pcc r/w ? 02h note pd789104a, 789114a subseries only
chapter 4 cpu architecture user?s manual u14643ej3v0ud 71 4.3 instruction address addressing an instruction address is determined by the program c ounter (pc) contents. the pc contents are normally incremented (+1 for each byte) automatically according to t he number of bytes of the instruction to be fetched each time another instruction is executed. when a branch instru ction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of each inst ruction, refer to the 78k/0s series instructions user?s manual (u11047e) ). 4.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to t he program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, the range of branch in relative addressing is between ? 128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instru ction or a conditional branc h instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates all bits ?0?. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates all bits ?1?.
chapter 4 cpu architecture user?s manual u14643ej3v0ud 72 4.3.2 immediate addressing [function] immediate data in the instruction word is tran sferred to the program counter (pc) and branched. this function is carried out when the call !a ddr16 and br !addr16 instructions are executed. the call !addr16 and br !addr16 instructio ns can branch to all the memory spaces. [illustration] in case of call !addr16, br !addr16 instruction 15 0 pc 87 70 call or br low addr. high addr.
chapter 4 cpu architecture user?s manual u14643ej3v0ud 73 4.3.3 table indirect addressing [function] the table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (pc) and branched. table indirect addressing is carried out when the callt [ addr5] instruction is executed. this instruction can refer to the address stored in the memory table 40h to 7fh and branch to all the memory spaces. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 instruction code 4.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 4 cpu architecture user?s manual u14643ej3v0ud 74 4.4 operand address addressing the following methods are available to specify the r egister and memory (addressing) to undergo manipulation during instruction execution. 4.4.1 direct addressing [function] the memory indicated by immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 0 0 1 0 1 0 0 1 op code 0 0 0 0 0 0 0 0 00h 1 1 1 1 1 1 1 0 feh [illustration] 70 op code addr16 (low) addr16 (high) memory
chapter 4 cpu architecture user?s manual u14643ej3v0ud 75 4.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit data in an instruction word. the fixed space where this addressing is applied to is the 256-byte space fe20h to ff1fh. an internal high- speed ram and special-function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the total sfr area. in this area, ports which are frequently accessed in a program and a compare register of the timer/event counter are mapped, and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effectiv e address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to [illustration] . [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh immediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1 1 1 0 1 0 1 op code 1 0 0 1 0 0 0 0 90h (saddr-offset) 0 1 0 1 0 0 0 0 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1.
chapter 4 cpu architecture user?s manual u14643ej3v0ud 76 4.4.3 special-function register (sfr) addressing [function] memory-mapped special-function registers (sfrs) are addressed with 8-bit immediat e data in an instruction word. this addressing is applied to the 240-byte spaces ff 00h to ffcfh and ffe0h to ffffh. however, sfrs mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special-function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 4 cpu architecture user?s manual u14643ej3v0ud 77 4.4.4 register addressing [function] general-purpose registers are accessed as operands. the general-purpose register to be accessed is specified with the register specify code and functi onal name in the instruction code. register addressing is carried out when an instruction wi th the following operand format is executed. when an 8- bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 register specify code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1 0 0 0 register specify code
chapter 4 cpu architecture user?s manual u14643ej3v0ud 78 4.4.5 register indirect addressing [function] the memory is addressed with the contents of the register pair specified as an operand. the register pair to be accessed is specified with the register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 0 0 1 0 1 0 1 1 [illustration] 15 0 8 d 7 e 0 7 7 0 a de the contents of addressed memory are transferred memory address specified by register pair de
chapter 4 cpu architecture user?s manual u14643ej3v0ud 79 4.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by exp anding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addr essing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 4.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call, and return instructions are executed or the register is sa ved/reset upon generation of an interrupt request. stack addressing can be used to address the internal high-speed ram area only. [description example] in the case of push de instruction code 1 0 1 0 1 0 1 0
user?s manual u14643ej3v0ud 80 chapter 5 port functions 5.1 functions of ports the pd789104a/114a/124a/134a subseries provides the ports shown in figure 5-1, enabling various methods of control. numerous other functions are provided that can be used in addition to the digital i/o port function. for more information on these additional functions, refer to chapter 3 pin functions . figure 5-1. port types port 5 p50 p53 port 6 p60 p63 p00 p03 p10 port 0 port 1 p11 p20 p25 port 2
chapter 5 port functions user?s manual u14643ej3v0ud 81 table 5-1. port functions pin name i/o function after reset alternate function p00 to p03 i/o port 0 4-bit i/o port input/output can be specified in 1-bit units. when used as input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (pu0). input ? p10, p11 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. when used as input port, use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (pu0). input ? p20 asck20/sck20 p21 txd20/so20 p22 rxd20/si20 p23 intp0/cpt20/ss20 p24 intp1/to80/to20 p25 i/o port 2 6-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of pull-up resistor option register b2 (pub2). input intp2/ti80 p50 to p53 i/o port 5 4-bit n-ch open-drain i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified for mask rom versions by a mask option. input ? p60 to 63 input port 6 4-bit input-only port input ani0 to ani3
chapter 5 port functions user?s manual u14643ej3v0ud 82 5.2 port configuration a port consists of the following hardware. table 5-2. configuration of port item configuration control register port mode register (pm0 to pm2, pm5) pull-up resistor option register 0 (pu0) pull-up option register b2 (pub2) port total: 20 (input: 4, i/o: 16) pull-up resistor ? mask rom versions total: 16 (software control: 12, mask option specification: 4) ? flash memory versions total: 12 (software control only) 5.2.1 port 0 this is a 4-bit i/o port with output latche s. port 0 can be set to input or out put mode in 1-bit un its by using port mode register 0 (pm0). when pins p00 to p03 are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull-up resistor option register 0 (pu0). reset input sets port 0 to input mode. figure 5-2 shows the block diagram of port 0. figure 5-2. block diagram of p00 to p03 internal bus wr pu0 rd wr port wr pm pu00 output latch (p00 to p03) pm00 to pm03 v dd p-ch p00 to p03 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 5 port functions user?s manual u14643ej3v0ud 83 5.2.2 port 1 this is a 2-bit i/o port with output latches. port 1 can be set to input or output mode in 1-bit units by using port mode register 1 (pm1). when pins p10 and p11 are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (pu0). reset input sets port 1 to input mode. figure 5-3 shows the block diagram of port 1. figure 5-3. block diagram of p10 and p11 internal bus wr pu0 rd wr port wr pm pu01 output latch (p10, p11) pm10, pm11 v dd p-ch p10, p11 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 5 port functions user?s manual u14643ej3v0ud 84 5.2.3 port 2 this is a 6-bit i/o port with output latches. port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). use of on-chip pull-up resistors can be specified for pins p20 to p25 in 1-bit units by using pull-up resistor option register b2 (pub2). the port is also used as the serial interface data i/o , clock i/o, timer i/o, and external interrupt input. reset input sets port 2 to input mode. figures 5-4 to 5-7 show block diagrams of port 2. caution when using the pins of po rt 2 as the serial interface, the i/o or output latch must be set according to the function to be used. for how to set the latches, see tabl e 13-2 serial interface 20 operating mode settings. figure 5-4. block diagram of p20 internal bus v dd p-ch p20/asck20/ sck20 wr pub2 rd wr port wr pm pub20 alternate function output latch (p20) pm20 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 5 port functions user?s manual u14643ej3v0ud 85 figure 5-5. block diagram of p21 internal bus v dd p-ch p21/txd20/ so20 wr pub2 rd wr port wr pm pub21 output latch (p21) pm21 alternate function selector serial output enable signal pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 5 port functions user?s manual u14643ej3v0ud 86 figure 5-6. block diagram of p22, p23, and p25 internal bus v dd p-ch p22/rxd20/si20 p23/intp0/cpt20/ ss20 p25/intp2/ti80 wr pub2 rd wr port wr pm pub22, pub23, pub25 alternate function output latch (p22, p23, p25) pm22, pm23, pm25 selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 5 port functions user?s manual u14643ej3v0ud 87 figure 5-7. block diagram of p24 wr pub2 selector rd pm24 pub24 alternate function alternate function p24/intp1/ to80/to20 p-ch wr port output latch (p24) wr pm internal bus alternate function v dd pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 5 port functions user?s manual u14643ej3v0ud 88 5.2.4 port 5 this is a 4-bit n-ch open-drain i/o port with output latches. port 5 can be set to input or output mode in 1-bit units by using port mode register 5 (pm5). for a mask rom version, whether a pull-up resistor is to be incorporated can be specified by a mask option. reset input sets port 5 to input mode. figure 5-8 shows a block diagram of port 5. figure 5-8. block diagram of p50 to p53 internal bus selector rd pm50 to pm53 p50 to p53 n-ch wr port output latch (p50 to p53) wr pm v dd mask option resistor mask rom versions only. for flash memory versions, a pull-up resistor is not incorporated. pm: port mode register rd: port 5 read signal wr: port 5 write signal caution when using port 5 of the pd78f9116a and 78f9136a as an input port, be sure to observe the restrictions listed below. <1> when v dd = 1.8 to 5.5 v use within the range of t a = 25 to 85 c <2> when t a = ? 40 to +85 c use within the range of v dd = 2.7 to 5.5 v <3> when t a = ? 40 to +85 c and v dd = 1.8 to 5.5 v issue three con secutive read instructions when reading port 5. if the above restrictions are not observed, the input valu e may be read incorrectly. note, however, that these restrictions do not appl y when port 5 pins are used as output pins, or when the product is other than pd78f9116a or 78f 9136a.
chapter 5 port functions user?s manual u14643ej3v0ud 89 5.2.5 port 6 this is a 4-bit input port. the port is also used for analog input to the a/d converter. reset input sets port 6 to input mode. figure 5-9 shows a block diagram of port 6. figure 5-9. block diagram of p60 to p63 internal bus v ref rd a/d converter p60/ani0 to p63/ani3 + ?
chapter 5 port functions user?s manual u14643ej3v0ud 90 5.3 port function control registers the following three types of registers control the ports. ? port mode registers (pm0 to pm2, pm5) ? pull-up resistor option register 0 (pu0) ? pull-up resistor option register b2 (pub2) (1) port mode registers (pm0 to pm2, pm5) these registers are used to set port i/o in 1-bit units. port mode registers are independently set with a 1- bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to table 5-3. caution as port 2 has an alternate function as exte rnal interrupt input, when the port function output mode is specified and th e output level is changed, the interr upt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. table 5-3. port mode register and output latch settings when using alternate functions alternate function pin name name i/o pm p intp0 input 1 p23 cpt20 input 1 intp1 input 1 to80 output 0 0 p24 to20 output 0 0 intp2 input 1 p25 ti80 input 1 caution when port 2 is used for se rial interface pins, the i/o latch or output latch must be set according to its function. for the setting method, refer to table 13-2 serial inte rface 20 operating mode settings. remark : don?t care pm : port mode register p : port output latch
chapter 5 port functions user?s manual u14643ej3v0ud 91 figure 5-10. port mode register format pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 1 1 1 1 1 1 1 1 1 1 pm25 1 1 1 pm24 1 pm03 1 pm23 pm53 pm02 1 pm22 pm52 pm01 pm11 pm21 pm51 pm00 pm10 pm20 pm50 pm0 pm1 pm2 pm5 7 symbol address after reset 6543210 r/w ff20h ff21h ff22h ff25h ffh ffh ffh ffh r/w r/w r/w r/w pmn pin input/output mode selection (m = 0 to 2, 5, n = 0 to 7) (2) pull-up resistor option register 0 (pu0) pull-up resistor option register 0 (pu0) sets whether to use on-chip pull-up resistors at each port or not. at a port where use of on-chip pull-up resistors has been specified by pu0, the pull-up resistors can be internally used only for the bits set in input mode. no on-chip pull-up resistors can be used for the bits set in output mode, in spite of the setting of pu0. on-chip pull-up resistors can also not be used when the pins are used as the alternate-function output pins. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pu0 to 00h. figure 5-11. format of pull-up resistor option register 0 pu0m 0 1 000000 pu01 pu00 pu0 symbol address pm on-chip pull-up resistor selection (m = 0, 1) on-chip pull-up resistor not used on-chip pull-up resistor used after reset 7654 r/w fff7h 00h r/w 3 2 <1> <0>
chapter 5 port functions user?s manual u14643ej3v0ud 92 (3) pull-up resistor option register b2 (pub2) this register specifies whether an on-chip pull-up resistor is connected to each pin of port 2. a pin so specified by pub2 is connected to an on-chip pull-up resistor regardless of the setting of the port mode register. pub2 is set with a 1-bit or 8-bit manipulation instruction. reset input sets this register to 00h. figure 5-12. format of pull-up resistor option register b2 pub2n 0 1 00 pub25 pub24 pub23 pub22 pub21 pub20 pub2 symbol address p2n on-chip pull-up resistor selection (n = 0 to 5) on-chip pull-up resistor not used on-chip pull-up resistor used after reset 7 6 <5> <4> r/w ff32h 00h r/w <3> <2> <1> <0>
chapter 5 port functions user?s manual u14643ej3v0ud 93 5.4 operation of port functions the operation of a port differs depending on whether the port is set in input or output mode, as described below. 5.4.1 writing to i/o port (1) in output mode a value can be written to the output latch of a port by using a transfer instruction. the contents of the output latch can be output from the pins of the port. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. (2) in input mode a value can be written to the output latch by using a transf er instruction. however, the status of the port pin is not changed because the output buffer is off. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units . when this instruction is executed to manipulate a bit of an i/o port, therefore, the cont ents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 5.4.2 reading from i/o port (1) in output mode the contents of the output latc h can be read by using a transfer instruct ion. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer in struction. the contents of the output latch are not changed. caution when using port 5 of pd78f9116a and 78f9136a as an input port, be sure to observe the restrictions listed below. <1> when v dd = 1.8 to 5.5 v use within the range of t a = 25 to 85 c <2> when t a = ? 40 to +85 c use within the range of v dd = 2.7 to 5.5 v <3> when t a = ? 40 to +85 c and v dd = 1.8 to 5.5 v issue three con secutive read instructions when reading port 5. if the above restrictions are not observed, the input valu e may be read incorrectly. note, however, that these restrictions do not ap ply when port 5 pins are used as output pins, or when the product is other than pd78f9116a or 78f9136a.
chapter 5 port functions user?s manual u14643ej3v0ud 94 5.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed on the contents of the output latch. the re sult of the operation is written to the output latch. the contents of the output latch are output from the port pins. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. (2) in input mode the contents of the output latch become undefined. however, the stat us of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units . when this instruction is executed to manipulate a bit of an i/o port, therefore, the cont ents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined.
user?s manual u14643ej3v0ud 95 chapter 6 clock generator ( pd789104a, 789114a subseries) 6.1 function of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. oscillation is stopped by executing the stop instruction. the system clock oscillator is as follows. ? system clock (crystal/ceramic) oscillator this circuit oscillates a clock at a frequency of 1.0 to 10.0 mhz. this circuit oscillates a clock at a frequency of 1.0 to 5.0 mhz. 6.2 configuration of clock generator the clock generator consists of the following hardware. table 6-1. configuration of clock generator item configuration control register processor clock control register (pcc) oscillator crystal/ceramic oscillator figure 6-1. block diagram of clock generator f x prescaler system clock oscillator 2 2 f x selector pcc1 internal bus processor clock control register (pcc) prescaler standby controller wait controller cpu clock (f cpu ) clock to peripheral hardware stop x1 x2
chapter 6 clock generator ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 96 6.3 register controlling clock generator the clock generator is controlled by the following register. ? processor clock control register (pcc) (1) processor clock control register (pcc) pcc sets the cpu clock selection and the division ratio. pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc to 02h. figure 6-2. format of processor clock control register 000000 pcc1 0 pcc symbol address after reset r/w fffbh 02h r/w 76543210 pcc1 cpu clock (f cpu ) selection 0 1 f x f x /2 2 0.2 s 0.8 s 0.4 s 1.6 s minimum instruction execution time: 2/f cpu @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation note expanded-specification products only caution bit 0 and bits 2 to 7 must be set to 0. remark f x : system clock oscillation frequency
chapter 6 clock generator ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 97 6.4 system clock oscillator 6.4.1 system clock oscillator the system clock oscillator is oscillated by the crystal or ceramic resonator connected across the x1 and x2 pins. an external clock can also be input to the system clock oscilla tor. in this case, input the clock signal to the x1 pin, and leave the x2 pin open. figure 6-3 shows the external circui t of the system clock oscillator. figure 6-3. external circuit of system clock oscillator (a) crystal or ceramic oscillation (b) external clock v ss x1 x2 crystal or ceramic resonator external clock x1 x2 caution when using the system clock oscillator, wire as follows in the area enclo sed by the broken lines in the above figures to avoid an ad verse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. figure 6-4 shows examples of in correct resonator connection.
chapter 6 clock generator ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 98 figure 6-4. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss x1 x2 v ss x1 x2 portn (n = 0 to 2, 5, 6)
chapter 6 clock generator ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 99 figure 6-4. examples of incorrect resonator connection (2/2) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 ab c p mn v dd high current x2 (e) signal is fetched v ss x1 x2 6.4.2 divider the divider divides the output of the system clock oscillator (f x ) to generate various clocks.
chapter 6 clock generator ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 100 6.5 operation of clock generator the clock generator generates the following clocks and c ontrols the operating modes of the cpu, such as the standby mode. ? system clock f x ? cpu clock f cpu ? clock to peripheral hardware the operation of the clock generator is determined by t he processor clock control register (pcc), as follows. (a) the slow mode (0.8 s: at 10.0 mhz operation, 1.6 s: at 5.0 mhz operation) of the system clock is selected when the reset signal is generated (pcc = 02h). while a low level is being input to the reset pin, oscillation of the system clock is stopped. (b) two types of minimum instruction execution time (0.2 s and 0.8 s: at 10.0 mhz operation, 0.4 s and 1.6 s: at 5.0 mhz operation) can be selected by setting the pcc register. (c) two standby modes, stop and halt, can be used. (d) the clock to the peripheral hardware is supplied by dividing the system clock. the other peripheral hardware is stopped when the system clock is st opped (except the external clock input operation).
chapter 6 clock generator ( pd789104a, 789114a subseries) user?s manual u14643ej3v0ud 101 6.6 changing setting of cpu clock 6.6.1 time required for switching cpu clock the cpu clock can be switched by using bit 1 (pcc1) of the processor clock control register (pcc). actually, the specified clock is not switched immediately af ter the setting of pcc has been changed; the old clock is used for the duration of several instructions after that (refer to table 6-2 ). table 6-2. maximum time required for switching cpu clock set value before switching set value after switching pcc1 pcc1 pcc1 0 1 0 4 clocks 1 2 clocks remark two clocks are the minimum instruction execution time of the cpu clock before switching. 6.6.2 switching cpu clock the following figure illustrates how the cpu clock is switched. figure 6-5. switching cpu clock v dd reset cpu clock slow operation fastest operation wait (3.28 ms: at 10.0 mhz operation, 6.55 ms: at 5.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on po wer application. the effect of resetting is released when the reset pin is later made high, and the system clock starts oscillating. at this time, the time during which oscillation stabilizes (2 15 /f x ) is automatically secured. after that, the cpu starts instruction executi on at the low speed of the system clock (8.0 s: at 10.0 mhz operation, 1.6 s: at 5.0 mhz operation). <2> after the time during which the v dd voltage rises to the level at whic h the cpu can operate at the highest speed has elapsed, the processor clock control register (pcc) is rewritten so that the highest speed can be selected.
user?s manual u14643ej3v0ud 102 chapter 7 clock generator ( pd789124a, 789134a subseries) 7.1 function of clock generator the clock generator generates the cloc k to be supplied to th e cpu and peripheral hardware. the system clock oscillator is as follows. ? system clock (rc) oscillator this circuit oscillates a clock at a frequency of 2.0 to 4. 0 mhz. oscillation can be stopped by executing the stop instruction. 7.2 configuration of clock generator the clock generator consists of the following hardware. table 7-1. configuration of clock generator item configuration control register processor clock control register (pcc) oscillator rc oscillator figure 7-1. block diagram of clock generator f cc prescaler system clock oscillator 2 2 f cc selector pcc1 internal bus processor clock control register (pcc) prescaler standby controller wait controller cpu clock (f cpu ) clock to peripheral hardware stop cl1 cl2
chapter 7 clock generator ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 103 7.3 register controlling clock generator the clock generator is controlled by the following register. ? processor clock control register (pcc) (1) processor clock control register (pcc) pcc sets the cpu clock selection and the division ratio. pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the pcc to 02h. figure 7-2. format of processor clock control register 000000 pcc1 0 pcc symbol address after reset r/w fffbh 02h r/w 76543210 pcc1 cpu clock (f cpu ) selection 0 1 f cc f cc /2 2 0.5 s 2.0 s minimum instruction execution time: 2/f cpu @ f cc = 4.0 mhz operation caution bit 0 and bits 2 to 7 must be set to 0. remark f cc : system clock oscillation frequency
chapter 7 clock generator ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 104 7.4 system clock oscillator 7.4.1 system clock oscillator the system clock oscillator is oscillated by the resistor (r) and capacitor (c) (4.0 mhz typ.) connected across the cl1 and cl2 pins. an external clock can also be input to the system clock oscill ator. in this case, input the clock signal to the cl1 pin, and leave the cl2 pin open. figure 7-3 shows the external circui t of the system clock oscillator. figure 7-3. external circuit of system clock oscillator (a) rc oscillation (b) external clock v ss cl1 r c cl2 external clock cl1 cl2 caution when using the system clock oscillator, wire as follows in the area enclo sed by the broken lines in the above figures to avoid an ad verse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 7 clock generator ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 105 7.4.2 examples of incorr ect resonator connection figure 7-4 shows examples of incorrect resonator connection. figure 7-4. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss cl2 cl1 v ss cl2 portn (n = 0 to 2, 5, 6) cl1
chapter 7 clock generator ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 106 figure 7-4. examples of incorrect resonator connection (2/2) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a and b fluctuates) v ss cl2 cl1 high current v ss v dd cl2 cl1 portn (n = 0 to 2, 5, 6) ab high current (e) signal is fetched v ss cl2 cl1 7.4.3 divider the divider divides the output of the system clock oscillator (f cc ) to generate various clocks.
chapter 7 clock generator ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 107 7.5 operation of clock generator the clock generator generates the following clocks and c ontrols the operating modes of the cpu, such as the standby mode. ? system clock f cc ? cpu clock f cpu ? clock to peripheral hardware the operation of the clock generator is determined by t he processor clock control register (pcc), as follows. (a) the slow mode (2.0 s: at 4.0 mhz operation) of the system clock is selected when the reset signal is generated (pcc = 02h). while a low level is being inpu t to the reset pin, oscillation of the system clock is stopped. (b) two types of minimum instruction execution time (0.5 s and 2.0 s: at 4.0 mhz operation) can be selected by setting the pcc register. (c) two standby modes, stop and halt, can be used. (d) the clock to the peripheral hardware is supplied by dividing the system clock. the other peripheral hardware is stopped when the system clock is st opped (except the external clock input operation).
chapter 7 clock generator ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 108 7.6 changing setting of cpu clock 7.6.1 time required for switching cpu clock the cpu clock can be switched by using bit 1 (pcc1) of the processor clock control register (pcc). actually, the specified clock is not switched immediately af ter the setting of pcc has been changed; the old clock is used for the duration of several instructions after that (refer to table 7-2 ). table 7-2. maximum time required for switching cpu clock set value before switching set value after switching pcc1 pcc1 pcc1 0 1 0 4 clocks 1 2 clocks remark two clocks are the minimum instruction execution time of the cpu clock before switching.
chapter 7 clock generator ( pd789124a, 789134a subseries) user?s manual u14643ej3v0ud 109 7.6.2 switching cpu clock the following figure illustrates how the cpu clock is switched. figure 7-5. switching cpu clock v dd reset cpu clock slow operation fastest operation wait (32 s: at 4.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on po wer application. the effect of resetting is released when the reset pin is later made high, and the system clock starts oscillating. at this time, the time during which oscillation stabilizes (2 7 /f cc ) is automatically secured. after that, the cpu starts instruction execut ion at the low speed of the system clock (2.0 s: at 4.0 mhz operation). <2> after the time during which the v dd voltage rises to the level at whic h the cpu can operate at the highest speed has elapsed, the processor clock control register (pcc) is rewritten so that the highest speed can be selected.
user?s manual u14643ej3v0ud 110 chapter 8 16-bit timer 20 the 16-bit timer counter references the free-running counter and provides functions such as timer interrupt and timer output. in addition, the count value can be captured by a capture trigger pin. 8.1 16-bit time r 20 functions 16-bit timer 20 has the following functions. ? timer interrupt ? timer output ? count value capture (1) timer interrupt an interrupt is generated when the count value and compare value match. (2) timer output timer output control is possible when t he count value and compare value match. (3) count value capture the tm20 count value is latched in synchronization with the capture trigger and held.
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 111 8.2 16-bit timer 20 configuration 16-bit timer 20 consists of the following hardware. table 8-1. configuration of 16-bit timer 20 item configuration timer counter 16 bits 1 (tm20) registers compare register: 16 bits 1 (cr20) capture register: 16 bits 1 (tcp20) timer output 1 (to20) control registers 16-bit timer mode control register 20 (tmc20) port mode register 2 (pm2) port 2 (p2) figure 8-1. block diagram of 16-bit timer 20 cpt20/p23/ intp0/ss20 internal bus internal bus 16-bit timer mode control register 20 (tmc20) 16-bit timer mode control register 20 tof20 cpt201cpt200 toc20 tcl201tcl200 toe20 f clk /2 2 f clk /2 6 edge detector 16-bit capture register 20 (tcp20) 16-bit counter read buffer 16-bit timer counter 20 (tm20) 16-bit compare register 20 (cr20) match selector ovf f/f tod20 to20/p24/ intp1/to80 inttm20 p24 output latch pm24 remark f clk : f x or f cc
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 112 (1) 16-bit compare register 20 (cr20) this register compares the value set to cr20 with the count value of 16-bit timer counter 20 (tm20), and when they match, generates an interrupt request (inttm20). cr20 is set with a 16-bit memory manipulation instruction. the values 0000h to ffffh can be set. reset input sets this register to ffffh. cautions 1. although this register is manipulated with a 16-bit memory manipulation instruction, an 8- bit memory manipulation instruction can also be used. when manipulating with an 8-bit memory manipulation instruct ion, the accessing method should be direct addressing. 2. when rewriting cr20 during a count operat ion, set cr20 to the in terrupt-disabled state using interrupt mask flag register 0 (mk10) befo rehand. also, set the timer output data to inversion disabled using 16-bit timer mode control register 20 (tmc20). when cr20 is rewritten in the interrupt-enabl ed state, an interrupt request may occur at the moment of rewrite. (2) 16-bit timer counter 20 (tm20) this is a 16-bit register that counts count pulses. tm20 is read with a 16-bit memory manipulation instruction. this register is free running during count clock input. reset input clears this register to 0000h and after which it resumes free running. cautions 1. the count value after releasing st op becomes undefined because the count operation is executed during the oscillation stabilization time. 2. although this register is manipulated with a 16-bit memory manipulation instruction, an 8- bit memory manipulation instruction can also be used. when manipulating with an 8-bit memory manipulation instruct ion, the accessing method should be direct addressing. 3. when manipulating with an 8-bit memory manipulation instruction, readout should be performed in the order of lower byte to hi gher byte and must be performed in pairs. (3) 16-bit capture register 20 (tcp20) this is a 16-bit register that captures t he contents of 16-bit timer counter 20 (tm20). tcp20 is set with a 16-bit memory manipulation instruction. reset input makes this register undefined. caution although this register is manipulated with a 16-bit memory ma nipulation instruction, an 8-bit memory manipulation instruction can also be used. when manipul ating with an 8-bit memory manipulation instruct ion, the accessing method should be direct addressing. (4) 16-bit counter read buffer this buffer latches the counter value and holds the count value of 16-bit timer counter 20 (tm20).
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 113 8.3 registers controlling 16-bit timer 20 the following three registers control 16-bit timer 20. ? 16-bit timer mode control register 20 (tmc20) ? port mode register 2 (pm2) ? port 2 (p2) (1) 16-bit timer mode control register 20 (tmc20) 16-bit timer mode control register 20 (tmc20) controls the setting of the counter cl ock, capture edge, etc. tmc20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc20 to 00h.
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 114 figure 8-2. format of 16-bit timer mode control register 20 cpt201 0 0 1 1 cpt200 0 1 0 1 capture operation disabled rising edge of cpt20 falling edge of cpt20 both edges of cpt20 tof20 0 1 set by overflow of 16-bit timer toc20 0 1 timer output data inversion control inversion disabled inversion enabled tod20 0 1 timer output data timer output of 0 timer output of 1 capture edge selection toe20 0 1 tcl201 0 0 other than above tcl200 0 1 f x /2 2 or f cc /2 2 f x /2 6 or f cc /2 6 setting prohibited 16-bit timer 20 output control output disabled (port mode) output enabled 16-bit timer counter 20 count clock selection overflow flag set clear by reset and software 1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 r/w ff48h 00h r/w note 1 <6>54321 7 <0> symbol address after reset @ f x = 10.0 mhz note 2 operation @ f x = 5.0 mhz operation 1.25 mhz 78.1 khz 2.5 mhz 156.2 khz 1.0 mhz 62.5 khz @ f cc = 4.0 mhz operation notes 1. bit 7 is read-only. 2. expanded-specification products only. remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation)
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 115 (2) port mode register 2 (pm2) this register sets the input/output of port 2 in 1-bit units. to use the p24/to20/intp1/to80 pin for timer out put, set the output latch of pm24 and p24 to 0. pm2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 8-3. format of port mode register 2 11 pm25 pm24 pm23 pm22 pm21 pm20 pm2 r/w ff22h ffh r/w 654321 pm24 0 1 70 input mode (output buffer off) symbol address after reset p24 pin i/o mode selection output mode (output buffer on)
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 116 8.4 16-bit timer 20 operation 8.4.1 operation as timer interrupt an interrupt is generated repeatedly each time the free-runni ng counter value reaches the value set to cr20. after interrupt occurs, the counter is not cleared and continues counti ng. therefore, the interval time is equivalent to one count clock cycle set by tcl201 and tcl200. to operate the 16-bit timer 20 as a timer interrupt, the following settings are required. ? set count values to cr20. ? set 16-bit timer mode control register 20 (tmc20) as shown in figure 8-4. figure 8-4. settings of 16-bit timer mode cont rol register 20 at timer interrupt operation ? 0/1 0/1 0/1 0/1 0 0/1 0/1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 setting of count clock (see table 8-2 ) caution if both the cpt201 and cpt200 flags are set to 0, the capture edge becomes setting prohibited. when the count value of 16-bit timer counter 20 (tm20) co incides with the value set to cr20, counting of tm20 continues and an interrupt request signal (inttm20) is generated. table 8-2 shows the interval time, and figure 8-5 sh ows the timing of the timer interrupt operation. caution when rewriting cr20 durin g count operation, be sure to follow the procedure below. <1> set cr20 to interrupt disable (by setting bit 7 of interrupt mask flag register 0 (mk0) to 1). <2> set inversion control of timer out put data to disable (toc20 = 0) when cr20 is rewritten in the interrupt-enabled state, an inte rrupt request may occur at the moment of rewrite. table 8-2. interval time of 16-bit timer 20 count clock interval time tcl201 tcl200 @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation @ f cc = 4.0 mhz operation @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation @ f cc = 4.0 mhz operation 0 0 2 2 /f x or 2 2 /f cc 0.4 s 0.8 s 1.0 s 2 18 /f x or 2 18 /f cc 26.2 ms 52.4 ms 65.5 ms 0 1 2 6 /f x or 2 6 /f cc 6.4 s 12.8 s 16 s 2 22 /f x or 2 22 /f cc 419.4 ms 838.9 ms 1048 ms other than above setting prohibited note expanded-specification products only. remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation)
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 117 figure 8-5. timing of timer interrupt operation count clock tm20 count value cr20 inttm20 to20 tof20 nn n nn interrupt acknowledged interrupt acknowledged overflow flag set t 0000h n ffffh n 0000h 0001h 0001h remark n = 0000h to ffffh
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 118 8.4.2 operation as timer output the timer output is inverted repeatedly each time the free -running counter value reaches the value set to cr20. after the timer output is inverted, the counter is not cleared and continues counting. therefore, the interval time is equivalent to one count clock cycle set by tcl201 and tcl200. to operate the 16-bit timer 20 as a timer output, the following settings are required. ? set p24 to output mode (pm24 = 0). ? set the p24 output latch to 0. ? set the count value to cr20. ? set 16-bit timer mode control register 20 (tmc20) as shown in figure 8-6. figure 8-6. settings of 16-bit timer mode c ontrol register 20 for timer output operation ? 0/1 0/1 0/1 1 0 0/1 1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 setting of count clock (see table 8-2 ) inversion enable for timer output data to20 output enable caution if both the cpt201 flag and cpt200 flag ar e set to 0, the capture edge becomes operation prohibited. when the count value of 16-bit timer counter 20 (tm20) ma tches the value set in cr20, the output status of the to20/p24/intp1/to80 pin is inverted. this enables timer output. at that time, tm20 continues counting and an interrupt request signal (inttm20) is generated. figure 8-7 shows the timing of timer output (refer to table 8-2 for the interval time of 16-bit timer 20). figure 8-7. timer output timing count clock tm20 count value cr20 inttm20 tof20 nn n nn interrupt acknowledged interrupt acknowledged overflow flag set t 0000h n ffffh n 0000h 0001h 0001h to20 note note the to20 initial value becomes low level while output is enabled (toe20 = 1). remark n = 0000h to ffffh
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 119 8.4.3 capture operation the capture operation functions to c apture and latch the count value of 16-bit timer counter 20 (tm20) in synchronization with a capture trigger. set as shown in figure 8-8 to allow 16-bit timer 20 to start the capture operation. figure 8-8. settings of 16-bit timer mode control register 20 for capture operation ? 0/1 0/1 0/1 0/1 0 0/1 0/1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 count clock selection capture edge selection (see table 8-3 ) 16-bit capture register 20 (tcp20) st arts the capture operation after th e cpt20 capture trigger edge has been detected, and latches and holds the count value of 16-bit timer counter 20. tcp20 fetches the count value within 2 clocks and holds the count value unt il the next capture edge detection. table 8-3 and figure 8-9 show the setting contents of the capture edge and the capture operation timing, respectively. table 8-3. settings of capture edge cpt201 cpt200 capture edge selection 0 0 capture operation prohibited 0 1 cpt20 pin rising edge 1 0 cpt20 pin falling edge 1 1 cpt20 pin both edges caution because tcp20 is rewritten when a capture tr igger edge is detected during tcp20 read, disable capture trigger detection during tcp20 read. figure 8-9. capture operation timing (both edges of cpt20 pin are specified) count clock tm20 count read buffer tcp20 cpt20 0000h 0000h 0001h 0001h undefined n n n m ? 1 m m m capture start capture start capture edge detection capture edge detection remark n, m = 0000h to ffffh
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 120 8.4.4 16-bit timer counter 20 readout the count value of 16-bit timer counter 20 (tm20) is read out by a 16-bit manipulation instruction. tm20 readout is performed via a counter read buffer. the counter read buffer latches the tm20 count value. the buffer operation is then held pending at the cpu clock fal ling edge after the read signal of the tm20 lower byte rises and the count value is held. the counter read buffer va lue in the hold state can be read out as the count value. cancellation of the pending state is performed at the cpu clock falling e dge after the read signal of the tm20 higher byte falls. reset input clears tm20 to 0000h and restarts free running. figure 8-10 shows the timing of 16-bit timer counter 20 readout. cautions 1. the count value a fter releasing stop becomes undefined because the count operation is executed during oscillation stabilization time. 2. although tm20 is a dedicated 16-bit transfer in struction register, an 8- bit transfer instruction can also be used. execute an 8-bit transfer in struction by direct addressing. 3. when using an 8-bit transfer instruction, execute in the order of lower byte to higher byte in pairs. if the only lower byte is read, the pe nding state of the counter read buffer is not canceled, and if the only higher byte is read, an undefined count value is read. figure 8-10. 16-bit timer counter 20 readout timing cpu clock count clock tm20 count read buffer tm20 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch prohibited period remark n = 0000h to ffffh
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 121 8.5 notes on using 16-bit timer 20 8.5.1 restrictions on rewritin g 16-bit compare register 20 (1) when rewriting the compare register (cr20), be su re to disable interrupts (tmmk20 = 1), and disable inversion control of timer output (toc20 = 0) first. if cr20 is rewritten with interrupts enabled, an interrup t request may be generated at the point of rewrite. (2) the interval time may be double the intended time depending on the timing at which the compare register (cr20) is rewritten. likewise, the timer output waveform may be shorter or double the intended output. to avoid this, rewrite using one of the following procedures. rewriting by 8-bit access <1> disable interrupts (tmmk20 = 1), and disable inversion control of timer output (toc20 = 0). <2> rewrite the higher byte of cr20 (16 bits) first. <3> next, rewrite the lower byte of cr20 (16 bits). <4> clear the interrupt request flag (tmif20). <5> after more than half the cycle of the count clock has passed from the start of the interrupt, enable timer interrupts and timer output inversion. (when count clock = 64/f x , cpu clock = f x ) tm20_vct: set1 tmmk20 ;timer interrupt disable (6 clocks) clr1 tmc20.3 ;timer output inversio n disable (6 clocks) mov a,#xxh ;higher byte rewrite value setting (6 clocks) mov !0ff17h,a ;cr20 higher byte rewriting (8 clocks) mov a,#yyh ;lower byte rewrite value setting (6 clocks) mov !0ff16h,a ;cr20 lower byte rewriting (8 clocks) clr1 tmif20 ;interrupt request flag clearing (6 clocks) clr1 tmmk20 ;timer interrupt enable (6 clocks) set1 tmc20.3 ;timer output inversion enable note this is because the inttm20 signal is set to the high level for a period of half the cycle of the count clock after an interrupt is generated, so the output will be inverted if toc20 is set to 1 during this period. more than 32 clocks in total note
chapter 8 16-bit timer 20 user?s manual u14643ej3v0ud 122 rewriting by 16-bit access <1> disable interrupts (tmmk20 = 1), and disable inversion control of timer output (toc20 = 0). <2> rewrite cr20 (16 bits). <3> wait for more than one cycle of the count clock. <4> clear the interrupt request flag (tmif20). <5> enable timer interrupts and timer output inversion (when count clock = 64/f x , cpu clock = f x ) tm20_vct: set1 tmmk20 ;timer interrupt disable clr1 tmc20.3 ;timer output inversion disable movw ax,#xxyyh ;cr20 rewrite value setting movw cr20,ax ;cr20 rewriting nop nop : nop nop clr1 tmif20 ;interrupt request flag clearing clr1 tmmk20 ;timer interrupt enable set1 tmc20.3 ;timer output inversion enable note wait for more than one cycle of the count clock after the instruction rewriting cr20 (movw cr20, ax) before clearing the interr upt request flag (tmif20). ;32 nop (wait for 64/f x ) note
user?s manual u14643ej3v0ud 123 chapter 9 8-bit ti mer/event counter 80 the 8-bit timer/event counter can be used as an interval timer, external event counter, and for square-wave output and pwm output of arbitrary frequency. 9.1 functions of 8-bit timer/event counter 80 8-bit timer/event counter 80 has the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output (1) 8-bit interval timer when the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time interval set in advance. table 9-1. interval time of 8-bit timer/event counter 80 minimum interval time maximum interval time resolution 1/f x (100 ns) 2 8 /f x (25.6 s) 1/f x (100 ns) at f x = 10.0 mhz note 2 3 /f x (0.8 s) 2 11 /f x (204.8 s) 2 3 /f x (0.8 s) 1/f x (200 ns) 2 8 /f x (51.2 s) 1/f x (200 ns) at f x = 5.0 mhz 2 3 /f x (1.6 s) 2 11 /f x (409.6 s) 2 3 /f x (1.6 s) 1/f cc (250 ns) 2 8 /f cc (64 s) 1/f cc (250 ns) at f cc = 4.0 mhz 2 3 /f cc (2.0 s) 2 11 /f cc (512 s) 2 3 /f cc (2.0 s) note expanded-specification products only remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation) (2) external event counter the number of pulses of an exter nally input signal can be measured.
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 124 (3) square-wave output a square wave of arbitrary frequency can be output. table 9-2. square-wave output range of 8-bit timer/event counter 80 minimum pulse width maximum pulse width resolution 1/f x (100 ns) 2 8 /f x (25.6 s) 1/f x (100 ns) at f x = 10.0 mhz note 2 3 /f x (0.8 s) 2 11 /f x (204.8 s) 2 3 /f x (0.8 s) 1/f x (200 ns) 2 8 /f x (51.2 s) 1/f x (200 ns) at f x = 5.0 mhz 2 3 /f x (1.6 s) 2 11 /f x (409.6 s) 2 3 /f x (1.6 s) 1/f cc (250 ns) 2 8 /f cc (64 s) 1/f cc (250 ns) at f cc = 4.0 mhz 2 3 /f cc (2.0 s) 2 11 /f cc (512 s) 2 3 /f cc (2.0 s) note expanded-specification products only remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation) (4) pwm output 8-bit resolution pwm output can be produced. 9.2 8-bit timer/event counter 80 configuration 8-bit timer/event counter 80 consists of the following hardware. table 9-3. 8-bit timer/event counter 80 configuration item configuration timer counter 8 bits 1 (tm80) register compare register: 8 bits 1 (cr80) timer output 1 (to80) control registers 8-bit timer mode control register 80 (tmc80) port mode register 2 (pm2) port 2 (p2)
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 125 figure 9-1. block diagram of 8-bit timer/event counter 80 internal bus internal bus 8-bit compare register 80 (cr80) match 8-bit timer counter 80 (tm80) clear ovf selector inttm80 to20 output note f clk f clk /2 3 ti80/p25/ intp2 to80/p24/ intp1/to20 pwme80 tce80 tcl801 tcl800 toe80 8-bit timer mode control register 80 (tmc80) p24 output latch pm24 r q inv s q note refer to block diagram of 16-bit timer 20 remark f clk : f x or f cc (1) 8-bit compare register 80 (cr80) this is an 8-bit register that compares the value se t to cr80 with the 8-bit timer counter 80 (tm80) count value, and if they match, generates an interrupt request (inttm80). cr80 is set with an 8-bit memory manipulation instruction. the values 00h to ffh can be set. reset input makes cr80 undefined. cautions 1. when rewriting cr80 in timer counter ope ration mode (i.e., pwme80 (bit 6 of 8-bit timer mode control register 80 (tmc 80)) is set to 0), be sure to stop the timer operation before hand. if cr80 is rewritten in the timer oper ation-enabled state, a match interrupt request signal may occur at the moment of rewrite. 2. do not set cr80 to 00h in the pwm out put mode (when pwme80 = 1); otherwise, pwm may not be output normally. (2) 8-bit timer counter 80 (tm80) this is an 8-bit register used to count count pulses. tm80 is read with an 8-bit memory manipulation instruction. reset input clears tm80 to 00h.
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 126 9.3 registers controlling 8-bi t timer/event counter 80 the following three registers are used to control 8-bit timer/event counter 80. ? 8-bit timer mode control register 80 (tmc80) ? port mode register 2 (pm2) ? port 2 (p2) (1) 8-bit timer mode control register 80 (tmc80) this register enables/stops operation of 8-bit timer counter 80 (tm80), sets the counter clock of tm80, and controls the operation of the output contro ller of 8-bit timer/event counter 80. tmc80 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc80 to 00h. figure 9-2. format of 8-bit timer mode control register 80 toe80 0 1 tce80 pwme80 000 tcl801tcl800 toe80 tmc80 r/w ff53h 00h r/w <6>54321 tce80 0 1 <7> <0> operation enable symbol address after reset 8-bit timer/event counter 80 output control output disable (port mode) output enable 8-bit timer counter 80 operation control operation stop (tm80 cleared to 0) pwme80 0 1 pwm output operating mode operation mode selection timer counter operating mode tcl801 0 0 tcl800 0 1 1 1 0 1 f x or f cc f x /2 3 or f cc /2 3 rising edge of ti80 falling edge of ti80 8-bit timer counter 80 count clock selection @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation 5.0 mhz 625 khz 10.0 mhz 1.25 mhz 4.0 mhz 500 khz @ f cc = 4.0 mhz operation note expanded-specification products only caution be sure to set tmc80 after stopping timer operation. remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation)
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 127 (2) port mode register 2 (pm2) this register sets port 2 to input/output in 1-bit units. when using the p24/to80/intp1/to20 pin for timer output , set the output latch of pm24 and p24 to 0. when using it for timer input, set pm24 to 1. pm2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 9-3. format of port mode register 2 pm2n 0 1 1 1 pm25 pm24 pm23 pm22 pm21 pm20 pm2 7654 r/w r/w 3210 input mode (output buffer off) symbol address ff22h ffh after reset p2n pin i/o mode selection (n = 0 to 5) output mode (output buffer on)
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 128 9.4 operation of 8-bit timer/event counter 80 9.4.1 operation as interval timer the interval timer repeatedly generates an interrupt at ti me intervals specified by the count value set to 8-bit compare register 80 (cr80) in advance. to operate the 8-bit timer/event counter as an in terval timer, the following settings are required. <1> set 8-bit timer counter 80 (tm80) to operation disabl ed (by setting tce80 (bit 7 of 8-bit timer mode control register 80 (tmc80)) to 0). <2> set the count clock of 8-bit timer/event counter 80 (refer to figure 9-2 ) <3> set the count value to cr80 <4> set tm80 to operation enable (tce80 = 1) when the count value of 8-bit timer counter 80 (tm80) matches the value set to cr80, the value of tm80 is cleared to 0 and tm80 continues counting. at the same time, an interrupt request signal (inttm80) is generated. tables 9-4 and 9-5 show the interval time, and figure 9-4 shows the timing of interval timer operation. cautions 1. before rewriting cr80, stop the timer operation once. if cr80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at th e moment of rewrite. 2. if the count clock setting and tm80 operation- enabled are set in tmc 80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. therefore, always follow the above procedure wh en operating the 8-bit timer/event counter as an interval timer. table 9-4. interval time of 8-bit timer/event counter 80 (at f x = 5.0 mhz, 10.0 mhz operation) tcl801 tcl800 minimum interval time maximum interval time resolution 0 0 1/f x (100 ns) [200 ns] 2 8 /f x (25.6 s) [51.2 s] 1/f x (100 ns) [200 ns] 0 1 2 3 /f x (0.8 s) [1.6 s] 2 11 /f x (204.8 s) [409.6 s] 2 3 /f x (0.8 s) [1.6 s] 1 0 ti80 input cycle 2 8 ti80 input cycle ti80 input edge cycle 1 1 ti80 input cycle 2 8 ti80 input cycle ti80 input edge cycle remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. the values in parentheses ( ) are for operation at f x = 10.0 mhz (expanded-specification products only). 3. the values in square brackets [ ] are for operation at f x = 5.0 mhz. table 9-5. interval time of 8-bit timer/event counter 80 (at f cc = 4.0 mhz operation) tcl801 tcl800 minimum interval time maximum interval time resolution 0 0 1/f cc (250 ns) 2 8 /f cc (64 s) 1/f cc (250 ns) 0 1 2 3 /f cc (2.0 s) 2 11 /f cc (512 s) 2 3 /f cc (2.0 s) 1 0 ti80 input cycle 2 8 ti80 input cycle ti80 input edge cycle 1 1 ti80 input cycle 2 8 ti80 input cycle ti80 input edge cycle remark f cc : system clock oscillation frequency (rc oscillation)
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 129 figure 9-4. interval timer operation timing clear clear interrupt acknowledged interrupt acknowledged count start interval time interval time interval time count clock tm80 count value cr80 tce80 inttm80 to80 n 01h 00h n 01h 00h n 00h 01h nn nn t remark interval time = (n + 1) t : n = 00h to ffh
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 130 9.4.2 operation as external event counter the external event counter counts the nu mber of external clock pulses input to the ti80/p25/intp2 pin by using 8- bit timer counter 80 (tm80). to operate 8-bit timer/event counter 80 as an external event counter, the following settings are required. <1> set p25 to input mode (pm25 = 1). <2> set 8-bit timer counter 80 (tm80) to operation disabl ed (by setting tce80 (bit 7 of 8-bit timer mode control register 80 (tmc80)) to 0). <3> specify the rising/falling edges of ti80 (refer to figure 9-2 ), and set to80 to output disabled (i.e., set toe80 (bit 0 of tmc80) to 0) and pwm output to disabled (i.e., set pwme80 (bit 6 of tmc80) to 0). <4> set the count value to cr80. <5> set tm80 to operation enabled (tce80 = 1). each time the valid edge specified by bit 1 (tcl800) of tmc80 is input, the value of 8-bit timer counter 80 (tm80) is incremented. when the count value of tm80 matches the value set to cr80, the value of tm80 is cleared to 0 and tm80 continues counting. at the same time, an inte rrupt request signal (inttm80) is generated. figure 9-5 shows the timing of the external event counter operation (with the rising edge specified). cautions 1. before rewriting cr80, stop the timer operation once. if cr80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at th e moment of rewrite. 2. if the count clock setting and tm80 operation- enabled are set in tmc 80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. therefore, always follow the above procedure wh en operating the 8-bit timer/event counter as an external event counter. figure 9-5. external event counter operat ion timing (with rising edge specified) ti80 pin input tm80 count value cr80 tce80 inttm80 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n remark n = 00h to ffh
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 131 9.4.3 operation as square-wave output the 8-bit timer/event counter can output square waves of a given frequency at intervals specified by the count value set to 8-bit compare register 80 (cr80) in advance. to operate 8-bit timer/event counter 80 as square- wave output, the following settings are required. <1> set p24 to output mode (pm24 = 0) and the p24 output latch to 0. <2> set 8-bit timer counter 80 (tm80) to operation disabled (tce80 = 0). <3> set the count clock of 8-bit timer/event counter 80 (refer to figure 9-2 ), to80 to output enabled (toe80 = 1), and pwm output to disabled (pwme80 = 0). <4> set the count value to cr80. <5> set tm80 to operation enabled (tce80 = 1). when the count value of 8-bit timer counter 80 (tm80) matches the value set in cr80, the to80/p24/intp1/to20 pin output will be inverted. through application of this me chanism, square waves of any frequency can be output. as soon as a match occurs, the tm80 value is cleared to 0 and tm80 continues counting. at the same time, an interrupt request signal (inttm80) is generated. square-wave output is cleared (0) when bit 7 (tce80) of tmc80 is set to 0. tables 9-6 and 9-7 show the square-wave output range, and figure 9-6 shows the timing of square-wave output. cautions 1. before rewriting cr80, stop the timer operation once. if cr80 is rewritten in the timer operation-enabled state, a match interrupt request signal may occur at th e moment of rewrite. 2. if the count clock setting and tm80 operation- enabled are set in tmc 80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. therefore, always follow the above procedure wh en operating the 8-bit timer/event counter as square-wave output. table 9-6. square-wave output range of 8-bit timer/event counter 80 (at f x = 5.0 mhz, 10.0 mhz operation) tcl801 tcl800 minimum pulse width maximum pulse width resolution 0 0 1/f x (100 ns) [200 ns] 2 8 /f x (25.6 s) [51.2 s] 1/f x (100 ns) [200 ns] 0 1 2 3 /f x (0.8 s) [1.6 s] 2 11 /f x (204.8 s) [409.6 s] 2 3 /f x (0.8 s) [1.6 s] remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. the values in parentheses ( ) are for operation at f x = 10.0 mhz (expanded-specification products only). 3. the values in square brackets [ ] are for operation at f x = 5.0 mhz. table 9-7. square-wave output range of 8-bit timer/event counter 80 (at f cc = 4.0 mhz operation) tcl801 tcl800 minimum interval time maximum interval time resolution 0 0 1/f cc (250 ns) 2 8 /f cc (64 s) 1/f cc (250 ns) 0 1 2 3 /f cc (2.0 s) 2 11 /f cc (512 s) 2 3 /f cc (2.0 s) remark f cc : system clock oscillation frequency (rc oscillation)
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 132 figure 9-6. square-wave output timing clear clear interrupt acknowledged interrupt acknowledged count start count clock tm80 count value cr80 tce80 inttm80 to80 note n 01h 00h n 01h 00h n 00h 01h nn nn note the to80 initial value becomes low level while output is enabled (toe80 = 1).
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 133 9.4.4 operation as pwm output pwm output enables interrupt generation repeatedly at interval s specified by the count value set to 8-bit compare register 80 (cr80) in advance. to use 8-bit timer/counter 80 for pwm output, the following settings are required. <1> set p24 to output mode (pm24 = 0) and the p24 output latch to 0. <2> set 8-bit timer counter 80 (tm80) to operation disabled (tce80 = 0). <3> set the count clock of 8-bit timer/event counter 80 (refer to figure 9-2 ), to80 to output enabled (toe80 = 1), and pwm output to enabled (pwme80 = 1). <4> set the count value to cr80. <5> set tm80 to operation enabled (tce80 = 1). when the count value of 8-bit timer c ounter 80 (tm80) matches the value se t to cr80, tm80 continues counting, and an interrupt request signal (inttm80) is generated. cautions 1. when cr80 is rewritte n during timer operation, a high level may be output for the next cycle (refer to 9.5 (2) setting of 8-bit compare register 80). 2. if the count clock setting and tm80 operation- enabled are set in tmc 80 simultaneously using an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may occur after the timer starts. therefore, alwa ys follow the above procedure when operating 8- bit compare register 80 as a pwm output. figure 9-7. pwm output timing count clock tm80 cr80 tce80 inttm80 m = 01h to ffh ovf to80 note 00h 01h m m ffh 00h 01h 02h m m + 1 m + 2 ffh 00h 01h m note the to80 initial value becomes low leve l while output is enabled (toe80 = 1). caution do not set cr80 to 00h in the pwm output mode; otherwise pwm may not be output normally.
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 134 9.5 notes on using 8-bit timer/event counter 80 (1) error on starting timer an error of up to 1 clock occurs after the timer is start ed until a match signal is generated. this is because 8- bit timer counter 80 (tm80) is start ed asynchronous to the count pulse. figure 9-8. start timing of 8-bit timer counter count pulse tm80 count value timer start 00h 01h 02h 03h 04h (2) setting of 8-bit compare register 80 8-bit compare register 80 (cr80) can be set to 00h. therefore, one pulse can be counted when the 8-bit timer/event counter operates as an event counter. figure 9-9. external event counter operation timing tl80 input cr80 00h tm80 count value 00h 00h 00h 00h interrupt request flag cautions 1. when rewriting cr80 in timer counter oper ation mode (i.e., pwme80 (bit 6 of 8-bit timer mode control register 80 (tmc80)) is set to 0), be su re to stop the timer operation before hand. if cr80 is rewritten in the timer operation-enable d state, a match interrupt request signal may occur at the moment of rewrite. 2. if cr80 is rewritten while the timer is ope rating in pwm output operation mode (pwme80 = 1), a pulse may not be generated just in th e cycle immediately after the rewrite. 3. do not set cr80 to 00h in the pwm output mode; otherwise pwm may not be output normally.
chapter 9 8-bit timer/event counter 80 user?s manual u14643ej3v0ud 135 (3) operation after rewriting co mpare register during pwm output when 8-bit compare register 80 (cr80) is rewritten du ring pwm output, a high level may be output for a cycle after rewriting cr80 (count pulse 256) if the 8-bit compare register 80 value is smaller than the 8-bit timer counter 80 (tm80) value. the timing in this case is shown in figure 9-10. figure 9-10. timing after rewriting compare register during pwm output count clock tm80 cr80 tce80 inttm80 m = 02h to ffh ovf to80 00h 01h m h ... m ... ffh 00h 01h 02h ... ffh 00h 01h ... ... 01h ... ... rewriting cr80 (4) notes on stop mode setting before executing the stop instruction, be sure to set the timer to operation stopped (tce80 = 0). (5) external event counter start timing when the rising edge of ti80 is selected as the count clock, start the timer (tce80 = 0 1) at the timing when ti80 changes to low level. similarly, when the falling edge of ti80 is selected as the count clock, start the timer (tce80 = 0 1) at the timing when ti80 changes to high level.
user?s manual u14643ej3v0ud 136 chapter 10 watchdog timer the watchdog timer can generate non-maskable interrupts , maskable interrupts and reset at arbitrary preset intervals. 10.1 functions of watchdog timer the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or interv al timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect a program loop . when a program loop is detected, a non-maskable interrupt or the reset signal can be generated. table 10-1. program loop detection time of watchdog timer program loop detection time at f x = 10.0 mhz note operation at f x = 5.0 mhz operation at f cc = 4.0 mhz operation 2 11 1/f w 205 s 410 s 512 s 2 13 1/f w 819 s 1.64 ms 2.05 ms 2 15 1/f w 3.28 ms 6.55 ms 8.19 ms 2 17 1/f w 13.1 ms 26.2 ms 32.8 ms note expanded-specification products only remark f w : f x or f cc f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation) (2) interval timer the interval timer generates an interrupt at a given interval set in advance. table 10-2. interval time interval time at f x = 10.0 mhz note operation at f x = 5.0 mhz operation at f cc = 4.0 mhz operation 2 11 1/f w 205 s 410 s 512 s 2 13 1/f w 819 s 1.64 ms 2.05 ms 2 15 1/f w 3.28 ms 6.55 ms 8.19 ms 2 17 1/f w 13.1 ms 26.2 ms 32.8 ms note expanded-specification products only remark f w : f x or f cc f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation)
chapter 10 watchdog timer user?s manual u14643ej3v0ud 137 10.2 configuration of watchdog timer the watchdog timer consists of the following hardware. table 10-3. configuration of watchdog timer item configuration control registers timer clock select register 2 (tcl2) watchdog timer mode register (wdtm) figure 10-1. block diagram of watchdog timer internal bus internal bus prescaler selector f w 2 6 f w 2 8 f w 2 10 3 7-bit counter tmif4 tmmk4 tcl22 tcl21 tcl20 timer clock select register 2 (tcl2) watchdog timer mode register (wdtm) clear wdtm4 run wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f w 2 4 controller remark f w : f x or f cc
chapter 10 watchdog timer user?s manual u14643ej3v0ud 138 10.3 watchdog timer control registers the following two registers are used to control the watchdog timer. ? timer clock select register 2 (tcl2) ? watchdog timer mode register (wdtm) (1) timer clock select register 2 (tcl2) this register sets the watchdog timer count clock. tcl2 is set with an 8-bit memory manipulation instruction. reset input clears tcl2 to 00h. figure 10-2. format of timer clock select register 2 tcl22 0 0 1 1 00000 tcl22 tcl21 tcl20 tcl2 r/w r/w 76543210 tcl21 0 1 0 1 f x /2 4 or f cc /2 4 f x /2 6 or f cc /2 6 f x /2 8 or f cc /2 8 f x /2 10 or f cc /2 10 625 khz 156.2 khz 39.0 khz 9.76 khz 312.5 khz 78.1 khz 19.5 khz 4.88 khz 250 khz 62.5 khz 15.6 khz 3.91 khz 2 11 /f x or 2 11 /f cc 2 13 /f x or 2 13 /f cc 2 15 /f x or 2 15 /f cc 2 17 /f x or 2 17 /f cc 205 s 819 s 3.28 ms 13.1 ms 410 s 1.64 ms 6.55 ms 26.2 ms 512 s 2.05 ms 8.19 ms 32.8 ms tcl20 0 0 0 0 setting prohibited symbol address ff42h 00h after reset other than above watchdog timer count clock selection interval time @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation @ f cc = 4.0 mhz operation @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation @ f cc = 4.0 mhz operation ? note expanded-specification products only remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation)
chapter 10 watchdog timer user?s manual u14643ej3v0ud 139 (2) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 10-3. format of watchdog timer mode register run 0 1 selection of operation of watchdog timer note 1 run 0 0 wdtm4 wdtm3 000 wdtm symbol address after reset r/w fff9h 00h r/w <7>6543210 stop counting clear counter and start counting wdtm4 selection of operation mode of watchdog timer note 2 wdtm3 0 1 1 0 1 1 operation stop interval timer mode (overflow and maskable interrupt occur) note 3 watchdog timer mode 1 (overflow and non-maskable interrupt occur) watchdog timer mode 2 (overflow occurs and reset operation started) 0 0 notes 1. once run has been set (1), it cannot be cleared (0) by software. therefore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set (1), they cannot be cleared (0) by software. 3. the watchdog timer starts operations as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by se tting run to 1, the actual overflow time is up to 0.8% shorter than the time set by timer clock select register 2 (tcl2). 2. in watchdog timer mode 1 or 2, set wdtm4 to 1 after confirming tmif4 (bit 0 of interrupt request flag 0) has been set to 0. when watchdog timer mode 1 or 2 is selected under the condition that tmif4 is 1, a non-maskable interr upt occurs at the completion of rewriting.
chapter 10 watchdog timer user?s manual u14643ej3v0ud 140 10.4 operation of watchdog timer 10.4.1 operation as watchdog timer the watchdog timer operates to detect a program loop when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (tcl20 to tcl22) of timer clock select register 2 (tcl2). the watc hdog timer is started by setting bit 7 (run) of wdtm to 1. set run to 1 within the set program loop detection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and start c ounting. if run is not set to 1, and the program loop detection time is exceeded, the system is reset or a non-maskable interrupt is gen erated according to the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in the halt mode, but stops in the stop mode. therefore, set run to 1 before entering the stop mode to clear the watchdo g timer, and then execute the stop instruction. caution the actual program loop detection time ma y be up to 0.8% shorter than the set time. table 10-4. program loop detection time of watchdog timer tcl22 tcl21 tcl20 program loop detection time at f x = 10.0 mhz note operation at f x = 5.0 mhz operation at f cc = 4.0 mhz operation 0 0 0 2 11 1/f w 205 s 410 s 512 s 0 1 0 2 13 1/f w 819 s 1.64 ms 2.05 ms 1 0 0 2 15 1/f w 3.28 ms 6.55 ms 8.19 ms 1 1 0 2 17 1/f w 13.1 ms 26.2 ms 32.8 ms note expanded-specification products only remark f w : f x or f cc f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation)
chapter 10 watchdog timer user?s manual u14643ej3v0ud 141 10.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog time r mode register (wdtm) are set to 1, the watchdog timer also operates as an interval timer that repeatedly gener ates an interrupt at time intervals specified by the count value set in advance. select the count clock (or interval time) by setting bits 0 to 2 (tcl20 to tcl22) of timer clock select register 2 (tcl2). the watchdog timer starts operation as an interval timer when the run bit (bit 7 of wdtm) is set to 1. in the interval timer mode, the interrupt mask flag (tmmk4) is vali d, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in the halt mode, but stops in the stop mode. therefore, set run to 1 before entering the stop mode to clear the interval timer, and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the reset signal is input. 2. the interval time immediat ely after the setting by wdtm may be up to 0.8% shorter than the set time. table 10-5. interval ti me of interval timer tcl22 tcl21 tcl20 interval time at f x = 10.0 mhz note operation at f x = 5.0 mhz operation at f cc = 4.0 mhz operation 0 0 0 2 11 1/f w 205 s 410 s 512 s 0 1 0 2 13 1/f w 819 s 1.64 ms 2.05 ms 1 0 0 2 15 1/f w 3.28 ms 6.55 ms 8.19 ms 1 1 0 2 17 1/f w 13.1 ms 26.2 ms 32.8 ms note expanded-specification products only remark f w : f x or f cc f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation)
user?s manual u14643ej3v0ud 142 chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) 11.1 8-bit a/d converter functions the 8-bit a/d converter is an 8-bit resolution converter t hat converts analog inputs into digital signals. this converter can control up to four channels of analog inputs (ani0 to ani3). a/d conversion can only be started by software. one of analog inputs ani0 to ani3 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time an a/d session is completed. 11.2 8-bit a/d converter configuration the 8-bit a/d converter consis ts of the following hardware. table 11-1. configuration of 8-bit a/d converter item configuration analog input 4 channels (ani0 to ani3) registers successive appro ximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) figure 11-1. block diagram of 8-bit a/d converter ani0/p60 ani1/p61 ani2/p62 ani3/p63 selector sample & hold circuit voltage comparator successive approximation register (sar) controller 2 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus av ss adcs0 fr02 fr01 fr00 ads01 ads00 p-ch av dd
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 143 (1) successive approximation register (sar) the sar receives the result of comparing an anal og input voltage and a volt age at the voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) each time a/d conversion ends, the conversion result re ceived from the successive approximation register is loaded into adcr0, which is an 8-bit register that holds the result of a/d conversion. adcr0 can be read with an 8-bit memory manipulation instruction. reset input makes this register undefined. (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled anal og input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the series resistor string. (5) series resistor string the series resistor stri ng is configured between av dd and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani3 pins pins ani0 to ani3 are the 4-channel analog input pins for the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply pins ani0 to ani3 with voltages th at fall outside the rated range. if a voltage of av dd or greater or av ss or lower (even if within the absolu te maximum ratings) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ss pin the av ss pin is the ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss pin, even while the a/d converter is not being used. (8) av dd pin the av dd pin is the analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd pin, even while the a/d converter is not being used.
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 144 11.3 registers controlling 8-bit a/d converter the following two registers are used to control the 8-bit a/d converter. ? a/d converter mode register 0 (adm0) ? analog input channel specif ication register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears adm0 to 00h. figure 11-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 fr02 fr01 fr00 0 0 0 adm0 symbol address after reset r/w ff80h 00h r/w <7>6543210 adcs0 0 1 a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/f x or 144/f cc 120/f x or 120/f cc 96/f x or 96/f cc 72/f x or 72/f cc 60/f x or 60/f cc 48/f x or 48/f cc fr01 0 0 1 0 0 1 fr00 0 1 0 0 1 0 other than above conversion disabled conversion enabled setting prohibited @ f cc = 4.0 mhz operation @ f x = 10.0 mhz note 2 operation @ f x = 5.0 mhz operation 14.4 s 12 s setting prohibited note 3 setting prohibited note 3 setting prohibited note 3 setting prohibited note 3 28.8 s 24 s 19.2 s 14.4 s 12 s note 4 setting prohibited note 3 36 s 30 s 24 s 18 s 15 s setting prohibited note 3 notes 1. set the a/d conversion time to satisfy the following specifications. when 4.5 v v dd 5.5 v: 12 s min. when 2.7 v v dd < 4.5 v: 14 s min. when 1.8 v v dd < 2.7 v: 28 s min. when 2.7 v v dd 5.5 v: 14 s min. when 1.8 v v dd < 2.7 v: 28 s min. 2. expanded-specification products only 3. setting prohibited because the a/d conversion time does not satisfy the rating shown in note 1 . 4. can be set only for expanded-specification products when 4.5 v v dd 5.5 v. otherwise, setting prohibited.
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 145 cautions 1. the result of conversion performed i mmediately after bit 7 (adcs 0) is set is undefined. 2. the result of conversion after adcs0 is cleared may be undefined (for details, refer to 11.5 (5) timing when a/d con version result become undefined). remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation) (2) analog input channel specification register 0 (ads0) the ads0 register specifies the port used to input the analog voltages to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 11-3. format of analog input channel specification register 0 000000 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification ani0 ani1 ani2 ani3 ads01 0 0 1 1 ads00 0 1 0 1
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 146 11.4 8-bit a/d converter operation 11.4.1 basic operation of 8-bit a/d converter <1> select the channel for a/d conversion using anal og input channel specification register 0 (ads0). <2> the voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> after sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <4> bit 7 of the successive approximation register (sar) is set. the tap selector sets the series resistor string voltage tap to half av dd . <5> the series resistor string voltage tap is compared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half av dd , the msb of the sar is left set. if it is lower than half av dd , the msb is reset. <6> bit 6 of the sar is set automatically, and comparison shifts to the next stage. the next voltage tap of the series resistor string is selected according to bit 7, whic h reflects the previous comparison result, as follows. ? bit 7 = 1: three quarters of av dd ? bit 7 = 0: one quarter of av dd the voltage tap is compared with the an alog input voltage. bit 6 is set or reset according to the result of comparison. ? analog input voltage voltage tap: bit 6 = 1 ? analog input voltage < voltage tap: bit 6 = 0 <7> comparison is repeated until bit 0 of the sar is reached. <8> when comparison is completed for all of the 8 bits, a significant digital result is left in the sar. this value is sent to and latched in a/d conversion result register 0 (ad cr0). at the same time, it is possible to generate an a/d conversion end interrupt request (intad0). cautions 1. the first a/d conversion value imme diately after starting the a/d conversion operation may be undefined. 2. when in standby mode, the a/d converter stops operation.
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 147 figure 11-4. basic operation of 8-bit a/d converter conversion time sampling time sampling a/d conversion undefined 80h c0h or 40h conversion result conversion result a/d converter operation sar adcr0 intad0 a/d conversion continues until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. if an attempt is made to write to adm0 or analog input channel specification register 0 (ads0) during a/d conversion, the a/d conversion in progress is canceled. in this case, if adcs0 is set (1), a/d conversion is restarted from the beginning. reset input makes a/d conversion re sult register 0 (adcr0) undefined. 11.4.2 input voltage and conversion result the relationship between the analog input voltage at the a nalog input pins (ani0 to ani3) and the a/d conversion result (a/d conversion result register 0 (adcr0)) is represented by: v in adcr0 = int ( av dd 256 + 0.5) or av dd av dd (adcr0 ? 0.5) 256 v in < (adcr0 + 0.5) 256 int( ): function that returns the in teger part of the parenthesized value v in : analog input voltage av dd : a/d converter supply voltage adcr0: value in a/d conversion result register 0 (adcr0) figure 11-5 shows the relationship between the analog input voltage and the a/d conversion result.
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 148 figure 11-5. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av dd
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 149 11.4.3 operation mode of 8-bit a/d converter the 8-bit a/d converter is initially in the select mode. in this mode, analog input chan nel specification register 0 (ads0) is used to select the analog input ch annel from ani0 to ani3 for a/d conversion. a/d conversion can only be started by software; that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion resu lt register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (a dm0) triggers a/d conversion for the voltage applied to the analog input pin specified by analog input channel s pecification register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conver sion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated until new data is written to adm0. if data where adcs0 is 1 is written to adm0 again during a/d conversion, the session of a/d conversion in progress is discontinued, and a new session of a/d conversion begins for the new data. if data where adcs0 is 0 is written to adm0 again during a/d conversion, a/ d conversion is completely stopped. figure 11-6. software-started a/d conversion rewriting adm0 adcs0 = 1 rewriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 150 11.5 notes on using 8-bit a/d converter (1) current consumption in the standby mode when the a/d converter enters the standb y mode, it stops operating. clearing bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0 can reduce the current consumption. figure 11-7 shows how to reduce the current consumption in the standby mode. figure 11-7. how to reduce current consumption in standby mode av dd av ss p-ch series resistor string adcs0 (2) input range for the ani0 to ani3 pins be sure to keep the input voltage at ani0 to ani3 within the rated values. if a voltage of av dd or grater or av ss or lower (even if within the absolute maximum ratings) is input to a conversion channel, the conversion output of the channel becomes undefined, an d the conversion output of the other channels may also be affected. (3) conflict <1> conflict between writing to a/d conversion result register 0 (adcr0) at the end of conversion and reading from adcr0 reading from adcr0 takes precedence. after reading, the new conversion result is written to adcr0. <2> conflict between writing to adcr0 at the end of conv ersion and writing to a/d converter mode register 0 (adm0) or analog input channel s pecification register 0 (ads0) writing to adm0 or ads0 takes precedence. a request to write to adcr0 is ignored. no conversion end interrupt request signal (intad0) is generated. (4) conversion results immediately following start of a/d conversion the first a/d conversion value immediately following the start of a/d converter operation may be undefined. be sure to perform processing such as polling the a/d conversion end interrupt request (intad0) and discarding the first conversion result. (5) timing that makes the a/d conversion result undefined if the timing of the end of a/d conversi on and the timing of the stop of opera tion of the a/c converter conflict, the a/d conversion value may be undefined. because of this, be sure to read out the a/d conversion result while the a/d converter is operating. furthermore, when reading out an a/d conversion result after a/d converter operation has stopped, be sure to have done so by the time the next conver sion result is complete. the conversion result readout timing is shown in figures 11-8 and 11-9.
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 151 figure 11-8. conversion result readout timing (when conversion result is undefined value) a/d conversion end a/d conversion end normal conversion result undefined value normal conversion result read out undefined value read out a/d operation stopped adcr0 intad0 adcs0 figure 11-9. conversion result readout timi ng (when conversion result is normal value) normal conversion result a/d conversion end normal conversion result read out a/d operation stopped adcr0 intad0 adcs0 (6) noise prevention to maintain a resolution of 8 bits, watch for noise at the av dd and ani0 to ani3 pins. the higher the output impedance of the analog input source is, the larger the effect by noise. to reduce noise, attach an external capacitor to the relevant pins as shown in figure 11-10. figure 11-10. analog input pin treatment c = 100 to 1000 pf if noise of av dd or greater or av ss or lower is likely to come to the av dd pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss v ss av dd v dd ani0 to ani3
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 152 (7) ani0 to ani3 the analog input pins (ani0 to ani3) are alternate-function pins. they are also used as port pins (p60 to p63). if any of ani0 to ani3 has been selected for a/d conver sion, do not execute input instructions for the ports; otherwise the conversion resolution may become lower. if a digital pulse is applied to a pin adjacent to the analog input pin being a/d converted, coupling noise may occur which prevents an a/d conversion result from being attained as expected. avoid applying a digital pulse to pins adjacent to the analog input pin being a/d converted. (8) input impedance of ani0 to ani3 pins this a/d converter charges the internal sampling capacit or for about 1/10 of the conversion time, and performs sampling. therefore at times other than sampling, only the leak age current flows. during sampling, the current for charging the capacitor also flows, so the in put impedance fluctuates and has no meaning. however, to ensure adequate sampling, it is recomme nd that the output impedance of the analog input source be set to 10 k ? or lower, or a capacitor of about 100 pf be connected to the ani0 to ani3 pins (refer to figure 11-10 ). (9) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the analog input pins are changed during a/d conversion, therefore, the conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to adm0 occurs. in this case, adif0 may appear to be set if it is read-accessed immediately after adm0 is write-accessed, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is rest arted, adif0 must be cleared beforehand. figure 11-11. a/d conversion end interrupt request generation timing rewriting to adm0 (to begin conversion for anin) a/d conversion adcr0 intad0 anin anin anim anin anin anim anim anim rewriting to adm0 (to begin conversion for anim) adif0 has been set, but conversion for anim has not been completed. remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3
chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) user?s manual u14643ej3v0ud 153 (10) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani3 input circuit. therefore, if the application is designed to be switched to backup power, the av dd pin must be supplied with the same voltage level as for the v dd pin, as shown in figure 11-12. figure 11-12. av dd pin treatment main power source backup capacitor v dd av dd v ss av ss (11) input impedance of the av dd pin a series resistor string of several 10 k ? is connected across the av dd and av ss pins. therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually connected in serial with the series resistor string across the av dd and av ss pins, leading to a higher reference voltage error.
user?s manual u14643ej3v0ud 154 chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) 12.1 10-bit a/d converter functions the 10-bit a/d converter is a 10-bit resolution converter that converts analog inputs into digital signals. this converter can control up to four channels of analog inputs (ani0 to ani3). a/d conversion can only be started by software. one of analog inputs ani0 to ani3 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time an a/d session is completed. 12.2 10-bit a/d converter configuration the a/d converter consists of the following hardware. table 12-1. configuration of 10-bit a/d converter item configuration analog input 4 channels (ani0 to ani3) registers successive appro ximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) figure 12-1. block diagram of 10-bit a/d converter sample & hold circuit voltage comparator successive approximation register (sar) controller 2 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus av ss p-ch av dd ani0/p60 ani1/p61 ani2/p62 ani3/p63 selector adcs0 fr02 fr01 fr00 ads01 ads00
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 155 (1) successive approximation register (sar) the sar receives the result of comparing an anal og input voltage and a volt age at the voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 is a 16-bit register that holds the result of a/d conversion. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion result in the succe ssive approximation register is loaded into adcr0. the results are stored in adcr0 from the most significant bit. the higher 8 bits of the conversion re sult are stored in ff15h and the lower 2 bits of the conversion result are stored in ff14h. adcr0 can be read with a 16-bit memory manipulation instruction. reset input makes adcr0 undefined. adcr0 symbol ff15h 0 0 0 0 0 0 ff14h ff14h, ff15h address after reset undefined r/w r caution when using the pd78f9116a and 78f9116b as flash memory versions of the pd789101a, 789102a, and 789104a, or the pd78f9136a and 78f9136b as flash memory versions of the pd789121a, 789122a, and 789124a, an 8-bit access can be made by adcr0. however, it is performed only with the object file assembled by the pd789101a, 789102a, or 789104a, or by the pd789121a, 789122a, or 789124a, respectively. (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled anal og input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the series resistor string. (5) series resistor string the series resistor stri ng is configured between av dd and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani3 pins pins ani0 to ani3 are the 4-channel analog input pins for the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply pins ani0 to ani3 with voltages th at fall outside the rated range. if a voltage of av dd or greater or av ss or lower (even if within the absolu te maximum ratings) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ss pin the av ss pin is the ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss pin, even while the a/d converter is not being used.
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 156 (8) av dd pin the av dd pin is the analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd pin, even while the a/d converter is not being used. 12.3 registers controlling 10-bit a/d converter the following two registers are used to control the 10-bit a/d converter. ? a/d converter mode register 0 (adm0) ? analog input channel specif ication register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears the adm0 to 00h. figure 12-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 fr02 fr01 fr00 0 0 0 adm0 symbol address after reset r/w ff80h 00h r/w <7>6543210 adcs0 0 1 conversion disabled conversion enabled a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/f x or 144/f cc 120/f x or 120/f cc 96/f x or 96/f cc 72/f x or 72/f cc 60/f x or 60/f cc 48/f x or 48/f cc fr01 0 0 1 0 0 1 fr00 0 1 0 0 1 0 other than above setting prohibited @ f cc = 4.0 mhz operation @ f x = 10.0 mhz note 2 operation @ f x = 5.0 mhz operation 14.4 s 12 s setting prohibited note 3 setting prohibited note 3 setting prohibited note 3 setting prohibited note 3 28.8 s 24 s 19.2 s 14.4 s 12 s note 4 setting prohibited note 3 36 s 30 s 24 s 18 s 15 s setting prohibited note 3 notes 1. set the a/d conversion time to satisfy the following specifications. when 4.5 v v dd 5.5 v: 12 s min. when 2.7 v v dd < 4.5 v: 14 s min. when 1.8 v v dd < 2.7 v: 28 s min. when 2.7 v v dd 5.5 v: 14 s min. when 1.8 v v dd < 2.7 v: 28 s min. 2. expanded-specification products only 3. setting prohibited because the a/d conversion time does not satisfy the rating shown in note 1 . 4. can be set only for expanded-specification products when 4.5 v v dd 5.5 v. otherwise, setting prohibited.
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 157 cautions 1. the result of conversion performed i mmediately after bit 7 (adcs 0) is set is undefined. 2. the result of conversion after adcs0 is cleared may be undefined (for details, refer to 12.5 (5) timing when a/d con version result becomes undefined). remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation) (2) analog input channel specification register 0 (ads0) the ads0 register specifies the port used to input the analog voltages to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 12-3. format of analog input channel specification register 0 000000 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification ani0 ani1 ani2 ani3 ads01 0 0 1 1 ads00 0 1 0 1
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 158 12.4 10-bit a/d converter operation 12.4.1 basic operation of 10-bit a/d converter <1> select the channel for a/d conversion, using anal og input channel specification register 0 (ads0). <2> the voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> after sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <4> bit 9 of the successive approximation a/d conversion regi ster (sar) is set. the tap selector sets the series resistor string voltage tap to half av dd . <5> the series resistor string voltage tap is compared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half av dd , the msb of the sar is left set. if it is lower than half av dd , the msb is reset. <6> bit 8 of the sar is set automatically, and comparison shifts to the next stage. the next voltage tap of the series resistor string is selected according to bit 9, whic h reflects the previous comparison result, as follows. ? bit 9 = 1: three quarters of av dd ? bit 9 = 0: one quarter of av dd the voltage tap is compared with the an alog input voltage. bit 8 is set or reset according to the result of comparison. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <7> comparison is repeated until bit 0 of the sar is reached. <8> when comparison is completed for all of the 10 bits, a significant digital result is left in the sar. this value is sent to and latched in a/d conversion result register 0 (ad cr0). at the same time, it is possible to generate an a/d conversion end interrupt request (intad0). cautions 1. the a/d conversion value immediatel y after starting the a/d conversion operation may be undefined. 2. when in standby mode, the a/d converter stops operation.
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 159 figure 12-4. basic operation of 10-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 a/d conversion continues until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. if an attempt is made to write to adm0 or analog input channel specification register 0 (ads0) during a/d conversion, the a/d conversion in progress is canceled. in this case, a/d conversion is restarted from the beginning, if adcs0 is set (1). reset input makes a/d conversion re sult register 0 (adcr0) undefined. 12.4.2 input voltage and conversion result the relationship between the analog input voltage at the a nalog input pins (ani0 to ani3) and the a/d conversion result (a/d conversion result register 0 (adcr0)) is represented by: v in adcr0 = int ( av dd 1,024 + 0.5) or av dd av dd (adcr0 ? 0.5) 1,024 v in < (adcr0 + 0.5) 1,024 int( ): function that returns the in teger part of the parenthesized value v in : analog input voltage av dd : a/d converter supply voltage adcr0: value in a/d conversion result register 0 (adcr0) figure 12-5 shows the relationship between the analog input voltage and the a/d conversion result.
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 160 figure 12-5. relationship between analog input voltage and a/d conversion result 1,023 1,022 1,021 3 2 1 0 a/d conversion result (adcr0) 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 input voltage/av dd
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 161 12.4.3 operation mode of 10-bit a/d converter the 10-bit a/d converter is initially in the select mode. in this mode, analog input channel specification register 0 (ads0) is used to select the analog input ch annel from ani0 to ani3 for a/d conversion. a/d conversion can be started only by software; that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion resu lt register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (a dm0) triggers a/d conversion for the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated, and completed, another session of a/d conver sion is started. a/d conversion is repeated until new data is written to adm0. if data where adcs0 is 1 is written to adm0 aga in during a/d conversion, the session of a/d conversion in progress is discontinued, and a new session of a/d co nversion begins for the new data. if data where adcs0 is 0 is written to adm0 again during a/d conver sion, a/d conversion is completely stopped. figure 12-6. software-started a/d conversion rewriting adm0 adcs0 = 1 rewriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 162 12.5 notes on using 10-bit a/d converter (1) current consumption in the standby mode when the a/d converter enters the standb y mode, it stops operating. clearing bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0 can reduce the current consumption. figure 12-7 shows how to reduce the current consumption in the standby mode. figure 12-7. how to reduce current consumption in standby mode av dd av ss p-ch series resistor string adcs0 (2) input range for the ani0 to ani3 pins be sure to keep the input voltage at ani0 to ani3 within the rated values. if a voltage of av dd or greater or av ss or lower (even if within the absolute maximum rati ngs) is input a conversion channel, the conversion output of the channel becomes undef ined, and the conversion output of the other channels may also be affected. (3) conflict <1> conflict between writing to a/d conversion result register 0 (adcr0) at the end of conversion and reading from adcr0 reading from adcr0 takes precedence. after reading, the new conversion result is written to adcr0. <2> conflict between writing to adcr0 at the end of conv ersion and writing to a/d converter mode register 0 (adm0) or analog input channel s pecification register 0 (ads0) writing to adm0 or ads0 takes precedence. a request to write to adcr0 is ignored. no conversion end interrupt request signal (intad0) is generated. (4) conversion results immediately following start of a/d conversion the first a/d conversion value immediately following the start of a/d converter operation may be undefined. be sure to perform processing such as polling the a/d conversion end interrupt request (intad0) and discarding the first conversion result. (5) timing that makes the a/d conversion result undefined if the timing of the end of a/d conversi on and the timing of the stop of opera tion of the a/c converter conflict, the a/d conversion value may be undefined. because of this, be sure to read out the a/d conversion result while the a/d converter is operating. furthermore, when reading out an a/d conversion result after a/d converter operation has stopped, be sure to have done so by the time the next conver sion result is complete. the conversion result readout timing is shown in figures 12-8 and 12-9.
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 163 figure 12-8. conversion result readout timing (when conversion result is undefined value) a/d conversion end a/d conversion end normal conversion result undefined value normal conversion result read out undefined value read out a/d operation stopped adcr0 intad0 adcs0 figure 12-9. conversion result readout timi ng (when conversion result is normal value) normal conversion result a/d conversion end normal conversion result read out a/d operation stopped adcr0 intad0 adcs0 (6) noise prevention to maintain a resolution of 10 bits, watch for noise at the av dd and ani0 to ani3 pins. the higher the output impedance of the analog input source is, the larger the effect by noise is. to reduce noise, attach an external capacitor to the relevant pins as shown in figure 12-10. figure 12-10. analog input pin treatment c = 100 to 1000 pf if noise of av dd or greater or av ss or lower is likely to come to the av dd pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss v ss av dd v dd ani0 to ani3
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 164 (7) ani0 to ani3 the analog input pins (ani0 to ani3) are alternate-function pins. they are also used as port pins (p60 to p63). if any of ani0 to ani3 has been selected for a/d conver sion, do not execute input instructions for the ports; otherwise, the conversion resolution may become lower. if a digital pulse is applied to a pin adjacent to the analog input pin being a/d converted, coupling noise may occur which prevents an a/d conversion result from being attained as expected. avoid applying a digital pulse to pins adjacent to the analog input pin being a/d converted. (8) input impedance of ani0 to ani3 pins this a/d converter charges the internal sampling capacit or for about 1/10 of the conversion time, and performs sampling. therefore at times other than sampling, only the leak age current flows. during sampling, the current for charging the capacitor also flows, so the in put impedance fluctuates and has no meaning. however, to ensure adequate sampling, it is recomme nd that the output impedance of the analog input source be set to 10 k ? or lower, or a capacitor of about 100 pf be connected to the ani0 to ani3 pins (refer to figure 12-10 ). (9) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the analog input pins are changed during a/d conversion, therefore, the conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to adm0 occurs. in this case, adif0 may appear to be set if it is read-accessed immediately after adm0 is write-accessed, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is rest arted, adif0 must be cleared beforehand. figure 12-11. a/d conversion end interrupt request generation timing rewriting to adm0 (to begin conversion for anin) a/d conversion adcr0 intad0 anin anin anim anin anin anim anim anim rewriting to adm0 (to begin conversion for anim) adif0 has been set, but conversion for anim has not been completed. remarks 1. n = 0, 1, 2, 3 2. m = 0, 1, 2, 3
chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) user?s manual u14643ej3v0ud 165 (10) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani3 input circuit. therefore, if the applicat ion is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as for the v dd pin, as shown in figure 12-12. figure 12-12. av dd pin treatment main power source backup capacitor v dd av dd v ss av ss (11) input impedance of the av dd pin a series resistor string of several 10 k ? is connected across the av dd and av ss pins. therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually connected in serial with the series resistor string across the av dd and av ss pins, leading to a higher reference voltage error.
user?s manual u14643ej3v0ud 166 chapter 13 serial interface 20 13.1 functions of serial interface 20 serial interface 20 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (2) asynchronous serial interface (uart) mode this mode is used to transmit and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface channel 0 contains a dedicated uart baud rate generator, enabling communication over a wide range of baud rates. it is also possible to defi ne baud rates by dividing the frequency of the input clock pulse at the asck20 pin. it is recommended that ceramic/crystal oscillation be used for the system clock in the uart mode. because the frequency deviation is large in rc os cillation, if an internal clock is selected as the source clock for the baud rate generator, there may be problems in transmit/receive operations. (3) 3-wire serial i/o mode (switchable between msb-first and lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock (sck20) line and two serial data lines (si20 and so20). as it supports simultaneous transmiss ion and reception, 3-wire serial i/o mode requires less processing time for data transmission than asynchronous serial interface mode. because, in 3-wire serial i/o mode, it is possible to select whether 8-bi t data transmission begins with the msb or lsb, channel 0 can be connected to any device regardl ess of whether that device is designed for msb-first or lsb-first transmission. 3-wire serial i/o mode is useful for connecting peripheral i/o circuits and display controllers having conventional clocked serial interfaces, such as those of the 75xl, 78k, and 17k series devices. 13.2 serial interface 20 configuration serial interface 20 consists of the following hardware. table 13-1. configuration of serial interface 20 item configuration registers transmit shi ft register 20 (txs20) receive shift register 20 (rxs20) receive buffer register 20 (rxb20) control registers serial operating mode register 20 (csim20) asynchronous serial interface mode register 20 (asim20) asynchronous serial interface status register 20 (asis20) baud rate generator control register 20 (brgc20) port mode register 2 (pm2) port 2 (p2)
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 167 figure 13-1. block diagra m of serial interface 20 internal bus receive buffer register 20 (rxb20) switching of first bit asynchronous serial interface status register 20 serial operation mode register 20 (csim20) receive shift register 20 (rxs20) csie20 sse20 dap20 dir20 csck20 ckp20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 transmit shift register 20 (txs20) transmit shift clock selector csie20 dap20 data phase control reception shift clock si20/p22/ rxd20 so20/p21/ txd20 4 parity detection stop bit detection reception data counter parity operation stop bit addition transmission data counter sl20, cl20, ps200, ps201 reception enabled reception clock detection clock start bit detection output latch (p21) port mode register (pm21) csie20 csck20 sck20/p20/ asck20 ss20/p23/ cpt20/intp0 clock phase control reception detected internal clock output external clock input transmission and reception clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f x /2 to f x /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus (asis20) (asim20) note refer to figure 13-2 for the configuration of the baud rate generator.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 168 figure 13-2. baud rate generator block diagram reception detection clock transmission shift clock reception shift clock reception detection txe20 rxe20 csie20 selector selector selector 1/2 1/2 transmission clock counter reception clock counter 4 f x /2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 2 sck20/asck20/p20 tps203 tps202 tps201 tps200 baud rate generator control register 20 (brgc20) internal bus
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 169 (1) transmit shift register 20 (txs20) txs20 is a register in which transmit data is prepared. the transmit data is output from txs20 bit-serially. when the data length is seven bits, bits 0 to 6 of the data in txs20 will be transmit da ta. writing data to txs20 triggers transmission. txs20 can be written with an 8-bit memory m anipulation instruction, but cannot be read. reset input sets txs20 to ffh. caution do not write to txs20 during transmission. txs20 and receive buffer register 20 (rxb20) are mapped at the same address, so that any attempt to read from txs20 results in a value being read from rxb20. (2) receive shift register 20 (rxs20) rxs20 is a register in which serial data, received at the rxd20 pin, is converted to parallel data. once one entire byte has been received, rxs20 transfers the rece ive data to receive buffer register 20 (rxb20). rxs20 cannot be manipulated directly by a program. (3) receive buffer register 20 (rxb20) rxb20 holds receive data. new receive data is transferred from receive shift register 0 (rxs20) per 1 byte of data received. when the data length is specified as seven bits, the receive data is sent to bits 0 to 6 of rxb20, in which the msb is always fixed to 0. rxb20 can be read with an 8-bit memory manipulation instruction, but cannot be written to. reset input makes rxb20 undefined. caution rxb20 and transmit shift register 20 (txs 20) are mapped at the same address, so that any attempt to write to rxb20 results in a value being written to txs20. (4) transmission controller the transmission controller controls transmission. for exampl e, it adds start, parity, and stop bits to the data in transmit shift register 20 (txs20), according to the setti ng of asynchronous serial interface mode register 20 (asim20). (5) reception controller the reception controller controls re ception according to the setting of asynchronous serial interface mode register 20 (asim20). it also checks for errors, such as parity errors, during reception. if an error is detected, asynchronous serial interface status register 20 (asi s20) is set according to the status of the error.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 170 13.3 serial interface 20 control registers serial interface 20 is controlled by the following six registers. ? serial operating mode register 20 (csim20) ? asynchronous serial interface mode register 20 (asim20) ? asynchronous serial interface status register 20 (asis20) ? baud rate generator control register 20 (brgc20) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operating mode register 20 (csim20) csim20 is used to make the settings related to 3-wire serial i/o mode. csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 171 figure 13-3. format of serial operating mode register 20 csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock pulse input to sck20 pin output of dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection output at falling edge of sck20 output at rising edge of sck20 ss20-pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active low, and sck20 is at high level in the idle state clock is active high, and sck20 is at low level in the idle state cautions 1. bits 4 and 5 must be fixed to 0. 2. csim20 must be cleared to 00h if uart mode is selected.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 172 (2) asynchronous serial interfa ce mode register 20 (asim20) asim20 is used to make the settings relat ed to asynchronous serial interface mode. asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. figure 13-4. format of asynchronous serial interface mode register 20 txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 00 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stop transmit operation enable rxe20 0 1 receive operation control receive operation stop receive operation enable ps201 0 0 1 1 parity bit specification ps200 0 1 0 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity cl20 0 1 transmit data character length specification 7 bits 8 bits sl20 0 1 transmit data stop bit length 1 bit 2 bits cautions 1. bits 0 and 1 must be fixed to 0. 2. if 3-wire serial i/o mode is sel ected, asim20 must be cleared to 00h. 3. switch operating modes after halti ng the serial transmit/receive operation.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 173 table 13-2. serial interface 20 operating mode settings (1) operation stopped mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p21 pm21 p21 pm20 p20 first bit shift clock p22/si20/rxd20 pin function p21/so20/txd20 pin function p20/sck20/ asck20 pin function 0 0 0 note 1 note 1 note 1 note 1 note 1 note 1 ? ? p22 p21 p20 other than above setting prohibited (2) 3-wire serial i/o mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p21 pm21 p21 pm20 p20 first bit shift clock p22/si20/rxd20 pin function p21/so20/txd20 pin function p20/sck20/ asck20 pin function 0 1 external clock sck20 input 1 0 1 0 1 msb internal clock sck20 output 0 1 external clock sck20 input 0 0 1 1 1 note 1 note 2 0 1 0 1 lsb internal clock si20 note 2 sck20(cmos output) sck20 output other than above setting prohibited (3) asynchronous serial interface mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p21 pm21 p21 pm20 p20 first bit shift clock p22/si20/rxd20 pin function p21/so20/txd20 pin function p20/sck20/ asck20 pin function 1 external clock asck20 input 1 0 0 0 0 note 1 note 1 0 1 note 1 note 1 internal clock p22 txd20 (cmos output) p20 1 external clock asck20 input 0 1 0 0 0 1 note 1 note 1 note 1 note 1 internal clock p21 p20 1 external clock asck20 input 1 1 0 0 0 1 0 1 note 1 note 1 lsb internal clock rd20 txd20 (cmos output) p20 other than above setting prohibited notes 1. these pins can be used for port functions. 2. when only transmission is used, thes e pins can be used as p22 (cmos i/o). remark : don?t care.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 174 (3) asynchronous serial interface status register 20 (asis20) asis20 is used to display the type of a reception error, if it occurs while asynchronous serial interface mode is set. asis20 is read with a 1-bit or 8-bi t memory manipulation instruction. the contents of asis20 are undefined in 3-wire serial i/o mode. reset input clears asis20 to 00h. figure 13-5. format of asynchronous se rial interface status register 20 pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543210 no parity error has occurred. a parity error has occurred (when the transmission parity and reception parity do not match). fe20 0 1 framing error flag no framing error has occurred. a framing error has occurred (when no stop bit is detected). note 1 ove20 0 1 overrun error flag no overrun error has occurred. an overrun error has occurred. note 2 (before data was read from the reception buffer register, the subsequent reception sequence was completed.) notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the stop bit detection in the case of reception is performed with 1 bit. 2. be sure to read receive buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error will occur.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 175 (4) baud rate generator cont rol register 20 (brgc20) brgc20 is used to specify the serial clock for the serial interface. brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. figure 13-6. format of baud rate generator control register 20 tps203 0 0 0 0 0 0 0 0 1 selection of source clock for baud rate generator tps203 tps202 tps201 tps200 0000 brgc20 symbol address after reset r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock pulse input at the asck20 pin note 2 setting prohibited 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 19.5 khz other than above tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? 5.0 mhz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz @ f x = 10.0 mhz note 1 operation @ f x = 5.0 mhz operation notes 1. expanded-specification products only 2. an external clock can only be used in uart mode. cautions 1. when writing to brg c20 is performed during a communication operation, the output of baud rate generator is disrup ted and communications cannot be performed normally. be sure not to write to brgc20 during communication operations. 2. be sure not to select n = 1 when f x > 2.5 mhz in uart mode because n = 1 exceeds the rating of the baud rate. 3. be sure not to select n = 2 when f x > 5.0 mhz in uart mode because n = 2 exceeds the rating of the baud rate. 4. be sure not to select n = 1 when f x > 5.0 mhz in 3-wire serial i/o mode because n = 1 exceeds the rating of the serial clock. 5. when the external input cl ock is selected, set port mode regi ster 2 (pm2) in input mode. remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. n: value specified in tps200 to tps203 (1 n 8)
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 176 the baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a signal divided from the clock input from the asck20 pin. (a) generation of baud rate uart transmit/receive clock by means of system clock the transmit/receive clock is generated by dividing the system clock. the baud rate generated from the system clock is estimated by using the following expression. f x [baud rate] = 2 n + 1 8 [bps] f x : system clock oscillation frequency (ceramic/crystal oscillation) n: values in figure 13-6 specified by the setting in tps200 to tps203 (2 n 8) table 13-3. example of relationship between system clock and baud rate f x = 10.0 mhz note f x = 5.0 mhz f x = 4.9152 mhz baud rate (bps) n brgc20 setting error (%) n brgc20 setting error (%) n brgc20 setting error (%) 1,200 ? ? 8 70h 8 70h 2,400 8 70h 7 60h 7 60h 4,800 7 60h 6 50h 6 50h 9,600 6 50h 5 40h 5 40h 19,200 5 40h 4 30h 4 30h 38,400 4 30h 3 20h 3 20h 76,800 3 20h 1.73 2 10h 1.73 2 10h 0 note expanded-specification products only. cautions 1. be sure not to select n = 1 when f x > 2.5 mhz because n = 1 exceeds the rating of the baud rate. 2. be sure not to select n = 2 when f x > 5.0 mhz because n = 2 exceeds the rating of the baud rate.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 177 (b) generation of baud rate uart transmit/receive clock by means of external clock from asck20 pin the transmit/receive clock is generated by dividing t he clock input from the asck20 pin. the baud rate generated from the clock input from the asck20 pin is estimated by using the following expression. f asck [baud rate] = 16 [bps] f asck : frequency of clock pulse received at the asck20 pin table 13-4. relationship between asck20 pin input frequency and baud rate (when brg c20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 (c) generation of serial clock from syst em clock in 3-wire serial i/o mode the serial clock is generated by dividing the system clock. the serial clock frequency is estimated by using the following expression. brgc20 does not need to be set when an external serial clock is input to the sck20 pin. f x serial clock frequency = 2 n + 1 [hz] f x : system clock oscillation frequency n: value determined by the settings of tps200 to tps203 as shown in figure 13-6 (1 n 8)
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 178 13.4 operation of serial interface 20 serial interface 20 provides the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 13.4.1 operation stop mode in the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. the p20/sck20/asck20, p21/so20/txd20, and p22/si20/rx d20 pins can be used as normal i/o port pins. (1) register setting operation stop mode is set by serial operating mode register 20 (csim20) and asynchronous serial interface mode register 20 (asim20). (a) serial operating mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 operation control in 3-wire serial i/o mode csie20 sse20 0 0 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled caution be sure to clear bits 4 and 5 to 0. (b) asynchronous serial interfa ce mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 receive operation control caution be sure to clear bits 0 and 1 to 0.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 179 13.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. this device incorporates a uart-dedicated baud rate gene rator that enables communication at the desired transfer rate from many options. in addition, the baud rate can also be defined by dividing the clock input to the asck pin. the uart-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the midi standard. it is recommended that ceramic/crystal oscillation be used for the system clock in the uart mode. because the frequency deviation is large in rc oscillation, if an internal clock is selected as the source clock for the baud rate generator, there may be problems in transmit/receive operations. (1) register setting the uart mode is set by serial operating mode regist er 20 (csim20), asynchronous serial interface mode register 20 (asim20), asynchronous serial interface st atus register 20 (asis20), baud rate generator control register 20 (brgc20), port mode register 2 (pm2), and port 2 (p2).
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 180 (a) serial operating mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock pulse input to sck20 pin output of dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection output at falling edge of sck20 output at rising edge of sck20 ss20-pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active low, and sck20 is high level in the idle state clock is active high, and sck20 is low level in the idle state cautions 1. bits 4 and 5 must be fixed to 0. 2. when uart mode is selected, clear csim20 to 00h.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 181 (b) asynchronous serial interfa ce mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification cautions 1. be sure to clear bits 0 and 1 to 0. 2. switch operating modes after halti ng the serial transmit/receive operation.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 182 (c) asynchronous serial interface status register 20 (asis20) asis20 is read with a 1-bit or 8-bit memory manipulation instruction. reset input clears asis20 to 00h. 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543210 pe20 0 1 parity error flag no parity error has occurred. a parity error has occurred (when the transmission parity and reception parity do not match). fe20 0 1 framing error flag no framing error has occurred. a framing error has occurred (when no stop bit is detected). note 1 ove20 0 1 overrun error flag no overrun error has occurred. an overrun error has occurred. note 2 (before data was read from the reception buffer register, the subsequent reception sequence was completed.) notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the stop bit det ection in the case of reception is performed with 1 bit. 2. be sure to read receive buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error will occur.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 183 (d) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 1 tps203 tps202 tps201 tps200 0000 brgc20 r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? setting prohibited symbol address after reset selection of source clock for baud rate generator external clock input to asck20 pin other than above 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 19.5 khz 5.0 mhz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation note expanded-specification products only cautions 1. when writing to brgc20 is perf ormed during a communication operation, the output of baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during communication operations. 2. be sure not to select n = 1 when f x > 2.5 mhz because n = 1 exceeds the rating of the baud rate. 3. be sure not to select n = 2 when f x > 5.0 mhz because n = 2 exceeds the rating of the baud rate. 4. when the external input clock is select ed, set port mode register 2 (pm2) to input mode. remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. n: values specified by the setting in tps200 to tps203 (1 n 8) the baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a signal divided from the clock input from the asck20 pin. (i) generation of baud rate transmit/receive clock by means of system clock the transmit/receive clock is generated by dividing the system clock. the baud rate generated from the system clock is estimated by using the following expression. f x [baud rate] = 2 n + 1 8 [bps] f x : system clock oscillation frequency (ceramic/crystal oscillation) n: values in the above table specified by the setting in tps200 to tps203 (2 n 8)
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 184 table 13-5. example of relationship between system clock and baud rate f x = 10.0 mhz note f x = 5.0 mhz f x = 4.9152 mhz baud rate (bps) n brgc20 setting error (%) n brgc20 setting error (%) n brgc20 setting error (%) 1,200 ? ? 8 70h 8 70h 2,400 8 70h 7 60h 7 60h 4,800 7 60h 6 50h 6 50h 9,600 6 50h 5 40h 5 40h 19,200 5 40h 4 30h 4 30h 38,400 4 30h 3 20h 3 20h 76,800 3 20h 1.73 2 10h 1.73 2 10h 0 note expanded-specification products only. cautions 1. be sure not to select n = 1 when f x > 2.5 mhz because n = 1 exceeds the rating of the baud rate. 2. be sure not to select n = 2 when f x > 5.0 mhz because n = 2 exceeds the rating of the baud rate. (ii) generation of baud rate tran smit/receive clock by means of external clock from asck20 pin the transmit/receive clock is generated by dividing the clock input from the asck20 pin. the baud rate generated from the clock input from the asck20 pin is estimated by using the following expression. f asck [baud rate] = 16 [bps] f asck : frequency of clock input to asck20 pin table 13-6. relationship between asck20 pin input frequency and baud rate (when brg c20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 185 (2) communication operation (a) data format the transmit/receive data format is as shown in figure 13-7. one data frame consists of a start bit, character bits, parity bit and stop bit(s). the specification of character bit length, parity select ion, and specification of stop bit length for each data frame is carried out using asynchronous serial interface mode register 20 (asim20). figure 13-7. asynchronous serial in terface transmit/receive data format d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame ? start bits ..................... 1 bit ? character bits .............. 7 bits/8 bits ? parity bits..................... even parity/o dd parity/0 parity/no parity ? stop bits ...................... 1 bit/2 bits when 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always ?0?. the serial transfer rate is selected by baud rate generator control register 20 (brgc20). if a serial data receive error occurs, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (asis20).
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 186 (b) parity types and operation the parity bit is used to detect a bit error in the comm unication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a ?1? bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity ? at transmission the transmission operation is contro lled so that the number of bits with a value of ?1? in the transmit data including parity bit is even. the parity bit value should be as follows. the number of bits with a value of ?1 ? is an odd number in transmit data: 1 the number of bits with a value of ?1 ? is an even number in transmit data: 0 ? at reception the number of bits with a value of ?1? in the rece ive data including parity bit is counted, and if the number is odd, a parity error is generated. (ii) odd parity ? at transmission opposite to even parity, the transmission operation is controlled so that t he number of bits with a value of ?1? in the transmit data including parity bit is odd. the parity bit value should be as follows. the number of bits with a value of ?1 ? is an odd number in transmit data: 0 the number of bits with a value of ?1 ? is an even number in transmit data: 1 ? at reception the number of bits with a value of ?1? in the rece ive data including parity bit is counted, and if the number is even, a parity error is generated. (iii) 0 parity when transmitting, the parity bit is set to ?0? irrespective of the transmit data. at reception, a parity bit check is not performed. t herefore, a parity error does not occur, irrespective of whether the parity bit is set to ?0? or ?1?. (iv) no parity a parity bit is not added to the transmit data. at recept ion, data is received assuming that there is no parity bit. since there is no parity bit, a parity error does not occur.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 187 (c) transmission a transmit operation is started by writ ing transmit data to transmit shift register 20 (txs20). the start bit, parity bit and stop bit(s) are added automatically. when the transmit operation starts, the data in txs20 is shifted out, and when txs20 is empty, a transmission completion interrupt (intst20) is generated. figure 13-8. asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 caution do not rewrite asynchronous serial interfa ce mode register 20 (asim20) during a transmit operation. if the asim20 register is re written during transmission, subsequent transmission may not be performed (the norma l state is restored by reset input). it is possible to determine whether transm ission is in progress by software by using a transmission completion interrupt (intst20) or the interrupt request flag (stif20) set by intst20.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 188 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set (1), a receive operation is enabled and sampling of the rxd20 pin input is performed. rxd20 pin input sampling is performed using the serial clock specified by brgc20. when the rxd20 pin input becomes low, the 3-bit co unter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling star t timing signal is output. if the rxd20 pin input sampled again as a result of this start ti ming signal is low, it is i dentified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to receive buffer register 20 (rxb20), and a reception co mpletion interrupt (intsr20) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb20, and intsr20 is generated. if the rxe20 bit is reset (0) during the receive operatio n, the receive operation is stopped immediately. in this case, the contents of rxb20 and asynchronous se rial interface status regi ster 20 (asis20) are not changed, and intsr20 is not generated. figure 13-9. asynchronous serial interfac e reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 caution be sure to read receive buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will occu r when the next data is received, and the receive error state will continue indefinitely.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 189 (e) receive errors the following three errors may occur during a receive operation: a parity error, framing error, or overrun error. the data reception result error flag is set in asynchronous serial interface status register 20 (asis20). receive error causes are shown in table 13-7. it is possible to determine what kind of error occurr ed during reception by r eading the contents of asis20 in the reception error inte rrupt servicing (refer to table 13-7 and figure 13-10 ). the contents of asis20 are reset (0) by reading receiv e buffer register 20 (rxb20) or receiving the next data (if there is an error in the next dat a, the corresponding error flag is set). table 13-7. receive error causes receive errors cause parity error transmission-time parity specification and receive data parity do not match framing error stop bit not detected overrun error reception of next data is completed before data is read from receive register buffer figure 13-10. receive error timing (a) parity error occurred stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 (b) framing error or overrun error occurred stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 cautions 1. the contents of the asis20 register ar e reset (0) by reading receive buffer register 20 (rxb20) or receiving the next data. to asc ertain the error contents, read asis20 before reading rxb20. 2. be sure to read receive buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 190 (f) reading receive data when the reception completion interrupt (intsr20) occurs, receive data can be read by reading the value of receive buffer register 20 (rxb20). to read the receive data stored in receive buffer register 20 (rxb20), read while reception is enabled (rxe20 = 1). remark however, if it is necessary to read receive data after reception has stopped (rxe20 = 0), read using either of the following methods. (a) read after setting rxe20 = 0 after waiting for one cycle or more of the source clock selected by brgc20. (b) read after bit 2 (dir20) of serial operating mode register 20 (csim20) is set (1). program example of (a) (brgc20 = 00h (source clock = f x /2)) intrxe: ; nop ;2 clocks clr1 rxe20 ;reception stopped mov a, rxb20 ;read receive data program example of (b) intrxe: ; set1 csim20.2 ;dir20 flag is set to lsb first clr1 rxe20 ;reception stopped mov a, rxb20 ;read receive data
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 191 (3) uart mode cautions (a) when bit 7 (txe20) of asynchronous serial interf ace mode register 20 (asim20) is cleared during transmission, be sure to set transmit shift register 20 (txs20) to ffh, then set txe20 to 1 before executing the next transmission. (b) when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is cleared during reception, receive buffer register 20 (rxb20) a nd receive completion interrupt 20 (intsr20) are as follows. parity rxd20 pin rxb20 intsr20 <3> <1> <2> when rxe20 is set to 0 at the time indicated by <1>, rxb20 holds the previous data and does not generate intsr20. when rxe20 is set to 0 at the time indicated by <2>, rxb20 renews the data and does not generate intsr20. when rxe20 is set to 0 at the time indicated by <3>, rxb20 renews the data and generates intsr20.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 192 13.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc. that incorporate a conventional clocked serial interface, such as the 75xl series, 78k series, and 17k series. communication is performed using three lines: the serial clock (sck20), serial output (so20), and serial input (si20). (1) register setting 3-wire serial i/o mode settings are performed using serial operating mode register 20 (csim20), asynchronous serial interface mode register 20 (asim20), baud rate generator control register 20 (brgc20), port mode register 2 (pm2), and port 2 (p2). (a) serial operating mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock pulse input to sck20 pin output of dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection output at falling edge of sck20 output at rising edge of sck20 ss20-pin selection function of ss20/p23 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active low, and sck20 is at high level in the idle state clock is active high, and sck20 is at low level in the idle state caution bits 4 and 5 must be fixed to 0.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 193 (b) asynchronous serial interfa ce mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification cautions 1. be sure to clear bits 0 and 1 to 0. 2. when the 3-wire serial i/o mode is selected, asim20 must be cleared to 00h. 3. switching operation modes must be pe rformed after the seri al transmit/receive operation is halted.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 194 (c) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 tps203 tps202 tps201 tps200 0000 brgc20 r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 tps201 0 0 1 1 0 0 1 1 tps200 0 1 0 1 0 1 0 1 n 1 2 3 4 5 6 7 8 setting prohibited symbol address after reset other than above f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 selection of source clock for baud rate generator 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz 19.5 khz 5.0 mhz 2.5 mhz 1.25 mhz 625 khz 313 khz 156 khz 78.1 khz 39.1 khz @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation note expanded-specification products only cautions 1. when writing to brgc20 is perf ormed during a communication operation, the baud rate generator output is disrupted and co mmunication cannot be performed normally. be sure not to write to brgc 20 during communication operations. 2. be sure not to select n = 1 when f x > 5.0 mhz in 3-wire serial i/o mode because n = 1 exceeds the rating of the serial clock. remarks 1. f x : system clock oscillation frequency (ceramic/crystal oscillation) 2. n: values specified by tps200 to tps203 (1 n 8) if the internal clock is used as the serial clock fo r the 3-wire serial i/o mode, set the tps200 to tps203 bits to set the frequency of the serial clock. to obtain the frequency to be set, use the following formula. when the serial clock is input from off-chip, setting brgc20 is not necessary. f x serial clock frequency = 2 n + 1 [hz] f x : system clock oscillation frequency (ceramic/crystal oscillation) n: values in the above table specified by the setting in tps200 to tps203 (1 n 8)
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 195 (2) communication operation in the 3-wire serial i/o mode, dat a transmission/rec eption is performed in 8- bit units. data is transmitted/received bit by bit in synchronization with the serial clock. the transmit shift register (txs20/sio20) and receive sh ift register (rxs20) shift operations are performed in synchronization with the fall of the serial clock (sck20 ). then transmit data is held in the so20 latch and output from the so20 pin. also, receive data input to the si0 pin is latched in the receive buffer register (rxb20/sio20) on the rise of sck20. at the end of an 8-bit transfer, the operation of txs20/sio20 or rxs20 st ops automatically, and an interrupt request signal (intcsi20) is generated. figure 13-11. 3-wire serial i/o mode timing (1/7) (i) master operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 note si20 sio20 write intcsi20 note the value of the last bit previously output is output.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 196 figure 13-11. 3-wire serial i/o mode timing (2/7) (ii) slave operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 sio20 write intcsi20 note the value of the last bit previously output is output. (iii) slave operation (when dap20 = 0, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 note 1 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 197 figure 13-11. 3-wire serial i/o mode timing (3/7) (iv) master operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20 (v) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 198 figure 13-11. 3-wire serial i/o mode timing (4/7) (vi) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state. (vii) master operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 199 figure 13-11. 3-wire serial i/o mode timing (5/7) (viii) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first falling edge of sck20. make sure that the mast er outputs the first bit before the first falling of sck20. (ix) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first falling edge of sck20. make sure that the master outputs the first bit before the first falling of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 200 figure 13-11. 3-wire serial i/o mode timing (6/7) (x) master operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 do7 note do6 do5 doi4 do3 do2 do1 di7 di6 di5 di4 di3 di2 di1 sck20 so20 si20 sio20 write intcsi20 di0 do0 note the value of the last bit previously output is output. (xi) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 sck20 si20 so20 sio20 write intcsi20 do7 note do6 do5 doi4 do3 do2 do1 do0 di0 note the value of the last bit previously output is output.
chapter 13 serial interface 20 user?s manual u14643ej3v0ud 201 figure 13-11. 3-wire serial i/o mode timing (7/7) (xii) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 note 1 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state. (3) transfer start serial transfer is started by setting transfer data to the transmit shift register (txs20/sio20) when the following two conditions are satisfied. ? serial operating mode register 20 (csim20) bit 7 (csie20) = 1 ? internal serial clock is stopped or sck20 is a high level after 8-bit serial transfer. caution if csie20 is set to ?1? after data is written to txs20/ sio20, transfer does not start. termination of 8-bit transfer stops the serial transfe r automatically and generates an interrupt request signal (intcsi20).
user?s manual u14643ej3v0ud 202 chapter 14 multiplier 14.1 multiplier function the multiplier has the following function. ? calculation of 8 bits 8 bits = 16 bits 14.2 multiplier configuration (1) 16-bit multiplication result storage register 0 (mul0) this register stores the 16-bi t result of multiplication. this register holds the result of multip lication after 16 cpu clocks have elapsed. mul0 is set with a 16-bit memory manipulation instruction. reset input makes this register undefined. caution although this register is manipulated with a 16-bit memory manipulation instruction, it can also be manipulated with an 8-bit memory manipulation instruction. when using an 8-bit memory manipulation instruction, however, access the register by means of direct addressing. (2) multiplication data regist ers a and b (mra0 and mrb0) these are 8-bit multiplicati on data storage registers. t he multiplier multiplies the values of mra0 and mrb0. mra0 and mrb0 are set with a 1-bit or 8-bit memory manipulation instructions. reset input makes these registers undefined. figure 14-1 shows the block diagram of the multiplier.
chapter 14 multiplier user?s manual u14643ej3v0ud 203 figure 14-1. block diagram of multiplier internal bus selector counter value 3 cpu clock start clear counter output 16-bit adder 16-bit multiplication result storage register 0 (master) (mul0) 16-bit multiplication result storage register 0 (slave) multiplication data register a (mra0) multiplication data register b (mrb0) internal bus 3-bit counter mulst0 reset multiplier control register 0 (mulc0)
chapter 14 multiplier user?s manual u14643ej3v0ud 204 14.3 multiplier control register the multiplier is controlled by the following register. ? multiplier control register 0 (mulc0) mulc0 indicates the operating status of the multiplier after operation, as well as controls the multiplier. mulc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 14-2. format of multiplier control register 0 mulst0 0 1 multiplier operation start control bit 0000000 mulst0 mulc0 symbol address after reset r/w ffd2h 00h r/w 76543210 stop operation after resetting counter to 0. enable operation operation stopped operation in progress operating status of multiplier caution be sure to clear bits 1 to 7 to 0.
chapter 14 multiplier user?s manual u14643ej3v0ud 205 14.4 multiplier operation the multiplier of the pd789104a/114a/124a/134a subseries can execute the calculation of 8 bits 8 bits = 16 bits. figure 14-3 shows the operation timing of the multip lier where mra0 is set to aah and mrb0 is set to d3h. <1> counting is started by setting mulst0. <2> the data generated by the selector is added to the data of mul0 at each cpu clock, and the counter value is incremented by one. <3> if mulst0 is cleared when the counter value is 111b, the operation is stopped. at this time, mul0 holds the data. <4> while mulst0 is low, the counter and slave are cleared. figure 14-3. multiplier operation timing aa d3 000b 00aa 0000 001b 010b 011b 100b 101b 110b 111b 000b 0154 0000 0000 0aa0 0000 2a80 5500 00aa 00aa 01fe 01fe 01fe 0c9e 0c9e 371e 8c1e 00aa 01fe 01fe 01fe 0c9e 0c9e 371e 0000 cpu clock mra0 mrb0 mulst0 counter selector output mul0 (master) (slave)
user?s manual u14643ej3v0ud 206 chapter 15 interrupt functions 15.1 interrupt function types the following two types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. there is one non-maskable interrupt source, which is from the watchdog timer. (2) maskable interrupt these interrupts undergo mask control. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in table 15-1. a standby release signal is generated. there are nine maskable interrupt sources: three external interrupts and six internal interrupts.
chapter 15 interrupt functions user?s manual u14643ej3v0ud 207 15.2 interrupt sources and configuration there are total of 10 non-maskable and maskable interrupt sources (refer to table 15-1 ). table 15-1. interrupt source list interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration ty p e note 2 non- maskable ? intwdt watchdog timer overflow (watchdog timer mode 1 selected) (a) 0 intwdt watchdog timer overflow (interval timer mode selected) internal 0004h (b) 1 intp0 0006h 2 intp1 0008h 3 intp2 pin input edge detection external 000ah (c) intsr20 end of serial interface 20 uart reception 4 intcsi20 end of serial interface 20 3-wire transfer 000ch 5 intst20 end of serial interface 20 uart transmission 000eh 6 inttm80 generation of 8-bit timer/event counter 80 match signal 0010h 7 inttm20 generation of 16-bit timer 20 match signal 0012h maskable 8 intad0 a/d conversion completion signal internal 0014h (b) notes 1. priority is the priority applicable when two or more maskable interrupts are simultaneously generated. 0 is the highest priority and 8 is the lowest priority. 2. basic configuration types a to c correspond to a to c in figure 15-1. remark as the interrupt source of the watchdog timer (intwd t), either a non-maskable interrupt or a maskable interrupt (internal) can be selected.
chapter 15 interrupt functions user?s manual u14643ej3v0ud 208 figure 15-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus external interrupt mode register (intm0) interrupt request edge detector vector table address generator standby release signal if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
chapter 15 interrupt functions user?s manual u14643ej3v0ud 209 15.3 interrupt function control registers the following four registers are used to control the interrupt functions. ? interrupt request flag registers (if0, if1) ? interrupt mask flag registers (mk0, mk1) ? external interrupt mode register (intm0) ? program status word (psw) table 15-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. table 15-2. flags corresponding to interrupt request signals interrupt request signal name interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intsr20/intcsi20 intst20 inttm80 inttm20 intad0 tmif4 pif0 pif1 pif2 srif20 stif20 tmif80 tmif20 adif0 tmmk4 pmk0 pmk1 pmk2 srmk20 stmk20 tmmk80 tmmk20 admk0
chapter 15 interrupt functions user?s manual u14643ej3v0ud 210 (1) interrupt request flag registers (if0, if1) the interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset input. if0 and if1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input clears these registers to 00h. figure 15-2. format of interrupt request flag register 0 1 tmif20 tmif80 stif20 srif20 pif2 pif1 pif0 tmif4 if0 r/w ffe0h 00h r/w symbol address after reset interrupt request flag no interrupt request signal is generated interrupt request signal is generated; interrupt request state if <6> <5> <4> <3> <2> <1> <7> <0> 0000000 adif0 if1 r/w ffe1h 00h r/w symbol address after reset 654321 7 <0> cautions 1. tmif4 flag is r/w enabled only when the watchdog timer is used as an interval timer. if watchdog timer mode 1 and 2 are used, set the tmif4 flag to 0. 2. because port 2 has an altern ate function as the external in terrupt input, wh en the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask fl ag should be set to 1 before using the output mode. 3. when an interrupt is acknowledged, the inte rrupt request flag is automatically cleared and the interrupt routine is entered.
chapter 15 interrupt functions user?s manual u14643ej3v0ud 211 (2) interrupt mask flag registers (mk0, mk1) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. mk0 and mk1 are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. figure 15-3. format of interrupt mask flag register 0 1 tmmk20 tmmk80 stmk20 srmk20 pmk2 pmk1 pmk0 tmmk4 mk0 r/w ffe4h ffh r/w symbol address after reset interrupt servicing control interrupt servicing enabled interrupt servicing disabled <6> <5> <4> <3> <2> <1> <7> <0> mk 1111111 admk0 mk1 r/w ffe5h ffh r/w symbol address after reset 654321 7 <0> cautions 1. if the tmmk4 flag is read when th e watchdog timer is used in watchdog timer mode 1 and 2, its value becomes undefined. 2. because port 2 has an altern ate function as the external in terrupt input, wh en the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask fl ag should be set to 1 before using the output mode.
chapter 15 interrupt functions user?s manual u14643ej3v0ud 212 (3) external interrupt m ode register 0 (intm0) this register is used to set the valid edge of intp0 to intp2. intm0 is set with an 8-bit memory manipulation instruction. reset input clears intm0 to 00h. figure 15-4. format of external interrupt mode register 0 0 0 1 1 es21 es20 es11 es10 es01 es00 0 0 intm0 r/w ffech 00h r/w 76543210 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 symbol address after reset intp0 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp1 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp2 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es00 es01 es11 es10 es20 es21 cautions 1. be sure to clear bits 0 and 1 to 0. 2. before setting the intm0 register, be sure to set the corresponding interrupt mask flag ( mk = 1) to disable interrupts. after setti ng the intm0 register, clear the interrupt request flag ( if = 0), then clear the interrupt mask flag ( mk = 0), which will enable interrupts.
chapter 15 interrupt functions user?s manual u14643ej3v0ud 213 (4) program status word (psw) the program status word is a register used to hold the instruction execut ion result and the current status for interrupt requests. the ie flag used to set maskable interrupt enable/disable is mapped to the psw. this register can be read/written in 8-bit units an d can carry out operations using bit manipulation and dedicated instructions (ei, di). when a vectored interrup t request is acknowledged, the psw is automatically saved into a stack, and the ie flag is reset to 0. it is restored from the stack by the reti and pop psw instructions. reset input sets the psw to 02h. figure 15-5. program status word configuration ie z 0 ac 0 0 1 cy psw 76543210 ie 0 1 02h symbol after reset used when normal instruction is executed interrupt acknowledgment enable/disable disabled enabled
chapter 15 interrupt functions user?s manual u14643ej3v0ud 214 15.4 interrupt servicing operation 15.4.1 non-maskable interrupt request acknowledgment operation a non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when a non-maskable interrupt request is acknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector tabl e are loaded to the pc, and then program execution branches. figure 15-6 shows the flowchart from non-maskable interrupt request generation to acknowledgment. figure 15-7 shows the timing of non-maskable interrupt request acknowledgment. figure 15-8 shows the acknowledgment operation if multiple non-maskable interrupts are generated. caution during non-maskable interr upt servicing program execution, do not input another non-maskable interrupt request; if it is input, the servicing program will be interrupted and the new interrupt request will be acknowledged.
chapter 15 interrupt functions user?s manual u14643ej3v0ud 215 figure 15-6. flowchart from non-maskable in terrupt request generation to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing is started wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 15-7. timing of non-maskable interrupt request acknowledgment instruction instruction save psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing tmif4 figure 15-8. acknowledging n on-maskable interrupt request second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine
chapter 15 interrupt functions user?s manual u14643ej3v0ud 216 15.4.2 maskable interrupt requ est acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vectored interrupt request is acknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in ta bl e 1 5 - 3 . refer to figures 15-10 and 15-11 for the interrupt request acknowledgment timing. table 15-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated immediately before the bt or bf instruction. 1 remark 1 clock: f cpu (f cpu : cpu clock) when two or more maskable interrupt requests are gener ated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. a pending interrupt is acknowledged when the status in which it can be acknowledged is set. figure 15-9 shows the algorithm of acknowledging interrupt requests. when a maskable interrupt request is acknowledged, the contents of the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt servic ing, use the reti instruction.
chapter 15 interrupt functions user?s manual u14643ej3v0ud 217 figure 15-9. interrupt acknowledgment program algorithm start if = 1 ? mk = 0 ? ie = 1 ? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending if: interrupt request flag mk: interrupt mask flag ie: flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)
chapter 15 interrupt functions user?s manual u14643ej3v0ud 218 figure 15-10. interrupt request acknow ledgment timing (example of mov a,r) clock cpu interrupt mov a,r save psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program if an interrupt request flag ( if) is set before instruction clock n (n = 4 to 10) under execution becomes n ? 1, the interrupt is acknowledged after the instruction under execut ion is complete. figure 15-10 shows an example of the interrupt request acknowledgment timing for an 8-bit data tr ansfer instruction mov a,r. since this instruction is executed for 4 clocks, if an interrupt occurs for 3 cloc ks after the execution starts, the interrupt acknowledgment processing is performed after the mo v a,r instruction is completed. figure 15-11. interrupt request acknowledgment timing (when interrupt request fl ag is generated at last clock during instruction execution) save psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program clock cpu interrupt nop mov a,r if an interrupt request flag ( if) is set at the last clock of the instru ction, the interrupt acknowledgment processing starts after the next instruction is executed. figure 15-11 shows an example of the interrupt acknowledgm ent timing for an interrupt request flag that is set at the second clock of nop (2-clock instruction). in this case, the mov a,r instruction after the nop instruction is executed, and then the interrupt acknowledgment processing is performed. caution interrupt requests are held pending while the in terrupt request flag register (if0, if1) or the interrupt mask flag register (mk0, mk1) is being accessed. 15.4.3 multiple interrupt servicing multiple interrupt servicing, in which an interrupt is ac knowledged while another interrupt is being serviced, can be executed by priority. when the priority is controlled by th e default priority and two or more interrupts are generated at the same time, interrupt servicing is performed according to the priority assigned to each interrupt request in advance (refer to table 15-1 ).
chapter 15 interrupt functions user?s manual u14643ej3v0ud 219 figure 15-12. example of multiple interrupt servicing example 1. multiple interrupts are acknowledged intyy ei main processing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 during interrupt intxx servicing, interrupt request intyy is acknowledged, and multiple interrupt servicing occurs. the ei instruction is issued before each interrupt req uest acknowledgment, and the interrupt request acknowledgment enabled state is set. example 2. multiple interrupt servicing do es not occur because inte rrupts are not enabled intyy ei main processing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupts are not enabled in interrupt intxx servic ing (the ei instruction is not issued), interrupt request intyy is not acknowledged, and a multiple interrupt servic ing does not occur. the intyy request is held pending and acknowledged after the intxx servicing is performed. ie = 0: interrupt request acknowledgment disabled
chapter 15 interrupt functions user?s manual u14643ej3v0ud 220 15.4.4 interrupt request hold some instructions may hold the acknowledgment of an instruction request pending until completion of the execution of the next instru ction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. the follo wing shows such instructions (interrupt request hold instructions). ? manipulation instruction for the interrupt request flag registers (if0, if1) ? manipulation instruction for the interrupt mask flag registers (mk0, mk1)
user?s manual u14643ej3v0ud 221 chapter 16 standby function 16.1 standby function and configuration 16.1.1 standby function the standby function is used to reduce the power cons umption of the system and can be effected in the following two modes. (1) halt mode this mode is set when the halt instruction is executed. the halt mode stops the operation clock of the cpu. the system clock oscillator continues oscillating. this mode does not reduce the power consumption as much as the stop mode, but is useful for resuming proce ssing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is ex ecuted. the stop mode stops the main system clock oscillator and stops the entire system. the power consumption of the cpu ca n be substantially reduced in this mode. the low voltage of the data memory (v dd = 1.8 v) can be held. therefore, this mode is useful for holding the contents of the data memory at an ex tremely low current consumption. the stop mode can be released by an interrupt reque st, so that this mode can be used for intermittent operations. however, some time is required until th e system clock oscillator stab ilizes after the stop mode has been released. if processing must be resumed immediately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all held. in addition, the statuses of the output latches of the i/o ports and output buffers are also retained. caution to set the stop mode, be sure to stop th e operations of the periph eral hardware, and then execute the stop instruction.
chapter 16 standby function user?s manual u14643ej3v0ud 222 16.1.2 standby function control register ( pd789104a, 789114a subseries) the wait time after the stop mode is released upon interrupt request until the oscillation stabilizes is controlled by the oscillation stabilization ti me select register (osts) note . osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, the osci llation stabilization time after reset input is 2 15 /f x , instead of 2 17 /f x . note pd789104a and 789114a subseries only. the pd789124a and 789134a subseries do not provide an o scillation stabilization time select register. the oscillation stabiliz ation time of the pd789124a and 789134a subseries is fixed to 2 7 /f cc . figure 16-1. format of oscillation st abilization time select register osts2 0 0 1 00000 osts2 osts1 osts0 osts r/w fffah 04h r/w 76543210 osts1 0 1 0 2 12 /f x 2 15 /f x 2 17 /f x osts0 0 0 0 setting prohibited symbol address after reset oscillation stabilization time selection other than above @ f x = 10.0 mhz note operation @ f x = 5.0 mhz operation 409 s 3.28 ms 13.1 ms 819 s 6.55 ms 26.2 ms note expanded-specification products only caution the wait time after the st op mode is released when using a ceramic/crystal oscillator does not include the time from stop mode release to clock oscillation start ( ? a ? in the figure below), regardless of whether stop mode was released by reset input or by interrupt generation. stop mode release x1 pin voltage waveform a remark f x : system clock oscillation frequency (ceramic/crystal oscillation)
chapter 16 standby function user?s manual u14643ej3v0ud 223 16.2 operation of standby function 16.2.1 halt mode (1) halt mode the halt mode is set by exec uting the halt instruction. the operation status in the halt m ode is shown in the following table. table 16-1. halt mode operating status item halt mode operating status clock generator system clock can be oscillated. clock supply to cpu stops. cpu operation stopped port (output latch) holds status before setting the halt mode. 16-bit timer 20 operable 8-bit timer/event counter 80 operable watchdog timer operable serial interface 20 operable a/d converter operation stopped multiplier operation stopped external interrupt operable note note maskable interrupt that is not masked
chapter 16 standby function user?s manual u14643ej3v0ud 224 (2) releasing halt mode the halt mode can be released by the following three sources. (a) releasing by unmasked interrupt request the halt mode is released by an unmasked interrupt request. in this case, if the interrupt request is able to be acknowledged, vectored interrupt servicing is per formed. if interrupts are disabled, the instruction at the next address is executed. figure 16-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operating mode operating mode clock oscillation remarks 1. the broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt servicing is performed: 9 to 10 clocks ? when vectored interrupt servicing is not performed: 1 to 2 clocks (b) releasing by non-maskable interrupt request the halt mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed.
chapter 16 standby function user?s manual u14643ej3v0ud 225 (c) releasing by reset input when the halt mode is released by the reset signal, ex ecution branches to the reset vector address in the same manner as an ordinary reset operat ion, and program execution is started. figure 16-3. releasing halt mode by reset input halt instruction reset signal wait note reset period halt mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation note in the pd789104a and 789114a subseries, 2 15 /f x : 6.55 ms (at f x = 5.0 mhz operation), 3.28 ms (at f x = 10.0 mhz operation) in the pd789124a and 789134a subseries, 2 7 /f cc : 32 s (at f cc = 4.0 mhz operation) remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation) table 16-2. operation after release of halt mode releasing source mk ie operation 0 0 next address instruction is executed 0 1 interrupt servicing is executed maskable interrupt request 1 halt mode is held non-maskable interrupt request ? interrupt servicing is executed reset input ? ? reset processing : don?t care
chapter 16 standby function user?s manual u14643ej3v0ud 226 16.2.2 stop mode (1) setting and operation status of stop mode the stop mode is set by exec uting the stop instruction. caution because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt s ource whose interrupt request flag is set and interrupt mask flag is reset. when the stop mode is set, therefore, the halt mode is set immediately after the stop instruction h as been executed, the wait time set by the oscillation stabilization time select register (ost s) elapses, and then an operation mode is set. the operation status in the stop m ode is shown in the following table. table 16-3. stop mode operating status item stop mode operating status clock generator system clock oscillation stopped cpu operation stopped port (output latch) holds the status before setting the stop mode 16-bit timer 20 operation stopped 8-bit timer/event counter 80 operable note 1 watchdog timer operation stopped serial interface 20 operable note 2 a/d converter operation stopped multiplier operation stopped external interrupt operable note 3 notes 1. operation is possible only when ti80 is selected as the count clock. 2. operation is possible in both 3-wire serial i/o and uart modes while an external clock is being used. 3. maskable interrupt that is not masked
chapter 16 standby function user?s manual u14643ej3v0ud 227 (2) releasing stop mode the stop mode can be released by the following two sources. (a) releasing by unmasked interrupt request the stop mode can be released by an unmasked interrupt request. in this case, if the interrupt is able to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed. if interrupts are disabled, the inst ruction at the next address is executed. figure 16-4. releasing stop mode by interrupt stop instruction standby release signal wait note (set time by osts) stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation note osts is not provided in the pd789124a and 789134a subseries, and the wait time is fixed to 2 7 /f cc . remark the broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged.
chapter 16 standby function user?s manual u14643ej3v0ud 228 (b) releasing by reset input when the stop mode is released by the reset si gnal, the reset operation is performed after the oscillation stabilization time has elapsed. figure 16-5. releasing stop mode by reset input stop instruction reset signal wait note stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation reset period note in the pd789104a and 789114a subseries, 2 15 /f x : 6.55 ms (at f x = 5.0 mhz operation), 3.28 ms (at f x = 10.0 mhz operation) in the pd789124a and 789134a subseries, 2 7 /f cc : 32 s (at f cc = 4.0 mhz operation) remark f x : system clock oscillation frequency (ceramic/crystal oscillation) f cc : system clock oscillation frequency (rc oscillation) table 16-4. operation after release of stop mode releasing source mk ie operation 0 0 next address instruction is executed 0 1 interrupt servicing is executed maskable interrupt request 1 stop mode is held reset input ? ? reset processing : don?t care
user?s manual u14643ej3v0ud 229 chapter 17 reset function the following two operations are available to generate reset signals. (1) external reset input via reset pin (2) internal reset by program loop time detection with watchdog timer external and internal resets have no functional differences . in both cases, program execution starts at addresses 0000h and 0001h by reset signal input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware item is set to the status shown in table 17-1. each pin is high impedance during reset input or during the oscillation stabilization time just after reset clear. when a high level is input to the reset pin, the reset is cleared and program execution is started after the oscillation stabilization time has elapsed. the reset applie d by the watchdog timer overflow is automatically cleared after reset, and program execution is started after t he oscillation stabilization time has elapsed (refer to figures 17-2 to 17-4 ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pins become high impedance. figure 17-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer over- flow reset signal stop
chapter 17 reset function user?s manual u14643ej3v0ud 230 figure 17-2. reset timing by reset input x1, cl1 reset internal reset signal port pin during normal operation reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing) delay delay hi-z figure 17-3. reset timing by overflow in watchdog timer x1, cl1 internal reset signal port pin overflow in watchdog timer during normal operation reset period (oscillation continues) oscillation stabilization time wait normal operation (reset processing) hi-z figure 17-4. reset timing by reset input in stop mode x1, cl1 reset internal reset signal port pin hi-z delay delay stop instruction execution during normal operation stop status (oscillation stops) reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing)
chapter 17 reset function user?s manual u14643ej3v0ud 231 table 17-1. hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 the contents of reset vector tables (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0 to p2, p5) (output latch) 00h port mode registers (pm0 to pm2, pm5) ffh pull-up resistor option register 0 (pu0) 00h pull-up resistor option register b2 (pub2) 00h processor clock control register (pcc) 02h oscillation stabilization time select register (osts) note 3 04h timer counter (tm20) 0000h compare register (cr20) ffffh mode control register (tmc20) 00h 16-bit timer 20 capture register (tpc20) undefined timer counter (tm80) 00h compare register (cr80) undefined 8-bit timer/event counter 80 mode control register (tmc80) 00h timer clock select register (tcl2) 00h watchdog timer mode register (wdtm) 00h mode register (adm0) 00h input channel specification register (ads0) 00h a/d converter conversion result register (adcr0) undefined mode register (csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface status register (asis20) 00h baud rate generator control register (brgc20) 00h transmit shift register (txs20) ffh serial interface 20 receive buffer register (rxb20) undefined notes 1. during reset input and oscillation stabilization ti me wait, only the pc contents among the hardware statuses become undefined. all other hardware remains unchanged after reset. 2. if the reset signal is input in the standby mode, t he status before reset is retained even after reset. 3. pd789104a, 789114a subseries only
chapter 17 reset function user?s manual u14643ej3v0ud 232 table 17-1. hardware status after reset (2/2) hardware status after reset 16-bit multiplication result storage register (mul0) undefined data register a (mra0) undefined data register b (mrb0) undefined multiplier control register (mulc0) 00h request flag register (if0, if1) 00h mask flag register (mk0, mk1) ffh interrupts external interrupt mode register (intm0) 00h
user?s manual u14643ej3v0ud 233 chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b the pd78f9116a and 78f9116b are versions with flash memo ry instead of the internal rom of the mask rom versions in the pd789104a and 789114a subseries. the pd78f9136a and 78f9136b are versions with flash memory instead of the internal ro m of the mask rom versions in the pd789124a and 789134a subseries. the differences between the flash memory and the mask rom versions are shown in table 18-1. table 18-1. differences between fl ash memory and mask rom versions flash memory mask rom pd78f9116a pd78f9116b pd789101a pd789111a pd789102a pd789112a pd789104a pd789114a item pd78f9136a pd78f9136b pd789121a pd789131a pd789122a pd789132a pd789124a pd789134a rom 16 kb (flash memory) 2 kb 4 kb 8 kb internal memory high-speed ram 256 bytes pull-up resistors 12 (software control only) 16 (software control: 12, mask option specification: 4) v pp pin provided not provided electrical specifications refer to the re levant electrical specifications chapter. cautions 1. there are differences in noise imm unity and noise radiation be tween the flash memory versions and mask rom versions. when pre- producing an application set with the flash memory version and then mass-p roducing it with the mask rom version, be sure to conduct sufficient evaluations for th e commercial samples (not engi neering samples) of the mask rom versions. 2. a/d conversion result register 0 (adcr0) is manipulated by an 8-bit memory manipulation instruction or a 16-bit memory manipulation instru ction, when used as an 8-bit a/d converter ( pd789104a, 789124a subseries) or 10-bit a/d converter ( pd789114a, 789134a subseries), respectively. however, if the pd78f9116a and 78f9116b are used as the flash memory versions of the pd789101a, 789102a, and 789104a, adcr0 can be manipulated by an 8-bit memory manipulation instruction, providing an ob ject file has been assembled in the pd789101a, 789102a, 789104a. if the pd78f9136a and 78f9136b are used as the flash memory versions of the pd789121a, 789122a, and 789124a, adcr0 ca n be manipulated by an 8-bit memory manipulation instruction, providing an ob ject file has been assembled in the pd789121a, 789122a, or 789124a.
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 234 18.1 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the fl ash memory mounted on the target system (on-board programming). a flash memory writ ing adapter (program adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are produc ts of naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcont roller is solder-mounted on the target system. ? distinguishing software facilities low-quantity, varied model production ? easy data adjustment when starting mass production 18.1.1 programming environment the following shows the environment required for pd78f9116a, 78f9116b, 78f9136a, and 78f9136b flash memory programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 18-1. environment for wr iting program to flash memory host machine rs-232c usb dedicated flash programmer pd78f9116a, 78f9116b, 78f9136a, 78f9136b v pp v dd v ss reset 3-wire serial i/o or uart or pseudo 3-wire
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 235 18.1.2 communication mode use the communication mode shown in table 18-2 or 18-3 to perform communication between the dedicated flash programmer and the pd78f9116a, 78f9116b, 78f9136a, or 78f9136b. table 18-2. communication mode list ( pd78f9116a, 78f9136a) type setting note 1 communication mode comm port sio clock cpu clock flash clock multiple rate pins used note 2 number of v pp pulses 3-wire serial i/o (sio3) sio ch-0 (3-wire, sync.) 100 hz to 1.25 mhz note 3 optional 1 to 5 mhz note 3 1.0 sck20/asck20/p20 so20/txd20/p21 si20/rxd20/p22 0 uart (uart0) uart ch-0 4800 to 76800 bps note 3, 4 optional note 5 4.91 or 5 mhz note 3 1.0 txd20/so20/p21 rxd20/si20/p22 8 pseudo 3-wire port a (pseudo 3- wire) 100 hz to 1 mhz note 3 optional 1 to 5 mhz note 3 1.0 p00 p01 p02 12 table 18-3. communication mode list ( pd78f9116b, 78f9136b) type setting note 1 communication mode comm port sio clock cpu clock flash clock multiple rate pins used note 2 number of v pp pulses sio ch-0 (3-wire, sync.) sck20/asck20/p20 so20/txd20/p21 si20/rxd20/p22 0 3-wire serial i/o sio ch-1 (3-wire, sync.) 100 hz to 1.25 mhz note 3 optional 1 to 10 mhz note 3 1.0 p00 p01 p02 1 uart uart ch-0 4800 to 76800 bps note 3, 4 optional note 5 4.91, 5, or 10 mhz note 3 1.0 txd20/so20/p21 rxd20/si20/p22 8 notes 1. selection items for type setti ngs on the dedicated flash progra mmer (flashpro iii/flashpro iv). 2. when the system shifts to the flash memory programmi ng mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. if the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to v dd or v ss via a resistor. 3. the possible setting range differs depending on the voltag e. for details, refer to the relevant electrical specifications chapter. 4. because signal wave slew also affects uart communication, in addition to the baud rate error, thoroughly evaluate the slew. 5. only for flashpro iv. however, when using flashpro iii, be sure to select the cl ock of the resonator on the board. uart cannot be used with the clock supplied by flashpro iii. caution be sure to select the communication mode accord ing to the number of v pp pulses shown in table 18-2 or 18-3.
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 236 figure 18-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n v pp pulses
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 237 figure 18-3. example of connection with dedicated flash programmer (1/2) (a) 3-wire serial i/o mode (sio ch-0) vpp1 vdd reset sck so si gnd v pp v dd , av dd reset clk note 1 x1 (p03 note 2 ) sck20 si20 so20 v ss , av ss dedicated flash programmer pd78f9116a, 78f9116b, 78f9136a, 78f9136b (b) 3-wire serial i/o mode (sio ch-1) ( pd78f9116b, 78f9136b only) vpp1 vdd reset sck so si gnd v pp v dd , av dd reset clk note 1 x1 (p03 note 2 ) p00 (serial clock) p02 (serial input) p01 (serial output) v ss , av ss pd78f9116b, 78f9136b dedicated flash programmer notes 1. connect this pin when the system clock is supp lied by the dedicated flash programmer. when a resonator has already been connected to the x1 pin, the clk pin does not need to be connected. 2. pd78f9136a, 78f9136b only cautions 1. the v dd pin, if already connected to the power s upply, must be connected to the vdd pin of the dedicated flash programmer. before using the power supply connected to the v dd pin, supply voltage before starting programming. 2. in the pd78f9136a and 78f9136b, use the p03 pin as the pin for system clock input from the dedicated flash programmer.
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 238 figure 18-3. example of connection with dedicated flash programmer (2/2) (c) uart mode vpp1 vdd reset so si gnd v pp v dd , av dd reset clk note 1 x1 (p03 note 2 ) rxd20 txd20 v ss , av ss pd78f9116a, 78f9116b, 78f9136a, 78f9136b dedicated flash programmer (d) pseudo 3-wire mode ( pd78f9116a, 78f9136a only) vpp1 vdd reset sck so si gnd v pp v dd , av dd reset clk note 1 x1 (p03 note 2 ) p00 (serial clock) p02 (serial input) p01 (serial output) v ss , av ss pd78f9116a, 78f9136a dedicated flash programmer notes 1. connect this pin when the system clock is supp lied by the dedicated flash programmer. when a resonator has already been connected to the x1 pin, the clk pin does not need to be connected. 2. pd78f9136a, 78f9136b only cautions 1. the v dd pin, if already connected to the power s upply, must be connected to the vdd pin of the dedicated flash programmer. before using the power supply connected to the v dd pin, supply voltage before starting programming. 2. in the pd78f9136a and 78f9136b, use the p03 pin as the pin for system clock input from the dedicated flash programmer.
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 239 if flashpro iii/flashpro iv is used as the dedicated flas h programmer, the following signals are generated for the pd78f9116a, 78f9116b, 78f9136a, and 78f 9136b. for details, refer to the manual of flashpro iii/flashpro iv. table 18-4. pin connection list signal name i/o pin function pin name 3-wire serial i/o uart pseudo 3-wire vpp1 output write voltage v pp vpp2 ? ? ? vdd i/o v dd voltage generation/ voltage monitoring v dd /av dd note 1 note 1 note 1 gnd ? ground v ss /av ss clk output clock output x1 (p03 note 2 ) reset output reset signal reset si input reception signal so20/p01/txd20 so output transmit signal si20/p02/rxd20 sck output transfer clock sck20/p00 hs ? ? ? notes 1. v dd voltage must be supplied befor e programming is started. 2. pd78f9136a, 78f9136b only remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected.
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 240 18.1.3 on-board pin processing when performing programming on the target system, provi de a connector on the target system to connect the dedicated flash programmer. an on-board function that allows swit ching between normal operation mode and flash memory programming mode may be required in some cases. in normal operation mode, input 0 v to the v pp pin. in flash memory programming mode, a write voltage of 10.0 v (typ.) is supplied to the v pp pin, so perform the following. (1) connect a pull-down resistor (rv pp = 10 k ? ) to the v pp pin. (2) use the jumper on the board to switch the v pp pin input to either the programmer or directly to gnd. a v pp pin connection example is shown below. figure 18-4. v pp pin connection example pd78f9116a, 78f9116b, 78f9136a, 78f9136b v pp connection pin of dedicated flash programmer pull-down resistor (rv pp ) the following shows the pins used by the serial interface. < pd78f9116a, 78f9136a> serial interface pins used 3-wire serial i/o sck20, so20, si20 uart txd20, rxd20 pseudo 3-wire p00, p01, p02 < pd78f9116b, 78f9136b> serial interface pins used sck20, so20, si20 3-wire serial i/o p00, p01, p02 uart txd20, rxd20 when connecting the dedicated flash programmer to a serial interface pin that is connected to another device on- board, signal conflict or abnormal oper ation of the other device may occur. care must therefore be taken with such connections.
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 241 (1) signal conflict if the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this, isolate t he connection with the other device or set the other device to the output high impedance status. figure 18-5. signal conflict (input pin of serial interface) input pin signal conflict connection pin of dedicated flash programmer other device output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict; therefore, isolate the signal of the other device. pd78f9116a, 78f9116b, 78f9136a, 78f9136b (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connec ted to a serial interface pi n (input or output) that is connected to another device (input), a signal is out put to the device, and this may cause an abnormal operation. to prevent this abnormal operation, isolate t he connection with the other de vice or set so that the input signals to the other device are ignored. figure 18-6. abnormal operation of other device pin connection pin of dedicated flash programmer other device input pin if the signal output by the pd78f9116a, 78f9116b, 78f9136a, or 78f9136b affects another device in the flash memory programming mode, isolate the signals of the other device. pin connection pin of dedicated flash programmer other device input pin if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. pd78f9116a, 78f9116b, 78f9136a, 78f9136b pd78f9116a, 78f9116b, 78f9136a, 78f9136b
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 242 if the reset signal of the dedicated flash programmer is connected to the reset pin connected to the reset signal generator on-board, a signal conflict occurs. to prevent this, isolate the connection with the reset signal generator. if the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. therefore, do not in put reset signals from other than the dedicated flash programmer. figure 18-7. signal conflict (reset pin) reset connection pin of dedicated flash programmer reset signal generator signal conflict output pin the signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator. pd78f9116a, 78f9116b, 78f9136a, 78f9136b when the flash memory programming mode is set, all the pi ns other than those that communicate with the flash programmer are in the same status as immediately after reset. if the external device does not recognize initial statuses such as the output high im pedance status, therefore, connect the external device to v dd or v ss . when using the on-board clock, connect x1 and x2 as required in the normal operation mode. when using the clock output of the flash programmer, connec t it directly to x1, disconnecting the main resonator on-board, and leave the x2 pin open. when using the power supply output of the flash programmer, connect the v dd and v ss pins to vdd and gnd of the flash programmer, respectively. when using the on-board power supply, connect it as requ ired in the normal operation mode. because the flash programmer monitors the voltage, however, v dd of the flash programmer must be connected. for the other power pins (av dd and a ss ), supply the same power supply as in the normal operation mode.
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 243 18.1.4 connection when using fl ash memory writing adapter the following shows an example of the recommended connec tion when using the flash memory writing adapter. figure 18-8. example of flash me mory writing adapter connection when using 3-wire serial i/o mode (sio-ch0) (a) pd78f9116a, 78f9116b 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9116a pd78f9116b vdd2 (lvdd) vdd gnd si so sck clkout reset vpp reserve/hs flash programmer interface v dd (2.7 to 5.5 v) gnd (b) pd78f9136a, 78f9136b 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9136a pd78f9136b vdd2 (lvdd) vdd gnd si so sck clkout reset vpp reserve/hs flash programmer interface v dd (2.7 to 5.5 v) gnd
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 244 figure 18-9. example of flash me mory writing adapter connection when using 3-wire serial i/o mode (sio-ch1) (a) pd78f9116b 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9116b vdd2 (lvdd) vdd gnd si so sck clkout reset vpp reserve/hs v dd (2.7 to 5.5 v) gnd flash programmer interface (b) pd78f9136b 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9136b vdd2 (lvdd) vdd gnd si so sck clkout reset vpp reserve/hs v dd (2.7 to 5.5 v) gnd flash programmer interface
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 245 figure 18-10. example of flash memory writin g adapter connection when using uart mode (a) pd78f9116a, 78f9116b 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9116a pd78f9116b vdd2 (lvdd) vdd gnd si so sck clkout reset vpp reserve/hs v dd (2.7 to 5.5 v) gnd flash programmer interface (b) pd78f9136a, 78f9136b 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9136a pd78f9136b vdd2 (lvdd) vdd gnd si so sck clkout reset vpp reserve/hs v dd (2.7 to 5.5 v) gnd flash programmer interface
chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b user?s manual u14643ej3v0ud 246 figure 18-11. example of flash memory writing ad apter connection when using pseudo 3-wire mode (a) pd78f9116a 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9116a vdd2 (lvdd) vdd gnd si so sck clkout reset vpp reserve/hs v dd (2.7 to 5.5 v) gnd flash programmer interface (b) pd78f9136a 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 pd78f9136a vdd2 (lvdd) vdd gnd si so sck clkout reset vpp reserve/hs v dd (2.7 to 5.5 v) gnd flash programmer interface
user?s manual u14643ej3v0ud 247 chapter 19 mask option (mask rom version) table 19-1. selection of mask option for pins pin mask option p50 to p53 on-chip pull-up resistor can be specified in 1-bit units. for p50 to p53 (port 5), an on-chip pull-up resistor can be specified by the mask opt ion. the mask option is specified in 1-bit units. caution the flash memory versions do not provid e the on-chip pull-up resistor function.
user?s manual u14643ej3v0ud 248 chapter 20 instruction set this chapter lists the instruction set of the pd789104a/114a/124a/134a subseries. for details of the operation and machine language (instruction code) of each instruction, refer to the 78k/0s series instructions user?s manual (u11047e) . 20.1 operation 20.1.1 operand identifier s and description methods operands are described in the ?operand? column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more description methods, select one of them. uppercase lette rs and the symbols #, !, $, and [ ] are keywords and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate nume ric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for the operand register identifiers, r and rp, either func tion names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 20-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark refer to table 4-3 special-function register list for the symbols of the special-function registers.
chapter 20 instruction set user?s manual u14643ej3v0ud 249 20.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by addre ss or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) ? : exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 20.1.3 description of ?flag operation? column (blank): unchanged 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
chapter 20 instruction set user?s manual u14643ej3v0ud 250 20.2 operation list flag mnemonic operands bytes clocks operation z ac cy r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte a, psw 2 4 a psw psw, a 2 4 psw a a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl+byte] 2 6 a (hl+byte) mov [hl+byte], a 2 6 (hl+byte) a a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl+byte] 2 8 a ? (hl+byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 20 instruction set user?s manual u14643ej3v0ud 251 flag mnemonic operands bytes clocks operation z ac cy rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp movw rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 (saddr), cy (saddr) + byte a, r 2 4 a, cy a + r a, saddr 2 4 a, cy a + (saddr) a, !addr16 3 8 a, cy a + (addr16) a, [hl] 1 6 a, cy a + (hl) add a, [hl+byte] 2 6 a, cy a + (hl+byte) a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy a, r 2 4 a, cy a + r + cy a, saddr 2 4 a, cy a + (saddr) + cy a, !addr16 3 8 a, cy a + (addr16) + cy a, [hl] 1 6 a, cy a + (hl) + cy addc a, [hl+byte] 2 6 a, cy a + (hl+byte) + cy a, #byte 2 4 a, cy a ? byte saddr, #byte 3 6 (saddr), cy (saddr) ? byte a, r 2 4 a, cy a ? r a, saddr 2 4 a, cy a ? (saddr) a, !addr16 3 8 a, cy a ? (addr16) a, [hl] 1 6 a, cy a ? (hl) sub a, [hl+byte] 2 6 a, cy a ? (hl+byte) note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 20 instruction set user?s manual u14643ej3v0ud 252 flag mnemonic operands bytes clocks operation z ac cy a, #byte 2 4 a, cy a ? byte ? cy saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy a, r 2 4 a, cy a ? r ? cy a, saddr 2 4 a, cy a ? (saddr) ? cy a, !addr16 3 8 a, cy a ? (addr16) ? cy a, [hl] 1 6 a, cy a ? (hl) ? cy subc a, [hl+byte] 2 6 a, cy a ? (hl+byte) ? cy a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) and a, [hl+byte] 2 6 a a (hl+byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) or a, [hl+byte] 2 6 a a (hl+byte) a, #byte 2 4 a a ? byte saddr, #byte 3 6 (saddr) (saddr) ? byte a, r 2 4 a a ? r a, saddr 2 4 a a ? (saddr) a, !addr16 3 8 a a ? (addr16) a, [hl] 1 6 a a ? (hl) xor a, [hl+byte] 2 6 a a ? (hl+byte) remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 20 instruction set user?s manual u14643ej3v0ud 253 flag mnemonic operands bytes clocks operation z ac cy a, #byte 2 4 a ? byte saddr, #byte 3 6 (saddr) ? byte a, r 2 4 a ? r a, saddr 2 4 a ? (saddr) a, !addr16 3 8 a ? (addr16) a, [hl] 1 6 a ? (hl) cmp a, [hl+byte] 2 6 a ? (hl+byte) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ? word cmpw ax, #word 3 6 ax ? word r 2 4 r r + 1 inc saddr 2 4 (saddr) (saddr) + 1 r 2 4 r r ? 1 dec saddr 2 4 (saddr) (saddr) ? 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 set1 [hl].bit 2 10 (hl).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 clr1 [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 20 instruction set user?s manual u14643ej3v0ud 254 flag mnemonic operands bytes clocks operation z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 r r r psw 1 2 (sp ? 1) psw, sp sp ? 1 push rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 4 psw (sp), sp sp + 1 r r r pop rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 sp, ax 2 8 sp ax movw ax, sp 2 6 ax sp !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 br ax 1 6 pc h a, pc l x bc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 dbnz saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 20 instruction set user?s manual u14643ej3v0ud 255 20.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !addr16 psw [de] [hl] [hl+byte] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl+byte] mov note except r = a.
chapter 20 instruction set user?s manual u14643ej3v0ud 256 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 20 instruction set user?s manual u14643ej3v0ud 257 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
user?s manual u14643ej3v0ud 258 chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (expanded-specificat ion products) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd , av dd v dd = av dd ?0.3 to +6.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v with n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 with an on-chip pull-up resistor ?0.3 to v dd + 0.3 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?10 ma total for all pins pd78910xa, 78911xa ?30 ma per pin ?7 ma output current, high i oh total for all pins pd78910xa(a), 78911xa(a) ?22 ma per pin 30 ma total for all pins pd78910xa, 78911xa 160 ma per pin 10 ma output current, low i ol total for all pins pd78910xa(a), 78911xa(a) 120 ma operating ambient temperature t a ?40 to +85 c storage temperature t stg ?65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (e xpanded-specification products) user?s manual u14643ej3v0ud 259 system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 10 mhz ceramic resonator x2 x1 ic0 c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency (f x ) note 1 1.0 10 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 ic0 c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 10 mhz v dd = 4.5 to 5.5 v 45 500 ns v dd = 3.0 to 5.5 v 75 500 ns x1 x2 x1 input high-/low-level width (t xh , t xl ) v dd = 1.8 to 5.5 v 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after a reset or stop mode release. use a resonator that stabilizes oscillation during the oscillation wait time. caution when using the system clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator.
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (exp anded-specification products) user?s manual u14643ej3v0ud 260 recommended oscillator constant ceramic resonator (t a = ? 40 to +85 c) ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a )) (expanded-specification products) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remark csbla1m00j58-b0 note csbfb1m00j58-r1 note 1.0 100 100 2.1 rd = 2.2 k ? cstcc2m00g56-r0 cstls2m00g56-b0 2.0 cstcr4m00g53-r0 cstls4m00gg53-b0 4.0 cstcr4m19g53-r0 cstls4m19gg53-b0 4.194 cstcr4m91g53-r0 cstls4m91gg53-b0 4.915 cstcr5m00g53-r0 cstls5m00gg53-b0 5.0 cstcr6m00g53-r0 cstls6m00gg53-b0 6.0 cstce8m00g52-r0 cstls8m00g53-b0 8.0 cstce8m38g52-r0 cstls8m38g53-b0 8.388 cstce10m0g52-r0 murata mfg. co., ltd. cstls10m00g53-b0 10.0 ? ? 1.8 5.5 on-chip capacitor version note a limiting resistor (rd = 2.2 k ? ) is required when the csbla1m00j58-b0 and csbfb1m00j58-r1 (1.0 mhz) of murata mfg. co., ltd. are used as ceramic reso nators (see the figure below). a limiting resistor is not necessary when other reco mmended resonators are used. x2 x1 c2 c1 csbla1m00j58-b0 csbfb1m00j58-r1 rd caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator ma nufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only oscilla tor characteristics. use the pd78910xa, 78911xa, 78 910xa(a), and 78911xa(a) so that th e internal operating conditions are within the specifications of the dc and ac characteristics.
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (e xpanded-specification products) user?s manual u14643ej3v0ud 261 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma total for all pins pd78910xa, 78911xa ?15 ma per pin ?1 ma output current, high i oh total for all pins pd78910xa(a), 78911xa(a) ?11 ma per pin 10 ma total for all pins pd78910xa, 78911xa 80 ma per pin 3 ma output current, low i ol total for all pins pd78910xa(a), 78911xa(a) 60 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 pins other than described below v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v with n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 with on-chip pull-up resistor v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 pins other than described below v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2 v dd = 1.8 to 5.5 v 0 0.1 v v oh1 v dd = 4.5 to 5.5 v, i oh = ?1 ma v dd ? 1.0 v output voltage, high v oh2 v dd = 1.8 to 5.5 v, i oh = ?100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78910xa, 78911xa) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78910xa(a), 78911xa(a)) 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78910xa, 78911xa) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78910xa(a), 78911xa(a)) 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (exp anded-specification products) user?s manual u14643ej3v0ud 262 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 pins other than x1, x2, or p50 to p53 3 a i lih2 x1, x2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 12 v 20 a i lil1 pins other than x1, x2, or p50 to p53 ?3 a i lil2 x1, x2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?3 note 1 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 or p60 to p63 50 100 200 k ? mask option pull-up resistance r 2 v i = 0 v, p50 to p53 10 30 60 k ? 10.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 4 3.2 8.0 ma 6.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 4 2.0 4.7 ma v dd = 5.0 v 10% note 4 1.8 3.2 ma v dd = 3.0 v 10% note 5 0.45 0.9 ma i dd1 note 2 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.25 0.45 ma 10.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 4 1.5 3.0 ma 6.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 4 0.9 1.8 ma v dd = 5.0 v 10% note 4 0.8 1.6 ma v dd = 3.0 v 10% note 5 0.3 0.6 ma i dd2 note 2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.15 0.3 ma v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a i dd3 note 2 stop mode v dd = 2.0 v 10% 0.05 5.0 a 10.0 mhz crystal oscillation a/d operating mode v dd = 5.0 v 10% note 4 4.4 10.3 ma 6.0 mhz crystal oscillation a/d operating mode v dd = 5.0 v 10% note 4 3.2 7.0 ma v dd = 5.0 v 10% note 4 3.0 5.5 ma v dd = 3.0 v 10% note 5 1.65 3.2 ma power supply current i dd4 note 3 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.25 2.7 ma
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (e xpanded-specification products) user?s manual u14643ej3v0ud 263 notes 1. when pull-up resistors are not connected to p50 to p53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 3. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (exp anded-specification products) user?s manual u14643ej3v0ud 264 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 4.5 to 5.5 v 0.2 8 s v dd = 3.0 to 5.5 v 0.33 8 s v dd = 2.7 to 5.5 v 0.4 8 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 8 s v dd = 2.7 to 5.5 v 0.1 s ti80 input high-/low- level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] cycle time t cy [ s] 12 4 356 0.1 0.4 1.0 10 60 guaranteed operation range
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (e xpanded-specification products) user?s manual u14643ej3v0ud 265 (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (to ss20 when ss20 is used) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (for ss20 when ss20 is used) t kds2 v dd = 1.8 to 5.5 v 800 ns v dd = 2.7 to 5.5 v 100 ns ss20 setup time (to sck20 first edge) t ssk2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns ss20 hold time (from sck20 last edge) t kss2 v dd = 1.8 to 5.5 v 600 ns note r and c are the load resistance and lo ad capacitance of t he so output line.
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (exp anded-specification products) user?s manual u14643ej3v0ud 266 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (e xpanded-specification products) user?s manual u14643ej3v0ud 267 ac timing measurement points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (exp anded-specification products) user?s manual u14643ej3v0ud 268 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (e xpanded-specification products) user?s manual u14643ej3v0ud 269 8-bit a/d converter characteristics ( pd78910xa, 78910xa(a)) (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bits v dd = 2.7 to 5.5 v 0.4 0.6 %fsr overall error notes 1, 2 v dd = 1.8 to 5.5 v 0.8 1.2 %fsr v dd = 4.5 to 5.5 v 12 100 s v dd = 2.7 to 5.5 v 14 100 s conversion time t conv v dd = 1.8 to 5.5 v 28 100 s analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.2%). 2. this value is indicated as a ratio to the full-scale value (%fsr). 10-bit a/d converter characteristics ( pd78911xa, 78911xa(a)) (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits 4.5 v v dd 5.5 v 0.2 0.4 %fsr 2.7 v v dd < 4.5 v 0.4 0.6 %fsr overall error notes 1, 2 1.8 v v dd < 2.7 v 0.8 1.2 %fsr 4.5 v v dd 5.5 v 12 100 s 2.7 v v dd < 4.5 v 14 100 s conversion time t conv 1.8 v v dd < 2.7 v 28 100 s 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr zero-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr full-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 2.5 lsb 2.7 v v dd < 4.5 v 4.5 lsb integral linearity error note 1 ile 1.8 v v dd < 2.7 v 8.5 lsb 4.5 v v dd 5.5 v 1.5 lsb 2.7 v v dd < 4.5 v 2.0 lsb differential linearity error note 1 dle 1.8 v v dd < 2.7 v 3.5 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 21 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (exp anded-specification products) user?s manual u14643ej3v0ud 270 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization wait time is the period during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible using bits 0 to 2 (ost s0 to osts2) of the oscillation stabilization time select register (osts). remark f x : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 271 chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd , av dd v dd = av dd ?0.3 to +6.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v with n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 with an on-chip pull-up resistor ?0.3 to v dd + 0.3 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?10 ma total for all pins pd78910xa, 78911xa ?30 ma per pin ?7 ma output current, high i oh total for all pins pd78910xa(a), 78911xa(a) ?22 ma per pin 30 ma total for all pins pd78910xa, 78911xa 160 ma per pin 10 ma output current, low i ol total for all pins pd78910xa(a), 78911xa(a) 120 ma operating ambient temperature t a ?40 to +85 c storage temperature t stg ?65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 272 system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator x2 x1 ic0 c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency (f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 ic0 c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 x2 x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after a reset or stop mode release. use a resonator that stabilizes oscillation during the oscillation wait time. caution when using the system clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator.
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 273 recommended oscillator constant ceramic resonator (t a = ? 40 to +85 c) ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remark csbla1m00j58-b0 note csbfb1m00j58-r1 note 1.0 100 100 2.1 rd = 2.2 k ? cstcc2m00g56-r0 cstls2m00g56-b0 2.0 cstcr4m00g53-r0 cstls4m00gg53-b0 4.0 cstcr4m19g53-r0 cstls4m19gg53-b0 4.194 cstcr4m91g53-r0 cstls4m91gg53-b0 4.915 cstcr5m00g53-r0 murata mfg. co., ltd. cstls5m00gg53-b0 5.0 ? ? 1.8 5.5 on-chip capacitor version note a limiting resistor (rd = 2.2 k ? ) is required when the csbla1m00j58-b0 and csbfb1m00j58-r1 (1.0 mhz) of murata mfg. co., ltd. are used as ceramic reso nators (see the figure below). a limiting resistor is not necessary when other reco mmended resonators are used. x2 x1 c2 c1 csbla1m00j58-b0 csbfb1m00j58-r1 rd caution this oscillator constant is a reference value based on evalua tion under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator ma nufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only oscilla tor characteristics. use the pd78910xa, 78911xa, 78 910xa(a), and 78911xa(a) so that th e internal operating conditions are within the specifications of the dc and ac characteristics.
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 274 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma total for all pins pd78910xa, 78911xa ?15 ma per pin ?1 ma output current, high i oh total for all pins pd78910xa(a), 78911xa(a) ?11 ma per pin 10 ma total for all pins pd78910xa, 78911xa 80 ma per pin 3 ma output current, low i ol total for all pins pd78910xa(a), 78911xa(a) 60 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 pins other than described below v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v with n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 with on-chip pull-up resistor v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 pins other than described below v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2 v dd = 1.8 to 5.5 v 0 0.1 v v oh1 v dd = 4.5 to 5.5 v, i oh = ?1 ma v dd ? 1.0 v output voltage, high v oh2 v dd = 1.8 to 5.5 v, i oh = ?100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78910xa, 78911xa) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78910xa(a), 78911xa(a)) 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78910xa, 78911xa) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78910xa(a), 78911xa(a)) 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 275 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 pins other than x1, x2, or p50 to p53 3 a i lih2 x1, x2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 12 v 20 a i lil1 pins other than x1, x2, or p50 to p53 ?3 a i lil2 x1, x2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?3 note 1 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 or p60 to p63 50 100 200 k ? mask option pull-up resistance r 2 v i = 0 v, p50 to p53 10 30 60 k ? v dd = 5.0 v 10% note 4 1.8 3.2 ma v dd = 3.0 v 10% note 5 0.45 0.9 ma i dd1 note 2 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.25 0.45 ma v dd = 5.0 v 10% note 4 0.8 1.6 ma v dd = 3.0 v 10% note 5 0.3 0.6 ma i dd2 note 2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.15 0.3 ma v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a i dd3 note 2 stop mode v dd = 2.0 v 10% 0.05 5.0 a v dd = 5.0 v 10% note 4 3.0 5.5 ma v dd = 3.0 v 10% note 5 1.65 3.2 ma power supply current i dd4 note 3 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.25 2.7 ma notes 1. when pull-up resistors are not connected to p50 to p53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 3. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 276 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 8 s v dd = 2.7 to 5.5 v 0.1 s ti80 input high-/low- level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 277 (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (for ss20 when ss20 is used) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (for ss20 when ss20 is used) t kds2 v dd = 1.8 to 5.5 v 800 ns v dd = 2.7 to 5.5 v 100 ns ss20 setup time (to sck20 first edge) t ssk2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns ss20 hold time (from sck20 last edge) t kss2 v dd = 1.8 to 5.5 v 600 ns note r and c are the load resistance and lo ad capacitance of t he so output line.
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 278 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 279 ac timing measurement points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 280 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 281 8-bit a/d converter characteristics ( pd78910xa, 78910xa(a)) (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bits v dd = 2.7 to 5.5 v 0.4 0.6 %fsr overall error notes 1, 2 v dd = 1.8 to 5.5 v 0.8 1.2 %fsr v dd = 2.7 to 5.5 v 14 100 s conversion time t conv v dd = 1.8 to 5.5 v 28 100 s analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.2%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr). 10-bit a/d converter characteristics ( pd78911xa, 78911xa(a)) (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits 4.5 v v dd 5.5 v 0.2 0.4 %fsr 2.7 v v dd < 4.5 v 0.4 0.6 %fsr overall error notes 1, 2 1.8 v v dd < 2.7 v 0.8 1.2 %fsr 2.7 v v dd 5.5 v 14 100 s conversion time t conv 1.8 v v dd < 2.7 v 28 100 s 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr zero-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr full-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 2.5 lsb 2.7 v v dd < 4.5 v 4.5 lsb integral linearity error note 1 ile 1.8 v v dd < 2.7 v 8.5 lsb 4.5 v v dd 5.5 v 1.5 lsb 2.7 v v dd < 4.5 v 2.0 lsb differential linearity error note 1 dle 1.8 v v dd < 2.7 v 3.5 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 22 electrical specifications ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) (conventional-specification products) user?s manual u14643ej3v0ud 282 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization wait time is the period during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible using bits 0 to 2 (ost s0 to osts2) of the oscillation stabilization time select register (osts). remark f x : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 283 chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd , av dd v dd = av dd ?0.3 to +6.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v with n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 with an on-chip pull-up resistor ?0.3 to v dd + 0.3 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?4 ma total for all pins pd78910xa(a1), 78911xa(a1) ?14 ma per pin ?2 ma output current, high i oh total for all pins pd78910xa(a2), 78911xa(a2) ?6 ma per pin 5 ma total for all pins pd78910xa(a1), 78911xa(a1) 80 ma per pin 2 ma output current, low i ol total for all pins pd78910xa(a2), 78911xa(a2) 40 ma pd78910xa(a1), 78911xa(a1) ?40 to +110 c operating ambient temperature t a pd78910xa(a2), 78911xa(a2) ?40 to +125 c storage temperature t stg ?65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 284 system clock oscillator characteristics (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78910xa(a1), 78911xa(a1)), ?40 to +125 c ( pd78910xa(a2), 78911xa(a2)) ) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator x2 x1 ic0 c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after a reset or stop mode release. use a resonator that stabilizes oscillation during the oscillation wait time. cautions 1. when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. use a ceramic resonator th at is guaranteed by the resona tor manufacturer to operate under the following conditions. pd78910xa(a1), 78911xa(a1): t a = 110 c pd78910xa(a2), 78911xa(a2): t a = 125 c remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 285 dc characteristics (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78910xa(a1), 78911xa(a1)), ?40 to +125 c ( pd78910xa(a2), 78911xa(a2)) ) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma total for all pins pd78910xa(a1), 78911xa(a1) ?7 ma per pin ?1 ma output current, high i oh total for all pins pd78910xa(a2), 78911xa(a2) ?3 ma per pin 1.6 ma total for all pins pd78910xa(a1), 78911xa(a1) 40 ma per pin 1.6 ma output current, low i ol total for all pins pd78910xa(a2), 78911xa(a2) 20 ma v ih1 pins other than described below 0.7v dd v dd v with n-ch open drain 0.7v dd 10 v v ih2 p50 to p53 with on-chip pull-up resistor 0.7v dd v dd v v ih3 reset, p20 to p25 0.8v dd v dd v input voltage, high v ih4 x1, x2 v dd ? 0.1 v dd v v il1 pins other than described below 0 0.3v dd v v il2 p50 to p53 0 0.3v dd v v il3 reset, p20 to p25 0 0.2v dd v input voltage, low v il4 x1, x2 0 0.1 v v oh1 i oh = ?1 ma v dd ? 2.0 v output voltage, high v oh2 i oh = ?100 a v dd ? 1.0 v i ol = 1.6 ma 2.0 v v ol1 pins other than p50 to p53 i ol = 400 a 1.0 v output voltage, low v ol2 p50 to p53 i ol = 1.6 ma 1.0 v i lih1 pins other than x1, x2, or p50 to p53 10 a i lih2 x1, x2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 10 v 80 a i lil1 pins other than x1, x2, or p50 to p53 ?10 a i lil2 x1, x2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?10 note a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ?10 a note when pull-up resistors are not connected to p50 to p 53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 286 dc characteristics (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78910xa(a1), 78911xa(a1)), ?40 to +125 c ( pd78910xa(a2), 78911xa(a2)) ) (2/2) parameter symbol conditions min. typ. max. unit software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 or p60 to p63 50 100 300 k ? mask option pull-up resistance r 2 v i = 0 v, p50 to p53 10 30 100 k ? i dd1 note 1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) note 3 1.8 8.0 ma i dd2 note 1 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) note 3 0.8 5.0 ma i dd3 note 1 stop mode 0.1 1000 a power supply current i dd4 note 2 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) note 3 3.0 10 ma notes 1. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 2. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 3. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 287 ac characteristics (1) basic operation (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78910xa(a1), 78911xa(a1)), ?40 to +125 c ( pd78910xa(a2), 78911xa(a2)) ) parameter symbol conditions min. typ. max. unit cycle time (minimum instruction execution time) t cy 0.4 8 s ti80 input high-/low- level width t tih , t til 0.1 s ti80 input frequency f ti 0 4 mhz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 288 (2) serial interface (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78910xa(a1), 78911xa(a1)), ?40 to +125 c ( pd78910xa(a2), 78911xa(a2)) ) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy1 800 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 ? 50 ns si20 setup time (to sck20 ) t sik1 150 ns si20 hold time (from sck20 ) t ksi1 400 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note 0 250 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy2 800 ns sck20 high-/low- level width t kh2 , t kl2 400 ns si20 setup time (to sck20 ) t sik2 100 ns si20 hold time (from sck20 ) t ksi2 400 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note 0 300 ns so20 setup time (to ss20 when ss20 is used) t kas2 120 ns so20 disable time (for ss20 when ss20 is used) t kds2 240 ns ss20 setup time (to sck20 first edge) t ssk2 100 ns ss20 hold time (from sck20 last edge) t kss2 400 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 78125 bps
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 289 (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck20 cycle time t kcy3 800 ns asck20 high-/low- level width t kh3 , t kl3 400 ns transfer rate 39063 bps asck20 rise/fall time t r , t f 1 s
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 290 ac timing measurement points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 291 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 292 8-bit a/d converter characteristics ( pd78910xa(a1), 78910xa(a2) only) (av dd = v dd = 4.5 to 5.5 v, av ss = v ss = 0 v, t a = ?40 to +110 c ( pd78910xa(a1)), ?40 to +125 c ( pd78910xa(a2)) ) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bits overall error notes 1, 2 0.4 1.0 %fsr conversion time t conv 14 28 s analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.2%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr). 10-bit a/d converter characteristics ( pd78911xa(a1), 78911xa(a2) only) (av dd = v dd = 4.5 to 5.5 v, av ss = v ss = 0 v, t a = ?40 to +110 c ( pd78911xa(a1)), ?40 to +125 c ( pd78911xa(a2)) ) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits overall error notes 1, 2 0.4 0.6 %fsr conversion time t conv 14 28 s zero-scale error notes 1, 2 0.6 %fsr full-scale error notes 1, 2 0.6 %fsr integral linearity error note 1 ile 4.5 lsb differential linearity error note 1 dle 2.0 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 23 electrical specifications ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 293 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +110 c ( pd78910xa(a1), 78911xa(a1)), ?40 to +125 c ( pd78910xa(a2), 78911xa(a2)) ) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization wait time is the period during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible using bits 0 to 2 (ost s0 to osts2) of the oscillation stabilization time select register (osts). remark f x : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 294 chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd , av dd v dd = av dd ?0.3 to +6.5 v supply voltage v pp note ?0.3 to +10.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v input voltage v i2 p50 to p53 with n-ch open drain ?0.3 to +13 v output voltage v o ?0.3 to v dd + 0.3 v per pin pd78f9116b ?10 ma total for all pins ?30 ma per pin pd78f9116b(a) ?7 ma output current, high i oh total for all pins ?22 ma per pin pd78f9116b 30 ma total for all pins 160 ma per pin pd78f9116b(a) 10 ma output current, low i ol total for all pins 120 ma in normal operation mode ?40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg ?40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 295 system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz v dd = 1.8 to 5.5 v 1.0 5.0 mhz ceramic resonator x2 x1 v pp c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency (f x ) note 1 v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz v dd = 1.8 to 5.5 v 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 v pp c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 x1 input frequency (f x ) note 1 v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz v dd = 1.8 to 5.5 v 1.0 5.0 mhz v dd = 4.5 to 5.5 v 45 500 ns x1 x2 v dd = 3.0 to 5.5 v 75 500 ns x1 input high-/low-level width (t xh , t xl ) v dd = 1.8 to 5.5 v 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after a reset or stop mode release. use a resonator that stabilizes oscillation during the oscillation wait time. caution when using the system clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator.
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 296 recommended oscillator constant ceramic resonator (t a = ? 40 to +85 c) ( pd78f9116b, 78f9116b(a)) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remark csbla1m00j58-b0 note 1.0 100 100 rd = 2.2 k ? cstcc2m00g56-r0 2.0 cstcr4m00g53-r0 cstls4m00g53-b0 4.0 2.0 cstcr5m00g53-r0 cstls5m00g53-b0 5.0 cstcr6m00g53-r0 2.1 cstls6m00g53-b0 6.0 2.2 cstce8m38g52-r0 2.0 cstls8m38g53-b0 8.388 2.2 cstce10m0g52-r0 2.1 murata mfg. co., ltd. (standard products) cstls10m0g53-b0 10.0 ? ? 2.4 5.5 on-chip capacitor version cstcr4m00g53u-r0 cstls4m00g53093-b0 4.0 cstcr5m00g53u-r0 cstls5m00g53u-b0 5.0 1.8 cstcr6m00g53093-r0 cstls6m00g53u-b0 6.0 1.9 cstls8m38g53193-b0 8.0 murata mfg. co., ltd. (low-voltage drive type) cstls10m0g53u-b0 10.0 ? ? 2.0 5.5 on-chip capacitor version note a limiting resistor (rd = 2.2 k ? ) is required when the csbla1m00j58-b0 (1.0 mhz) of murata mfg. co., ltd. is used as the ceramic resonator (see the figure below). a limiting resistor is not necessary when other recommended resonators are used. x2 x1 c2 c1 csbla1m00j58-b0 rd caution this oscillator constant is a reference value based on eval uation under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator ma nufacturer for evaluation on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteristics. use the pd78f9116b and 78f9116b(a) so th at the internal operating conditions are within the specifications of the dc and ac characteristics.
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 297 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin pd78f9116b ?1 ma output current, high i oh total for all pins ?15 ma per pin pd78f9116b(a) ?1 ma total for all pins ?11 ma per pin pd78f9116b 10 ma total for all pins 80 ma per pin pd78f9116b(a) 3 ma output current, low i ol total for all pins 60 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 pins other than described below v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v v ih2 p50 to p53 n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 pins other than described below v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 n-ch open drain v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2 v dd = 1.8 to 5.5 v 0 0.1 v v oh1 v dd = 4.5 to 5.5 v, i oh = ?1 ma v dd ? 1.0 v output voltage, high v oh2 v dd = 1.8 to 5.5 v, i oh = ?100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78f9116b) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78f9116b(a)) 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78f9116b) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78f9116b(a)) 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 298 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 pins other than x1, x2, or p50 to p53 v i = v dd 3 a i lih2 x1, x2 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 12 v 20 a i lil1 pins other than x1, x2, or p50 to p53 v i = 0 v ?3 a i lil2 x1, x2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) ?3 note 1 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 or p60 to p63 50 100 200 k ? 10.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 4 10.0 20.0 ma 6.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 4 6.0 12.0 ma v dd = 5.0 v 10% note 4 4.0 10.0 ma v dd = 3.0 v 10% note 5 1.0 2.5 ma i dd1 note 2 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.8 2.0 ma 10.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 4 1.2 6.0 ma 6.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 4 0.9 2.8 ma v dd = 5.0 v 10% note 4 0.6 2.5 ma v dd = 3.0 v 10% note 5 0.3 2.0 ma i dd2 note 2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.2 1.5 ma v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a i dd3 note 2 stop mode v dd = 2.0 v 10% 0.05 10 a 10.0 mhz crystal oscillation a/d operating mode v dd = 5.0 v 10% note 4 11.0 22.5 ma 6.0 mhz crystal oscillation a/d operating mode v dd = 5.0 v 10% note 4 7.0 14.5 ma v dd = 5.0 v 10% note 4 5.0 12.5 ma v dd = 3.0 v 10% note 5 2.0 5.0 ma power supply current i dd4 note 3 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.8 4.5 ma notes 1. when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 3. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 299 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit operating frequency v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz v dd = 2.7 to 5.5 v 1.0 5.0 mhz f x v dd = 1.8 to 5.5 v 1.0 1.25 mhz write current (v dd pin) note i ddw when v pp supply voltage = v pp1 (@ 5.0 mhz operation) 21 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 22.5 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 (@ 5.0 mhz operation) 21 ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 115 ma unit erase time t er 0.2 0.2 0.2 s total erase time t era 20 s rewrite count erase/write are regarded as 1 cycle 20 20 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the curr ent flowing through on-chip pull-up resistors) and av dd current are not included.
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 300 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 4.5 to 5.5 v 0.2 8 s v dd = 3.0 to 5.5 v 0.33 8 s v dd = 2.7 to 5.5 v 0.4 8 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 8 s v dd = 2.7 to 5.5 v 0.1 s ti80 input high-/low- level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] cycle time t cy [ s] 12 4 356 0.1 0.4 1.0 10 60 guaranteed operation range
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 301 (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (for ss20 when ss20 is used) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (for ss20 when ss20 is used) t kds2 v dd = 1.8 to 5.5 v 800 ns v dd = 2.7 to 5.5 v 100 ns ss20 setup time (to sck20 first edge) t ssk2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns ss20 hold time (from sck20 last edge) t kss2 v dd = 1.8 to 5.5 v 600 ns note r and c are the load resistance and lo ad capacitance of t he so output line.
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 302 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 303 ac timing measurement points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 304 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 305 10-bit a/d converter characteristics (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits 4.5 v v dd 5.5 v 0.2 0.4 %fsr 2.7 v v dd < 4.5 v 0.4 0.6 %fsr overall error notes 1, 2 1.8 v v dd < 2.7 v 0.8 1.2 %fsr 4.5 v v dd 5.5 v 12 100 s 2.7 v v dd < 4.5 v 14 100 s conversion time t conv 1.8 v v dd < 2.7 v 28 100 s 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr zero-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr full-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 2.5 lsb 2.7 v v dd < 4.5 v 4.5 lsb integral linearity error note 1 ile 1.8 v v dd < 2.7 v 8.5 lsb 4.5 v v dd 5.5 v 1.5 lsb 2.7 v v dd < 4.5 v 2.0 lsb differential linearity error note 1 dle 1.8 v v dd < 2.7 v 3.5 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 24 electrical specifications ( pd78f9116b, 78f9116b(a)) user?s manual u14643ej3v0ud 306 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization wait time is the period during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible using bits 0 to 2 (ost s0 to osts2) of the oscillation stabilization time select register (osts). remark f x : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 307 chapter 25 electrical specifications ( pd78f9116b(a1)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd , av dd v dd = av dd ?0.3 to +6.5 v supply voltage v pp note ?0.3 to +10.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v input voltage v i2 p50 to p53 with n-ch open drain ?0.3 to +13 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?4 ma output current, high i oh total for all pins ?14 ma per pin 5 ma output current, low i ol total for all pins 80 ma in normal operation mode ?40 to +105 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg ?40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (4.5 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (4.5 v) of the operating voltage range of v dd (see b in the figure below). 4.5 v v dd 0 v 0 v v pp 4.5 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 308 system clock oscillator characteristics (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator x2 x1 v pp c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after a reset or stop mode release. use a resonator that stabilizes oscillation during the oscillation wait time. cautions 1. when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. use a ceramic resonator that is guaranteed by the resonator manufacturer to operate at t a = 105 c. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 309 dc characteristics (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma output current, high i oh total for all pins ?7 ma per pin 1.6 ma output current, low i ol total for all pins 40 ma v ih1 pins other than described below 0.7v dd v dd v v ih2 p50 to p53 with n-ch open drain 0.7v dd 10 v v ih3 reset, p20 to p25 0.8v dd v dd v input voltage, high v ih4 x1, x2 v dd ? 0.1 v dd v v il1 pins other than described below 0 0.3v dd v v il2 p50 to p53 0 0.3v dd v v il3 reset, p20 to p25 0 0.2v dd v input voltage, low v il4 x1, x2 0 0.1 v v oh1 i oh = ?1 ma v dd ? 2.0 v output voltage, high v oh2 i oh = ?100 a v dd ? 1.0 v i ol = 1.6 ma 2.0 v v ol1 pins other than p50 to p53 i ol = 400 a 1.0 v output voltage, low v ol2 p50 to p53 i ol = 1.6 ma 1.0 v i lih1 pins other than x1, x2, or p50 to p53 10 a i lih2 x1, x2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 10 v 80 a i lil1 pins other than x1, x2, or p50 to p53 ?10 a i lil2 x1, x2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?10 note a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ?10 a note when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 310 dc characteristics (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 or p60 to p63 50 100 300 k ? i dd1 note 1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) note 3 7.5 20.0 ma i dd2 note 1 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) note 3 3.0 5.5 ma i dd3 note 1 stop mode 1 1000 a power supply current i dd4 note 2 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) note 3 8.7 22.3 ma notes 1. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 2. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 3. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins. flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp supply voltage = v pp1 (@ 5.0 mhz operation) 21 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 22.5 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 (@ 5.0 mhz operation) 21 ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 115 ma unit erase time t er 0.2 0.2 0.2 s total erase time t era 20 s rewrite count erase/write are regarded as 1 cycle 20 20 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the curr ent flowing through on-chip pull-up resistors) and av dd current are not included.
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 311 ac characteristics (1) basic operation (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time (minimum instruction execution time) t cy 0.4 8 s ti80 input high-/low- level width t tih , t til 0.1 s ti80 input frequency f ti 0 4 mhz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 312 (2) serial interface (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy1 800 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 ? 50 ns si20 setup time (to sck20 ) t sik1 150 ns si20 hold time (from sck20 ) t ksi1 400 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note 0 250 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy2 800 ns sck20 high-/low- level width t kh2 , t kl2 400 ns si20 setup time (to sck20 ) t sik2 100 ns si20 hold time (from sck20 ) t ksi2 400 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note 0 300 ns so20 setup time (to ss20 when ss20 is used) t kas2 120 ns so20 disable time (for ss20 when ss20 is used) t kds2 240 ns ss20 setup time (to sck20 first edge) t ssk2 100 ns ss20 hold time (from sck20 last edge) t kss2 400 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 78125 bps
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 313 (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck20 cycle time t kcy3 800 ns asck20 high-/low- level width t kh3 , t kl3 400 ns transfer rate 39063 bps asck20 rise/fall time t r , t f 1 s
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 314 ac timing measurement points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 315 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 316 10-bit a/d converter characteristics (t a = ?40 to +105 c, av dd = v dd = 4.5 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits overall error notes 1,2 0.4 0.6 %fsr conversion time t conv 14 28 s zero-scale error notes 1,2 0.6 %fsr full-scale error notes 1,2 0.6 %fsr integral linearity error note 1 ile 4.5 lsb differential linearity error note 1 dle 2.0 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 25 electrical specifications ( pd78f9116b(a1)) user?s manual u14643ej3v0ud 317 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +105 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization wait time is the period during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible with bits 0 to 2 (ost s0 to osts2) of the oscillation stabilization time select register (osts). remark f x : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 318 chapter 26 electrical specifications ( pd78f9116a) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd , av dd v dd = av dd ?0.3 to +6.5 v supply voltage v pp note ?0.3 to +10.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v input voltage v i2 p50 to p53 with n-ch open drain ?0.3 to +13 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?10 ma output current, high i oh total for all pins ?30 ma per pin 30 ma output current, low i ol total for all pins 160 ma in normal operation mode ?40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg ?40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 319 system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator x2 x1 v pp c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency (f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 v pp c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 x2 x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after a reset or stop mode release. use a resonator that stabilizes oscillation during the oscillation wait time. caution when using the system clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 320 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma output current, high i oh total for all pins ?15 ma per pin 10 ma output current, low i ol total for all pins 80 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 pins other than described below v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v v ih2 p50 to p53 n-ch open drain v dd = 1.8 to 5.5 v, t a = 25 to 85 c 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 pins other than described below v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 n-ch open drain v dd = 1.8 to 5.5 v, t a = 25 to 85 c 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2 v dd = 1.8 to 5.5 v 0 0.1 v v oh1 v dd = 4.5 to 5.5 v, i oh = ?1 ma v dd ? 1.0 v output voltage, high v oh2 v dd = 1.8 to 5.5 v, i oh = ?100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 321 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 pins other than x1, x2, or p50 to p53 3 a i lih2 x1, x2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 12 v 20 a i lil1 pins other than x1, x2, or p50 to p53 ?3 a i lil2 x1, x2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?3 note 1 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 or p60 to p63 50 100 200 k ? v dd = 5.0 v 10% note 4 5.0 15.0 ma v dd = 3.0 v 10% note 5 1.9 4.9 ma i dd1 note 2 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.5 3.0 ma v dd = 5.0 v 10% note 4 2.5 5.0 ma v dd = 3.0 v 10% note 5 1.0 2.0 ma i dd2 note 2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.75 1.5 ma v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a i dd3 note 2 stop mode v dd = 2.0 v 10% 0.05 10 a v dd = 5.0 v 10% note 4 6.2 17.3 ma v dd = 3.0 v 10% note 5 3.1 7.2 ma power supply current i dd4 note 3 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 2.5 5.0 ma notes 1. when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 3. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 322 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp supply voltage = v pp1 (@ 5.0 mhz operation) 18 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 22.5 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 (@ 5.0 mhz operation) 18 ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 115 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s rewrite count erase/write are regarded as 1 cycle 20 20 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the curr ent flowing through on-chip pull-up resistors) and av dd current are not included.
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 323 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 8 s v dd = 2.7 to 5.5 v 0.1 s ti80 input high-/low- level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 324 (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (to ss20 when ss20 is used) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (for ss20 when ss20 is used) t kds2 v dd = 1.8 to 5.5 v 800 ns v dd = 2.7 to 5.5 v 100 ns ss20 setup time (to sck20 first edge) t ssk2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns ss20 hold time (from sck20 last edge) t kss2 v dd = 1.8 to 5.5 v 600 ns note r and c are the load resistance and lo ad capacitance of t he so output line.
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 325 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 326 ac timing measurement points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 327 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 328 10-bit a/d converter characteristics (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits 4.5 v v dd 5.5 v 0.2 0.4 %fsr 2.7 v v dd < 4.5 v 0.4 0.6 %fsr overall error notes 1, 2 1.8 v v dd < 2.7 v 0.8 1.2 %fsr 2.7 v v dd 5.5 v 14 100 s conversion time t conv 1.8 v v dd < 2.7 v 28 100 s 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr zero-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr full-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 2.5 lsb 2.7 v v dd < 4.5 v 4.5 lsb integral linearity error note 1 ile 1.8 v v dd < 2.7 v 8.5 lsb 4.5 v v dd 5.5 v 1.5 lsb 2.7 v v dd < 4.5 v 2.0 lsb differential linearity error note 1 dle 1.8 v v dd < 2.7 v 3.5 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 26 electrical specifications ( pd78f9116a) user?s manual u14643ej3v0ud 329 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization wait time is the period during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible using bits 0 to 2 (ost s0 to osts2) of the oscillation stabilization time select register. remark f x : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 330 chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd , av dd v dd = av dd ?0.3 to +6.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v with n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 with an on-chip pull-up resistor ?0.3 to v dd + 0.3 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?10 ma total for all pins pd78912xa, 78913xa ?30 ma per pin ?7 ma output current, high i oh total for all pins pd78912xa(a), 78913xa(a) ?22 ma per pin 30 ma total for all pins pd78912xa, 78913xa 160 ma per pin 10 ma output current, low i ol total for all pins pd78912xa(a), 78913xa(a) 120 ma operating ambient temperature t a ?40 to +85 c storage temperature t stg ?65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 331 system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit rc oscillator cl2 cl1 oscillation frequency (f cc ) note 2.0 4.0 mhz cl1 input frequency (f cc ) note 1.0 5.0 mhz cl1 cl2 cl1 input high-/low-level width (t xh , t xl ) 85 500 ns cl1 input frequency (f cc ) note v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock cl1 cl2 open cl1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. caution when using the system clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. rc oscillator frequency characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit f cc1 v dd = 2.7 to 5.5 v 1.5 2.0 2.5 mhz f cc2 v dd = 1.8 to 3.6 v 0.5 2.0 2.5 mhz f cc3 r = 11.0 k ? , c = 22 pf target: 2 mhz v dd = 1.8 to 5.5 v 0.5 2.0 2.5 mhz f cc4 v dd = 2.7 to 5.5 v 2.5 3.0 3.5 mhz f cc5 v dd = 1.8 to 3.6 v 0.75 3.0 3.5 mhz f cc6 r = 6.8 k ? , c = 22 pf target: 3 mhz v dd = 1.8 to 5.5 v 0.75 3.0 3.5 mhz f cc7 v dd = 2.7 to 5.5 v 3.5 4.0 4.7 mhz f cc8 v dd = 1.8 to 3.6 v 1.0 4.0 4.7 mhz oscillator frequency f cc9 r = 4.7 k ? , c = 22 pf target: 4 mhz v dd = 1.8 to 5.5 v 1.0 4.0 4.7 mhz remark so that the typ. spec. is satisfied between 2.0 to 4.0 mhz, set one of the above nine patterns for r and c.
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 332 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma total for all pins pd78912xa, 78913xa ?15 ma per pin ?1 ma output current, high i oh total for all pins pd78912xa(a), 78913xa(a) ?11 ma per pin 10 ma total for all pins pd78912xa, 78913xa 80 ma per pin 3 ma output current, low i ol total for all pins pd78912xa(a), 78913xa(a) 60 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 pins other than described below v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v with n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 with on-chip pull-up resistor v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 cl1, cl2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 pins other than described below v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 cl1, cl2 v dd = 1.8 to 5.5 v 0 0.1 v v oh1 v dd = 4.5 to 5.5 v, i oh = ?1 ma v dd ? 1.0 v output voltage, high v oh2 v dd = 1.8 to 5.5 v, i oh = ?100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78912xa, 78913xa) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78912xa(a), 78913xa(a)) 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78912xa, 78913xa) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78912xa(a), 78913xa(a)) 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 333 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 pins other than cl1, cl2, or p50 to p53 3 a i lih2 cl1, cl2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 12 v 20 a i lil1 pins other than cl1, cl2, or p50 to p53 ?3 a i lil2 cl1, cl2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?3 note 1 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistor r 1 v i = 0 v, for pins other than p50 to p53 50 100 200 k ? mask option pull-up resistor r 2 v i = 0 v, p50 to p53 10 30 60 k ? v dd = 5.0 v 10% note 4 1.8 3.2 ma v dd = 3.0 v 10% note 5 0.45 0.9 ma i dd1 note 2 4.0 mhz rc oscillation operating mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 0.25 0.45 ma v dd = 5.0 v 10% note 4 0.8 1.6 ma v dd = 3.0 v 10% note 5 0.3 0.6 ma i dd2 note 2 4.0 mhz rc oscillation halt mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 0.15 0.3 ma v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a i dd3 note 2 stop mode v dd = 2.0 v 10% 0.05 5.0 a v dd = 5.0 v 10% note 4 3.0 5.5 ma v dd = 3.0 v 10% note 5 1.65 3.2 ma power supply current i dd4 note 3 4.0 mhz rc oscillation a/d operating mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 1.25 2.7 ma notes 1. when pull-up resistors are not connected to p50 to p53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 3. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 334 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 16 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 16 s v dd = 2.7 to 5.5 v 0.1 s ti80 input high-/low- level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 335 (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (to ss20 when ss20 is used) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (for ss20 when ss20 is used) t kds2 v dd = 1.8 to 5.5 v 800 ns v dd = 2.7 to 5.5 v 100 ns ss20 setup time (to sck20 first edge) t ssk2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns ss20 hold time (from sck20 last edge) t kss2 v dd = 1.8 to 5.5 v 600 ns note r and c are the load resistance and lo ad capacitance of t he so output line.
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 336 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 337 ac timing measurement points (excluding cl1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f cc t xl t xh cl1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 338 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 339 8-bit a/d converter characteristics ( pd78912xa, 78912xa(a)) (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bits v dd = 2.7 to 5.5 v 0.4 0.6 %fsr overall error notes 1, 2 v dd = 1.8 to 5.5 v 0.8 1.2 %fsr v dd = 2.7 to 5.5 v 14 100 s conversion time t conv v dd = 1.8 to 5.5 v 28 100 s analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.2%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr). 10-bit a/d converter characteristics ( pd78913xa, 78913xa(a)) (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits 4.5 v v dd 5.5 v 0.2 0.4 %fsr 2.7 v v dd < 4.5 v 0.4 0.6 %fsr overall error notes 1, 2 1.8 v v dd < 2.7 v 0.8 1.2 %fsr 2.7 v v dd 5.5 v 14 100 s conversion time t conv 1.8 v v dd < 2.7 v 28 100 s 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr zero-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr full-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 2.5 lsb 2.7 v v dd < 4.5 v 4.5 lsb integral linearity error note 1 ile 1.8 v v dd < 2.7 v 8.5 lsb 4.5 v v dd 5.5 v 1.5 lsb 2.7 v v dd < 4.5 v 2.0 lsb differential linearity error note 1 dle 1.8 v v dd < 2.7 v 3.5 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 27 electrical specifications ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a)) user?s manual u14643ej3v0ud 340 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 7 /f cc s oscillation stabilization wait time note t wait release by interrupt request 2 7 /f cc s note the oscillation stabilization wait time is the perio d during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. remark f cc : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 341 chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd , av dd v dd = av dd ?0.3 to +6.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v with n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 with an on-chip pull-up resistor ?0.3 to v dd + 0.3 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?4 ma total for all pins pd78912xa(a1), 78913xa(a1) ?14 ma per pin ?2 ma output current, high i oh total for all pins pd78912xa(a2), 78913xa(a2) ?6 ma per pin 5 ma total for all pins pd78912xa(a1), 78913xa(a1) 80 ma per pin 2 ma output current, low i ol total for all pins pd78912xa(a2), 78913xa(a2) 40 ma pd78912xa(a1), 78913xa(a1) ?40 to +110 c operating ambient temperature t a pd78912xa(a2), 78913xa(a2) ?40 to +125 c storage temperature t stg ?65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 342 system clock oscillator characteristics (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78912xa(a1), 78913xa(a1)), ?40 to +125 c ( pd78912xa(a2), 78913xa(a2)) ) resonator recommended circuit parameter conditions min. typ. max. unit rc oscillator cl2 cl1 oscillation frequency (f cc ) note 2.0 4.0 mhz cl1 input frequency (f cc ) note 1.0 5.0 mhz external clock cl1 cl2 open cl1 input high-/low-level width (t xh , t xl ) 85 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. construct the oscillator with r and c devi ces that are guaranteed to operate under the following temperature conditions. pd78912xa(a1), 78913xa(a1): t a = 110 c pd78912xa(a2), 78913xa(a2): t a = 125 c
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 343 dc characteristics (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78912xa(a1), 78913xa(a1)), ?40 to +125 c ( pd78912xa(a2), 78913xa(a2)) ) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma total for all pins pd78912xa(a1), 78913xa(a1) ?7 ma per pin ?1 ma output current, high i oh total for all pins pd78912xa(a2), 78913xa(a2) ?3 ma per pin 1.6 ma total for all pins pd78912xa(a1), 78913xa(a1) 40 ma per pin 1.6 ma output current, low i ol total for all pins pd78912xa(a2), 78913xa(a2) 20 ma v ih1 pins other than described below 0.7v dd v dd v with n-ch open drain 0.7v dd 10 v v ih2 p50 to p53 with on-chip pull-up resistor 0.7v dd v dd v v ih3 reset, p20 to p25 0.8v dd v dd v input voltage, high v ih4 cl1, cl2 v dd ? 0.1 v dd v v il1 pins other than described below 0 0.3v dd v v il2 p50 to p53 0 0.3v dd v v il3 reset, p20 to p25 0 0.2v dd v input voltage, low v il4 cl1, cl2 0 0.1 v v oh1 i oh = ?1 ma v dd ? 2.0 v output voltage, high v oh2 i oh = ?100 a v dd ? 1.0 v i ol = 1.6 ma 2.0 v v ol1 pins other than p50 to p53 i ol = 400 a 1.0 v output voltage, low v ol2 p50 to p53 i ol = 1.6 ma 1.0 v i lih1 pins other than cl1, cl2, or p50 to p53 10 a i lih2 cl1, cl2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 10 v 80 a i lil1 pins other than cl1, cl2, or p50 to p53 ?10 a i lil2 cl1, cl2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?10 note a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ?10 a note when pull-up resistors are not connected to p50 to p 53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 344 dc characteristics (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78912xa(a1), 78913xa(a1)), ?40 to +125 c ( pd78912xa(a2), 78913xa(a2)) ) (2/2) parameter symbol conditions min. typ. max. unit software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 or p60 to p63 50 100 300 k ? mask option pull-up resistance r 2 v i = 0 v, p50 to p53 10 30 100 k ? i dd1 note 1 4.0 mhz crystal oscillation operating mode (r = 4.7 k ? , c = 22 pf) note 3 1.8 8.0 ma i dd2 note 1 4.0 mhz crystal oscillation halt mode (r = 4.7 k ? , c = 22 pf) note 3 0.8 5.0 ma i dd3 note 1 stop mode 0.1 1000 a power supply current i dd4 note 2 4.0 mhz crystal oscillation a/d operating mode (r = 4.7 k ? , c = 22 pf) note 3 3.0 10 ma notes 1. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 2. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 3. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 345 ac characteristics (1) basic operation (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78912xa(a1), 78913xa(a1)), ?40 to +125 c ( pd78912xa(a2), 78913xa(a2)) ) parameter symbol conditions min. typ. max. unit cycle time (minimum instruction execution time) t cy 0.4 8 s ti80 input high-/low- level width t tih , t til 0.1 s ti80 input frequency f ti 0 4 mhz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 346 (2) serial interface (v dd = 4.5 to 5.5 v, t a = ?40 to +110 c ( pd78912xa(a1), 78913xa(a1)), ?40 to +125 c ( pd78912xa(a2), 78913xa(a2)) ) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy1 800 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 ? 50 ns si20 setup time (to sck20 ) t sik1 150 ns si20 hold time (from sck20 ) t ksi1 400 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note 0 250 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy2 800 ns sck20 high-/low- level width t kh2 , t kl2 400 ns si20 setup time (to sck20 ) t sik2 100 ns si20 hold time (from sck20 ) t ksi2 400 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note 0 300 ns so20 setup time (to ss20 when ss20 is used) t kas2 120 ns so20 disable time (for ss20 when ss20 is used) t kds2 240 ns ss20 setup time (to sck20 first edge) t ssk2 100 ns ss20 hold time (from sck20 last edge) t kss2 400 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 78125 bps
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 347 (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck20 cycle time t kcy3 800 ns asck20 high-/low- level width t kh3 , t kl3 400 ns transfer rate 39063 bps asck20 rise/fall time t r , t f 1 s
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 348 ac timing measurement points (excluding cl1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f cc t xl t xh cl1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 349 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 350 8-bit a/d converter characteristics ( pd78912xa(a1), 78912xa(a2) only) (av dd = v dd = 4.5 to 5.5 v, av ss = v ss = 0 v, t a = ?40 to +110 c ( pd78912xa(a1)), ?40 to +125 c ( pd78912xa(a2)) ) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bits overall error notes 1, 2 0.4 1.0 %fsr conversion time t conv 14 28 s analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.2%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr). 10-bit a/d converter characteristics ( pd78913xa(a1), 78913xa(a2) only) (av dd = v dd = 4.5 to 5.5 v, av ss = v ss = 0 v, t a = ?40 to +110 c ( pd78913xa(a1)), ?40 to +125 c ( pd78913xa(a2)) ) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits overall error notes 1, 2 0.4 0.6 %fsr conversion time t conv 14 28 s zero-scale error notes 1, 2 0.6 %fsr full-scale error notes 1, 2 0.6 %fsr integral linearity error note 1 ile 4.5 lsb differential linearity error note 1 dle 2.0 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 28 electrical specifications ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 351 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +110 c ( pd78912xa(a1), 78913xa(a1)), ?40 to +125 c ( pd78912xa(a2), 78913xa(a2)) ) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 7 /f cc s oscillation stabilization wait time note t wait release by interrupt request 2 7 /f cc s note the oscillation stabilization wait time is the perio d during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. remark f cc : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 352 chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd , av dd v dd = av dd ?0.3 to +6.5 v supply voltage v pp note ?0.3 to +10.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v input voltage v i2 p50 to p53 with n-ch open drain ?0.3 to +13 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?10 ma total for all pins pd78f9136b ?30 ma per pin ?7 ma output current, high i oh total for all pins pd78f9136b(a) ?22 ma per pin 30 ma total for all pins pd78f9136b 160 ma per pin 10 ma output current, low i ol total for all pins pd78f9136b(a) 120 ma in normal operation mode ?40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg ?40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 353 system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit rc oscillator cl2 cl1 oscillation frequency (f cc ) note 2.0 4.0 mhz cl1 input frequency (f cc ) note 1.0 5.0 mhz cl1 cl2 cl1 input high-/low-level width (t xh , t xl ) 85 500 ns cl1 input frequency (f cc ) note v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock cl1 cl2 open cl1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. caution when using the system clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. rc oscillator frequency characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit f cc1 v dd = 2.7 to 5.5 v 1.5 2.0 2.5 mhz f cc2 v dd = 1.8 to 3.6 v 0.5 2.0 2.5 mhz f cc3 r = 11.0 k ? , c = 22 pf target: 2 mhz v dd = 1.8 to 5.5 v 0.5 2.0 2.5 mhz f cc4 v dd = 2.7 to 5.5 v 2.5 3.0 3.5 mhz f cc5 v dd = 1.8 to 3.6 v 0.75 3.0 3.5 mhz f cc6 r = 6.8 k ? , c = 22 pf target: 3 mhz v dd = 1.8 to 5.5 v 0.75 3.0 3.5 mhz f cc7 v dd = 2.7 to 5.5 v 3.5 4.0 4.7 mhz f cc8 v dd = 1.8 to 3.6 v 1.0 4.0 4.7 mhz oscillator frequency f cc9 r = 4.7 k ? , c = 22 pf target: 4 mhz v dd = 1.8 to 5.5 v 1.0 4.0 4.7 mhz remark so that the typ. spec. is satisfied between 2.0 to 4.0 mhz, set one of the above nine patterns for r and c.
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 354 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma total for all pins pd78f9136b ?15 ma per pin ?1 ma output current, high i oh total for all pins pd78f9136b(a) ?11 ma per pin 10 ma total for all pins pd78f9136b 80 ma per pin 3 ma output current, low i ol total for all pins pd78f9136b(a) 60 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 pins other than described below v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v v ih2 p50 to p53 with n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 cl1, cl2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 pins other than described below v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 cl1, cl2 v dd = 1.8 to 5.5 v 0 0.1 v v oh1 v dd = 4.5 to 5.5 v, i oh = ?1 ma v dd ? 1.0 v output voltage, high v oh2 v dd = 1.8 to 5.5 v, i oh = ?100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78f9136b) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78f9136b(a)) 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78f9136b) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78f9136b(a)) 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 355 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 pins other than cl1, cl2, or p50 to p53 3 a i lih2 cl1, cl2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 12 v 20 a i lil1 pins other than cl1, cl2, or p50 to p53 ?3 a i lil2 cl1, cl2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?3 note 1 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 50 100 200 k ? v dd = 5.0 v 10% note 4 6.5 18.0 ma v dd = 3.0 v 10% note 5 3.9 7.9 ma i dd1 note 2 4.0 mhz rc oscillation operating mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 3.0 5.0 ma v dd = 5.0 v 10% note 4 2.5 5.0 ma v dd = 3.0 v 10% note 5 1.0 2.0 ma i dd2 note 2 4.0 mhz rc oscillation halt mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 0.75 1.5 ma v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a i dd3 note 2 stop mode v dd = 2.0 v 10% 0.05 10 a v dd = 5.0 v 10% note 4 7.7 20.3 ma v dd = 3.0 v 10% note 5 5.1 10.2 ma power supply current i dd4 note 3 4.0 mhz rc oscillation a/d operating mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 4.0 7.0 ma notes 1. when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 3. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 356 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v, rc oscillation mode) parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp supply voltage = v pp1 21 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 22.5 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 21 ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 115 ma unit erase time t er 0.2 0.2 0.2 s total erase time t era 20 s rewrite count erase/write are regarded as 1 cycle 20 20 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the curr ent flowing through on-chip pull-up resistors) and av dd current are not included.
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 357 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 16 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 16 s v dd = 2.7 to 5.5 v 0.1 s ti80 input high-/low- level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 358 (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (to ss20 when ss20 is used) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (for ss20 when ss20 is used) t kds2 v dd = 1.8 to 5.5 v 800 ns v dd = 2.7 to 5.5 v 100 ns ss20 setup time (to sck20 first edge) t ssk2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns ss20 hold time (from sck20 last edge) t kss2 v dd = 1.8 to 5.5 v 600 ns note r and c are the load resistance and lo ad capacitance of t he so output line.
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 359 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 360 ac timing measurement points (excluding cl1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f cc t xl t xh cl1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 361 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 362 10-bit a/d converter characteristics (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits 4.5 v v dd 5.5 v 0.2 0.4 %fsr 2.7 v v dd < 4.5 v 0.4 0.6 %fsr overall error notes 1, 2 1.8 v v dd < 2.7 v 0.8 1.2 %fsr 2.7 v v dd 5.5 v 14 100 s conversion time t conv 1.8 v v dd < 2.7 v 28 100 s 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr zero-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr full-scale error notes 1, 2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 2.5 lsb 2.7 v v dd < 4.5 v 4.5 lsb integral linearity error note 1 ile 1.8 v v dd < 2.7 v 8.5 lsb 4.5 v v dd 5.5 v 1.5 lsb 2.7 v v dd < 4.5 v 2.0 lsb differential linearity error note 1 dle 1.8 v v dd < 2.7 v 3.5 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 29 electrical specifications ( pd78f9136b, 78f9136b(a)) user?s manual u14643ej3v0ud 363 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 7 /f cc s oscillation stabilization wait time note t wait release by interrupt request 2 7 /f cc s note the oscillation stabilization wait time is the perio d during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. remark f cc : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 364 chapter 30 electrical specifications ( pd78f9136b(a1)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd , av dd v dd = av dd ?0.3 to +6.5 v supply voltage v pp note ?0.3 to +10.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v input voltage v i2 p50 to p53 with n-ch open drain ?0.3 to +13 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?4 ma output current, high i oh total for all pins ?14 ma per pin 5 ma output current, low i ol total for all pins 80 ma in normal operation mode ?40 to +105 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg ?40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (4.5 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (4.5 v) of the operating voltage range of v dd (see b in the figure below). 4.5 v v dd 0 v 0 v v pp 4.5 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 365 system clock oscillator characteristics (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit rc oscillator cl2 cl1 oscillation frequency (f cc ) note 2.0 4.0 mhz cl1 input frequency (f cc ) note 1.0 5.0 mhz external clock cl1 cl2 open cl1 input high-/low-level width (t xh , t xl ) 85 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. construct the oscillator with r and c d evices that are guaranteed to operate at t a = 105 c.
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 366 dc characteristics (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma output current, high i oh total for all pins ?7 ma per pin 1.6 ma output current, low i ol total for all pins 40 ma v ih1 pins other than described below 0.7v dd v dd v v ih2 p50 to p53 with n-ch open drain 0.7v dd 10 v v ih3 reset, p20 to p25 0.8v dd v dd v input voltage, high v ih4 cl1, cl2 v dd ? 0.1 v dd v v il1 pins other than described below 0 0.3v dd v v il2 p50 to p53 0 0.3v dd v v il3 reset, p20 to p25 0 0.2v dd v input voltage, low v il4 cl1, cl2 0 0.1 v v oh1 i oh = ?1 ma v dd ? 2.0 v output voltage, high v oh2 i oh = ?100 a v dd ? 1.0 v i ol = 1.6 ma 2.0 v v ol1 pins other than p50 to p53 i ol = 400 a 1.0 v output voltage, low v ol2 p50 to p53 i ol = 1.6 ma 1.0 v i lih1 pins other than cl1, cl2, or p50 to p53 10 a i lih2 cl1, cl2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 10 v 80 a i lil1 pins other than cl1, cl2, or p50 to p53 ?10 a i lil2 cl1, cl2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?10 note a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ?10 a note when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 367 dc characteristics (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 or p60 to p63 50 100 300 k ? i dd1 note 1 4.0 mhz rc oscillation operating mode (r = 4.7 k ? , c = 22 pf) note 3 7.5 20.0 ma i dd2 note 1 4.0 mhz rc oscillation halt mode (r = 4.7 k ? , c = 22 pf) note 3 3.0 5.5 ma i dd3 note 1 stop mode 1 1000 a power supply current i dd4 note 2 4.0 mhz rc oscillation a/d operating mode (r = 4.7 k ? , c = 22 pf) note 3 8.7 22.3 ma notes 1. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 2. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 3. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins. flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 4.5 to 5.5 v, rc oscillation operating mode) parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp supply voltage = v pp1 21 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 22.5 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 21 ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 115 ma unit erase time t er 0.2 0.2 0.2 s total erase time t era 20 s rewrite count erase/write are regarded as 1 cycle 20 20 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the curr ent flowing through on-chip pull-up resistors) and av dd current are not included.
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 368 ac characteristics (1) basic operation (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time (minimum instruction execution time) t cy 0.4 8 s ti80 input high-/low- level width t tih , t til 0.1 s ti80 input frequency f ti 0 4 mhz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 369 (2) serial interface (t a = ?40 to +105 c, v dd = 4.5 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy1 800 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 ? 50 ns si20 setup time (to sck20 ) t sik1 150 ns si20 hold time (from sck20 ) t ksi1 400 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note 0 250 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy2 800 ns sck20 high-/low- level width t kh2 , t kl2 400 ns si20 setup time (to sck20 ) t sik2 100 ns si20 hold time (from sck20 ) t ksi2 400 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note 0 300 ns so20 setup time (to ss20 when ss20 is used) t kas2 120 ns so20 disable time (for ss20 when ss20 is used) t kds2 240 ns ss20 setup time (to sck20 first edge) t ssk2 100 ns ss20 hold time (from sck20 last edge) t kss2 400 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 78125 bps
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 370 (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck20 cycle time t kcy3 800 ns asck20 high-/low- level width t kh3 , t kl3 400 ns transfer rate 39063 bps asck20 rise/fall time t r , t f 1 s
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 371 ac timing measurement points (excluding cl1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f cc t xl t xh cl1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 372 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 373 10-bit a/d converter characteristics (t a = ?40 to +105 c, av dd = v dd = 4.5 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits overall error notes 1,2 0.4 0.6 %fsr conversion time t conv 14 28 s zero-scale error notes 1,2 0.6 %fsr full-scale error notes 1,2 0.6 %fsr integral linearity error note 1 ile 4.5 lsb differential linearity error note 1 dle 2.0 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 30 electrical specifications ( pd78f9136b(a1)) user?s manual u14643ej3v0ud 374 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +105 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 7 /f cc s oscillation stabilization wait time note t wait release by interrupt request 2 7 /f cc s note the oscillation stabilization wait time is the perio d during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. remark f cc : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 375 chapter 31 electrical specifications ( pd78f9136a) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd , av dd v dd = av dd ?0.3 to +6.5 v supply voltage v pp note ?0.3 to +10.5 v v i1 pins other than p50 to p53 ?0.3 to v dd + 0.3 v input voltage v i2 p50 to p53 with n-ch open drain ?0.3 to +13 v output voltage v o ?0.3 to v dd + 0.3 v per pin ?10 ma output current, high i oh total for all pins ?30 ma per pin 30 ma output current, low i ol total for all pins 160 ma in normal operation mode ?40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg ?40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ra tings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 376 system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit rc oscillator cl2 cl1 oscillation frequency (f cc ) note 1 v dd = oscillation voltage range 2.0 4.0 mhz cl1 input frequency (f cc ) note 1 1.0 5.0 mhz cl1 cl2 cl1 input high-/low-level width (t xh , t xl ) 85 500 ns cl1 input frequency (f cc ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock cl1 cl2 open cl1 input high-/low-level width (t xh , t xl ) 85 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. caution when using the system clock oscillator, wire as follows in the ar ea enclosed by th e broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. rc oscillator frequency characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit f cc1 v dd = 2.7 to 5.5 v 1.5 2.0 2.5 mhz f cc2 v dd = 1.8 to 3.6 v 0.5 2.0 2.5 mhz f cc3 r = 11.0 k ? , c = 22 pf target: 2 mhz v dd = 1.8 to 5.5 v 0.5 2.0 2.5 mhz f cc4 v dd = 2.7 to 5.5 v 2.5 3.0 3.5 mhz f cc5 v dd = 1.8 to 3.6 v 0.75 3.0 3.5 mhz f cc6 r = 6.8 k ? , c = 22 pf target: 3 mhz v dd = 1.8 to 5.5 v 0.75 3.0 3.5 mhz f cc7 v dd = 2.7 to 5.5 v 3.5 4.0 4.7 mhz f cc8 v dd = 1.8 to 3.6 v 1.0 4.0 4.7 mhz oscillator frequency f cc9 r = 4.7 k ? , c = 22 pf target: 4 mhz v dd = 1.8 to 5.5 v 1.0 4.0 4.7 mhz remark so that the typ. spec is satisfied between 2.0 to 4.0 mhz, set one of the above nine patterns for r and c.
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 377 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ?1 ma output current, high i oh total for all pins ?15 ma per pin 10 ma output current, low i ol total for all pins 80 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 pins other than described below v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v v ih2 p50 to p53 with n-ch open drain v dd = 1.8 to 5.5 v t a = 25 to 85 c 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 cl1, cl2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 pins other than described below v dd = 1.8 to 5.5 v 0 0.1v dd v v il2 p50 to p53 v dd = 2.7 to 5.5 v 0 0.3v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p25 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 cl1, cl2 v dd = 1.8 to 5.5 v 0 0.1 v v oh1 v dd = 4.5 to 5.5 v, i oh = ?1 ma v dd ? 1.0 v output voltage, high v oh2 v dd = 1.8 to 5.5 v, i oh = ?100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 378 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 pins other than cl1, cl2, or p50 to p53 3 a i lih2 cl1, cl2 v i = v dd 20 a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v i = 12 v 20 a i lil1 pins other than cl1, cl2, or p50 to p53 ?3 a i lil2 cl1, cl2 ?20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v i = 0 v ?3 note 1 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistance r 1 v i = 0 v, for pins other than p50 to p53 50 100 200 k ? v dd = 5.0 v 10% note 4 5.0 15.0 ma v dd = 3.0 v 10% note 5 1.9 4.9 ma i dd1 note 2 4.0 mhz rc oscillation operating mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 1.5 3.0 ma v dd = 5.0 v 10% note 4 2.5 5.0 ma v dd = 3.0 v 10% note 5 1.0 2.0 ma i dd2 note 2 4.0 mhz rc oscillation halt mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 0.75 1.5 ma v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a i dd3 note 2 stop mode v dd = 2.0 v 10% 0.05 10 a v dd = 5.0 v 10% note 4 6.2 17.3 ma v dd = 3.0 v 10% note 5 3.1 7.2 ma power supply current i dd4 note 3 4.0 mhz rc oscillation a/d operating mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 5 2.5 5.0 ma notes 1. when port 5 is in input mode, a low-level input leakage current of ?60 a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. the current flowing to the ports (including the cu rrent flowing through on-chip pull-up resistors) and av dd current are not included. 3. the current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not included. 4. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 379 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v, rc oscillation operating mode) parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp supply voltage = v pp1 18 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 22.5 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 18 ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 115 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s rewrite count erase/write are regarded as 1 cycle 20 20 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the curr ent flowing through on-chip pull-up resistors) and av dd current are not included.
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 380 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 16 s cycle time (minimum instruction execution time) t cy v dd = 1.8 to 5.5 v 1.6 16 s v dd = 2.7 to 5.5 v 0.1 s ti80 input high-/low- level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 s reset low-level width t rsl 10 s cpt20 input high- /low-level width t cph , t cpl 10 s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 381 (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and lo ad capacitance of t he so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (to ss20 when ss20 is used) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (for ss20 when ss20 is used) t kds2 v dd = 1.8 to 5.5 v 800 ns v dd = 2.7 to 5.5 v 100 ns ss20 setup time (to sck20 first edge) t ssk2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns ss20 hold time (from sck20 last edge) t kss2 v dd = 1.8 to 5.5 v 600 ns note r and c are the load resistance and lo ad capacitance of t he so output line.
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 382 (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 383 ac timing measurement points (excluding cl1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd measurement points clock timing 1/f cc t xl t xh cl1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti capture input timing cpt20 t cpl t cph interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 384 serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 t ssk2 t kss2 ss20 sck20 (ckp20 = 0) sck20 (ckp20 = 1) uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 385 10-bit a/d converter characteristics (t a = ? 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bits 4.5 v v dd 5.5 v 0.2 0.4 %fsr 2.7 v v dd < 4.5 v 0.4 0.6 %fsr overall error notes 1,2 1.8 v v dd < 2.7 v 0.8 1.2 %fsr 2.7 v v dd 5.5 v 14 100 s conversion time t conv 1.8 v v dd < 2.7 v 28 100 s 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr zero-scale error notes 1,2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr full-scale error notes 1,2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 2.5 lsb 2.7 v v dd < 4.5 v 4.5 lsb integral linearity error note 1 ile 1.8 v v dd < 2.7 v 8.5 lsb 4.5 v v dd 5.5 v 1.5 lsb 2.7 v v dd < 4.5 v 2.0 lsb differential linearity error note 1 dle 1.8 v v dd < 2.7 v 3.5 lsb analog input voltage v ian 0 av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. this value is indicated as a ratio to the full-scale value (%fsr).
chapter 31 electrical specifications ( pd78f9136a) user?s manual u14643ej3v0ud 386 data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 7 /f cc s oscillation stabilization wait time note t wait release by interrupt request 2 7 /f cc s note the oscillation stabilization wait time is the peri od during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. remark f cc : system clock oscillation frequency data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14643ej3v0ud 387 chapter 32 characteristics curves (reference values) ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) i dd vs v dd (system clock: 5.0 mhz crystal resonator) 01 2 34 5 6 7 8 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 pcc = 00h pcc = 02h pcc = 00h (halt mode) pcc = 02h (halt mode) x2 x1 crystal resonator 5.0 mhz 22 pf 22 pf (t a = 25?c) power supply voltage v dd (v) power supply current i dd (ma)
chapter 32 characteristics curves (reference values) ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) user?s manual u14643ej3v0ud 388 i dd vs v dd (system clock: 4.0 mhz crystal resonator) 01 2 34 5 6 7 8 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 pcc = 00h pcc = 02h pcc = 00h (halt mode) pcc = 02h (halt mode) x2 x1 crystal resonator 4.0 mhz 22 pf 22 pf (t a = 25?c) power supply voltage v dd (v) power supply current i dd (ma)
chapter 32 characteristics curves (reference values) ( pd78910xa, 78911xa, 78910xa(a), 78911xa(a)) user?s manual u14643ej3v0ud 389 i dd vs v dd (system clock: 2.0 mhz crystal resonator) 01 2 34 5 6 7 8 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 pcc = 00h pcc = 02h pcc = 00h (halt mode) pcc = 02h (halt mode) x2 x1 crystal resonator 2.0 mhz 47 pf 47 pf (t a = 25?c) power supply current i dd (ma) power supply voltage v dd (v)
user?s manual u14643ej3v0ud 390 chapter 33 characteristics curves (reference values) ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) i dd vs v dd (system clock: 5.0 mhz ceramic resonator) 01 2 34 5 6 7 8 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 pcc = 00h pcc = 02h pcc = 00h (halt mode) pcc = 02h (halt mode) x2 x1 ceramic resonator 5.0 mhz 22 pf 22 pf (t a = 25?c) power supply voltage v dd (v) power supply current i dd (ma)
chapter 33 characteristics curves (reference values) ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 391 i dd vs v dd (system clock: 4.0 mhz ceramic resonator) 01 2 34 5 6 7 8 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 pcc = 00h pcc = 02h pcc = 00h (halt mode) pcc = 02h (halt mode) x2 x1 ceramic resonator 4.0 mhz 22 pf 22 pf (t a = 25?c) power supply voltage v dd (v) power supply current i dd (ma)
chapter 33 characteristics curves (reference values) ( pd78910xa(a1), 78911xa(a1), 78910xa(a2), 78911xa(a2)) user?s manual u14643ej3v0ud 392 i dd vs v dd (system clock: 2.0 mhz ceramic resonator) 01 2 34 5 6 7 8 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 pcc = 00h pcc = 02h pcc = 00h (halt mode) pcc = 02h (halt mode) x2 x1 ceramic resonator 2.0 mhz 47 pf 47 pf (t a = 25?c) power supply current i dd (ma) power supply voltage v dd (v)
user?s manual u14643ej3v0ud 393 chapter 34 example of rc oscillator frequency characteristics (reference values) ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a), 78f9136a) f cc vs v dd (rc oscillation, r = 11 k ? , c= 22 pf) 23 456 supply voltage v dd [v] 1.4 1.6 1.8 2.0 2.2 2.4 2.6 system clock frequency f cc [mhz] (t a = ?40 ?c ) sample a sample b sample c cl2 cl1 11 k ? 22 pf 1.4 1.6 1.8 2.0 2.2 2.4 2.6 23 456 supply voltage v dd [v] system clock frequency f cc [mhz] (t a = 25 ?c ) cl2 cl1 11 k ? 22 pf sample a sample b sample c 1.4 1.6 1.8 2.0 2.2 2.4 2.6 system clock frequency f cc [mhz] 23 456 supply voltage v dd [v] (t a = 85 ?c ) sample a sample b sample c cl2 cl1 11 k ? 22 pf
chapter 34 example of rc oscillator frequency characteristics (reference values) ( pd78912xa, 78913xa, 78912xa(a), 78913xa(a), 78f9136(a) user?s manual u14643ej3v0ud 394 f cc vs v dd (rc oscillation, r = 4.7 k ? , c= 22 pf) (t a = ?40 ?c ) 23 456 supply voltage v dd [v] 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] sample a sample b sample c cl2 cl1 4.7 k ? 22 pf (t a = 25 ?c ) 23 456 supply voltage v dd [v] 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] sample a sample b sample c cl2 cl1 4.7 k ? 22 pf 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] 23 456 supply voltage v dd [v] (t a = 85 ?c ) sample a sample b sample c cl2 cl1 4.7 k ? 22 pf
user?s manual u14643ej3v0ud 395 chapter 35 example of rc oscillator frequency characteristics (reference values) ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) f cc vs v dd (rc oscillation, r = 11 k ? , c= 22 pf) 23 456 supply voltage v dd [v] 1.4 1.6 1.8 2.0 2.2 2.4 2.6 system clock frequency f cc [mhz] (t a = ?40 ?c ) cl2 cl1 11 k ? 22 pf sample a sample b sample c 1.4 1.6 1.8 2.0 2.2 2.4 2.6 23 456 supply voltage v dd [v] system clock frequency f cc [mhz] (t a = 25 ?c ) cl2 cl1 11 k ? 22 pf sample a sample b sample c 1.4 1.6 1.8 2.0 2.2 2.4 2.6 system clock frequency f cc [mhz] 23 456 supply voltage v dd [v] (t a = 85 ?c ) sample a sample b sample c cl2 cl1 11 k ? 22 pf
chapter 35 example of rc oscillator fr equency characteristics (reference values) ( pd78912xa(a1), 78913xa(a1), 78912xa(a2), 78913xa(a2)) user?s manual u14643ej3v0ud 396 f cc vs v dd (rc oscillation, r = 4.7 k ? , c= 22 pf) (t a = ?40 ?c ) 23 456 supply voltage v dd [v] 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] cl2 cl1 4.7 k ? 22 pf sample a sample b sample c (t a = 25 ?c ) 23 456 supply voltage v dd [v] 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] cl2 cl1 4.7 k ? 22 pf sample a sample b sample c 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] 23 456 supply voltage v dd [v] (t a = 85 ?c ) cl2 cl1 4.7 k ? 22 pf sample a sample b sample c
user?s manual u14643ej3v0ud 397 chapter 36 package drawing s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2
user?s manual u14643ej3v0ud 398 chapter 37 recommended soldering conditions the pd789104a, 789114a, 789124a, and 789134a subserie s should be soldered and mounted under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 37-1. surface mounting type soldering cond itions (1/3) (1) pd789101amc- -5a4, pd789102amc- -5a4, pd789104amc- -5a4, pd789111amc- -5a4, pd789112amc- -5a4, pd789114amc- -5a4, pd789121amc- -5a4, pd789122amc- -5a4, pd789124amc- -5a4, pd789131amc- -5a4, pd789132amc- -5a4, pd789134amc- -5a4, pd789101amc(a)- -5a4, pd789102amc(a)- -5a4, pd789104amc(a)- -5a4, pd789111amc(a)- -5a4, pd789112amc(a)- -5a4, pd789114amc(a)- -5a4, pd789121amc(a)- -5a4, pd789122amc(a)- -5a4, pd789124amc(a)- -5a4, pd789131amc(a)- -5a4, pd789132amc(a)- -5a4, pd789134amc(a)- -5a4, pd789101amc(a1)- -5a4, pd789102amc(a1)- -5a4, pd789104amc(a1)- -5a4, pd789111amc(a1)- -5a4, pd789112amc(a1)- -5a4, pd789114amc(a1)- -5a4, pd789121amc(a1)- -5a4, pd789122amc(a1)- -5a4, pd789124amc(a1)- -5a4, pd789131amc(a1)- -5a4, pd789132amc(a1)- -5a4, pd789134amc(a1)- -5a4, pd789101amc(a2)- -5a4, pd789102amc(a2)- -5a4, pd789104amc(a2)- -5a4, pd789111amc(a2)- -5a4, pd789112amc(a2)- -5a4, pd789114amc(a2)- -5a4, pd789121amc(a2)- -5a4, pd789122amc(a2)- -5a4, pd789124amc(a2)- -5a4, pd789131amc(a2)- -5a4, pd789132amc(a2)- -5a4, pd789134amc(a2)- -5a4 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: three times or less ir35-00-3 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: three times or less vp15-00-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering methods together ( except for partial heating). remark for soldering methods and conditions other than those recommended above, contact an nec electronics sales representative.
chapter 37 recommended soldering conditions user?s manual u14643ej3v0ud 399 table 37-1. surface mounting type soldering cond itions (2/3) (2) pd78f9116bmc-5a4, pd78f9136bmc-5a4, pd78f9116bmc(a)-5a4, pd78f9136bmc(a)-5a4, pd78f9116bmc(a1)-5a4, pd78f9136bmc(a1)-5a4 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir35-107-2 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) vp15-107-2 wave soldering solder bath temperatur e: 260c max., time: 10 seconds max., count: once preheating temperature: 120c max. (pac kage surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ws60-107-1 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). remark for soldering methods and conditions other than those recommended above, contact an nec electronics sales representative. (3) pd78f9116amc-5a4, pd78f9136amc-5a4 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir35-107-3 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) vp15-107-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once preheating temperature: 120c max.(pack age surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ws60-107-1 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). remark for soldering methods and conditions other than those recommended above, contact an nec electronics sales representative.
chapter 37 recommended soldering conditions user?s manual u14643ej3v0ud 400 table 37-1. surface mounting type soldering cond itions (3/3) (4) pd789101amc- -5a4-a, pd789102amc- -5a4-a, pd789104amc- -5a4-a, pd789111amc- -5a4-a, pd789112amc- -5a4-a, pd789114amc- -5a4-a, pd789121amc- -5a4-a, pd789122amc- -5a4-a, pd789124amc- -5a4-a, pd789131amc- -5a4-a, pd789132amc- -5a4-a, pd789134amc- -5a4-a, pd78f9116amc-5a4-a, pd78f9136amc-5a4-a, pd78f9116bmc-5a4-a, pd78f9136bmc-5a4-a soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebaking is necessary at 125c for 20 to 72 hours) ir60-207-3 wave soldering when the pin pitch of the pac kage is 0.65 mm or more, wave soldering can also be performed. for details, ask an nec electronics sales representative. ? partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering methods together ( except for partial heating). remarks 1. products that have the part numbers suffixed by ?-a? are lead-free products. 2. for soldering methods and conditions other than those recommended above, contact an nec electronics sales representative.
user?s manual u14643ej3v0ud 401 appendix a development tools the following development tools are available for the development of syst ems that employ the pd789104a/114a/124a/134a subseries. figure a-1 shows the developm ent tool configuration. ? support of the pc98-nx series unless otherwise specified, the pd789104a/114a/124a/134a subseries supported by ibm pc/at tm and compatibles can be used for the pc98-nx series. when using the pc98-nx series, refer to the descriptions of ibm pc/at and compatibles. ? windows unless otherwise specified, ?windows? indicates the following oss. ? windows 3.1 ? windows 95 ? windows 98 ? windows 2000 ? windows nt tm ver. 4.0
appendix a development tools user?s manual u14643ej3v0ud 402 figure a-1. development tools software package software package assembler package c compiler package device file c library source file note 1 integrated debugger system simulator project manager (windows version only) note 2 language processing software debugging software control software host machine (pc or ews) interface adapter flash memory writing tools flash programmer in-circuit emulator power supply unit emulation board emulation probe target system conversion socket or conversion adapter flash memory writing adapter flash memory notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package and is available only for windows.
appendix a development tools user?s manual u14643ej3v0ud 403 a.1 software package various software tools for 78k/0s development are integrated in one package. the following tools are included. ra78k0s, cc78k0s, id78k0s-ns, sm78k0s, various device files sp78k0s software package part number: s sp78k0s remark in the part number differs depending on the operating system to be used. s sp78k0s host machine os supply medium ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom a.2 language processing software program that converts program written in mnemonic into object codes that can be executed by a microcontroller. in addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. used in combination with a device file (df789136) (sold separately). the assembler package is a dos-based application but may be used in the windows environment by using the project manager of windows (included in the package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into object codes that can be executed by a microcontroller. used in combination with an assembler package (r a78k0s) and device file (df789136) (both sold separately). the c compiler package is a dos-based application but may be used in the windows environment by using the project manager of windows (included in the assembler package). cc78k0s c compiler package part number: s cc78k0s file containing the information inherent to the device. used in combination with other tools (ra78k0s, cc78k0s, id78k0s-ns, sm78k0s) (all sold separately). df789136 note 1 device file part number: s df789136 source file of functions constituting the object library included in the c compiler package. necessary for changing the object library included in the c compiler package according to the customer?s specifications. since this is the source file, its working en vironment does not depend on any particular operating system. cc78k0s-l note 2 c library source file part number: s cc78k0s-l notes 1. df789136 is a common file that can be used with the ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. 2. cc78k0s-l is not included in the software package (sp78k0s).
appendix a development tools user?s manual u14643ej3v0ud 404 remark in the part number differs depending on the host machine and operating system to be used. s ra78k0s s cc78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5? 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows 3p17 hp9000 series 700 tm hp-ux tm (rel.10.10) 3k17 sparcstation tm sunos tm (rel.4.1.1), solaris tm (rel.2.5.1) cd-rom s df789136 s cc78k0s-l host machine os supply medium ab13 japanese windows bb13 pc-9800 series, ibm pc/at and compatibles english windows 3.5? 2hd fd 3p16 hp9000 series 700 hp-ux (rel.10.10) dat 3k13 3.5? 2hd fd 3k15 sparcstation sunos (rel.4.1.1), solaris (rel.2.5.1) 1/4? cgmt a.3 control software project manager control software provided for effi cient user program development in the windows environment. the project manager allows a series of tasks required for user program development to be performed, including star ting the editor, building, and starting the debugger. the project manager is included in the assembler package (ra78k0s). it cannot be used in an environment other than windows. a.4 flash memory writing tools flashpro iii (part number: fl-pr3, pg-fp3) flashpro iv (part number: fl-pr4, pg-fp4) flash programmer flash programmer dedicated to microcontrollers incorporating flash memory. fa-30mc flash memory writing adapter flash memory writing adapter. used connected to flashpro iii. 30-pin plastic ssop (mc-5a4 type) remark fl-pr3, fl-pr4, and fa-30mc are products of naito densei machida mfg. co., ltd. for further information, contact: naito d ensei machida mfg. co., ltd. (+81-45-475-4191)
appendix a development tools user?s manual u14643ej3v0ud 405 a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging the hardware and software of an application system using the 78k/0s series. used with an integrated debugger (id78k0s-ns). used in combination with an ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator in-circuit emulator with enhanced functions of the ie-78k0s-ns. the debug function is further enhanced by adding a coverage function and enhancing the tracer and timer functions. ie-70000-mc-ps-b ac adapter adapter for supplying power from a 100 to 240 vac outlet. ie-70000-98-if-c interface adapter adapter required when using a pc-9800 series (except notebook type) as the host machine (c bus supported). ie-70000-cd-if-a pc card interface pc card and interface cable required when using a notebook type pc as the host machine (pcmica socket supported). ie-70000-pc-if-c interface adapter adapter required when using an ibm pc/at or compatible as the host machine (isa bus supported). ie-70000-pci-if-a interface adapter adapter required when using a personal computer incorporating a pci bus as the host machine. ie-789136-ns-em1 emulation board emulation board for emulating the peripher al hardware inherent to the device. used in combination with an in-circuit emulator. np-30mc emulation probe probe for connecting the in-circuit emulator and target system. used in combination with the nspack30bk and yspack30bk. nspack30bk yspack30bk conversion adapter conversion adapter used to connect a target system board designed to allow mounting a 30- pin plastic ssop (mc-5a4 type) and the np-30mc. remarks 1. the np-30mc is a product of nait o densei machida mfg. co., ltd. for further information, contact: naito densei machida mfg. co., ltd. (+81-45-475-4191) 2. the nspack30bk and yspack30bk are products of tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672)
appendix a development tools user?s manual u14643ej3v0ud 406 a.6 debugging tools (software) this debugger supports the in-circuit emulators ie-78k0s-ns and ie-78k0s-ns-a for the 78k/0s series. the id78k0s-ns is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window func tion that associates the source program, disassemble display, and memory display with the trace result. used in combination with a device file (df789136) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s se ries. the sm78k0s is windows-based software. it can be used to debug the target system at c source level or assembler level while simulating the operation of the target system on the host machine. using sm78k0s, the logic and performance of t he application can be verified independently of hardware development. therefore, the development efficiency can be enhanced and the software quality can be improved. used in combination with a device file (df789136) (sold separately). sm78k0s system simulator part number: s sm78k0s file containing the information inherent to the device. used in combination with other tools (ra78k0s, cc78k0s, id78k0s-ns, sm78k0s) (all sold separately). df789136 note device file part number: s df789136 note df789136 is a common file that can be used with the ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the operating system to be used and the supply medium. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5? 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom
user?s manual u14643ej3v0ud 407 appendix b notes on target system design the following show the conditions when connecting the em ulation probe to the conversion adapter. follow the configuration below and consider t he shape of parts to be mounted on th e target system when designing a system. figure b-1. distance between in-circu it emulator and conversion adapter 150 mm emulation board ie-789136-ns-em1 cn2 emulation probe np-30mc conversion adapter: yspack30bk, nspack30bk board on end of np-30mc in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a target system remarks 1. the np-30mc is a product of nait o densei machida mfg. co., ltd. 2. the yspack30bk and nspack30bk are produc ts of tokyo eletech corporation.
appendix b notes on target system design user?s manual u14643ej3v0ud 408 figure b-2. connection condition of target system 31 mm 37 mm emulation probe np-30mc 13 mm emulation board ie-789136-ns-em1 15 mm 20 mm 5 mm board on end of np-30mc conversion adapter yspack30bk, nspack30bk guide pin yqguide target system remarks 1. the np-30mc is a product of nait o densei machida mfg. co., ltd. 2. the yspack30bk, nspack30bk, and yqguide are products of tokyo eletech corporation.
user?s manual u14643ej3v0ud 409 appendix c register index c.1 register name index (alphabetical order) [a] a/d conversion result register 0 (adcr0 )....................................................................................... ....................143, 155 a/d converter mode re gister 0 (adm0)........................................................................................... ....................144, 156 analog input channel specification re gister 0 (ads0) ........................................................................... ..............145, 157 asynchronous serial interface m ode register 20 ( asim20) ................................................................. 172, 17 8, 181, 193 asynchronous serial interface status register 20 (asi s20) ...................................................................... ...........174, 182 [b] baud rate generator contro l register 20 (brg c20)............................................................................... ...... 175, 183, 194 [e] 8-bit compare regi ster 80 (cr80)............................................................................................... .................................125 8-bit timer coun ter 80 (t m80).................................................................................................. ....................................125 8-bit timer mode contro l register 80 (tmc 80) ................................................................................... ..........................126 external interrupt mode register 0 (intm0)..................................................................................... ............................212 [i] interrupt mask flag register 0 (mk0)........................................................................................... ................................. 211 interrupt mask flag register 1 (mk1)........................................................................................... ................................. 211 interrupt request flag register 0 (if0) ........................................................................................ ..................................210 interrupt request flag register 1 (if1) ........................................................................................ ..................................210 [m] multiplication data register a0 (mra0)......................................................................................... ...............................202 multiplication data register b0 (mrb0)......................................................................................... ...............................202 multiplier control register 0 (mulc 0) .......................................................................................... ................................204 [o] oscillation stabilization time select regi ster (osts).......................................................................... ..........................222 [p] port 0 (p0).................................................................................................................... .................................................82 port 1 (p1).................................................................................................................... .................................................83 port 2 (p2).................................................................................................................... .................................................84 port 5 (p5).................................................................................................................... .................................................88 port 6 (p6).................................................................................................................... .................................................89 port mode regist er 0 (p m0)..................................................................................................... ......................................90 port mode regist er 1 (p m1)..................................................................................................... ......................................90 port mode regist er 2 (p m2)..................................................................................................... ...................... 90, 115, 127 port mode regist er 5 (p m5)..................................................................................................... ......................................90 processor clock cont rol regist er (pcc) ......................................................................................... ........................96, 103 pull-up resistor opti on register 0 (pu0) ....................................................................................... ..................................91 pull-up resistor option register b2 (pub2) ..................................................................................... ...............................92
appendix c register index user?s manual u14643ej3v0ud 410 [r] receive buffer regi ster 20 (rxb20)............................................................................................. ............................... 169 receive shift regi ster 20 (rxs20) .............................................................................................. ................................ 169 [s] serial operating mode register 20 (csim 20) ..................................................................................... ..170, 178, 180, 192 16-bit capture regi ster 20 (tcp20)............................................................................................. .................................112 16-bit compare regi ster 20 (cr20).............................................................................................. ................................112 16-bit multiplication result storage regist er 0 (mul0) ......................................................................... ........................ 202 16-bit timer count er 20 (t m20)................................................................................................. ...................................112 16-bit timer mode contro l register 20 (tmc 20).................................................................................. ..........................113 [t] timer clock select register 2 (tcl2)........................................................................................... ................................ 138 transmit shift regi ster 20 (txs20) ............................................................................................. ................................. 169 [w] watchdog timer mode r egister (wdtm)............................................................................................ ......................... 139
appendix c register index user?s manual u14643ej3v0ud 411 c.2 register symbol index (alphabetical order) [a] adcr0: a/d conversion result regi ster 0 ........................................................................................ .................143, 155 adm0: a/d converter mode regist er 0 ............................................................................................ ...............144, 156 ads0: analog input channel sp ecification re gister 0 ............................................................................ .........145, 157 asim20: asynchronous serial inte rface mode regist er 20 ................................................................ 172, 178, 181, 193 asis20: asynchronous serial in terface status register 20....................................................................... .........174, 182 [b] brgc20: baud rate generato r control r egister 20................................................................................ ...... 175, 183, 194 [c] cr20: 16-bit compar e regist er 20 ............................................................................................... .......................... 112 cr80: 8-bit compar e register 80 ................................................................................................ ...........................125 csim20: serial operat ing mode regi ster 20 ...................................................................................... 170, 178, 180, 192 [i] if0: interrupt reques t flag regi ster 0 ......................................................................................... .........................210 if1: interrupt reques t flag regi ster 1 ......................................................................................... .........................210 intm0: external interr upt mode regi ster 0...................................................................................... ........................212 [m] mk0: interrupt mask flag regist er 0 ............................................................................................ ......................... 211 mk1: interrupt mask flag regist er 1 ............................................................................................ ......................... 211 mra0: multiplication data regi ster a0 .......................................................................................... ..........................202 mrb0: multiplication data regi ster b0 .......................................................................................... ..........................202 mul0: 16-bit multiplication re sult storage register 0 .......................................................................... ....................202 mulc0: multiplier c ontrol regi ster 0 ........................................................................................... ..............................204 [o] osts: oscillation stabilizati on time select register........................................................................... .....................222 [p] p0: port 0 ..................................................................................................................... ......................................82 p1: port 1 ..................................................................................................................... ......................................83 p2: port 2 ..................................................................................................................... ......................................84 p5: port 5 ..................................................................................................................... ......................................88 p6: port 6 ..................................................................................................................... ......................................89 pcc: processor cloc k control register .......................................................................................... .................96, 103 pm0: port mode register 0...................................................................................................... ...............................90 pm1: port mode register 1...................................................................................................... ...............................90 pm2: port mode register 2...................................................................................................... ............... 90, 115, 127 pm5: port mode register 5...................................................................................................... ...............................90 pu0: pull-up resistor option regi ster 0 ........................................................................................ ..........................91 pub2: pull-up resistor option regi ster b2 ...................................................................................... ..........................92
appendix c register index user?s manual u14643ej3v0ud 412 [r] rxb20: receive buff er register 20.............................................................................................. ............................ 169 rxs20: receive sh ift register 20 ............................................................................................... ............................. 169 [t] tcl2: timer clock se lect regi ster 2 ............................................................................................ .......................... 138 tcp20: 16-bit capt ure regist er 20 .............................................................................................. .............................112 tm20: 16-bit time r counter 20 .................................................................................................. .............................112 tm80: 8-bit time r counte r 80 ................................................................................................... ............................. 125 tmc20: 16-bit timer mode control regi ster 20................................................................................... .......................113 tmc80: 8-bit timer mode control re gister 80.................................................................................... ....................... 126 txs20: transmit sh ift register 20 .............................................................................................. ............................. 169 [w] wdtm: watchdog time r mode r egist er ............................................................................................. ..................... 139
user?s manual u14643ej3v0ud 413 appendix d revision history d.1 major revisions in this edition page description pp. 26-28 pp. 30-32 chapter 1 general ( pd789104a and 789114a subseries) addition of lead-free products pd789101amc- -5a4-a, pd789102amc- -5a4-a, pd789104amc- -5a4-a, pd789111amc- -5a4-a, pd789112amc- -5a4-a, pd789114amc- -5a4-a, pd78f9116amc-5a4-a, pd78f9116bmc-5a4-a update of 1.7 78k/0s series lineup pp. 38-40 pp. 42-44 chapter 2 general ( pd789124a and 789134a subseries) addition of lead-free products pd789121amc- -5a4-a, pd789122amc- -5a4-a, pd789124amc- -5a4-a, pd789131amc- -5a4-a, pd789132amc- -5a4-a, pd789134amc- -5a4-a, pd78f9136amc-5a4-a, pd78f9136bmc-5a4-a update of 2.6 78k/0s series lineup p. 130 chapter 9 8-bit timer/event counters 80 to 82 modification of figure 9-5 external event counter operation timing (with rising edge specified) p. 400 chapter 37 recommended soldering conditions addition of recommended soldering c onditions for the lead-free products the mark shows major revised points.
appendix d revision history user?s manual u14643ej3v0ud 414 d.2 revision history up to previous edition revisions up to the previous edition are shown below. the ?applied to? column indicates the chapter in each edition to which the revision was applied. (1/2) edition major revision from previous edition applied to: ? addition of pd789101a(a1), 789102a(a1), 789104a(a1), 789111a(a1), 789112a(a1), 789114a(a1), 789121a(a1), 789122a(a1), 789124a(a1), 789131a(a1), 789132a(a1), 789134a(a1), 789101a(a2), 789102a(a2), 789104a(a2), 789111a(a2), 789112a(a2), 789114a(a2), 789121a(a2), 789122a(a2), 789124a(a2), 789131a(a2), 789132a(a2), 789134a(a2), 78f9116b, 78f9136b, 78f9116b(a), 78f9136b(a), 78f9116b(a1), 78f9136b(a1) ? addition of description related to expanded-specification products throughout ? addition of 1.1 expanded-specification products and conventional-specification products ? addition of 1.10 differences between standard quality grade products and (a), (a1), (a2) products chapter 1 general ( pd789104a, 789114a subseries) addition of 2.9 differences between standard quality grade products and (a), (a1), (a2) products chapter 2 general ( pd789124a, 789134a subseries) ? modification of description in 8.4.1 operation as timer interrupt ? modification of figure 8-5 timing of timer interrupt operation ? modification of description in 8.4.2 operation as timer output ? modification of description in figure 8-7 timer output timing ? addition of 8.5 notes on using 16-bit timer 20 chapter 8 16-bit timer 20 addition of description to 9.5 notes on using 8-bit timer/event counter 80 chapter 9 8-bit timer/event counter 80 addition of 11.5 (8) input impedance of ani0 to ani3 pins chapter 11 8-bit a/d converter ( pd789104a, 789124a subseries) ? modification of description in 12.2 (2) a/d conversion result register 0 (adcr0) ? addition of 12.5 (8) input impedance of ani0 to ani3 pins chapter 12 10-bit a/d converter ( pd789114a, 789134a subseries) ? modification of figure 13-1 block diagram of serial interface 20 ? addition of 13.3 (4) (c) generation of serial clock from system clock in 3-wire serial i/o mode ? addition of 13.4.2 (2) (f) reading receive data chapter 13 serial interface 20 addition of caution 3 in figure 15-2 format of interrupt request flag register chapter 15 interrupt functions 2nd revision of chapter chapter 18 pd78f9116a, 78f9116b, 78f9136a, 78f9136b
appendix d revision history user?s manual u14643ej3v0ud 415 (2/2) edition major revision from previous edition applied to: chapter 21 to chapter 31 electrical specifications chapter 32 , chapter 33 characteristics curves (reference values) chapter 34 , chapter 35 example of rc oscillator frequency characteristics (reference values) chapter 36 package drawing addition of chapters chapter 37 recommended soldering conditions revision of appendix appendix a development tools appendix b notes on target system design addition of appendices appendix d revision history 2nd deletion of appendix b embedded software ?

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