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hcpl-5150 & hcpl-5151, dscc smd 5962-04205 0.5fampfoutputfcurrentfigbtfgatefdrivefoptocoupler data sheet features ? performance guaranteed over full military temperature range: -55 c to +125 c ? manufactured and tested on a mil-prf-38534 certifed line ? hermetically sealed packages ? dual marked with device part number and dscc drawing number ? qml-38534 ? hcpl-3150 function compatibility ? 0.5 a minimum peak output current ? 10 kv/ m s minimum common mode rejection (cmr) at v cm = 1000 v ? 1.0 v maximum low level output voltage (v ol ) eliminates need for negative gate drive ? i cc = 5 ma maximum supply current ? under voltage lock-out protection (u vlo ) with hysteresis ? wide operating v cc range: 15 to 30 volts ? 500 ns maximum propagation delay ? +/- 0.35 m s maximum delay between devices applications ? industrial and military environments ? high reliability systems ? harsh industrial environments ? transportation, medical, and life critical systems ? isolated igbt/mosfet gate drive ? ac and brushless dc motor drives ? industrial inverters ? switch mode power supplies (smps) ? uninterruptible power supplies (ups) description the hcpl-5150 contains a gaasp led optically coupled to an integrated circuit with a power output stage. the device is ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and current supplied by this opto - coupler makes it ideally suited for directly driving igbts with ratings up to 1200 v/50 a. for igbts with higher ratings, the hcpl-5150 can be used to drive a discrete power stage, which drives the igbt gate. the products are capable of operation and storage over the full military temperature range and can be purchased as either commercial product, with full mil-prf-38534 class h testing, or from defense supply center columbus (dscc) standard microcircuit drawing (smd) 5962- 04205. all devices are manufactured and tested on a mil-prf-38534 certifed line and are included in the dscc qualifed manufacturers list, qml-38534 for hybrid microcircuits. schematic diagram 1 3 shield 2 4 8 6 7 5 n/c cathode anode n/c v cc v o v o v ee caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
truth table led v cc - v ee v cc - v ee v o positive going (i.e., turn-on) negative going (i.e., turn-off) off 0f-f30fv 0f-f30fv low on 0f-f fv 0f-f9.5fv low on f-f 3.5fv 9.5f-f fv transition on 3.5f-f30fv f-f30fv high a 0.1 m f bypass capacitor must be connected between pins 5 and 8. device marking selection guide lead confguration options avago part number and options commercial hcpl-5 50 mil-prf-38534,fclassfh hcpl-5 5 standardfleadffinish goldfplate solderfdippedf* optionf- 00 buttfcut/goldfplate optionf- 00 gullfwing/solderedf* optionf-300 outline drawing compliance indicator, * date code, suffix (if needed) a hcpl-515x 5962-04205 01hxx 5043 4 country of mfr. avago cage code* avago designator dscc smd* pin one/ esd ident avago p/ n dscc smd* * qualified parts only sgp qyywwz 3.81 (0.150) min. 4.32 (0.170) max. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) note: dimensions in millimeters (inches). smd part number prescriptfforfallfbelow 596- eitherfgoldforfsolder 04050 hpx goldfplate 04050hpc solderfdippedf* 04050 hpa buttfcut/goldfplate 04050 hyc buttfcut/solderedf* 04050 hya gullfwing/solderedf* 04050 hxa * solder contains lead
3 hermetic optocoupler options option description 00 surfacefmountablefhermeticfoptocouplerfwithfleadsftrimmedfforfbuttfjointfassembly.fthisfoptionfisfavailablefonfcommercialfandfhi-relf productf(seefdrawingsfbelowfforfdetails). 00 leadffnishfisfsolderfdippedfratherfthanfgoldfplated.fthisfoptionfisfavailablefonfcommercialfandfhi-relfproduct.fdsccfdrawingfpartf numbersfcontainfprovisionsfforfleadffnish. 300 surfacefmountablefhermeticfoptocouplerfwithfleadsfcutfandfbentfforfgullfwingfassembly.fthisfoptionfisfavailablefonfcommercialfandf hi-relfproductf(seefdrawingsfbelowfforfdetails).fthisfoptionfhasfsolderfdippedfleads. 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 0.51 (0.020) min. 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5 o max. 4.57 (0.180) max. 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches) . * solder contains lead
4 absolute maximum ratings parameter symbol min. max. units note storageftemperature t s -65 +50 c operatingftemperature t a -55 +5 c caseftemperature t c +45 c junctionftemperature t j +50 c leadfsolderftemperature 60fforf0s c averagefinputfcurrent i ffavg 5 ma peakftransientfinputfcurrentf f (<f m sfpulsefwidth,f300fpps) i ffpk .0 a reversefinputfvoltage v r 5 v highfpeakfoutputfcurrent i ohf(peak) 0.6 a lowfpeakfoutputfcurrent i olf(peak) 0.6 a supplyfvoltage (v cc -v ee ) 0 35 v outputfvoltage v of(peak) 0 v cc v inputfpowerfdissipation p e 45 mw outputfpowerfdissipation p o 50 mw 3 totalfpowerfdissipation p t 95 mw 4 notes: 1. no derating required with the typical case-to-ambient thermal resistance. ( q ca =140 c/w) refer to figure 35. 2. maximum pulse width = 10 m s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 0.5 a. see applications section for additional details on limiting i oh peak. 3. derate linearly above 102 c free air temperature at a rate of 6mw/ c with the typical case-to-ambient thermal resistance ( q ca =140 c/w). refer to figure 36. 4. derate linearly above 102 c free air temperature at a rate of 6mw/ c with the typical case-to-ambient thermal resistance ( q ca =140 c/w). refer to figure 35 and 36. recommended operating conditions parameter symbol min. max. units powerfsupplyfvoltage (v cc fCfv ee ) 5 30 volts inputfcurrentf(on) i f(on) 0 8 ma inputfvoltagef(off) v f(off) -3.0 0.8 volts operatingftemperature t a -55 5 c esd classifcation mil-std-883, method 3015 ( d ), class 1
5 electrical specifcations (dc) over recommended operating conditions (t a = -55 to +125 c, i f(on) = 10 to 18 ma, v f(off) = -3.0 to 0.8v, v cc = 15 to 30 v, v ee = ground) unless otherwise specifed. parameter symbol test conditions group a subgroups (13) limits units fig. note min. typ. max. highflevelfoutputfcurrent i oh v o f=f(v cc f-f4fv) ,f,f3 0. 0.4 a ,f3,f7 v o f=f(v cc f-f 5fv) 0.5 lowflevelfoutputfcurrent i ol v o f=f(v ee f+f .5fv) ,f,f3 0. 0.6 a 5,f6,f8 v o f=f(v ee f+f 5fv) 0.5 highflevelfoutputfvoltage v oh i o f=f-00fma ,f,f3 (v cc f-f4) (v cc f-f3) v ,f3,f9 3,f4 lowflevelfoutputfvoltage v ol i o f=f00fma ,f,f3 0.4 .0 v 4,f6,f0 highflevelfsupplyfcurrent i cch outputfopen,f f i f f=f 0ftof8fma ,f,f3 .5 5.0 ma 7,f8 lowflevelfsupplyfcurrent i ccl outputfopen,fv f f =f-3.0ftof+0.8v ,f,f3 .7 5.0 ma thresholdfinputfcurrentf f lowftofhigh i flh i o f=f0fma,f f v o f>f5fv ,f,f3 .6 9.0 ma 9,f5,f thresholdfinputfvoltagef f highftoflow v fhl ,f,f3 0.8 v inputfforwardfvoltage v f i f f=f0fma ,f,f3 . .5 .8 v 6 temperaturefcoefcientf f offforwardfvoltage d v f / d t a i f f=f0fma -.6 mv/ c inputfreversefbreakdownf f voltage bv r i r f=f0f m a ,f,f3 5 v inputfcapacitance c in ff=f fmhz,f v f f=f0fv 80 pf uvlofthreshold v uvlo+ v o f>f5fv,f f i f f=f0fma ,f,f3 .0 .3 3.5 v ,f37 v uvlo- ,f,f3 9.5 0.7 .0 uvlofhysteresis uvlo hys .6 *all typical values at t a = 25 c and v cc - v ee = 30 v, unless otherwise noted.
6 switching specifcations (ac) over recommended operating conditions (t a = -55 to +125 c, i f(on) = 10 to 18 ma, v f(off) = -3.0 to 0.8v, v cc = 15 to 30 v, v ee = ground) unless otherwise specifed. parameter symbol test conditions group a subgroups (13) limits units fig. note min. typ. max. propagationfdelayftime tofhighfoutputflevel t plh rgf=f47f w ,f cgf=f3fnf,f ff=f 0fkhz,f dutyfcyclef=f50% 9,f0,f 0.0 0.30 0.50 m s 0,f,f,f 3,f4,f3 propagationfdelayftime toflowfoutputflevel t phl 9,f0,f 0.0 0.30 0.50 m s pulsefwidthfdistortion pwd 9,f0,f 0.3 m s propagationfdelayfdiferencef betweenfanyftwofparts pdd (t phl f-ft plh ) 9,f0,f -0.35 0.35 m s 33,f34 7 riseftime t r 0. m s 3 fallftime t f 0. m s uvlofturnfonfdelay t uvlofon v o f>f5fv,fi f f=f0fma 0.8 m s uvlofturnfoffdelay t uvlofoff v o f 7 package characteristics over recommended operating conditions (t a = -55 to +125 c) unless otherwise specifed. parameter symbol test conditions group a subgroups (13) limits units fig. note min. typ. max. input-outputfleakagefcurrent i i-o v i-o f=f 500vdcfrhf f65%,f f tf=f5fsec.,ft a f=f5 c .0 m a 5,f6 resistancef(input-output) r i-o v i-o f=f500fvdc 0 0 w 6 capacitancef(input-output) c i-o ff=f fmhz .34 pf 6 *all typicals at t a = 25 c. notes: 1. maximum pulse width = 10 m s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 0.5 a. see applications section for additional details on limiting i oh peak. 2. maximum pulse width = 50 m s, maximum duty cycle = 0.5%. 3. in this test v oh is measured with a dc load current. when driving capacitive loads v oh will approach v cc as i oh approaches zero amps. 4. maximum pulse width = 1 ms, maximum duty cycle = 20%. 5. this is a momentary withstand test, not an operating condition. 6. device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 7. the diference between t phl and t plh between any two hcpl-5150 parts under the same test condition. 8. pins 1 and 4 need to be connected to led common. 9. common mode transient immunity in the high state is the maximum tolerable |dv cm /dt| of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15.0 v). 10. common mode transient immunity in a low state is the maximum tolerable |dv cm /dt| of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v). 11. this load condition approximates the gate load of a 1200 v/25 a igbt. 12. pulse width distortion (pwd) is defned as |t phl -t plh | for any given device. 13. standard parts receive 100% testing at 25 c (subgroups 1 and 9). smd and class h parts receive 100% testing at 25, 125 and -55 c (subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 14. parameters are tested as part of device initial characterization and after design and process changes. parameters are guaranteed to limits specifed for all lots not specifcally tested.
8 -4 -3 -2 -1 0 -60 -30 0 3 0 6 0 9 0 120 150 t a - temperature - o c (v oh -v cc ) - high output voltage drop - v i f = 10 to 18ma i o = 100 ma v cc = 15 to 30v v ee = 0v 0.68 0.70 0.72 0.74 0.76 0.78 0.80 0.82 -100 -50 0 5 0 100 150 t a - temperature - o c i oh - output high current - a i f = 10 to 18ma v o = v cc -4v v cc = 15 to 30v v ee = 0v -4 .5 - 4.0 -3 .5 - 3.0 -2 .5 - 2.0 -1 .5 - 1.0 0 0 .1 0. 2 0 .3 0. 4 0 .5 0. 6 0 .7 i oh - ou tp ut hi gh curre nt - a (v oh -v cc ) - ou tp ut hi gh vo lta ge dr op - v i f = 10 to 18ma v cc =15 to 30v v ee = 0v 1 25 o c 25 o c -5 5 o c figure 1. v oh vs. temperature figure 2. i oh vs. temperature figure 3. v oh vs. i oh figure 4. v ol vs. temperature v f(off ) = -3.0 to 0.8 v i o = 100m a v cc = 15 to 30v v ee = 0v t a - temperature - o c v ol - output low voltage - v -60 -30 0 30 60 90 120 150 0.7 0.6 0.5 0.4 0.2 0.1 0.3 0 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -60 -30 0 3 0 6 0 9 0 120 150 t a - temperature - o c i ol - output low current - a v f(off) = -3.0 to 0.8v v out = 2.5v v cc = 15 to 30v v ee = 0v 0 1 2 3 4 5 6 7 0 0.2 0.4 0.6 0.8 1 i ol - output low current - a v ol - output low voltage - v 125 o c 25 o c -55 o c v f(off) = -3.0 to 0.8v v cc = 15 to 30v v ee = 0v figure 5. i ol vs. temperature figure 6. v ol vs. i ol figure 7. i cc vs. temperature 1.5 2.0 2.5 3.0 3.5 -60 -30 0 3 0 6 0 9 0 120 150 t a - temperature - o c i cc - supply current - ma v cc = 30v v ee = 0v i f = 10ma for i cch i f = 0ma for i ccl i ccl i cch figure 8. i cc vs. v cc figure 9. i flh vs. temperature 1.5 2.0 2.5 3.0 3.5 10 20 30 40 v cc - supply voltage - v i cc - supply current - ma i f = 10ma for i cch i f = 0ma for i ccl t a = 25 o c v ee = 0v i cch i ccl 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -100 -50 0 5 0 100 150 t a - temperature - o c i flh - low to high current threshhold - ma v cc = 15 to 30 v v ee = 0v output = open
9 100 200 300 400 500 15 30 v cc - supply voltage - v t p - propagation delay - ns t plh t phl i f = 10ma, t a = 25?c r g = 47 ? , c g = 3nf, duty cycle = 50% f = 10khz 20 25 100 150 200 250 300 350 400 450 500 5 1 0 1 5 2 0 2 5 i f - forward led current - ma t p - propagation delay - ns t phl t plh v cc = 30v, v ee = 0v t a = 25?c r g = 47 ? , c g = 3nf duty cycle = 50% f =10khz 100 150 200 250 300 350 400 -100 -50 0 5 0 100 150 t a - temperature - o c t p - propagation delay - ns i f(on) = 10ma i f(off) = 0ma v cc = 30v, v ee = 0v r g = 47 ? , c g = 3nf duty cycle = 50% f =10khz t plh t phl figure 10. propagation delay vs. v cc figure 11. propagation delay vs. i f figure 12. propagation delay vs. temperature figure 13. propagation delay vs. rg 100 200 300 400 500 r g - series load resistance - ? t p - propogation delay - ns 50 100 150 200 0 t plh t phl 100 200 300 400 500 0 2 0 4 0 6 0 8 0 100 c g - load capacitance - nf t p - propogation delay - ns t plh t phl v o - output voltage - v 0 0 i f - forward led current - ma 5 25 15 1 30 2 5 20 10 4 3 figure 14. propagation delay vs. cg figure 15. transfer characteristics figure 16. input current vs. forward voltage 1.10 1.20 1.30 1.40 1.50 1.6 0 v f - forward voltage - volts i f - forward current - ma t a = 25 o c 1000 100 10 1 0.1 0.01 0.001
0 figure 17. i oh test circuit 0.1 f v cc = 15 to 30 v 1 3 + 2 4 8 6 7 5 + 4 v i oh i f = 10 to 18 ma _ _ figure 18. i ol test circuit figure 19. v oh test circuit figure 20. v ol test circuit figure 21. i flh test circuit figure 22. u vlo test circuit 0.1 f v cc = 15 to 30 v 1 3 i f = 10 to 18 ma + 2 4 8 6 7 5 100 ma v oh _ 0.1 f v cc = 15 to 30 v 1 3 + 2 4 8 6 7 5 100 ma v ol _ 0.1 f v cc = 15 to 30 v 1 3 i f + 2 4 8 6 7 5 v o > 5 v _ 0.1 f v cc 1 3 i f = 10 ma + 2 4 8 6 7 5 v o > 5 v _ 0.1 f v cc = 15 to 30 v 1 3 + 2 4 8 6 7 5 2.5 v i ol + _ _
figure 23. t plh , t phl , t r , and t f test circuit and waveforms figure 24. cmr test circuit and waveforms 0.1 f v cc = 30 v 1 3 i f v o + + 2 4 8 6 7 5 a + b v cm = 1000 v 5 v v cm ? t 0 v v o switch at b: i f = 0 m a v o switch at a: i f = 10 m a v ol v oh ? t v cm dv dt = _ _ _ 0.1 f v cc = 15 to 30 v 47 ? 1 3 i f = 10 to 18 ma v o + + 2 4 8 6 7 5 10 khz 50% duty cycl e 500 ? 3 n f i f v out t phl t pl h t f t r 10% 50% 90% t r = t f < 10 ns _ _ _
step 2: check the hcpl-5150 power dissipation and increase r g if necessary. the hcpl-5150 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ): applications information eliminating negative igbt gate drive to keep the igbt frmly of, the hcpl-5150 has a very low maximum v ol specifcation of 1.0 v. the hcpl-5150 realizes this very low v ol by using a dmos transistor with 4 w (typical) on resistance in its pull down circuit. when the hcpl-5150 is in the low state, the igbt gate is shorted to the emitter by r g + 4 w . minimizing r g and the lead inductance from the hcpl-5150 to the igbt gate and emitter (possibly by mounting the hcpl-5150 on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applications as shown in figure 25. care should be taken with such a pc board design to avoid routing the igbt collector or emitter traces close to the hcpl-5150 input as this can result in unwanted coupling of transient signals into the hcpl-5150 and degrade performance. (if the igbt drain must be routed near the hcpl-5150 input, then the led should be reverse-biased when in the of state, to prevent the transient signals coupled from the igbt drain from turning on the hcpl-5150.) selecting the gate resistor (r g ) to minimize igbt switch - ing losses. step 1: calculate r g minimum from the i ol peak specifcation. the igbt and r g in figure 26 can be analyzed as a simple rc circuit with a voltage supplied by the hcpl-5150. figure 25. recommended led drive and application circuit + hvdc 3-phase ac - hvdc 0.1 f v cc = 18 v 1 3 + 2 4 8 6 7 5 270 ? control input rg q1 q2 74xxx open collector _ +5 v the v ol value of 2 v in the previous equation is a con - servative value of v ol at the peak current of 0.6 a (see figure 6). at lower r g values the voltage supplied by the hcpl-5150 is not an ideal voltage step. this results in lower peak currents (more margin) than predicted by this analysis. when negative gate drive is not used, v ee in the previous equation is equal to zero volts. (v cc - v ee - v ol ) r g = i olpe ak (v cc C v ee C 1.7 v) = i olpe ak (1 5 v + 5 v C 1.7 v) = 0.6 a = 3 0.5 ? p t = p e + p o p e = i f ? v f ? dut y cycle p o = p o(bias ) + p o (switchi ng ) = i cc ? ( v cc - v ee ) sw (r g , q g ) ? f + e p e = 1 8 ma ? 1.8 v ? 0. 8 = 26 m w p o = 4 .2 5 ma ? 20 v + 2.0 j ? 20 kh z = 85 mw + 40 mw = 125 mw > 112 mw (p o(max) @125 c = 250m w - 23 c ? 6mw/ c) o o o p o(switching max) = p o(max) - p o(bias ) = 112m w C 85 mw = 27 mw p o(switching max) e sw(max) = f 27 mw = = 1.35 j 2 0kh z for the circuit in figure 26 with i f (worst case) = 18 ma, r g = 30.5 w , max duty cycle = 80%, q g = 250 nc, f = 20 khz and t a max = 125 c: the value of 4.25 ma for i cc in the previous equation was obtained by derating the i cc max of 5 ma (which occurs at -55 c) to i cc max at 125 c. since p o for this case is greater than p o(max) , r g must be increased to reduce the hcpl-5150 power dissipation. for q g = 250 nc, from figure 27, a value of e sw = 1.35 m j gives a r g = 90 w
3 figure 26. typical application circuit with negative igbt gate drive p e parameter description i f ledfcurrent v f ledfonfvoltage dutyfcycle maximumfledfdutyfcycle p o parameter description i cc supplyfcurrent v cc positivefsupplyfvoltage v ee negativefsupplyfvoltage e sw f(r g ,fq g ) energyfdissipationfinfthefhcpl-5 50fforfeachfigbtf switchingfcyclef(seeffiguref 7) f switchingffrequency led drive circuit considerations for ultra high cmr perfor - mance. without a detector shield, the dominant cause of opto - coupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 28. the hcpl-5150 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and optocoupler pins 5-8 as shown in figure 29. this capaci - tive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or of ) during common mode transients. for example, the rec - ommended application circuit, (figure 25) can achieve 10 kv/ m s cmr while minimizing component complex - ity. techniques to keep the led in the proper state are discussed in the next two sections. + hvdc 3-phase ac - hvdc 0.1 f v cc = 15 v 1 3 + 2 4 8 6 7 5 rg q1 q2 v ee = -5 v + 270 ? +5 v control input 74xxx open collector _ _ figure 27. energy dissipated in the hcpl-5150 for each igbt switching cycle figure 28. optocoupler input to output capacitance model for unshielded optocouplers figure 29. optocoupler input to output capacitance model for shielded optocouplers esw - energy per switching cycle - j 0 0 rg - gate resistance - ? 100 3 20 7 40 2 60 80 6 qg = 100 n c qg = 250 n c qg = 500 n c 5 4 1 v cc = 19 v v ee = -9 v 1 3 2 4 8 6 7 5 c ledp c ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield c ledo1 c ledo2
4 cmr with the led on (cmr h ). a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. a minimum led current of 10 ma provides adequate margin over the maximum i flh of 7 ma to achieve 10 kv/ m s cmr. cmr with the led of (cmrl). a high cmr led drive circuit must keep the led of (v f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 30, the current fowing through c ledp also fows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) , the led will remain of and no common mode failure will occur. figure 30. equivalent circuit for figure 25 during common mode transient the open collector drive circuit, shown in figure 31, cannot keep the led of during a +dv cm /dt transient, since all the current fowing through c ledn must be supplied by the led, and it is not recommended for appli - cations requiring ultra high cmr l performance. figure 32 is an alternative drive circuit which, like the recommend - ed application circuit (figure 25), does achieve ultra high cmr performance by shunting the led in the of state. figure 31. not recommended open collector drive circuit figure 32. recommended led drive circuit for ultra-high cmr 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v q1 i ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v rg 1 3 v sat 2 4 8 6 7 5 + v cm i ledp c ledp c ledn shield * the arrows indicate the direction of current flow during -dv cm /dt +5 v + v cc = 18 v * * * 0.1 f + _ _ * * * _ ipm dead time and propagation delay specifcations. the hcpl-5150 includes a propagation delay diference (pdd) specifcation intended to help designers minimize dead time in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 25) are of. any overlap in q1 and q2 conduction will result in large currents fowing through the power devices between the high and low voltage motor rail. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn of of led1) so that under worst-case conditions, transistor q1 has just turned of when transistor q2 turns on, as shown in figure 33. the amount of delay necessary to achieve this condition is equal to the maximum value of the propa - gation delay diference specifcation, p ddmax , which is specifed to be 350 ns over the operating temperature range of -55 c to 125 c. delaying the led signal by the maximum propagation delay diference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the diference between the maximum and minimum propagation delay diference specifcations as shown in figure 34. the maximum dead time for the hcpl-5150 is 700 ns (= 350 ns - (-350 ns)) over an operating tempera - ture range of -55 c to 125 c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts.
5 figure 33. minimum led skew for zero dead time figure 34. waveforms for dead time calculations figure 35. input thermal derating curve, dependence of case-to-ambient thermal resistance figure 36. output thermal derating curve, depen - dence of case-to-ambient thermal resistance maximum dead time (due to optocoupler) = (t phl max - t phl min ) + (t plh max - t plh mi n ) = (t phl max - t plh min ) - (t phl mi n - t plh max ) = pdd* max - pdd* min *pdd = propagation delay difference note: for dead time and pdd calculations all propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on t phl max t phl min t plh min t plh max (t phl - t plh ) max ? = pdd* max pdd* max = (t phl - t plh ) max = t phl max - t plh min *pdd = propagation delay difference v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on t phl max t plh min note: for pdd calculations the propagation delays are taken at the same temperature and test conditions. -55 -25 5 3 5 9 5 125 p e - input power - mw 65 t a - ambient temperature - o c 50 30 20 10 0 40 = 70 o c/w = 140 o c/w = 210 o c/w case-to-ambient thermal resistance 0 50 100 150 200 250 300 -55 -25 5 3 5 6 5 9 5 125 p o - output power - m w t a - ambient temperature - o c = 70 o c/w = 140 o c/w = 210 o c/w case-to-ambient thermal resistance
under voltage lockout feature. the hcpl-5150 contains an under voltage lockout (uvlo) feature that is designed to protect the igbt under fault conditions which cause the hcpl-5150 supply voltage (equivalent to the fully-charged igbt gate voltage) to drop below a level necessary to keep the igbt in a low resistance state. when the hcpl-5150 output is in the high state and the supply voltage drops below the hcpl- 5150 v uvloC threshold (9.5 < v uvloC < 12.0) the optocou - pler output will go into the low state with a typical delay, uvlo turn of delay, of 0.6 m s. when the hcpl-5150 output is in the low state and the supply voltage rises above the hcpl-5150 v uvlo+ threshold (11.0 < v uvlo+ < 13.5) the optocoupler output will go into the high state (assuming led is on) with a typical delay, uvlo turn on delay of 0.8 m s. figure 37. under voltage lock out mil-prf-38534 class h and dscc smd test program avago technologies hi-rel optocouplers are in compli - ance with mil-prf-38534 class h. class h devices are also in compliance with dscc drawing 5962-04205. testing consists of 100% screening and quality confor - mance inspection to mil-prf-38534. v o - output voltage - v 0 0 (v cc - v ee ) - supply voltage - v 10 5 14 10 15 2 20 6 8 4 12 (12.3, 10.8) (10.7, 9.2) (10.7, 0.1) (12.3, 0.1) forfproductfinformationfandfafcompleteflistfoffdistributors,fpleasefgoftofourfwebfsite:fffffffff www.avagotech.com avago,favagoftechnologies,fandfthefaflogofareftrademarksfoffavagoftechnologies,flimitedfinfthefunitedfstatesfandfotherfcountries. datafsubjectftofchange.ffcopyrightf?f 006favagoftechnologiesflimited.fallfrightsfreserved.ff 5989-0943enf-fjunef ,f007

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