k6t4008c1b family cmos sram revision 3.0 september 1998 1 document title 512kx8 bit low power cmos static ram revision history the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. revision no. 0 .0 0.1 1.0 2.0 3.0 remark advance preliminary final final final history initial draft revise - changed operating current by reticle revision i cc at write : 35ma ? 45ma i cc1 at read/write : 15/35ma ? 10/45ma finalize - changed operating current i cc1 at write : 45ma ? 40ma i cc 2; 90ma ? 80ma - change test load at 55ns : 100pf ? 50pf revise - change datasheet format revise - industrial product speed bin change:70/100ns ? 55/70ns draft date december 7, 1996 march 6, 1997 october 9, 1997 february 17, 1998 september 8, 1998
k6t4008c1b family cmos sram revision 3.0 september 1998 2 512kx8 bit low power cmos static ram general description the k6t4008c1b families are fabricated by samsung s advanced cmos process technology. the families support various operating temperature ranges and various package types for user flexibility of system design. the family also support low data retention voltage for battery back-up oper- ation with low data retention current. features process technology: tft organization: 512kx8 power supply voltage: 4.5~5.5v low data retention voltage: 2v(min) three state output and ttl compatible package type: 32-dip-600, 32-sop-525 32-tsop2-400f/r pin description pin name function we write enable input cs chip select input oe output enable input a 0 ~a 18 address inputs i/o 1 ~i/o 8 data inputs/outputs vcc power vss ground product family 1. the parameter is measured with 50pf test load. product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) k6t4008c1b-l commercial (0~70 c ) 4.5~5.5v 55 1) /70ns 100 m a 20 m a 80ma 32-dip,32-sop 32-tsop2-f/r k6t4008c1b-b k6t4008c1b-p inderstrial (-40~85 c ) 100 m a 50 m a 32-sop 32-tsop2-f/r k6t4008c1b-f functional block diagram 32-dip 32-sop (forward) 32-tsop2 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-tsop2 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (reverse) a18 a17 a17 a18 samsung electronics co., ltd. reserves the right to change products and specifications without notice. a3 precharge circuit. memory array 1024 rows 512 8 columns i/o circuit column select clk gen. row select a9 a8 a13 a17 a15 a11 a10 a18 a16 a14 a12 a7 a6 a4 i/o 1 data cont data cont i/o 8 a5 a1 a0 a2 cs we oe control logic
k6t4008c1b family cmos sram revision 3.0 september 1998 3 product list commercial temperature products(0~70 c) industrial temperature products(-40~85 c) part name function part name function K6T4008C1B-DL55 k6t4008c1b-db55 k6t4008c1b-dl70 k6t4008c1b-db70 k6t4008c1b-gl55 k6t4008c1b-gb55 k6t4008c1b-gl70 k6t4008c1b-gb70 k6t4008c1b-vb55 k6t4008c1b-vb70 k6t4008c1b-mb55 k6t4008c1b-mb70 32-dip, 55ns, l-pwr 32-dip, 55ns, ll-pwr 32-dip, 70ns, l-pwr 32-dip, 70ns, ll-pwr 32-sop, 55ns, l-pwr 32-sop, 55ns, ll-pwr 32-sop, 70ns, l-pwr 32-sop, 70ns, ll-pwr 32-tsop2-f, 55ns, ll-pwr 32-tsop2-f, 70ns, ll-pwr 32-tsop2-r, 55ns, ll-pwr 32-tsop2-r, 70ns, ll-pwr k6t4008c1b-gp55 k6t4008c1b-gf55 k6t4008c1b-gp70 k6t4008c1b-gf70 k6t4008c1b-vf55 k6t4008c1b-vf70 k6t4008c1b-mf55 k6t4008c1b-mf70 32-sop, 55ns, l-pwr 32-sop, 55ns, ll-pwr 32-sop, 70ns, l-pwr 32-sop, 70ns, ll-pwr 32-tsop2-f, 55ns, ll-pwr 32-tsop2-f, 70ns, ll-pwr 32-tsop2-r, 55ns, ll-pwr 32-tsop2-r, 70ns, ll-pwr functional description 1. x means don t care.( must be in low or high state.) cs oe we i/o pin mode power h x 1) x 1) high-z deselected standby l h h high-z output disbaled active l l h dout read active l x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to 7.0 v - voltage on vcc supply relative to vss v cc -0.5 to 7.0 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c k6t4008c1b-l/-b -40 to 85 c k6t4008c1b-p/-f soldering temperature and time t solder 260 c, 10sec(lead only) - -
k6t4008c1b family cmos sram revision 3.0 september 1998 4 recommended dc operating conditions 1) note: 1. commercial product : t a =0 to 70 c, otherwise specified industrial product : t a =-40 to 85 c, otherwise specified 2. overshoot : v cc +3.0v in case of pulse width 30ns 3. undershoot : -3.0v in case of pulse width 30ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.5 2) v input low voltage v il -0.5 3) - 0.8 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply i cc i io =0ma, cs =v il , v in =v il or v ih , read - 7.5 15 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma cs 0.2v, v in 3 0.2v or v in 3 vcc-0.2v read - 4 10 ma write - 27 40 i cc2 cycle time=min, 100% duty, i io =0ma, cs =v il, v in =v ih or v il - 65 80 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(ttl) i sb cs =v ih , other inputs = v il or v ih - - 3 ma standby current(cmos) i sb1 cs 3 vcc-0.2v, other inputs=0~vcc k6t4008c1b-l - 2 100 m a k6t4008c1b-b - 1 20 m a k6t4008c1b-p - 2 100 m a k6t4008c1b-f - 1 50 m a
k6t4008c1b family cmos sram revision 3.0 september 1998 5 ac characteristics (vcc=4.5~5.5v, k6t4008c1b-c family:t a =0 to 70 c, k6t4008c1b-i family:t a =-40 to 85 c) parameter list symbol speed bins units 55*ns 70ns min max min max read read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select to output t co - 55 - 70 ns output enable to valid output t oe - 25 - 35 ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 20 0 25 ns output disable to high-z output t ohz 0 20 0 25 ns output hold from address change t oh 10 - 10 - ns write write cycle time t wc 55 - 70 - ns chip select to end of write t cw 45 - 60 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 45 - 60 - ns write pulse width t wp 40 - 50 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 20 0 25 ns data to write time overlap t dw 25 - 30 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns c l 1) 1. including scope and jig capacitance ac operating conditions test conditions (test load and test input/output reference) input pulse level : 0.8 to 2.4v input rising and falling time : 5ns input and output reference voltage : 1.5v output load (see right) :c l =100pf+1ttl c l =50pf+1ttl data retention characteristics item symbol test condition min typ max unit vcc for data retention v dr cs 3 vcc-0.2v 2.0 - 5.5 v data retention current i dr vcc=3.0v, cs 3 vcc-0.2v k6t4008c1b-l - - 50 m a k6t4008c1b-b - - 15 k6t4008c1b-p - - 50 k6t4008c1b-f - - 20 data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
k6t4008c1b family cmos sram revision 3.0 september 1998 6 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs address oe data ou t notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. t oh t aa t olz t lz t ohz t hz t rc t oe t co1
k6t4008c1b family cmos sram revision 3.0 september 1998 7 timing waveform of write cycle(1) (we controlled) address cs t cw(2) t wr(4) timing waveform of write cycle(2) ( cs controlled) address cs t wc t wr(4) t as(3) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t dw t dh data valid we data in data out high-z high-z t wc t aw t as(3) t cw(2) t wp(1) t aw notes (write cycle) 1. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low : a write end at the earliest transition among cs going high and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. data retention wave form cs controlled v cc 4.5v 2.2v v dr cs gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr
k6t4008c1b family cmos sram revision 3.0 september 1998 8 package dimensions units: millimeter(inch) 0~15 1.91 #1 32 pin dual inline package (600mil) #32 13.60 0.20 0.535 0.008 41.91 0.20 1.650 0.008 ( ) 0.075 1 5 . 2 4 0 . 6 0 0 + 0.10 max 42.31 1.666 0.25 - 0.05 + 0.004 0.010 - 0.002 2.54 0.100 max 3.81 0.20 0.150 0.008 5.08 0.200 min 0.015 0.38 0.130 0.012 3.30 0.30 #16 #17 1.52 0.10 0.060 0.004 0.46 0.10 0.018 0.004 32 pin plastic small outline package (525mil) 0~8 #32 20.47 0.20 0.806 0.008 max 20.87 0.822 max 2.74 0.20 0.108 0.008 3.00 0.118 min 0.002 0.05 0.004 max 0.10 max #1 0.71 ( ) 0.028 1 3 . 3 4 0 . 5 2 5 11.43 0.20 0.450 0.008 0.80 0.20 0.031 0.008 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 14.12 0.30 0.556 0.012 #17 #16 1.27 0.050 + 0.100 0.41 - 0.050 + 0.004 0.016 - 0.002
k6t4008c1b family cmos sram revision 3.0 september 1998 9 32 pin thin small outline package type ii (400f) 0~8 #32 20.95 0.10 0.825 0.004 max 21.35 0.841 max 1.00 0.10 0.039 0.004 1.20 0.047 min 0.002 0.05 0.004 max 0.10 max #1 0.95 ( ) 0.037 1 0 . 1 6 0 . 4 0 0 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 11.76 0.20 0.463 0.008 #17 #16 0.50 ( ) 0.020 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 1.27 0.050 0.40 0.10 0.016 0.004 package dimensions 32 pin thin small outline package type ii (400r) 0~8 #32 #1 1 0 . 1 6 0 . 4 0 0 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 11.76 0.20 0.463 0.008 #17 #16 0.50 ( ) 0.020 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 20.95 0.10 0.825 0.004 max 21.35 0.841 max 1.00 0.10 0.039 0.004 1.20 0.047 min 0.002 0.05 0.004 max 0.10 max 0.95 ( ) 0.037 1.27 0.050 0.40 0.10 0.016 0.004 units: millimeter(inch)
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