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? no products described or contained herein are intended for use in surgical implants, life support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime prevention equipment, and the like, the failure of which may directly or indirectly cause injury death or property loss. ? anyone purchasing any products described or contained herein for an above-mentioned use shall: ?? accept full responsibility and indemnify sanyo electric co. ltd, its affiliates, subsidiaries, and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use. ?? not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co. ltd, its affiliates, subsidiaries and distributors or any of their officers and employers jointly and severally. ? information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringement of intellectual property rights or other rights of third parties. this catalog provides information as of december 1998. specification and information herein are subject to change without notic e. microcomputer development department, mos-lsi division, sanyo electric co. ltd. 1-1-1 sakata oizumi-machi, ora-gun, gunma, japan ver.1.2 december 7, 1998 i.takahashi 1 / 15 LC680100A 32 bit risc microcontroller 1. overview the LC680100A is a 32 bit microcontroller developed exclusively by sanyo, based on a 32 bit risc cpu and incorporating on a single chip a high speed multiplier, 2kb of cache ram, 2kb data ram, dram control unit, external memory control unit and peripheral it is an ideal control device for digital cameras, color printers and hand held data terminals. 2. features (1) cpu core :32 bit risc (speed: 15mhz, instruction cycle time: 67ns) (2) high speed multiplier :16bit x 16bit (in 1 instruction cycle) (3) instruction cache ram :2kb (512x32bit) (4) data ram :2kb (512x32bit) (5) dram control unit (6) external memory bus control unit (7) i/o port :one 16 bit i/o port, one 8 bit i/o port (8) uart :two full duplex asynchronous channels (one channel has 16bit fifo) (9) serial i/o :one three-wire synchronous clock, 8 bit (10) timer :4 channels (tm0 = 16bit + 16bit) (tm1, tm2, tm3 = 8bit + 8bit) (11) pwm output :three 8 bit resolution outputs (common with tm1, tm2, tm3) (12) interrupt controller :13 source events (5 internal, 8 external), 5 vectored (13) osc circuit :two types: main and rc. vco/pll is built-in, frequency multiplication possible. (14) standby :standby (hold) and sleep (halt) modes available (15) vdd :3.3v typ. 3. package and pins sqfp100, 100 pins 4. development tools a c compiler, assembler and emulator are available to be run on a pc.
LC680100A 2 / 15 ver.1.2 5. system block diagram 32bit risc core special function register sfr bus control dram control data ram 2k bytes instruction cache 2k bytes interrupt enable control coprocessor (multiplier) mode control reset control rc osc multiplier circuit main osc system clock, standby control interrupt control timer 0 timer 1 timer 2 timer 3 sio0 uart0 uart1 port 0 port 1 instruction cache control bus control sio0 uart0 uart1 tm0h tm0l tm1h tm2h tm3h figure 1 LC680100A system block diagram
LC680100A ver.1.2 3 / 15 6. terminal assignment diagram (sqfp100, 0.5mm pitch) ? ? y t ? ?????????y?t????? y t ? ? ? y t ? ? ?? ? ?? ? ?y ?t ?? ? ? t y ? ? y ? yt yy y y? y y t y y? y? t t? t t t? ?? ? ? ?? ? t? tt ty t ? ? ? ?? ?t ?y ? ? ? t y
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LC680100A 4 / 15 ver.1.2 7. terminal functions note: pu = pull-up pin number pin name i/o function description pin format 1,6,15,34,55 ,82 vdd - power supply +ve - 4,9,24,43,73 ,91 vss - power supply -ve - 2 ck1 i input to main oscillator schmitt input 3 ck2 o output from main oscillator cmos output 5 cmp i/o phase comparator filter pin (multiplier circuit). schmitt inputtristate output 7 ckot o ck1 or half frequency clock output from multiplier cmos output 8 ckin i external clock input schmitt input 10 phiot o system clock output cmos output 11 holdi i hold request input schmitt input 12 reset i reset terminal schmitt input 13 mode i bus mode setting at reset schmitt input 14 test i test input (normally connected to vss) schmitt input 16 p00/txd0 i/o port0 bit0 i/o. also uart0 send 17 p01/rxd0 i/o port0 bit1 i/o. also uart0 receive 18 p02/sdo i/o port0 bit2 i/o. also sio0 data out 19 p03/sdi i/o port0 bit3 i/o. also sio0 data in 20 p04/ sck i/o port0 bit4 i/o. also sio0 clock 21 p05/pwm0 i/o port0 bit5 i/o. also pwm0 output 22 p06/pwm1 i/o port0 bit6 i/o. also pwm1 output 23 p07/t0in/int0 i/o port0 bit7 i/o. timer0 event input int0 input 25 p08/int1 i/o port0 bit8 i/o. int1 input 26 p09/int2 i/o port0 bit9 i/o. int2 input 27 p0a/int3 i/o port0 bit10 i/o. int3 input 28 p0b/pwm2 i/o port0 bit11 i/o. pwm2 output 29 p0c/txd1 i/o port0 bit12 i/o. uart1 send 30 p0d/rxd1 i/o port0 bit13 i/o. uart1 receive 31 p0e i/o port0 bit14 i/o. 32 p0f i/o port0 bit15 i/o. used as input: schmitt input; presence of pu resistor software selectable. used as output: cmos/n-ch od mode software selectable.
LC680100A ver.1.2 5 / 15 pin number pin name i/o function description pin format 33 nmi i nmi interrupt schmitt input 35 p10/ bgnt i/o port1 bit0 input. also bus grant output. 36 p11/ ras i/o port1 bit1 input. also dram control ras signal out. 37 p12/ casu i/o port1 bit2 input. also dram control casu signal out. 38 p13/ casl i/o port1 bit3 input. also dram control casl signal out. 39 p14/ dmxs i/o port1 bit4 input. also dram control dmxs signal out. schmitt inputtristate output 40 p15/ rfreq i/o port1 bit5 input. also dram control rfreq i/o. schmitt inputpu output 41 p16/ irqot i/o port1 bit6 input. also irqot output. 42 p17/mclk/ hold0 i/o port1 bit7 input. mclk output, hold state output schmitt inputtristate output 44 a0/ lbs i/o bus address bit0 or lower byte strobe signal. 45 to 54, 56 to 69 a1to a24 i/o bus address bit1 to 24. 70 a25/ cs5 i/o bus address bit25 or cs5. 71 a26/ cs4 i/o bus address bit26 or cs4 72 a27/ cs3 i/o bus address bit27 or cs3. schmitt inputtristate output 74 to 81, 83 to 90 d0 to d15 i/o bus data bit0 to 15 schmitt inputtristate output 92 cs0 i/o cs0 93 cs1 i/o cs1 94 cs2 i/o cs2 95 cs6 i/o cs6 schmitt inputtristate output 96 rd i/o bus read signal. 97 wru / ubs i/o upper byte write signal or upper byte strobe. 98 wrl / wr i/o upper byte write signal or write. schmitt inputtristate output 99 wait i/o bus cycle wait schmitt inputpu output 100 breq i bus request. schmitt input
LC680100A 6 / 15 ver.1.2 8. absolute maximum ratings/ ta = 25c, vss = 0v limits parameter symbol pins conditions unit supply voltage vddmax vdd note1 -0.3 to +4.6 v input voltage vi(1) pins for each input only -0.3 to vdd+0.3 v output voltage vo(1) pins for each output only -0.3 to vdd+0.3 v input/output voltage vio(1) pins for both input and output -0.3 to vdd+0.3 v high level peak output current ioph(1) each output pin current at each pin -5 ma ioah(1) p00 to p08 total of 9 pins -80 ma high level total output current ioah(2) p09 to p0f total of 7 pins -80 ma low level peak output current iopl(1) each output pin current at each pin 20 ma ioal(1) p00 to p07 total of 8 pins 80 ma low level total output current ioal(2) p08 to p0f total of 8 pins 80 ma maximum power consumption pdmax sqfp100 note2 ta = -20 to 70c 440 mw operating temperature range topg -20 to +70 c storage temperature range tstg -55 to +125 c note1:all vdd terminals (pin1, 6, 15, 34, 55, 82) should be connected externally. all vss terminals (pin4, 9, 24, 43, 73, 91) should be connected externally. note2:reflow method is recommended when soldering the sqfp package.
LC680100A ver.1.2 7 / 15 9. recommended operating range / ta = -20 to 70c, vss = 0v limits parameter symbol pins conditions min. typ. max. unit operating supply voltage range vdd (1) vdd 3.0 3.3 3.6 v supply voltage (memory hold) vhd vdd keep ram and register data in standby mode. 2.5 3.6 v vih(1) input pins except ck1 0.7vdd vdd high level input voltage vih(2) ck1 0.7vdd vdd v vil(1) input pins except ck1 vss 0.3vdd low level input voltage vil(2) ck1 vss 0.3vdd v tcyc(1) ckin 300k to 15mhz 66 3333 operation cycle time tcyc(2) ck1 400k to 15mhz (vco is not used.) 132 5000 ns fexckin ckin figure 1 300k 15m external system clock frequency fexck1 ck1 figure 1 400k 15m hz tckinl tckinh ckin figure 1 28 external clock pulse width tck1l tck1h ck1 figure 1 28 ns external clock rising and falling time texr texf ckin, ck1 figure 1 5 ns operation frequency range fck1 ck1, ck2 figure 2, table 1 400k 8m hz
LC680100A 8 / 15 ver.1.2 10. electrical characteristics / ta = -20 to 70c, vss = 0v, vdd = 3.0 to 3.6v limits parameter symbol pins conditions min. typ. max. unit iih(1) pins for each input only vin = vdd 5 high level input current iih(2) pins for both input and output vin = vdd output disabled 5 a iil(1) pins for each input only vin = vss -5 iil(2) p15/ rfreq , wait vin = vss output disabled -5 low level input current iil(3) input/output commonly terminals except written above vin = vss output disabled -5 a voh(1) port0 with pu option, p15/ rfreq ioh = -0.05ma vdd-0.5 high level output voltage voh(2) input/output commonly terminals except written above, ckot, phiot ioh = -1ma vdd-0.5 v vol(1) pins for each output only iol = 4ma 0.4 low level output voltage vol(2) pins for both input and output iol = 4ma 0.4 v pu resistor rpu port0 with pu option, p15/ rfreq 1k 20k ? hysterisis voltage vhis each input only, i/o terminal 0.1 vdd nmi 2 external interrupt pulse width tintl tinth int0 to int3 figure 4 4 tcyc reset input pulse width tresl reset figure 4 2 ms vco frequency fvco ckot figure 5 4m 16m hz vco lock-up time tlock cmp,ckot figure 5, ccmp = 0.1f 10 ms rc oscillation frequency frc built-in rc oscillation circuit 300k 1m hz ceramic oscillation stabilizing time tcf ck1,ck2 figure 3 10 ms current consumption in run mode iddrun vdd ckin=15mhz 60 120 ma current consumption in sleep mode iddslp vdd 50 100 ma current consumption in standby mode iddsty vdd 10 200 a pin capacitance cp all pins 10 pf
LC680100A ver.1.2 9 / 15 11. serial input/output characteristics / ta = -20 to 70c, vss = 0v, vdd = 3.0 to 3.6v, with the load in figure 14 limits parameter symbol pins conditions min. typ. max. unit input clock cycle time tsck sck input figure 6 16 tcyc input clock l pulse width tsckl sck input figure 6 533 ns input clock h pulse width tsckh sck input figure 6 533 ns output clock cycle time tscko sck output figure 6 16 tcyc output clock l pulse width tsckol sck output figure 6 8 tcyc output clock h pulse width tsckoh sck output figure 6 8 tcyc input data set up time tsdi sck , sdi figure 6 200 ns input data hold time thdi sck , sdi figure 6 50 ns output delay time tddo sck , sdo figure 6 100 130 ns
LC680100A 10 / 15 ver.1.2 12. bus timing / ta = -20 to 70c, vss = 0v, vdd = 3.0 to 3.6v, with the load in figure14 limits parameter symbol pins conditio ns min. typ. max. unit address output delay time taad a27 to a0 figure 7, figure 8 75 address output hold time tada a27 to a0 figure 7, figure 8 75 cs delay time (1) tacs csn figure 7, figure 8 45 cs hold time (1) tcsa csn figure 7, figure 8 55 ns rd delay time (1) tard rd figure 7 45 rd hold time (1) trda rd figure 7 55 read data set up time (1) tsrd1 d15 to d0 figure 7 30 read data hold time (1) thrd1 d15 to d0, figure 7 0 ns wr delay time (1) tawr wru , wrl figure 8 45 wr hold time (1) twra wru , wrl , figure 8 55 write data delay time (1) tdwd1 d15 to d0, wru , wrl figure 8 70 write data hold time (1) thwd1 d15 to d0, wru , wrl figure 8 0 30 ns bus request input setup time tsbrq ckin, breq figure 12 30 bus request input hold time thbrq ckin, breq figure 12 30 bgnt output delay time tdbgt ckin, bgnt figure 12 50 bus release delay time tdbof ckin, a27 to a0, rd , wru , wrl figure 12 50 wait set up time tswait ckin, wait 30 wait input hold time thwait ckin, wait 30 ns
LC680100A ver.1.2 11 / 15 13. dram timing / ta = -20 to 70c, vss = 0v, vdd = 3.0 to 3.6v, with the load in figure 14 limits parameter symbol pins conditions min. typ. max. unit address (row) delay time tarow a27 to a0 figure 9, figure 10 75 address (col) delay time tacol a27 to a0 figure 9, figure 10 55 address (col) hold time tcola a27 to a0 figure 9, figure 10 70 ras delay time taras ras figure 9, figure 10 65 ras hold time trasa ras figure 9, figure 10 50 dmxs delay time tdmxsr dmxs figure 9, figure 10 70 dmxs hold time tdmxsc dmxs figure 9, figure 10 50 caslcasu delay time tacas(l/u) casu , casl figure 9, figure 10 65 caslcasu hold time tcas(l/u)a casu , casl figure 9, figure 10 50 ns read data set up time (2) tsrd2 d15 to d0 figure 9 30 read data hold time (2) thrd2 d15 to d0, rd figure 9 0 ns wrlwru delay time tawr(l/u) wru , wrl figure 10 45 wrlwru hold time twr(l/u)a wru , wrl figure 10 50 write data delay time (2) tdwd2 d15 to d0, wru , wrl figure 10 70 write data hold time (2) thwd2 d15 to d0, wru , wrl figure 10 0 ns table 1. guaranteed value for the ceramic oscillators oscillator manufacturer oscillator c1 c2 4mhz (external capacitor) csa4. oomg 33pf 33pf 4mhz (capacitor built-in) cst4. oomgw (30pf) (30pf) 8mhz (external capacitor) csa8. oomtz 33pf 33pf 8mhz (capacitor built-in) murata cst8. oomtw (30pf) (30pf)
LC680100A 12 / 15 ver.1.2 vco 1/2 vcosw 0.5vdd 0.8vdd 0.2vdd cmp ckot ck1 ck2 c2 c1 vdd ck2 ck2 ckin ck1 ccmp tintl tresl tinth tcf 1/fexck1 or 1/fexckin tckinl or tck1l tckinh or tck1h external input external input fi g ure2 ceramic oscillation fi g ure3 oscillation stabilizin g time ;()030a,+?6:*033(;065 figure5 vco vdd lowest limit oscillator figure4 external pulse input phase compare fi g ure1 external clock input 0.5vdd tsckl or tsckol tsckh or tsckoh tsck or tscko thdi tsdi tddo sdi sdo sck 0.5vdd 0.5vdd 0.<9,y?,90(3?57<;?<;7<;?0405.
LC680100A ver.1.2 13 / 15 c c c( c( c' c' # ?? ?? ?? ?? ?? (= ' ?? cb' 8= c7' 0.<9,t??;,95(3? <:?,(+?0405. ?++0;065(3?>(0;?:;(;,?5? 3(.e ?;6? ?;6? ?0405.?4,(:<9,?7605;???e figure8 external bus write timing ? additional ?>(0;?:;(;,?5? 3(.e d15 to d0 a27 to a0 (timing measure point=2v/0.8v) ckin tada taad 2v 0.8v tcsa 0.8v 0.8v 2v 2v 0.8v 0.8v 2v tacs wru wrl csn tawr twra tawr twra dout 2v 0.8v thwd1 tdwd1
LC680100A 14 / 15 ver.1.2 ) ), ), ) # "-( '(( 8= '$, $!*"# ?? ?? c"-(' c'( c'( cb' c$! c(! c(* c(! c(* c"-( c'$, c$! c7' ?? ?? ?? ?? ?? ?? ?? '( (! (* ,'*|,'! 0.<9,??,(+?0405. ?0405.?4,(:<9,?7605;???e ?694(3?(**,::?46+,?;
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LC680100A ver.1.2 15 / 15 # ;: ;+ ;+ ;/ 0.<9,??? ?57<;?<;7<;?0405. ?<;7<; ?57<; ?0405.?4,(:<9,?7605;?e ) ) - # - '(( ,'*|,'! ;: ;+ ;+ ;+ ;+ ;/ 0.<9,?? <:?,8<,:;?,3,(:,?0405. ?0405.?4,(:<9,?7605;?e ?57<; ?<;7<; <;7<;? ?<;7<; # ;: ;/ 0.<9,??(0;?57<;?<;7<;?0405. ?0405.?4,(:<9,?7605;?e ?57<;
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