View 5962R0420102QYA_6644589.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features ? >400.0 mbps (200 mhz) switching rates ? + 340mv differential signaling ? 3.3 v power supply ? ttl compatible outputs ? cold spare all pins ? nominal 100 integrated termination resistor ? 3.3ns maximum propagation delay ? 0.35ns maximum differential skew ? operational; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 300 krad(si) and 1mrad(si) - latchup immune (let > 100 mev-cm 2 /mg) ? packaging options: - 16-lead flatpack (dual in-line) ? standard microcircuit drawing 5962-04201 - qml q and v compliant part ? compatible with ieee 1596.3sci lvds ? compatible with ansi/tia/eia 644-1996 lvds standard introduction the ut54lvds032lvt with internal 100 integrated termination resistor quad receiver is a quad cmos differential line receiver desi gned for applications requiring ultra low power dissipation and high data rates. the device is designed to support data rates in excess of 400.0 mbps (200 mhz) utilizing low voltage differential signaling (lvds) technology. the ut54lvds032lvt accepts low voltage (340mv) differential input signals and tr anslates them to 3v ttl output levels. the receiver supports a th ree-state function that may be used to multiplex outputs. th e receiver also supports open, shorted and terminated (100 ) input fail-safe. receiver output will be high for all fail-safe conditions. all pins have cold spare buffers. these buffers will be high impedance when v dd is tied to v ss . an integrated termination resistor will reduce component count and save board space. + r1 - r in1+ r in1- r in2+ r in2- r in3+ r in3- r in4+ r in4- r out1 r out2 r out4 r out3 en en + r2 - + r3 - + r4 - standard products ut54lvds032lvt low voltage quad receiver with integrated termination resistor data sheet december, 2008 www.aeroflex.com/lvds figure 1. ut54lvds032lv qu ad receiver block diagram
2 truth table pin description applications information the ut54lvds032lvt receiver?s intended use is primarily in an uncomplicated point-to-point configuration as is shown in figure 3. this configuration provides a clean signaling environment for quick edge rates of the drivers. the receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply pcb traces. typically, the charact eristic impedance of the media is in the range of 100 . an integrated termination resistor of 100 is used to match the media. the termination resistor converts the current sourced by th e driver into voltages that are detected by the receiver. other co nfigurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account. the ut54lvds032lvt differential line receiver is capable of detecting signals as low as 100mv, over a + 1v common-mode range centered around +1.2v. this is related to the driver offset voltage which is typically +1.2v. the driven signal is centered around this voltage and may shift + 1v around this center point. the + 1v shifting may be the result of a ground potential difference between the driver ?s ground reference and the receiver?s ground reference, the common-mode effects of coupled noise or a combination of the two. both receiver input pins should honor their specified operating input voltage range of 0v to +2.4v (measured from each pin to ground). the integrated termination resistor is a nominal 100 when v dd is 3.0 to 3.6v. in cold spare mode, the integrated termination resistor is 140 . enables input output en en r in+ - r in - r out l h x z all other combinations of enable inputs v id > 0.1v h v id < -0.1v l full fail-safe open/short or terminated h pin no. name description 2, 6, 10, 14 r in+ non-inverting receiver input pin 1, 7, 9, 15 r in- inverting receiver input pin 3, 5, 11, 13 r out receiver output pin 4 en active high enable pin, or-ed with en 12 en active low enable pin, or-ed with en 16 v dd power supply pin, +3.3 + 0.3v 8v ss ground pin figure 2. ut54lvds032lvt pinout ut54lvds032lv receiver 16 15 14 13 12 11 10 9 v dd r in4- r in4+ r out4 en r out3 r in3+ r in3- 1 r in1- 2 r in1+ 3 r out1 4 en 5 r out2 6 r in2+ 7 r in2- 8 v ss enable data input 1/4 ut54lvds031lv 1/4 ut54lvds032lv + - data output figure 3. point-to-point application rt 100
receiver fail-safe the ut54lvds032lvt receiver is a high gain, high speed device that amplifies a small differential signal (20mv) to ttl logic levels. due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. the receiver?s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of high output voltage) for floating, terminated or shorted receiver inputs. 1. open input pins . the ut54lvds032lvt is a quad receiver device, and if an a pplication requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left open. do not ti e unused receiver inputs to ground or any other voltages. the input is biased by internal high value pull up and pull down resistors to set the output to a high stat e. this internal circuitry will guarantee a high, stab le output state for open inputs. 2. terminated input . if the driver is disconnected (cable unplugged), or if the driver is in a three-state or power-off condition, the receiver output will again be in a high state, even with the end of cable 100 integrated termination resistor across the input pins. the unplugged cable can become a floating antenna which can pick up noise. if the cable picks up more than 10mv of differential noise, the receiver may see the noise as a valid signal and switch. to insure that any noise is seen as common-mode and not differential, a balanced in terconnect should be used. twisted pair cable offers better balance than flat ribbon cable. 3. shorted inputs . if a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0v differential input voltage, the receiver output remains in a high state. shorte d input fail-safe is not supported across the common-mode range of the device (v ss to 2.4v). it is only supported with inputs shorted and no external common-mode voltage applied. 3
4 operational environment notes: 1. guarnteed but not tested. absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this sp ecification is not recommended. exposure to absolute maximum rating conditions for extended periods may aff ect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and life test. 3. test per mil-std-883, method 1012. recommended operating conditions parameter limit units total ionizing dose (tid) 1.0e6 rad(si) single event latchup (sel) >100 mev-cm 2 /mg neutron fluence 1 1.0e13 n/cm 2 symbol parameter limits v dd dc supply voltage -0.3 to 4.0v v i/o voltage on any pin during operation -0.3 to (v dd + 0.3v) voltage on any pin during cold spare -.3 to 4.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.25 w t j maximum junction temperature 2 +150 c jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6v t c case temperature range -55 to +125 c v in dc input voltage, receiver inputs dc input voltage, logic inputs 2.4v 0 to v dd for en, en
5 dc electrical characteristics * 1 (v dd = 3.3v + 0.3v; -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered notes: * for devices procured with a total ionizi ng dose tolerance guarantee, the post-irra diation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. current into device pins is defined as positive. current out of device pins is defined as ne gative. all voltages are referen ced to ground. 2. output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction on ly. only one output should be shorted at a time, for a maxim um duration of one second. 3. guaranteed by characterization. 4. tested functionally. symbol parameter condition min max unit v ih high-level input voltage (ttl) 2.0 v v il low-level input voltage (ttl) 0.8 v v ol low-level output voltage i ol = 2ma, v dd = 3.0v 0.25 v v oh high-level output voltage i oh = -0.4ma, v dd = 3.0v 2.7 v i in logic input leakage current enables = en/en = 3.6v, v dd = 3.6 -10 +10 a i i receiver input current v in = 2.4v, v dd = 3.6v -15 +15 ? i cs cold spare leakage current v in =3.6v, v dd =v ss -20 +20 ? v th 4 differential input high threshold v cm = +1.2v +100 mv v tl 4 differential input low threshold v cm = +1.2v -100 mv v cmr 4 common mode voltage range v id = 200mv peak to peak 0.1 2.3 v i oz output three-state current disabled, v out = 0 v or v dd -10 +10 ? v cl input clamp voltage i cl = +18ma -1.5 v i os 2, 3 output short circuit current enabled, v out = 0 v 2 -15 -130 ma i cc supply current, receivers enabled en, en = v dd or v ss inputs open 15 ma i ccz supply current, receivers disabled en = v ss , en = v dd inputs open 4 ma r term termination resistor v dd = 3.0v to 3.6v 83 114 v dd = 0.0v 125 154
6 ac switching characteristics* 1, 2, 3 (v dd = +3.3v + 0.3v, t c = -55 c to +125 c); unless otherwise noted, tc is per the temperature range ordered notes: * for devices procured with a total ionizi ng dose tolerance guarantee, the post-irra diation performance is guaranteed at 25 o c per mil-std-883 me thod 1019, condition a up to the maximum tid level procured. 1. channel-to-channel skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs. 2. generator waveform for all tests un less otherwise specified: f = 1 mhz, z 0 = 50 , t r and t f (0% - 100%) < 1ns for r in and t r and t f < 1ns for en or en . 3. c l includes probe and jig capacitance. 4. guaranteed by characterization. 5. chip to chip skew is defined as th e difference between the minimu m and maximum specified differential propagation delays. symbol parameter min max unit t phld 6 differential propagation delay high to low (figures 4 and 5) 1.8 3.3 ns t plhd 6 differential propagation delay low to high (figures 4 and 5) 1.8 3.3 ns t skd differential skew (t phld - t plhd ) (figures 4 and 5) 0 0.35 ns t sk1 channel-to-channel skew 1 (figures 4 and 5) 00.5ns t sk2 chip-to-chip skew 5 (figures 4 and 5) 3.0 ns t tlh rise time (figures 4 and 5) 1.2 ns t thl fall time (figures 4 and 5) 1.2 ns t phz disable time high to z (figures 6 and 7) 12 ns t plz disable time low to z (figures 6 and 7) 12 ns t pzh enable time z to high (figures 6 and 7) 12 ns t pzl enable time z to low (figures 6 and 7) 12 ns
7 r r in+ r out receiver enabled generator 50 figure 4. receiver propagation delay and transiti on time test circuit or equivalent circuit r in- 50 40pf 50 v dd/2 r in- r in+ r out t phld v ol v oh +1.1v 50% +1.2v t thl 20% 80% 50% 20% 80% t tlh 0v differential figure 5. receiver propagation delay and transition time waveforms t plhd v id = 200mv +1.3v
8 figure 6. receiver three-state delay te st circuit or equivalent circuit r in+ r in- en v dd 100 100 40pf en when en = v dd en when en = v ss output when v id = -100mv output when v id = +100mv t phz t pzh 0.5v 50% v oh v oz v oz 0v v dd 0v v dd 1.5v 1.5v 1.5v 1.5v 0.5v t pzl t plz figure 7. receiver three- state delay waveform 50% v ol
9 notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance to mil-prf-38535. 4. package dimensions and symbols are similar to mil-std-1835 variation f-5a. 5. lead position and copl anarity are not measured. 6. id mark symbol is vendor option. 7. with solder, increase maximum by 0.003. figure 8. 16-pin ceramic flatpack packaging
10 ordering information ut54lvds032lvt quad receiver: ut 54lvds032lvt - * * * * * device type: ut54lvds032lvt lvds access time: not applicable package type: (u) = 16-lead flatpack (dual-in-line) screening: (c) = hirel temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, th en the part marking will match the lead fini sh and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex manuf acturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. hirel temperature range flow per aeroflex manuf acturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
11 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs (aeroflex) reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. ut54lvds032lvt quad receiver: smd 5962 - ** * federal stock class designator: no options total dose (r) = 1e5 rad(si) (f) = 3e5 rad(si) (g) = 5e5 rad(si) (h) = 1e6 rad(si) drawing number: 04201 device type 01 = lvds receiver, 300k , 500k and 1m rad(si) 02 = lvds receiver, 100k rad(si) class designator: (q) = qml class q (v) = qml class v case outline: (y) = 16 lead flatpack (dual-in-line) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) ** 04201 notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.

▲Up To Search▲

Price & Availability of 5962R0420102QYA

	To Download 5962R0420102QYA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .