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motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. document number 9S12XDP512DGV2/d 1 mc9s12xdp512 device user guide v02.05 covers mc9s12xd-family & mc9s12xa-family original release date: june 2nd, 2003 revised: november 18th 2004 motorola, inc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. document number 9S12XDP512DGV2/d 2 revision history version number revision date effective date author description of changes v02.00 21 may 2004 ? 32k sram ? changed cop configuration table 15-1table 15-2 ? added xgate address mapping figure 1-3 ? added access source signals acc[2:0] ? added reduced threshold for ewait pin ? changed register map table 1-1 ? updated detailed register map v02.01 8 jun 2004 ? removed etea bit from dbgsr register ? direct register moved to address $0011 ? added mode description to section 4.1 overview v02.02 9 jul 2004 ? system stop/wait description ? updated detailed register map ? added spec change summary v02.03 27 jul 2004 ? updated spec change summary v02.04 13 oct 2004 ? added thermal package characteristics table a-5 ? updated appendix b spi electrical specifications ? added b.2 external bus timing and b.2 external tag trigger timing v02.05 18 nov 2004 ? added oscillator and pll electrical characteristics to table a-18 and table a-19 ? added table 0-1 derivative differences ? added section 1.5.2 memory map differences mc9s12xdp512 vs mc9s12xdt512/dt384 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 5 derivative differences table 0-1 shows the mc9s12xd-family members table 0-1 mc9s12xd-family members 1 notes : 1. all devices will be available in m, v and c temperature options device package flash ram eeprom xgate can sci spi iic a/d 2 2. a/d is the number of modules/total number of a/d channels. pwm i/o 3 3. i/o is the sum of ports capable to act as digital input or output. 9s12xdp512 4 4. pc9s12xdp512mfve and pc9s12xdp512mpve samples are available to order. please contact local sales office. all other derivate parts and temperature variations will be available following mc qualification (q205). 144lqfp 512k 32k 4k yes 5632 2/24 8 119 112lqfp 5431 2/16 8 91 9s12xdt512 5 5. pc9s12xdt512mfue samples are available to order. please contact local sales office. all other derivate parts and temperature variations will be available following mc qualification in (q205). 144lqfp 20k 3631 2/24 8 119 112lqfp 3431 2/16 8 91 80qfp 32211/8759 9s12xdt384 144lqfp 384k 20k 3331 2/24 8 119 112lqfp 3331 2/16 8 91 80qfp 33311/8759 9s12xdt256 144lqfp 256k 16k 3331 2/24 8 119 112lqfp 3331 2/16 8 91 80qfp 33311/8759 9s12xd256 144lqfp 14k 1221 2/24 8 119 112lqfp 1221 2/16 8 91 80qfp 12211/8759 9s12xdg128 112lqfp 128k 10k 2k 2221 2/16 8 91 80qfp 22211/8759 9s12xd128 112lqfp 8k 1221 2/16 8 91 80qfp 12211/8759 9s12xd64 80qfp 64k 4k 1k 12211/8759 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 6 table 0-2 mc9s12xa-family members pin out explanations: ? 144 pin packages C port a = 8, b = 8, c=8, d=8 ,e=6+2 input only, h = 8 ,j=7,k=8,m=8,p=8,s=8,t= 8, pad = 24 C 25 inputs provide interrupt capability (h =8, p= 8, j = 7, irq, xirq) ? 112 pin packages C port a = 8, b = 8, e = 6 + 2 input only, h = 8, j = 4, k = 7, m = 8, p = 8 ,s=8,t=8,pad=16 C 22 inputs provide interrupt capability (h =8, p= 8, j = 4, irq, xirq) ? 80 pin packages C port a = 8, b = 8, e = 6 + 2 input only, j = 2, m = 6, p = 7, s = 4, t = 8, pad = 8 C 11 inputs provide interrupt capability (p= 7, j = 2, irq, xirq) ? can0 can be routed under software control from pm1:0 to pins pm3:2 or pm5:4 or pj7:6. ? can4 pins are shared between iic0 pins. ? can4 can be routed under software control from pj7:6 to pins pm5:4 or pm7:6. ? versions with 5 can modules will have can0, can1, can2, can3 and can4 ? versions with 4 can modules will have can0, can1, can2 and can4. ? versions with 3 can modules will have can0, can1 and can4. ? versions with 2 spi modules will have spi0 and spi1. ? versions with 3 sci modules will have sci0, sci1 and sci2. ? versions with 4 sci modules will have sci0, sci1, sci2 and sci4. device package flash ram eeprom xgate sci spi iic a/d 1 notes : 1. a/d is the number of modules/total number of a/d channels. pwm i/o 2 2. i/o is the sum of ports capable to act as digital input or output. 9s12xa512 3 3. mc9s12xa512 samples will be available following mc qualification (q205), temperature option c and v 144lqfp 512k 32k 4k yes 6 3 2 2/24 8 119 112lqfp 4 3 1 2/16 8 91 80qfp 2 2 1 1/8 7 59 9s12xa256 4 4. mc9s12xa256 samples will be available following mc qualification (q205), temperature option c and v 144lqfp 256k 16k 4 3 1 2/24 8 119 112lqfp 4 3 1 2/16 8 91 80qfp 2 2 1 1/8 7 59 9s12xa128 5 5. mc9s12xa128 samples will be available following mc qualification (q205), temperature option c and v 112lqfp 128k 10k 2k 3 3 1 2/16 8 91 80qfp 2 2 1 1/8 7 59 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 7 ? versions with 1 iic module will have iic0. ? spi0 can be routed to either ports ps7:4 or pm5:2. ? spi1 pins are shared with pwm3:0; in 144 and 112 pin versions spi1 can be routed under software control to ph3:0. ? spi2 pins are shared with pwm7:4; in 144 and 112 pin versions spi2 can be routed under software control to ph7:4. in 80 pin packages ss-signal of spi2 is not bonded out! f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 8 ordering information the following figure provides an ordering number example for the mc9s12xd-family devices. figure 0-1 order part number example mc9s12x dp512 c fu package option temperature option device title controller family temperature options c = -40?c to 85?c v = -40?c to 105?c m = -40?c to 125?c package options fu = 80 qfp pv = 112 lqfp fv = 144 lqfp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 9 document references the device guide provides information about the mc9s12xdp512 device made up of standard hcs12 blocks and the s12x processor core this document is part of the customer documentation. a complete set of device manuals includes all the individual block guides of the implemented modules. in an effort to reduce redundancy all module specific information is located only in the respective block guide. if applicable, special implementation details of the module are given in the block description sections of this document.see table 0-3 for names and versions of the referenced documents throughout the device user guide. table 0-3 document references 1 user guide version document order number s12xcpu reference manual v01 s12xcpuv1/d external bus interface (s12x_ebi) block guide v02 s12xebiv2/d module mapping control (s12x_mmc) block guide v02 s12xmmcv2/d interrupt (s12x_int) block guide v01 s12xintv1/d background debug (s12x_bdm) block guide v02 s12xbdmv2/d debug (s12x_dbg) block guide v02 s12xdbgv2/d security (s12x9sec) block guide v02 s12x9secv2/d clock and reset generator (crg) block user guide v06 s12crgv6/d enhanced capture timer (ect_16b8c) block user guide v02 s12ect16b8cv2/d analog to digital converter 10 bit 16 channel (atd_10b16c) block userguide v04 s12atd10b16cv4/d analog to digital converter 10 bit 8 channels (atd_10b8c) block user guide v03 s12atd10b8cv3/d inter ic bus (iic) block user guide v02 s12iicv2/d asynchronous serial interface (sci) block user guide v05 s12sciv5/d serial peripheral interface (spi) block user guide v04 s12spiv4/d pulse width modulator 8 bit 8 channel (pwm_8b8c) block user guide v01 s12pwm8b8cv1/d 512 k byte flash (ftx512k4) block user guide v02 s12xftx512k4v2/d 4k byte eeprom (eetx4k) block user guide v02 s12xeetx4kv2/d xgate block user guide v02 s12xgatev2/d motorola scalable can (mscan) block user guide v03 s12mscanv3/d voltage regulator (vreg_3v3) block user guide v05 s12vreg_3v3v5/d port integration module (pim_9xd512) block user guide v02 s12xdp512pimv2/d oscillator (osc_lcp) block guide v01 s12osclcpv1/d periodic interrupt timer (pit_24b4c) block guide v01 s12pit24b4cv1/d notes : 1. specification changes are shown in bold (maskset l40v vs l15y) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 10 specification change summary maskset l40v vs l15y the following section lists all hardware and documentation changes. hardware changes represent all functional changes on maskset l15y vs l40v. (i.e. register movements) xsram ? hardware changes C ram size increased from 20k to 32k ? documentation changes C ram write protection register moved to s12xmmc C mc9s12xdp512v2 documentation doesnt include sram block guide xgate ? hardware changes C xgvbr became a 16-bit register C layout change of xgmctl register: xgmctl is now a 16-bit register added xgfact bit , when set mcu will never enter system stop mode added mask bits for all control bits xgss is now readable C new instruction: tfr rd,pc C added xgsweifm bit to xgmctl register ? documentation changes C xgate memory map and software error conditions described in s12x_mmc s12x_bdm ? hardware changes C debugging xgate while cpu in stop/wait mode via bdm hw-commands possible C added reserved register at address $7f_ff0a and $7f_ff0b. ? documentation change C modified command delay information for bdm commands f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 11 s12x9sec ? hardware change C internal visibility available in emulation modes if mcu is secured but internal flash and eeprom accesses are blocked pim ? hardware changes C replaced noacc with acc[2:0] C added eclkctl register at address $001c C added cs3 output s12x_mmc ? hardware changes C changed direct address from $0012 to $0011 C moved mode register ($000a) from s12x_ebi C renamed register eifctl to memctl0 ($000b). C renamed register misc to memctl1 ($0013). C reorganization of memctl0 bits to allow integrating new features (from [7:5] to [2:0]). C reorganization of memctl1 bits to eromon, romhm and romon only ([2:0]). C added cs3e in memctl0 register (position 3) C added third chip select (cs3), and redefined cs2 C xgate read access to a secured flash in expanded modes results in xgate software error C eromon bit in register mmcctl1 is (write never) instead of write once. ? documentation changes C moved write protection features from xsram C moved features chip selects and chip operating mode control from s12x_ebi C moved modes of operation description from s12x_ebi. C moved (eifctl->memctl0) register ($000b) from s12x_ebi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 12 s12x_ebi ? hardware changes C added ebisiz register for scalable external address bus width (asiz[4:0]) and 8-bit data bus option (hdbe) C added exstr[2:0] bits to mode register C added stretch functionality in special test mode C made eclkx2 available in all modes C added ebictl register at $000e C moved eifctl bits neclk, edivx, ewaite to pim C moved eifctl register bit ewaite to ebictl C moved mode register bits ithrs, ivis to ebictl C removed internal visibility feature in special test mode (along with ivis register bit) ? documentation changes C moved addresses $000a (eifctl->memctl0) and $000b (mode) to s12x_mmc block guide C moved modes of operation description to s12x_mmc C moved features chip selects and chip operating mode control to s12x_mmc C moved feature free-running clock outputs to pim crg ? hardware changes C added refdv5 and refdv4 bits to refdv register C removed cwai bit/feature C removed roawai bit/feature C specification of oscillator configuration via xclks pin has changed C cop watchdog rate cr[2:0] and mode wcop specification changed spi ? hardware change C modified functionality of data reception f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 13 vreg3v3 ? hardware changes C new api rate low register vregapirl at address $02f5 C new api rate high register vregapirh at address $02f4 C more precise api divider dbg ? hardware changes C allows writing comrv whilst armed C changed dbgcnt reset specification C changed trace buffer pointer specification C added trace buffer read unlock specification C added brk bit specification C added detail mode trace buffer databus entry alignment C xgate detail mode trace buffer format changed C changed dbgsr[7] specification C removed etea bit. external tags now always end aligned C aligned detailed mode data/address trace buffer entries C simplified comparator access considerations f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 15 table of contents section 1 introduction 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.5 device memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 1.5.1 device register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 1.5.2 mc9s12xdp512/mc9s12xa512 local to global address mapping . . . . . . . . . . . .34 1.5.3 logical address maps of s12xd and s12xa family devices. . . . . . . . . . . . . . . . . .36 1.5.4 detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 1.6 part id assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 section 2 signal description 2.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 2.2 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 2.3 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.1 extal, xtal oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.2 reset external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.3 test test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.4 vregen voltage regulator enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.5 xfc pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.6 bkgd / modc background debug and mode pin . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.7 pad[23:08] / an[23:8] port ad input pin of atd1 . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.8 pad[07:00] / an[7:0] port ad input pins of atd0 . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.9 pa[7:0] / addr[15:8] / ivd[15:8] port a i/o pins . . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.10 pb[7:1] / addr[7:1] / ivd[7:1] port b i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.11 pb0 / addr0 / uds / ivd[0] port b i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.3.12 pc[7:0] / data [15:8] port c i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.3.13 pd[7:0] / data [7:0] port d i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.3.14 pe7 / eclkx2 / xclks port e i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.3.15 pe6 / modb / taghi port e i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.3.16 pe5 / moda / taglo / re port e i/o pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.3.17 pe4 / eclk port e i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 16 2.3.18 pe3 / lstrb / lds / eromctl port e i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . .88 2.3.19 pe2 / r/w / we port e i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.3.20 pe1 / irq port e input pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.3.21 pe0 / xirq port e input pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 2.3.22 ph7 / kwh7 / ss2 / txd5 port h i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 2.3.23 ph6 / kwh6 / sck2 / rxd5 port h i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 2.3.24 ph5 / kwh5 / mosi2 / txd4 port h i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . .89 2.3.25 ph4 / kwh4 / miso2 / rxd4 port h i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .89 2.3.26 ph3 / kwh3 / ss1 port h i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 2.3.27 ph2 / kwh2 / sck1 port h i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 2.3.28 ph1 / kwh1 / mosi1 port h i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 2.3.29 ph0 / kwh0 / miso1 port h i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 2.3.30 pj7 / kwj7 / txcan4 / scl0 / txcan0 port j i/o pin 7 . . . . . . . . . . . . . . . . .90 2.3.31 pj6 / kwj6 / rxcan4 / sda0 / rxcan0 port j i/o pin 6 . . . . . . . . . . . . . . . .90 2.3.32 pj5 / kwj5 / scl1 / cs2 port j i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 2.3.33 pj4 / kwj4 / sda1 / cs0 port j i/o pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 2.3.34 pj2 / kwj2 / cs1 port j i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 2.3.35 pj1 / kwj1 / txd2 port j i/o pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 2.3.36 pj0 / kwj0 / rxd2 / cs3 port j i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 2.3.37 pk7 / ewait / romctl port k i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 2.3.38 pk[6:4] / addr[22:20] / acc[2:0] port k i/o pin [6:4] . . . . . . . . . . . . . . . . . . . . .91 2.3.39 pk[3:0] / addr[19:16] / iqstat[3:0] port k i/o pins [3:0]. . . . . . . . . . . . . . . . . .91 2.3.40 pm7 / txcan3 / txcan4 / txd3 port m i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . .91 2.3.41 pm6 / rxcan3 / rxcan4 / rxd3 port m i/o pin 6. . . . . . . . . . . . . . . . . . . . . . .92 2.3.42 pm5 / txcan0 / txcan2 / txcan4 / sck0 port m i/o pin 5. . . . . . . . . . . . . . .92 2.3.43 pm4 / rxcan0 / rxcan2 / rxcan4 / mosi0 port m i/o pin 4 . . . . . . . . . . . . .92 2.3.44 pm3 / txcan1 / txcan0 / ss0 port m i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . .92 2.3.45 pm2 / rxcan1 / rxcan0 / miso0 port m i/o pin 2 . . . . . . . . . . . . . . . . . . . . . .92 2.3.46 pm1 / txcan0 port m i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 2.3.47 pm0 / rxcan0 port m i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 2.3.48 pp7 / kwp7 / pwm7 / sck2 port p i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.3.49 pp6 / kwp6 / pwm6 / ss2 port p i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.3.50 pp5 / kwp5 / pwm5 / mosi2 port p i/o pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.3.51 pp4 / kwp4 / pwm4 / miso2 port p i/o pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.3.52 pp3 / kwp3 / pwm3 / ss1 port p i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.3.53 pp2 / kwp2 / pwm2 / sck1 port p i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .93 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 17 2.3.54 pp1 / kwp1 / pwm1 / mosi1 port p i/o pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.3.55 pp0 / kwp0 / pwm0 / miso1 port p i/o pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.56 ps7 / ss0 port s i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.57 ps6 / sck0 port s i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.58 ps5 / mosi0 port s i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.59 ps4 / miso0 port s i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.60 ps3 / txd1 port s i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.61 ps2 / rxd1 port s i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.62 ps1 / txd0 port s i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.63 ps0 / rxd0 port s i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.3.64 pt[7:0] / ioc[7:0] port t i/o pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.4.1 vddx1, vddx2, vssx1,vssx2 power & ground pins for i/o drivers . . . . . . . .95 2.4.2 vddr1, vddr2, vssr1, vssr2 power & ground pins for i/o drivers & for internal voltage regulator95 2.4.3 vdd1, vdd2, vss1, vss2 core power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.4.4 vdda, vssa power supply pins for atd and vreg . . . . . . . . . . . . . . . . . . . . .95 2.4.5 vrh, vrl atd reference voltage input pins . . . . . . . . . . . . . . . . . . . . . . . . . . .96 2.4.6 vddpll, vsspll power supply pins for pll . . . . . . . . . . . . . . . . . . . . . . . . . . .96 2.4.7 vregen on chip voltage regulator enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 section 3 system clock description 3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 section 4 modes of operation 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2 user modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.2.1 normal expanded mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.2 normal single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.3 special single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.4 emulation of expanded mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.5 emulation of single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.2.6 special test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3.1 system stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3.2 system wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3.3 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 03 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 18 4.4 freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 03 4.5 chip configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 4.5.1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 4.5.2 romon and eromon configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 4.5.3 oscillator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 4.5.4 voltage regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 4.6 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 section 5 resets and interrupts 5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.2 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.2.1 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 05 5.3 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.3.1 i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 5.3.2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 section 6 s12x_cpu block description section 7 s12x_mmc block description section 8 s12_xebi block description section 9 s12_xint block description section 10 s12x_dbg block description section 11 s12x_bdm block description section 12 xgate block description section 13 periodic interrupt timer (pit) block description section 14 oscillator (osc_lcp) block section 15 clock and reset generator (crg) block description section 16 enhanced capture timer (ect) block description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 19 section 17 10 bit 8 channel analog to digital converter (atd0) block de- scription section 18 10 bit 16 channel analog to digital converter (atd1) block de- scription section 19 inter-ic bus (iic) block description section 20 serial communications interface (sci) block description section 21 serial peripheral interface (spi) block description section 22 pulse width modulator (pwm) block description section 23 flash eeprom 512k block description section 24 eeprom 4k block description section 25 mscan block description section 26 port integration module (pim) block description section 27 voltage regulator (vreg_3v3) block description 27.1 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 appendix a electrical characteristics a.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 a.1.4 current injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .123 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 a.2 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 20 a.2.1 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 a.2.2 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 a.2.3 atd accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 a.3 nvm, flash and eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 a.3.1 nvm timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 37 a.3.2 nvm reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 9 a.4 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1 a.5 reset, oscillator and pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 a.5.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 a.5.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 a.5.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 a.6 mscan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 appendix b electrical specifications b.1 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 b.1.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 b.1.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5 b.2 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 b.2.1 normal expanded mode (external wait feature disabled) . . . . . . . . . . . . . . . . . . . .158 b.2.2 normal expanded mode (external wait feature enabled). . . . . . . . . . . . . . . . . . . . .160 b.2.3 emulation single-chip mode (without wait states). . . . . . . . . . . . . . . . . . . . . . . . . .164 b.2.4 emulation expanded mode (with optional access stretching) . . . . . . . . . . . . . . . . .166 b.3 external tag trigger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 appendix c package information c.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 c.2 144-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 72 c.3 112-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 c.4 80-pin qfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 21 list of figures figure 0-1 order part number example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 1-1 mc9s12xdp512 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 1-2 local to global address mapping s12x_cpu/s12x_bdm . . . . . . . . . . . . . . . .34 figure 1-3 local to global address mapping xgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 1-4 mc9s12xdp512/mc9s12xdt512/mc9s12xa512 memory map . . . . . . . . . . .36 figure 1-5 mc9s12xdt384 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 1-6 mc9s12xdt256/mc9s12xd256/mc9s12xa256 memory map . . . . . . . . . . . .38 figure 1-7 mc9s12xd128/mc9s12xdg128/mc9s12xa128 memory map . . . . . . . . . . . .39 figure 1-8 mc9s12xd64 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 2-1 mc9s12xd-family pin assignment 144 lqfp package . . . . . . . . . . . . . . . . . .77 figure 2-2 mc9s12xdp512 pin assignments 112 lqfp package . . . . . . . . . . . . . . . . . . .79 figure 2-3 mc9s12xdp512 pin assignments 80 qfp package . . . . . . . . . . . . . . . . . . . . .80 figure 2-4 pll loop filter connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 2-5 loop controlled pierce oscillator connections (pe7=1) . . . . . . . . . . . . . . . . . . .87 figure 2-6 full swing pierce oscillator connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . .87 figure 2-7 external clock connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 3-1 clock connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 figure 27-1 lqfp144 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 figure 27-2 lqfp112 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 figure 27-3 qfp80 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 figure a-1 atd accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure a-2 basic pll functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure a-3 jitter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure a-4 maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure b-1 spi master timing (cpha=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure b-2 spi master timing (cpha=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure b-3 spi slave timing (cpha=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure b-4 spi slave timing (cpha=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure b-5 example 1a: normal expanded mode - read followed by write{statement} . 158 figure b-6 example 1b: normal expanded mode - stretched read access . . . . . . . . . . 160 figure b-7 example 1b: normal expanded mode - stretched write access . . . . . . . . . . 161 figure b-8 example 2a: emulation single-chip mode - read followed by write. . . . . . . 164 figure b-9 example 2b: emulation expanded mode - read with 1 stretch cycle . . . . . . 166 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 22 figure b-10 example 2b: emulation expanded mode - write with 1 stretch cycle . . . . . . 167 figure b-11 external trigger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 27-4 144-pin lqfp mechanical dimensions (case no. 918-03 . . . . . . . . . . . . . . . . .172 figure c-1 112-pin lqfp mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 173 figure c-2 80-pin qfp mechanical dimensions (case no. 841b) . . . . . . . . . . . . . . . . . . . 174 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 23 list of tables table 0-1 mc9s12xd-family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 0-2 mc9s12xa-family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 0-3 document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 1-1 device register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 1-2 assigned part id numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 table 2-1 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 2-2 mc9s12xdp512 power and ground connection summary. . . . . . . . . . . . . . . . .96 table 4-1 mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 table 4-2 clock selection based on pe7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 table 4-3 voltage regulator vregen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 table 5-1 interrupt vector locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 table 15-1 initial cop rate configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 table 15-2 initial wcop configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 table 17-1 atd0 external trigger sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 table 18-1 atd1 external trigger sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 table 27-1 recommended decoupling capacitor choice . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 table a-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 table a-2 esd and latch-up test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 table a-3 esd and latch-up protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .122 table a-4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 table a-5 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 table a-6 3.3v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 table a-7 5v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 table a-8 i/o characteristics for port c, d, pe5, pe6 and pk7 for reduced input voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 table a-9 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 table a-10 atd operating characteristics 5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 table a-11 atd operating characteristics 3.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 table a-12 atd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 table a-13 atd conversion performance 5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 table a-14 atd conversion performance 3.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 table a-15 nvm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 table a-16 nvm reliability characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 24 table 27-2 voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 table a-17 startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 table a-18 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 table a-19 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 table a-20 mscan wake-up pulse characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 table b-1 measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 table b-2 spi master mode timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 table b-3 spi slave mode timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 table b-4 example 1a: normal expanded mode timing vdd35=5.0v (ewaite = 0) . . . .159 table b-5 example 1a: normal expanded mode timing vdd35=3.0v (ewaite = 0) all values: to be defined! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 table b-6 example 1b: normal expanded mode timing vdd35=5.0v (ewaite = 1) . . . .162 table b-7 example 1b: normal expanded mode timing vdd35=3.0v (ewaite = 1) all values: to be defined! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 table b-8 example 2a: emulation single-chip mode timing vdd35=5.0v (ewaite = 0) .165 table b-9 example 2b: emulation expanded mode timing vdd35=5.0v (ewaite = 0) . .168 table b-10 external tag trigger timing vdd35=5.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 25 section 1 introduction 1.1 overview the mc9s12xd family will retain the low cost, power consumption, emc and code-size efficiency advantages currently enjoyed by users of motorola's existing 16-bit mc9s12 mcu family. based around an enhanced s12 core, the mc9s12xd-family will deliver 2 to 5 times the performance of a 25mhz s12 whilst retaining a high degree of pin and code compatibility with the s12. the mc9s12xd-family introduces the performance boosting xgate module. using enhanced dma functionality, this parallel processing module offloads the cpu by providing high speed data processing and transfer between peripheral modules, ram and i/o ports. providing up to 80mips of performance additional to the cpu, the xgate can access all peripherals and the ram block. the mc9s12xdp512 is composed of standard on-chip peripherals including 512k bytes of flash eeprom, 32k bytes of ram, 4k bytes of eeprom, six asynchronous serial communications interfaces (sci), three serial peripheral interfaces (spi), an 8-channel ic/oc enhanced capture timer, an 8-channel, 10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel pulse-width modulator (pwm), five can 2.0 a, b software compatible modules (mscan12), two inter-ic bus blocks and a periodic interrupt timer. the mc9s12xdp512 has full 16-bit data paths throughout. the non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to external memories. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. system power consumption can be further improved with the new fast exit from stop mode feature. in addition to the i/o ports available in each module, up to 25 further i/o ports are available with interrupt capability allowing wake-up from stop or wait mode. the mc9s12xdp512 will be available in 144-pin lqfp with external bus interface and in 112-pin lqfp or 80-pin qfp package without external bus interface. 1.2 features ? hcs12x core C 16-bit hcs12x cpu i. upward compatible with mc9s12 instruction set ii. interrupt stacking and programmers model identical to mc9s12 iii. instruction queue iv. enhanced indexed addressing v. enhanced instruction set C ebi (external bus interface) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 26 C mmc (module mapping control) C int (interrupt controller) C dbg (debug module to monitor hcs12x cpu and xgate bus activity) C bdm (background debug mode) ? xgate (peripheral co-processo) C parallel processing module offloads the cpu by providing high speed data processing and transfer C data transfer between flash eeprom, ram, peripheral modules and i/o ports ? pit (periodic interrupt timer) C four timers with independent time-out periods C time-out periods selectable between 1 and 2 24 bus clock cycles ? crg (clock and reset generator) C low noise/low power pierce oscillator C pll C cop watchdog C real time interrupt C clock monitor C fast wake-up from stop mode ? 8-bit ports with interrupt functionality C digital filtering C programmable rising or falling edge trigger ? memory C 512k byte flash eeprom C 4k byte eeprom C 32k byte ram ? one 8-channel and one 16 channel analog-to-digital converter C 10-bit resolution C external conversion trigger capability ? five 1m bit per second, can 2.0 a, b software compatible modules C five receive and three transmit buffers C flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit C four separate interrupt channels for rx, tx, error and wake-up C low-pass filter wake-up function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 27 C loop-back for self test operation ? ect (enhanced capture timer) C 16-bit main counter with 7-bit prescaler C 8 programmable input capture or output compare channels C four 8-bit or two 16-bit pulse accumulators ? 8 pwm channels C programmable period and duty cycle C 8-bit 8-channel or 16-bit 4-channel C separate control for each pulse width and duty cycle C center-aligned or left-aligned outputs C programmable clock select logic with a wide range of frequencies C fast emergency shutdown input C usable as interrupt inputs ? serial interfaces C six asynchronous serial communication interfaces (sci) with additional lin support and selectable irda 1.4 return-to-zero-inverted (rzi) format with programmable pulse width C three synchronous serial peripheral interfaces (spi) ? iic (two inter-ic bus modules) C compatible with iic bus standard C multi-master operation C software programmable for one of 256 different serial clock frequencies ? on chip voltage regulator C two parallel, linear voltage regulators with bandgap reference C low voltage detect (lvd) with low voltage interrupt (lvi) C power on reset (por) circuit C 3.3v - 5.5v operation C low voltage reset (lvr) C ultra low power wake-up timer ? 144 pin lqfp, 112-pin lqfp package and 80-pin qfp package C i/o lines with 5v input and drive capability C input threshold on external bus interface inputs switchable for 3.3v or 5v operation C 5v a/d converter inputs C operation at 80mhz equivalent to 40mhz bus speed f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 28 ? development support C single-wire background debug? mode (bdm) C 4 on-chip hardware breakpoints 1.3 modes of operation user modes: ? normal and emulation operating modes C normal single-chip mode C normal expanded mode C emulation of single chip mode C emulation of expanded mode ? special operating modes C special single-chip mode with active background debug mode C special test mode ( motorola use only ) low power modes: ? system stop modes C pseudo stop mod C full stop mode ? system wait mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 29 1.4 block diagram figure 1-1 shows a block diagram of the mc9s12xdp512 device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 30 figure 1-1 mc9s12xdp512 block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 31 512k byte flash 32k byte ram enhanced capture reset extal xtal sci0 4k byte eeprom bkgd r/ w/ we modb/ taghi xirq eclkx2/ xclks vddr cpu12x periodic interrupt cop watchdog clock monitor single-wire background breakpoints pll vsspll xfc vddpll vdda vssa vrh vrl atd0 irq lstrb/ lds/eromctl eclk moda/ re/ taglo pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 test addr12 addr11 addr10 addr9 addr8 addr15 addr14 addr13 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 addr4 addr3 addr2 addr1 addr7 addr6 addr5 pe3 pe4 pe5 pe6 pe7 pe0 pe1 pe2 an2 an6 an0 an7 an1 an3 an4 an5 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 pt3 pt4 pt5 pt6 pt7 pt0 pt1 pt2 rxd txd miso mosi ps3 ps4 ps5 ps0 ps1 ps2 sci1 rxd txd pp3 pp4 pp5 pp6 pp7 pp0 pp1 pp2 sck ss ps6 ps7 spi0 iic0 sda scl pj2 cs1 pj4 cs0 can0 rxcan txcan pm1 pm0 can1 rxcan txcan pm2 pm3 can2 rxcan txcan pm4 pm5 pm6 pm7 kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ph3 ph4 ph5 ph6 ph7 ph0 ph1 ph2 kwj0 kwj1 pj0 cs3 pj1 ddra ddrb pta ptb ddre pte ddrad0 & ad0 ptt ddrt ptp ddrp pts ddrs ptm ddrm pth ddrh ptj ddrj clock and reset generation module voltage regulator vssr debug module vdd1,2 vss1,2 vregen vddr1,2 vssr1,2 voltage regulator 3-5v can4 rxcan txcan miso mosi sck ss spi2 miso mosi sck ss spi1 kwp2 kwp6 kwp0 kwp7 kwp1 kwp3 kwp4 kwp5 kwj2 kwj4 timer signals shown in bold-italics are neither available on the 112 pin nor on the 80 pin package option module to port routing pwm2 pwm6 pwm0 pwm7 pwm1 pwm3 pwm4 pwm5 pwm 8 bit ppage iqstat2 iqstat0 iqstat1 acc2 pk3 pk6 pk0 pk1 addr19 ew ait addr16 addr17 addr18 ptk ddrk pk2 acc1 pk4 pk5 addr20 addr21 romctl/ ewait pk7 addr22 vrh vrl vdda vssa vrh vrl atd1 an10 an14 an8 an15 an9 an11 an12 an13 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 vdda vssa ddrad1 & ad1 an18 an22 an16 an23 an17 an19 an20 an21 pad19 pad20 pad21 pad22 pad23 pad16 pad17 pad18 pc4 pc3 pc2 pc1 pc0 pc7 pc6 pc5 data12 data11 data10 data9 data8 data15 data14 data13 pd4 pd3 pd2 pd1 pd0 pd7 pd6 pd5 data4 data3 data2 data1 data0 data7 data6 data5 ddrc ddrd ptc ptd sci2 rxd txd pj6 pj7 pj5 cs2 kwj5 kwj6 kwj7 non-multiplexed external bus interface (ebi) vddx1,2 vssx1,2 i/o supply 3-5v vdda vssa analog supply 3-5v vddpll vsspll pll supply 2.5v enhanced multilevel interrupt module xgate peripheral co-processor vdd1,2 vss1,2 digital supply 2.5v signals shown in bold are not available on the 80 pin package allows 4mbyte program space sci3 rxd txd sci4 rxd txd sci5 rxd txd iic1 sda scl timer 4 channel 16 bit with prescaler for internal timebases can3 rxcan txcan addr0 uds iqstat3 acc0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 32 1.5 device memory map 1.5.1 device register memory map table 1-1 shows the device register memory map of the mc9s12xdp512 table 1-1 device register memory map address module size (bytes) $0000 - $0009 pim (port integration module ) 10 $000a -$000b mmc (memory map control) 2 $000c -$000d pim (port integration module) 2 $000e - $000f ebi (external bus interface) 2 $0010 - $0017 mmc (memory map control) 8 $0018 - $0019 reserved 2 $001a - $001b device id register 2 $001c - $001f pim (port integration module) 4 $0020 - $002f dbg (debug module) 16 $0030 - $0031 mmc (memory map control) 2 $0032 - $0033 pim (port integration module ) 2 $0034 - $003f crg (clock and reset generator) 12 $0040 - $007f ect (enhanced capture timer 16-bit 8 channel)s 64 $0080 - $00af atd1 (analog to digital converter 10-bit 16 channel) 48 $00b0 - $00b7 iic1 (inter ic bus) 8 $00b8 - $00bf sci2 (serial communications interface) 8 $00c0 - $00c7 sci3 (serial communications interface) 8 $00c8 - $00cf sci0 (serial communications interface) 8 $00d0 - $00d7 sci1 (serial communications interface) 8 $00d8 - $00df serial peripheral interface (spi0) 8 $00e0 - $00e7 iic0 (inter ic bus) 8 $00e8 - $00ef reserved 8 $00f0 - $00f7 spi1 (serial peripheral interface) 8 $00f8 - $00ff spi2 (serial peripheral interface) 8 $0100- $010f flash control register 16 $0110 - $011b eeprom control register 12 $011c - $011f mmc (memory map control) 4 $0120 - $012f int (interrupt module) 16 $0130 - $0137 sci4 (serial communications interface) 8 $0138 - $013f sci5 (serial communications interface) 8 $0140 - $017f can0 (motorola scalable can) 64 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 33 reserved register space shown in table 1-1 is not allocated to any module. this register space is reserved for future use. writing to these locations have no effect. read access to these locations returns zero. $0180 - $01bf can1 (motorola scalable can) 64 $01c0 - $01ff can2 (motorola scalable can) 64 $0200 - $023f can3 (motorola scalable can) 64 $0240 - $027f pim (port integration module) 64 $0280 - $02bf can4 (motorola scalable can) 64 $02c0 - $02df atd0 (analog to digital converter 10 bit 8 channel 32 $02e0 - $02ef reserved 16 $02f0 - $02f7 voltage regulator 8 $02f8 - $02ff reserved 8 $0300 - $0327 pulse width modulator 8 channels 40 $0328 - $033f reserved 24 $0340 - $0367 periodic interrupt timer 40 $0368 - $037f reserved 24 $0380 - $03bf xgate 64 $03c0 - $07ff reserved 1024 table 1-1 device register memory map address module size (bytes) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 34 1.5.2 mc9s12xdp512/mc9s12xa512 local to global address mapping figure 1-2 local to global address mapping s12x_cpu/s12x_bdm $7f_ffff $00_0000 $7f_c000 $14_0000 $13_fc00 $10_0000 $ffff vectors $c000 $8000 unpaged flash $4000 $1000 $0000 2k registers 8k ram $0f_e000 1k eeprom 3*1k paged eeprom unpaged 16k 29 * 16k ppages unpaged flash 16k paged $7f_8000 $7f_4000 $0c00 1k paged $2000 4k paged ram eeprom $0800 1k eeprom 8k ram 6*4k paged ram 2k registers $00_0800 epage rpage ppage flash $78_0000 unpaged 16k $0f_8000 $13_f000 ppage=$ff ppage=$fe ppage=$fd ppage=$e0 unpaged 16k or ppage $fd or ppage $fe or ppage $ff $0f_dfff $0f_ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 35 figure 1-3 local to global address mapping xgate $7f_ffff $00_0000 $10_0000 $ffff $0000 2k registers $0800 2k registers $00_0800 $00_1000 ram xgate local memory map device global memory map ram flash 30kb flash $78_0800 not used by xgate $78_8000 $0f_8000 $8000 $0f_ffff $7fff $78_7fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 36 1.5.3 logical address maps of mc9s12xd and mc9s12xa-family devices figure 1-4 mc9s12xdp512/mc9s12xdt512/mc9s12xa512 memory map $0000 $ffff $c000 $8000 $4000 $0800 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active, except for speci?c bdm hardware commands, $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window thirtytwo * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 1k, 2k, 4k or 8k protected sector $1000 $3fff $0000 $07ff 2k register space 32k bytes ram 20k bytes ram on mc9s12xdt512 $0800 $0fff 4k bytes eeprom four * 1k pages accessible through $0800 - $0bff $2000 $0c00 bdm visible on ppage = $ff (if active) $bf00 $bfff for details refer to bdm blockguide) eight * 4k pages accessible through $1000 - $1fff ?ve * 4k pages accessible through $1000 - $1fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 37 figure 1-5 mc9s12xdt384 memory map $0000 $ffff $c000 $8000 $4000 $0800 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active, except for speci?c bdm hardware commands, $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window 24 * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 1k, 2k, 4k or 8k protected sector $1000 $3fff $0000 $07ff 2k register space 20k bytes ram $0800 $0fff 4k bytes eeprom four * 1k pages accessible through $0800 - $0bff $2000 $0c00 bdm visible on ppage = $ff (if active) $bf00 $bfff for details refer to bdm blockguide) ?ve * 4k pages accessible through $1000 - $1fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 38 figure 1-6 mc9s12xdt256/mc9s12xd256/mc9s12xa256 memory map $0000 $ffff $c000 $8000 $4000 $0800 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active, except for speci?c bdm hardware commands, $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window 16 * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 1k, 2k, 4k or 8k protected sector $1000 $3fff $0000 $07ff 2k register space 16k bytes ram 14k bytes ram on mc9s12xd256 $0800 $0fff 4k bytes eeprom four * 1k pages accessible through $0800 - $0bff $2000 $0c00 bdm visible on ppage = $ff (if active) $bf00 $bfff for details refer to bdm blockguide) 4 * 4k pages accessible through $1000 - $1fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 39 figure 1-7 mc9s12xd128/mc9s12xdg128/mc9s12xa128 memory map $0000 $ffff $c000 $8000 $4000 $0800 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active, except for speci?c bdm hardware commands, $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window 8 * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 1k, 2k, 4k or 8k protected sector $1000 $3fff $0000 $07ff 2k register space 10k bytes ram 8k bytes ram on mc9s12xd128 $0800 $0fff 4k bytes eeprom four * 1k pages accessible through $0800 - $0bff $2000 $0c00 bdm visible on ppage = $ff (if active) $bf00 $bfff for details refer to bdm blockguide) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 40 figure 1-8 mc9s12xd64 memory map $0000 $ffff $c000 $8000 $4000 $0800 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active, except for speci?c bdm hardware commands, $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window 4 * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 1k, 2k, 4k or 8k protected sector $1000 $3fff $0000 $07ff 2k register space 4k bytes ram $0800 $0fff 4k bytes eeprom four * 1k pages accessible through $0800 - $0bff $2000 $0c00 bdm visible on ppage = $ff (if active) $bf00 $bfff for details refer to bdm blockguide) one * 4k pages accessible through $1000 - $1fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 41 1.5.4 detailed register map the following tables show the detailed register map of the mc9s12xdp512. $000a - $000b module mapping control (s12xmmc) map 1 of 4 $000c - $000d port integration module (pim) map 2 of 5 $0000 - $0009 port integration module (pim) map 1 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 porta read: pa 7 pa6 pa5 pa4 pa3 pa2 pa1 pa 0 write: $0001 portb read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: $0002 ddra read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: $0003 ddrb read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: $0004 portc read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: $0005 portd read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: $0006 ddrc read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: $0007 ddrd read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: $0008 porte read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: $0009 ddre read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 00 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $000a mmcctl0 read: 00000 cs2e cs1e cs0e write: $000b mode read: modc modb moda 00000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $000c pucr read: pupke bkpue 0 pupee pupde pupce pupbe pupae write: $000d rdriv read: rdpk 00 rdpe rdpd rdpc rdpb rdpa write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 42 $000e - $000f external bus interface (s12xebi) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $000e ebictl0 read: ithrs 0 hdbe asiz4 asiz3 asiz2 asiz1 asiz0 write: $000f ebictl1 read: ewaite 0000 exstr2 exstr1 exstr0 write: $0010 - $0017 module mapping control (s12xmmc) map 2 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 gpage read: 0 gp6 gp5 gp4 gp3 gp2 gp1 gp0 write: $0011 direct read: dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 write: $0012 reserved read: 00000000 write: $0013 mmcctl1 read: 00000 eromon romhm romon write: $0014 reserved read: 00000000 write: $0015 reserved read: 00000000 write: $0016 rpage read: rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 write: $0017 epage read: ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 write: $0018 - $001b miscellaneous peripheral address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0018 reserved read: 00000000 write: $0019 reserved read: 00000000 write: $001a partidh read: 11000100 write: $001b partidl read: 00000000 write: $001c - $001d port integration module (pim) map 3 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001c eclkctl read: neclk nclkx2 0000 ediv1 ediv0 write: $001d reserved read: 00000000 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 43 $001e - $001f port integration module (pim) map 3 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001e irqcr read: irqe irqen 000000 write: $001f reserved read: 00 000000 write: $0020 - $0027 debug module (s12xdbg) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 dbgc1 read: arm 0 xgsbpe bdm dbgbrk comrv write: trig $0021 dbgsr read: tbf extf 0 0 0 ssf2 ssf1 ssf0 write: $0022 dbgtcr read: tsource trange trcmod talign write: $0023 dbgc2 read: 0000 cdcm abcm write: $0024 dbgtbh read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: $0025 dbgtbl read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: $0026 dbgcnt read: 0 cnt write: $0027 dbgscrx read: 0000 sc3 sc2 sc1 sc0 write: $0028 1 notes : 1. this represents the contents if the comparator a or c control register is blended into this address dbgxctl (compa/c) read: 0 ndb tag brk rw rwe src compe write: $0028 2 2. this represents the contents if the comparator b or d control register is blended into this address dbgxctl (compb/d) read: sze sz tag brk rw rwe src compe write: $0029 dbgxah read: 0 bit 22 21 20 19 18 17 bit 16 write: $002a dbgxam read: bit 15 14 13 12 11 10 9 bit 8 write: $002b dbgxal read: bit 7 6 54321 bit 0 write: $002c dbgxdh read: bit 15 14 13 12 11 10 9 bit 8 write: $002d dbgxdl read: bit 7 654321 bit 0 write: $002e dbgxdhm read: bit 15 14 13 12 11 10 9 bit 8 write: $002f dbgxdlm read: bit 7 654321 bit 0 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 44 $0030 - $0031 module mapping control (s12xmmc) map 3of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0030 ppage read: pix7 pix6 pix5 pix4 pix3 pix2 pix1 pix0 write: $0031 reserved read: 00000000 write: $0032 - $0033 port integration module (pim) map 4 of 5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0032 portk read: pk7 pk6 pk5 pk4 pk3 pk2 pk1 pk0 write: $0033 ddrk read: ddrk7 ddrk6 ddrk5 ddrk4 ddrk3 ddrk2 ddrk1 ddrk0 write: $0034 - $003f clock and reset generator (crg) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0034 synr read: 0 0 syn5 syn4 syn3 syn2 syn1 syn0 write: $0035 refdv read: 0 0 refdv5 refdv4 refdv3 refdv2 refdv1 refdv0 write: $0036 ctflg read: 00000000 write: reserved for factory test $0037 crgflg read: rtif porf lvrf lockif lock track scmif scm write: $0038 crgint read: rtie ilaf 0 lockie 00 scmie 0 write: $0039 clksel read: pllsel pstp 00 pllwai 0 rtiwai copwai write: $003a pllctl read: cme pllon auto acq fstwkp pre pce scme write: $003b rtictl read: rtdec rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 write: $003c copctl read: wcop rsbck 000 cr2 cr1 cr0 write: $003d forbyp read: 00000000 write: reserved for factory test $003e ctctl read: 0000 000 write: reserved for factory test $003f armcop read: 00000000 write: bit 7 654321 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 45 $0040 - $007f enhanced capture timer 16 bit 8 channels (ect) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0040 tios read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: $0041 cforc read: 00000000 write: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 $0042 oc7m read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: $0043 oc7d read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: $0044 tcnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0045 tcnt (lo) read: bit 7 654321 bit 0 write: $0046 tscr1 read: ten tswai tsfrz tffca prnt 000 write: $0047 ttov read: tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 write: $0048 tctl1 read: om7 ol7 om6 ol6 om5 ol5 om4 ol4 write: $0049 tctl2 read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write: $004a tctl3 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: $004b tctl4 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: $004c tie read: c7i c6i c5i c4i c3i c2i c1i c0i write: $004d tscr2 read: toi 000 tcre pr2 pr1 pr0 write: $004e tflg1 read: c7f c6f c5f c4f c3f c2f c1f c0f write: $004f tflg2 read: tof 0000000 write: $0050 tc0 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0051 tc0 (lo) read: bit 7 654321 bit 0 write: $0052 tc1 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0053 tc1 (lo) read: bit 7 654321 bit 0 write: $0054 tc2 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0055 tc2 (lo) read: bit 7 654321 bit 0 write: $0056 tc3 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0057 tc3 (lo) read: bit 7 654321 bit 0 write: $0058 tc4 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 46 $0059 tc4 (lo) read: bit 7 654321 bit 0 write: $005a tc5 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005b tc5 (lo) read: bit 7 654321 bit 0 write: $005c tc6 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005d tc6 (lo) read: bit 7 654321 bit 0 write: $005e tc7 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005f tc7 (lo) read: bit 7 654321 bit 0 write: $0060 pactl read: 0 paen pamod pedge clk1 clk0 paovi pai write: $0061 paflg read: 000000 paovf paif write: $0062 pacn3 (hi) read: bit 7 654321 bit 0 write: $0063 pacn2 (lo) read: bit 7 654321 bit 0 write: $0064 pacn1 (hi) read: bit 7 654321 bit 0 write: $0065 pacn0 (lo) read: bit 7 654321 bit 0 write: $0066 mcctl read: mczi modmc rdmcl 00 mcen mcpr1 mcpr0 write: iclat flmc $0067 mcflg read: mczf 0 0 0 polf3 polf2 polf1 polf0 write: $0068 icpar read: 0000 pa3en pa2en pa1en pa0en write: $0069 dlyct read: dly7 dly6 dly5 dly4 dly3 dly2 dly1 dly0 write: $006a icovw read: novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 write: $006b icsys read: sh37 sh26 sh15 sh04 tfmod pacmx bufen latq write: $006c reserved read: 00000000 write: $006d timtst read: 00000000 write: reserved for factory test $006e ptpsr read: ptps7 ptps6 ptps5 ptps4 ptps3 ptps2 ptps1 ptps0 write: $006f ptmcpsr read: ptmps7 ptmps6 ptmps5 ptmps4 ptmps3 ptmps2 ptmps1 ptmps0 write: $0070 pbctl read: 0 pben 0000 pbovi 0 write: $0071 pbflg read: 000000 pbovf 0 write: $0040 - $007f enhanced capture timer 16 bit 8 channels (ect) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 47 $0080 - $00af analog to digital converter 10-bit 16 channels (atd1) map $0072 pa3h read: pa3h7 pa3h6 pa3h5 pa3h4 pa3h3 pa3h2 pa3h1 pa3h0 write: $0073 pa2h read: pa2h7 pa2h6 pa2h5 pa2h4 pa2h3 pa2h2 pa2h1 pa2h0 write: $0074 pa1h read: pa1h7 pa1h6 pa1h5 pa1h4 pa1h3 pa1h2 pa1h1 pa1h 0 write: $0075 pa0h read: pa0h7 pa0h6 pa0h5 pa0h4 pa0h3 pa0h2 pa0h1 pa0h0 write: $0076 mccnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0077 mccnt (lo) read: bit 7 654321 bit 0 write: $0078 tc0h (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0079 tc0h (lo) read: bit 7 654321 bit 0 write: $007a tc1h (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $007b tc1h (lo) read: bit 7 654321 bit 0 write: $007c tc2h (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $007d tc2h (lo) read: bit 7 654321 bit 0 write: $007e tc3h (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $007f tc3h (lo) read: bit 7 654321 bit 0 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0080 atd1ctl0 read: 0000 wrap3 wrap2 wrap1 wrap0 write: $0081 atd1ctl1 read: etrig sel 000 etrig ch3 etrig ch2 etrig ch1 etrig ch0 write: $0082 atd1ctl2 read: adpu affc awai etrigle etrigp etrige ascie ascif write: $0083 atd1ctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0084 atd1ctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0085 atd1ctl5 read: djm dsgn scan mult cd cc cb ca write: $0086 atd1stat0 read: scf 0 etorf fifor cc3 cc2 cc1 cc0 write: $0087 reserved read: 00000000 write: $0088 atd1test0 read: uuuuuuuu write: reserved for factory test $0040 - $007f enhanced capture timer 16 bit 8 channels (ect) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 48 $0089 atd1test1 read: 00000000 write: reserved for factory test $008a atd1stat2 read: ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 write: $008b atd1stat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $008c atd1dien0 read: ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 write: $008d atd1dien read: ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 write: $008e portad0 read: ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 write: $008f portad1 read: ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 write: $0090 atd1dr0h read: bit15 14 13 12 11 10 9 bit8 write: $0091 atd1dr0l read: bit7 bit6 000000 write: $0092 atd1dr1h read: bit15 14 13 12 11 10 9 bit8 write: $0093 atd1dr1l read: bit7 bit6 000000 write: $0094 atd1dr2h read: bit15 14 13 12 11 10 9 bit8 write: $0095 atd1dr2l read: bit7 bit6 000000 write: $0096 atd1dr3h read: bit15 14 13 12 11 10 9 bit8 write: $0097 atd1dr3l read: bit7 bit6 000000 write: $0098 atd1dr4h read: bit15 14 13 12 11 10 9 bit8 write: $0099 atd1dr4l read: bit7 bit6 000000 write: $009a atd1dr5h read: bit15 14 13 12 11 10 9 bit8 write: $009b atd1dr5l read: bit7 bit6 000000 write: $009c atd1dr6h read: bit15 14 13 12 11 10 9 bit8 write: $009d atd1dr6l read: bit7 bit6 000000 write: $009e atd1dr7h read: bit15 14 13 12 11 10 9 bit8 write: $009f atd1dr7l read: bit7 bit6 000000 write: $00a0 atd1dr8h read: bit15 14 13 12 11 10 9 bit8 write: $00a1 atd1dr8l read: bit7 bit6 000000 write: $00a2 atd1dr9h read: bit15 14 13 12 11 10 9 bit8 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 49 $00a3 atd1dr9l read: bit7 bit6 000000 write: $00a4 atd1dr10h read: bit15 14 13 12 11 10 9 bit8 write: $00a5 atd1dr10l read: bit7 bit6 000000 write: $00a6 atd1dr11h read: bit15 14 13 12 11 10 9 bit8 write: $00a7 atd1dr11l read: bit7 bit6 000000 write: $00a8 atd1dr12h read: bit15 14 13 12 11 10 9 bit8 write: $00a9 atd1dr12l read: bit7 bit6 000000 write: $00aa atd1dr13h read: bit15 14 13 12 11 10 9 bit8 write: $00ab atd1dr13l read: bit7 bit6 000000 write: $00ac atd1dr14h read: bit15 14 13 12 11 10 9 bit8 write: $00ad atd1dr14l read: bit7 bit6 000000 write: $00ae atd1dr15h read: bit15 14 13 12 11 10 9 bit8 write: $00af atd1dr15l read: bit7 bit6 000000 write: $00b0 - $00b7 inter ic bus (iic1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00b0 ibad read: adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 write: $00b1 ibfd read: ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 write: $00b2 ibcr read: iben ibie ms/ sl tx/ rx txak 00 ibswai write: rsta $00b3 ibsr read: tcf iaas ibb ibal 0srw ibif rxak write: $00b4 ibdr read: d7 d6 d5 d4 d3 d2 d1 d 0 write: $00b5 reserved read: 0 0 0 0 0 0 0 0 write: $00b6 reserved read: 00000000 write: $00b7 reserved read: 00000000 write: address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 50 $00b8 - $00bf asynchronous serial interface (sci2) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00b8 sci2bdh 1 read: iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00b9 sci2bdl 1 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00ba sci2cr1 1 read: loops sciswai rsrc m wake ilt pe pt write: $00b8 sci2asr1 2 read: rxedgi f 0000 berrv berrif bkdif write: $00b9 sci2acr1 2 read: rxedgi e 00000 berrie bkdie write: $00ba sci2acr2 2 read: 00000 berrm1 berrm0 bkdfe write: $00bb sci2cr2 read: tie tcie rie ilie te re rwu sbk write: $00bc sci2sr1 read: tdre tc rdrf idle or nf fe pf write: $00bd sci2sr2 read: amap 00 txpol rxpol brk13 txdir raf write: $00be sci2drh read: r8 t8 000000 write: $00bf sci2drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 notes : 1. those registers are accessible if the amap bit in the sci2sr2 register is set to zero 2. those registers are accessible if the amap bit in the sci2sr2 register is set to one $00c0 - $00c7 asynchronous serial interface (sci3) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00c0 sci3bdh 1 read: iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00c1 sci3bdl 1 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00c2 sci3cr1 1 read: loops sciswai rsrc m wake ilt pe pt write: $00c0 sci3asr1 2 read: rxedgi f 0000 berrv berrif bkdif write: $00c1 sci3acr1 2 read: rxedgi e 00000 berrie bkdie write: $00c2 sci3acr2 2 read: 00000 berrm1 berrm0 bkdfe write: $00c3 sci3cr2 read: tie tcie rie ilie te re rwu sbk write: $00c4 sci3sr1 read: tdre tc rdrf idle or nf fe pf write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 51 $00c5 sci3sr2 read: amap 00 txpol rxpol brk13 txdir raf write: $00c6 sci3drh read: r8 t8 000000 write: $00c7 sci3drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 notes : 1. those registers are accessible if the amap bit in the sci3sr2 register is set to zero 2. those registers are accessible if the amap bit in the sci3sr2 register is set to one $00c8 - $00cf asynchronous serial interface (sci0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00c8 sci0bdh 1 notes : 1. those registers are accessible if the amap bit in the sci0sr2 register is set to zero read: iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00c9 sci0bdl 1 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00ca sci0cr1 1 read: loops sciswai rsrc m wake ilt pe pt write: $00c8 sci0asr1 2 2. those registers are accessible if the amap bit in the sci0sr2 register is set to one read: rxedgi f 0000 berrv berrif bkdif write: $00c9 sci0acr1 2 read: rxedgi e 00000 berrie bkdie write: $00ca sci0acr2 2 read: 00000 berrm1 berrm0 bkdfe write: $00cb sci0cr2 read: tie tcie rie ilie te re rwu sbk write: $00cc sci0sr1 read: tdre tc rdrf idle or nf fe pf write: $00cd sci0sr2 read: amap 00 txpol rxpol brk13 txdir raf write: $00ce sci0drh read: r8 t8 000000 write: $00cf sci0drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d0 - $00d7 asynchronous serial interface (sci1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d0 sci1bdh 1 read: iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00d1 sci1bdl 1 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00c0 - $00c7 asynchronous serial interface (sci3) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 52 $00d2 sci1cr1 1 read: loops sciswai rsrc m wake ilt pe pt write: $00d0 sci1asr1 2 read: rxedgi f 0000 berrv berrif bkdif write: $00d1 sci1acr1 2 read: rxedgi e 00000 berrie bkdie write: $00d2 sci1acr2 2 read: 00000 berrm1 berrm0 bkdfe write: $00d3 sci1cr2 read: tie tcie rie ilie te re rwu sbk write: $00d4 sci1sr1 read: tdre tc rdrf idle or nf fe pf write: $00d5 sci1sr2 read: amap 00 txpol rxpol brk13 txdir raf write: $00d6 sci1drh read: r8 t8 000000 write: $00d7 sci1drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 notes : 1. those registers are accessible if the amap bit in the sci1sr2 register is set to zero 2. those registers are accessible if the amap bit in the sci1sr2 register is set to one $00d8 - $00df serial peripheral interface (spi0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d8 spi0cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00d9 spi0cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00da spi0br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00db spi0sr read: spif 0 sptef modf 0000 write: $00dc reserved read: 00000000 write: $00dd spi0dr read: bit7 654321 bit0 write: $00de reserved read: 00000000 write: $00df reserved read: 00000000 write: $00d0 - $00d7 asynchronous serial interface (sci1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 53 $00e0 - $00e7 inter ic bus (iic0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e0 ibad read: adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 write: $00e1 ibfd read: ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 write: $00e2 ibcr read: iben ibie ms/ sl tx/ rx txak 00 ibswai write: rsta $00e3 ibsr read: tcf iaas ibb ibal 0srw ibif rxak write: $00e4 ibdr read: d7 d6 d5 d4 d3 d2 d1 d 0 write: $00e5 reserved read: 0 0 0 0 0 0 0 0 write: $00e6 reserved read: 00000000 write: $00e7 reserved read: 00000000 write: $00e8 - $00ef reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e8 reserved read: 00000000 write: $00e9 reserved read: 00000000 write: $00ea reserved read: 00000000 write: $00eb reserved read: 0 0 0 0 0 0 0 0 write: $00ec reserved read: 0 0000000 write: $00ed reserved read: 0 0 0 0 0 0 0 0 write: $00ee reserved read: 0 0 0 0 0 0 0 0 write: $00ef reserved read: 0 0 0 0 0 0 0 0 write: $00f0 - $00f7 serial peripheral interface (spi1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00f0 spi1cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00f1 spi1cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00f2 spi1br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00f3 spi1sr read: spif 0 sptef modf 0000 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 54 $00f4 reserved read: 00000000 write: $00f5 spi1dr read: bit7 654321 bit0 write: $00f6 reserved read: 00000000 write: $00f7 reserved read: 00000000 write: $00f8 - $00ff serial peripheral interface (spi2) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00f8 spi2cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00f9 spi2cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00fa spi2br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00fb spi2sr read: spif 0 sptef modf 0000 write: $00fc reserved read: 00000000 write: $00fd spi2dr read: bit7 654321 bit0 write: $00fe reserved read: 00000000 write: $00ff reserved read: 00000000 write: $0100 - $010f flash control register (ftx512k4) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0100 fclkdiv read: fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 write: $0101 fsec read: keyen1 keyen0 rnv5 rnv4 rnv3 rnv2 sec1 sec0 write: $0102 ftstmod read: 0 mrds wrall 0000 write: $0103 fcnfg read: cbeie ccie keyacc 00000 write: $0104 fprot read: fpopen rnv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 write: $0105 f s tat read: cbeif ccif pviol accerr 0 blank 0 0 write: $0106 fcmd read: 0 cmdb[6:0] write: $0107 fctl read: nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 write: $00f0 - $00f7 serial peripheral interface (spi1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 55 $0108 faddrhi read: faddrhi write: $0109 faddrlo read: faddrlo write: $010a fdatahi read: fdatahi write: $010b fdatalo read: fdatalo write: $010c reserved read: 00000000 write: $010d reserved read: 00000000 write: $010e reserved read: 00000000 write: $010f reserved read: 00000000 write: $0110 - $011b eeprom control register (eetx4k) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0110 eclkdiv read: edivld prdiv8 ediv5 ediv4 ediv3 ediv2 ediv1 ediv0 write: $0111 reserved read: 00000000 write: $0112 reserved read: 00000000 write: $0113 ecnfg read: cbeie ccie 000000 write: $0114 eprot read: epopen rnv6 rnv5 rnv4 epdis eps2 eps1 eps0 write: $0115 estat read: cbeif ccif pviol accerr 0 blank 0 0 write: $0116 ecmd read: 0 cmdb[6:0] write: $0117 reserved read: 00000000 write: $0118 eaddrhi read: 00000 eabhi write: $0119 eaddrlo read: eablo write: $011a edatahi read: edhi write: $011b edatalo read: edlo write: $0100 - $010f flash control register (ftx512k4) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 56 $011c - $011f memory map control (s12xmmc) map 4 of 4 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $011c ramwpc read: rpwe 00000 avie avif write: $011d ramxgu read: 1 xgu6 xgu5 xgu4 xgu3 xgu2 xgu1 xgu0 write: $011e ramshl read: 1 shl6 shl5 shl4 shl3 shl2 shl1 shl0 write: $011f ramshu read: 1 shu6 shu5 shu4 shu3 shu2 shu1 shu0 write: $0120 - $012f interrupt module (s12xint) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0120 reserved read: 00000000 write: $0121 ivbr read: ivb_addr[7:0] write: $0122 reserved read: 00000000 write: $0123 reserved read: 00000000 write: $0124 reserved read: 00000000 write: $0125 reserved read: 00000000 write: $0126 int_xgprio read: 00000 xilvl[2:0] write: $0127 int_cfaddr read: int_cfaddr[7:4] 0000 write: $0128 int_cfdata0 read: rqst 0000 priolvl[2:0] write: $0129 int_cfdata1 read: rqst 0000 priolvl[2:0] write: $012a int_cfdata2 read: rqst 0000 priolvl[2:0] write: $012b int_cfdata3 read: rqst 0000 priolvl[2:0] write: $012c int_cfdata4 read: rqst 0000 priolvl[2:0] write: $012d int_cfdata5 read: rqst 0000 priolvl[2:0] write: $012e int_cfdata6 read: rqst 0000 priolvl[2:0] write: $012f int_cfdata7 read: rqst 0000 priolvl[2:0] write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 57 $00130 - $0137 asynchronous serial interface (sci4) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0130 sci4bdh 1 notes : 1. those registers are accessible if the amap bit in the sci4sr2 register is set to zero read: iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $0131 sci4bdl 1 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $0132 sci4cr1 1 read: loops sciswai rsrc m wake ilt pe pt write: $0130 sci4asr1 2 2. those registers are accessible if the amap bit in the sci4sr2 register is set to one read: rxedgi f 0000 berrv berrif bkdif write: $0131 sci4acr1 2 read: rxedgi e 00000 berrie bkdie write: $0132 sci4acr2 2 read: 00000 berrm1 berrm0 bkdfe write: $0133 sci4cr2 read: tie tcie rie ilie te re rwu sbk write: $0134 sci4sr1 read: tdre tc rdrf idle or nf fe pf write: $0135 sci4sr2 read: amap 00 txpol rxpol brk13 txdir raf write: $0136 sci4drh read: r8 t8 000000 write: $0137 sci4drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $0138 - $013f asynchronous serial interface (sci5) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0138 sci5bdh 1 read: iren tnp1 tnp0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $0139 sci5bdl 1 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $013a sci5cr1 1 read: loops sciswai rsrc m wake ilt pe pt write: $0138 sci5asr1 2 read: rxedgi f 0000 berrv berrif bkdif write: $0139 sci5acr1 2 read: rxedgi e 00000 berrie bkdie write: $013a sci5acr2 2 read: 00000 berrm1 berrm0 bkdfe write: $013b sci5cr2 read: tie tcie rie ilie te re rwu sbk write: $013c sci5sr1 read: tdre tc rdrf idle or nf fe pf write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 58 $013d sci5sr2 read: amap 00 txpol rxpol brk13 txdir raf write: $013e sci5drh read: r8 t8 000000 write: $013f sci5drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 notes : 1. those registers are accessible if the amap bit in the sci5sr2 register is set to zero 2. those registers are accessible if the amap bit in the sci5sr2 register is set to one $0140 - $017f motorola scalable can - mscan (can0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0140 can0ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0141 can0ctl1 read: cane clksrc loopb listen borm wupm slpak initak write: $0142 can0btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0143 can0btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0144 can0rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0145 can0rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0146 can0tflg read: 00000 txe2 txe1 txe0 write: $0147 can0tier read: 00000 txeie2 txeie1 txeie0 write: $0148 can0tarq read: 00000 abtrq2 abtrq1 abtrq0 write: $0149 can0taak read: 00000abtak2abtak1abtak0 write: $014a can0tbsel read: 00000 tx2 tx1 tx0 write: $014b can0idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $014c reserved read: 00000000 write: $014d can0misc read: 0000000 bohold write: $014e can0rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $014f can0txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0150 - $0153 can0idar0 - can0idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0154 - $0157 can0idmr0 - can0idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0138 - $013f asynchronous serial interface (sci5) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 59 $0158 - $015b can0idar4 - can0idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $015c - $015f can0idmr4 - can0idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0160 - $016f can0rxfg read: foreground receive buffer see detailed mscan foreground receive and transmit buffer layout write: $0170 - $017f can0txfg read: foreground transmit buffer see detailed mscan foreground receive and transmit buffer layout write: detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $xxx0 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 standard id read: id10 id9 id8 id7 id6 id5 id4 id3 canxridr0 write: $xxx1 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id read: id2 id1 id0 rtr ide=0 canxridr1 write: $xxx2 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 standard id read: canxridr2 write: $xxx3 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr standard id read: canxridr3 write: $xxx4- $xxxb canxrdsr0 - canxrdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $xxxc canrxdlr read: dlc3 dlc2 dlc1 dlc0 write: $xxxd reserved read: write: $xxxe canxrtsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $xxxf canxrtsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $xx10 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 canxtidr0 write: standard id read: id10 id9 id8 id7 id6 id5 id4 id3 write: $xx10 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 canxtidr1 write: standard id read: id2 id1 id0 rtr ide=0 write: $xx12 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 canxtidr2 write: standard id read: write: $0140 - $017f motorola scalable can - mscan (can0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 60 $xx13 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr canxtidr3 write: standard id read: write: $xx14- $xx1b canxtdsr0 - canxtdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $xx1c canxtdlr read: dlc3 dlc2 dlc1 dlc0 write: $xx1d canxttbpr read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: $xx1e canxttsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $xx1f canxttsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $0180 - $01bf motorola scalable can - mscan (can1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0180 can1ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0181 can1ctl1 read: cane clksrc loopb listen borm wupm slpak initak write: $0182 can1btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0183 can1btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0184 can1rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0185 can1rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0186 can1tflg read: 00000 txe2 txe1 txe0 write: $0187 can1tier read: 00000 txeie2 txeie1 txeie0 write: $0188 can1tarq read: 00000 abtrq2 abtrq1 abtrq0 write: $0189 can1taak read: 00000abtak2abtak1abtak0 write: $018a can1tbsel read: 00000 tx2 tx1 tx0 write: $018b can1idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $018c reserved read: 00000000 write: $018d can1misc read: 0000000 bohold write: $018e can1rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 61 $018f can1txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0190 can1idar0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0191 can1idar1 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0192 can1idar2 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0193 can1idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0194 can1idmr0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0195 can1idmr1 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0196 can1idmr2 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0197 can1idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0198 can1idar4 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0199 can1idar5 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $019a can1idar6 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $019b can1idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $019c can1idmr4 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $019d can1idmr5 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $019e can1idmr6 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $019f can1idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01a0 - $01af can1rxfg read: foreground receive buffer see detailed mscan foreground receive and transmit buffer layout write: $01b0 - $01bf can1txfg read: foreground transmit buffer see detailed mscan foreground receive and transmit buffer layout write: $01c0 - $01ff motorola scalable can - mscan (can2) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $01c0 can2ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $01c1 can2ctl1 read: cane clksrc loopb listen borm wupm slpak initak write: $01c2 can2btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0180 - $01bf motorola scalable can - mscan (can1) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 62 $01c3 can2btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $01c4 can2rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $01c5 can2rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $01c6 can2tflg read: 00000 txe2 txe1 txe0 write: $01c7 can2tier read: 00000 txeie2 txeie1 txeie0 write: $01c8 can2tarq read: 00000 abtrq2 abtrq1 abtrq0 write: $01c9 can2taak read: 00000abtak2abtak1abtak0 write: $01ca can2tbsel read: 00000 tx2 tx1 tx0 write: $01cb can2idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $01cc reserved read: 00000000 write: $01cd can2misc read: 0000000 bohold write: $01ce can2rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $01cf can2txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $01d0 can2idar0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $01d1 can2idar1 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $01d2 can2idar2 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $01d3 can2idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $01d4 can2idmr0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01d5 can2idmr1 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01d6 can2idmr2 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01d7 can2idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01d8 can2idar4 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $01d9 can2idar5 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $01da can2idar6 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $01db can2idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $01c0 - $01ff motorola scalable can - mscan (can2) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 63 $01dc can2idmr4 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01dd can2idmr5 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01de can2idmr6 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01df can2idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01e0 - $01ef can2rxfg read: foreground receive buffer see detailed mscan foreground receive and transmit buffer layout write: $01f0 - $01ff can2txfg read: foreground transmit buffer see detailed mscan foreground receive and transmit buffer layout write: $0200 - $023f motorola scalable can - mscan (can3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0200 can3ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0201 can3ctl1 read: cane clksrc loopb listen borm wupm slpak initak write: $0202 can3btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0203 can3btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0204 can3rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0205 can3rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0206 can3tflg read: 00000 txe2 txe1 txe0 write: $0207 can3tier read: 00000 txeie2 txeie1 txeie0 write: $0208 can3tarq read: 00000 abtrq2 abtrq1 abtrq0 write: $0209 can3taak read: 00000abtak2abtak1abtak0 write: $020a can3tbsel read: 00000 tx2 tx1 tx0 write: $020b can3idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $020c reserved read: 00000000 write: $020d reserved read: 0000000 bohold write: $020e can3rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $020f can3txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $01c0 - $01ff motorola scalable can - mscan (can2) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 64 $0210 can3idar0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0211 can3idar1 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0212 can3idar2 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0213 can3idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0214 can3idmr0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0215 can3idmr1 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0216 can3idmr2 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0217 can3idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0218 can3idar4 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0219 can3idar5 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $021a can3idar6 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $021b can3idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $021c can3idmr4 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $021d can3idmr5 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $021e can3idmr6 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $021f can3idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0220 - $022f can3rxfg read: foreground receive buffer see detailed mscan foreground receive and transmit buffer layout write: $0230 - $023f can3txfg read: foreground transmit buffer see detailed mscan foreground receive and transmit buffer layout write: $0240 - $027f port integration module pim_9dx (pim) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0240 ptt read: ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 write: $0241 ptit read: ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 write: $0242 ddrt read: ddrt7 ddrt7 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 write: $0243 rdrt read: rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 write: $0200 - $023f motorola scalable can - mscan (can3) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 65 $0244 pert read: pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 write: $0245 ppst read: ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 write: $0246 reserved read: 00000000 write: $0247 reserved read: 00000000 write: $0248 pts read: pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 write: $0249 ptis read: ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 write: $024a ddrs read: ddrs7 ddrs7 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: $024b rdrs read: rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 write: $024c pers read: pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 write: $024d ppss read: ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 write: $024e woms read: woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 write: $024f reserved read: 00000000 write: $0250 ptm read: ptm7 ptm6 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 write: $0251 ptim read: ptim7 ptim6 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 write: $0252 ddrm read: ddrm7 ddrm7 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 write: $0253 rdrm read: rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 write: $0254 perm read: perm7 perm6 perm5 perm4 perm3 perm2 perm1 perm0 write: $0255 ppsm read: ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 write: $0256 womm read: womm7 womm6 womm5 womm4 womm3 womm2 womm1 womm0 write: $0257 modrr read: 0 modrr6 modrr5 modrr4 modrr3 modrr2 modrr1 modrr0 write: $0258 ptp read: ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 write: $0259 ptip read: ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 write: $025a ddrp read: ddrp7 ddrp7 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 write: $025b rdrp read: rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 write: $025c perp read: perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 write: $0240 - $027f port integration module pim_9dx (pim) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 66 $025d ppsp read: ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 write: $025e piep read: piep7 piep6 piep5 piep4 piep3 piep2 piep1 piep0 write: $025f pifp read: pifp7 pifp6 pifp5 pifp4 pifp3 pifp2 pifp1 pifp0 write: $0260 pth read: pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 write: $0261 ptih read: ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 write: $0262 ddrh read: ddrh7 ddrh7 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 write: $0263 rdrh read: rdrh7 rdrh6 rdrh5 rdrh4 rdrh3 rdrh2 rdrh1 rdrh0 write: $0264 perh read: perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 write: $0265 ppsh read: ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 write: $0266 pieh read: pieh7 pieh6 pieh5 pieh4 pieh3 pieh2 pieh1 pieh0 write: $0267 pifh read: pifh7 pifh6 pifh5 pifh4 pifh3 pifh2 pifh1 pifh0 write: $0268 ptj read: ptj7 ptj6 ptj5 ptj4 0 ptj2 ptj1 ptj0 write: $0269 ptij read: ptij7 ptij6 ptij5 ptij4 0 ptij2 ptij1 ptij0 write: $026a ddrj read: ddrj7 ddrj7 ddrj5 ddrj4 0 ddrj2 ddrj1 ddrj0 write: $026b rdrj read: rdrj7 rdrj6 rdrj5 rdrj4 0 rdrj2 rdrj1 rdrj0 write: $026c perj read: perj7 perj6 perj5 perj4 0 perj2 perj1 perj0 write: $026d ppsj read: ppsj7 ppsj6 ppsj5 ppsj4 0 ppsj2 ppsj1 ppsj0 write: $026e piej read: piej7 piej6 piej5 piej4 0 piej2 piej1 piej0 write: $026f piej read: pifj7 pifj6 pifj5 pifj4 0 pifj2 pifj1 pifj0 write: $0270 reserved read: 00000000 write: $0271 pt1ad0 read: pt1ad07 pt1ad06 pt1ad05 pt1ad04 pt1ad03 pt1ad02 pt1ad01 pt1ad00 write: $0272 reserved read: 00000000 write: $0273 ddr1ad0 read: ddr1 ad07 ddr1 ad06 ddr1 ad05 ddr1 ad04 ddr1 ad03 ddr1 ad02 ddr1 ad01 ddr1 ad01 write: $0274 reserved read: 00000000 write: $0275 rdr1ad0 read: rdr1 ad07 rdr1 ad06 rdr1 ad05 rdr1 ad04 rdr1 ad03 rdr1 ad02 rdr1 ad01 rdr1 ad00 write: $0240 - $027f port integration module pim_9dx (pim) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 67 $0276 reserved read: 00000000 write: $0277 per1ad0 read: per1ad 07 per1ad 06 per1ad 05 per1ad 04 per1ad 03 per1ad 02 per1ad 01 per1ad 00 write: $0278 pt0ad1 read: pt0ad1 23 pt0ad1 22 pt0ad1 21 pt0ad1 20 pt0ad1 19 pt0ad1 18 pt0ad1 17 pt0ad1 16 write: $0279 pt1ad1 read: pt1ad1 15 pt1ad1 14 pt1ad1 13 pt1ad1 12 pt1ad1 11 pt1ad1 10 pt1ad1 9 pt1ad1 8 write: $027a ddr0ad1 read: ddr0 ad1 23 ddr0 ad1 22 ddr0 ad1 21 ddr0 ad1 20 ddr0 ad1 19 ddr0 ad1 18 ddr0 ad1 17 ddr0 ad1 16 write: $027b ddr1ad1 read: ddr1 ad1 15 ddr1 ad1 14 ddr1 ad1 13 ddr1 ad1 12 ddr1 ad1 11 ddr1 ad1 10 ddr1 ad1 9 ddr1 ad1 8 write: $027c rdr0ad1 read: rdr0 ad1 23 rdr0 ad1 22 rdr0 ad1 21 rdr0 ad1 20 rdr0 ad1 19 rdr0 ad1 18 rdr0 ad1 17 rdr0 ad1 16 write: $027d rdr1ad1 read: rdr1ad 1 15 rdr1ad 1 14 rdr1ad 1 13 rdr1ad 1 12 rdr1ad 1 11 rdr1ad 1 10 rdr1ad 1 9 rdr1ad 1 8 write: $027e per0ad1 read: per0 ad1 23 per0 ad1 22 per0 ad1 21 per0 ad1 20 per0 ad1 19 per0 ad1 18 per0 ad1 17 per0 ad1 16 write: $027f per1ad1 read: per1 ad1 15 per1 ad1 14 per1 ad1 13 per1 ad1 12 per1 ad1 11 per1 a1d 10 per1 ad1 9 per1 ad1 8 write: $0280 - $02bf motorola scalable can - mscan (can4) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0280 can4ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0281 can4ctl1 read: cane clksrc loopb listen borm wupm slpak initak write: $0282 can4btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0283 can4btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0284 can4rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0285 can4rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0286 can4tflg read: 00000 txe2 txe1 txe0 write: $0287 can4tier read: 00000 txeie2 txeie1 txeie0 write: $0288 can4tarq read: 00000 abtrq2 abtrq1 abtrq0 write: $0289 can4taak read: 00000abtak2abtak1abtak0 write: $0240 - $027f port integration module pim_9dx (pim) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 68 $028a can4tbsel read: 00000 tx2 tx1 tx0 write: $028b can4idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $028c reserved read: 00000000 write: $028d can4misc read: 0000000 bohold write: $028e can4rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $028f can4txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0290 can4idar0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0291 can4idar1 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0292 can4idar2 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0293 can4idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0294 can4idmr0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0295 can4idmr1 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0296 can4idmr2 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0297 can4idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0298 can4idar4 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0299 can4idar5 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $029a can4idar6 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $029b can4idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $029c can4idmr4 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $029d can4idmr5 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $029e can4idmr6 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $029f can4idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $02a0 - $02af can4rxfg read: foreground receive buffer see detailed mscan foreground receive and transmit buffer layout write: $02b0 - $02bf can4txfg read: foreground transmit buffer see detailed mscan foreground receive and transmit buffer layout write: $0280 - $02bf motorola scalable can - mscan (can4) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 69 $02c0 - $02df analog to digital converter 10 bit 8 channel (atd0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02c0 atd0ctl0 read: 00000 wrap2 wrap1 wrap0 write: $02c1 atd0ctl1 read: etrig sel 0000 etrig ch2 etrig ch1 etrig ch0 write: $02c2 atd0ctl2 read: adpu affc awai etrigle etrigp etrige ascie ascif write: $02c3 atd0ctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $02c4 atd0ctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $02c5 atd0ctl5 read: djm dsgn scan mult 0 cc cb ca write: $02c6 atd0stat0 read: scf 0 etorf fifor 0 cc2 cc1 cc0 write: $02c7 reserved read: uuuuuuuu write: $02c8 atd0test0 read: uuuuuuuu write: $02c9 atd0test1 read: u u 00000 sc write: $02ca reserved read: 00000000 write: $02cb atd0stat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $02cc reserved read: 00000000 write: $02cd atd0dien read: ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 write: $02ce reserved read: 00000000 write: $02cf portad0 read: bit7 654321 bit 0 write: $02d0 atd0dr0h read: bit15 14 13 12 11 10 9 bit8 write: $02d1 atd0dr0l read: bit7 bit6 000000 write: $02d2 atd0dr1h read: bit15 14 13 12 11 10 9 bit8 write: $02d3 atd0dr1l read: bit7 bit6 000000 write: $02d4 atd0dr2h read: bit15 14 13 12 11 10 9 bit8 write: $02d5 atd0dr2l read: bit7 bit6 000000 write: $02d6 atd0dr3h read: bit15 14 13 12 11 10 9 bit8 write: $02d7 atd0dr3l read: bit7 bit6 000000 write: $02d8 atd0dr4h read: bit15 14 13 12 11 10 9 bit8 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 70 $02d9 atd0dr4l read: bit7 bit6 000000 write: $02da atd0dr5h read: bit15 14 13 12 11 10 9 bit8 write: $02db atd0dr5l read: bit7 bit6 000000 write: $02dc atd0dr6h read: bit15 14 13 12 11 10 9 bit8 write: $02dd atd0dr6l read: bit7 bit6 000000 write: $02de atd0dr7h read: bit15 14 13 12 11 10 9 bit8 write: $02df atd0dr7l read: bit7 bit6 000000 write: $02e0 - $02ef reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02e0 - $02ef reserved read: 00000000 write: $02f0 - $02f7 voltage regulator (vreg_3v3) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02f0 vreghtcl read: reserved for factory test write: $02f1 vregctrl read: 00000lvds lvie lvif write: $02f2 vregapicl read: apiclk 0000 apife apie apif write: $02f3 vregapitr read: apitr5 apitr4 apitr3 apitr2 apitr1 apitr0 00 write: $02f4 vregapirh read: 0000 apir11 apir10 apir9 apir8 write: $02f5 vregapirl read: apir7 apir6 apir5 apir4 apir3 apir2 apir1 apir0 write: $02f6 reserved read: 00000000 write: $02f7 reserved read 00000000 write: $02f8 - $02ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02f8 - $02ff reserved read: 00000000 write: $02c0 - $02df analog to digital converter 10 bit 8 channel (atd0) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 71 $0300 - $0327 pulse width modulator 8 bit 8 channel (pwm) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0300 pwme read: pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 write: $0301 pwmpol read: ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 write: $0302 pwmclk read: pclk7 pclk6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 write: $0303 pwmprclk read: 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 write: $0304 pwmcae read: cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 write: $0305 pwmctl read: con67 con45 con23 con01 pswai pfrz 00 write: $0306 pwmtst test only read: 00000000 write: $0307 pwmprsc read: 00000000 write: $0308 pwmscla read: bit 7 6 5 4 3 2 1 bit 0 write: $0309 pwmsclb read: bit 7 6 5 4 3 2 1 bit 0 write: $030a pwmscnta read: 00000000 write: $030b pwmscntb read: 00000000 write: $030c pwmcnt0 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $030d pwmcnt1 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $030e pwmcnt2 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $030f pwmcnt3 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0310 pwmcnt4 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0311 pwmcnt5 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0312 pwmcnt6 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0313 pwmcnt7 read: bit 7 6 5 4 3 2 1 bit 0 write: 00000000 $0314 pwmper0 read: bit 7 6 5 4 3 2 1 bit 0 write: $0315 pwmper1 read: bit 7 6 5 4 3 2 1 bit 0 write: $0316 pwmper2 read: bit 7 6 5 4 3 2 1 bit 0 write: $0317 pwmper3 read: bit 7 6 5 4 3 2 1 bit 0 write: $0318 pwmper4 read: bit 7 6 5 4 3 2 1 bit 0 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 72 $0319 pwmper5 read: bit 7 6 5 4 3 2 1 bit 0 write: $031a pwmper6 read: bit 7 6 5 4 3 2 1 bit 0 write: $031b pwmper7 read: bit 7 6 5 4 3 2 1 bit 0 write: $031c pwmdty0 read: bit 7 6 5 4 3 2 1 bit 0 write: $031d pwmdty1 read: bit 7 6 5 4 3 2 1 bit 0 write: $031e pwmdty2 read: bit 7 6 5 4 3 2 1 bit 0 write: $031f pwmdty3 read: bit 7 6 5 4 3 2 1 bit 0 write: $0320 pwmdty4 read: bit 7 6 5 4 3 2 1 bit 0 write: $0321 pwmdty5 read: bit 7 6 5 4 3 2 1 bit 0 write: $0322 pwmdty6 read: bit 7 6 5 4 3 2 1 bit 0 write: $0323 pwmdty7 read: bit 7 6 5 4 3 2 1 bit 0 write: $0324 pwmsdn read: pwmif pwmie 0 pwmlvl 0 pwm7in pwm7in l pwm7e na write: pwm rstrt $0325 reserved read: 00000000 write: $0326 reserved read: 00000000 write: $0327 reserved read: 00000000 write: $0328 - $033f address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0328 - $033f reserved read: 00000000 write: $0340 - $0367 periodic interrupt timer (pit) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0340 pitcflmt read: pite pitswai pitfrz 00000 write: pflmt1 pflmt0 $0341 pitflt read: 00000000 write: pflt3 pflt2 pflt1 pflt0 $0342 pitce read: 0000 pce3 pce2 pce1 pce0 write: $0343 pitmux read: 0000 pmux3 pmux2 pmux1 pmux0 write: $0300 - $0327 pulse width modulator 8 bit 8 channel (pwm) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 73 $0344 pitinte read: 0 0 0 pinte3 pinte2 pinte1 pinte0 write: $0345 pittf read: 0000 ptf3 ptf2 ptf1 ptf0 write: $0346 pitmtld0 read: pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 write: $0347 pitmtld1 read: pmtld7 pmtld6 pmtld5 pmtld4 pmtld3 pmtld2 pmtld1 pmtld0 write: $0348 pitld0 (hi) read: pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 write: $0349 pitld0 (lo) read: pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 write: $034a pitcnt0 (hi) read: pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 write: $034b pitcnt0 (lo) read: pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 write: $034c pitld1 (hi) read: pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 write: $034d pitld1 (lo) read: pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 write: $034e pitcnt1 (hi) read: pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 write: $034f pitcnt1 (lo) read: pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 write: $0350 pitld2 (hi) read: pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 write: $0351 pitld2 (lo) read: pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 write: $0352 pitcnt2 (hi) read: pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 write: $0353 pitcnt2 (lo) read: pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 write: $0354 pitld3 (hi) read: pld15 pld14 pld13 pld12 pld11 pld10 pld9 pld8 write: $0355 pitld3 (lo) read: pld7 pld6 pld5 pld4 pld3 pld2 pld1 pld0 write: $0356 pitcnt3 (hi) read: pcnt15 pcnt14 pcnt13 pcnt12 pcnt11 pcnt10 pcnt9 pcnt8 write: $0357 pitcnt3 (lo) read: pcnt7 pcnt6 pcnt5 pcnt4 pcnt3 pcnt2 pcnt1 pcnt0 write: $0358 - $0367 reserved read: 00000000 write: $0368 - $037f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0368 - $037f reserved read: 00000000 write: $0340 - $0367 periodic interrupt timer (pit) map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 74 $0380 - $03bf xgate map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0380 xgmctl read: 000000 0 xgiem write: xgem xgfrzm xgdbgm xgssm xgfact m $0381 reserved read: xge xgfrz xgdbg xgss xgfact 0 xgswei f xgie write: $0382 xgchid read: 0 xgchid[6:0] write: $0383 reserved read: 00000000 write: $0384 xgvbr read: 00000000 write: $0385 xgvbr read: 0000 xgvbr[19:16] write: $0386 xgvbr read: xgvbr[15:8] write: $0387 xgvbr read: xgvbr[7:1] 0 write: $0388 xgif read: 0000000 xgif_78 write: $0389 xgif read: xgif_77 xgif_76 xgif_75 xgif_74 xgif_73 xgif_72 xgif_71 xgif_70 write: $038a xgif read: xgif_6f xgif_6e xgif_6d xgif_6c xgif_6b xgif_6a xgif_69 xgif_68 write: $023b xgif read: xgif_67 xgif_66 xgif_65 xgif_64 xgif_63 xgif_62 xgif_61 xgif_60 write: $023c xgif read: xgif_5f xgif_5e xgif_5d xgif_5c xgif_5b xgif_5a xgif_59 xgif_58 write: $038d xgif read: xgif_57 xgif_56 xgif_55 xgif_54 xgif_53 xgif_52 xgif_51 xgif_50 write: $038e xgif read: xgif_4f xgif_4e xgif_4d xgif_4c xgif_4b xgif_4a xgif_49 xgif_48 write: $038f xgif read: xgif_47 xgif_46 xgif_45 xgif_44 xgif_43 xgif_42 xgif_41 xgif_40 write: $0390 xgif read: xgif_3f xgif_3e xgif_3d xgif_3c xgif_3b xgif_3a xgif_39 xgif_38 write: $0391 xgif read: xgif_37 xgif_36 xgif_35 xgif_34 xgif_33 xgif_32 xgif_31 xgif_30 write: $0392 xgif read: xgif_2f xgif_2e xgif_2d xgif_2c xgif_2b xgif_2a xgif_29 xgif_28 write: $0393 xgif read: xgif_27 xgif_26 xgif_25 xgif_24 xgif_23 xgif_22 xgif_21 xgif_20 write: $0394 xgif read: xgif_1f xgif_1e xgif_1d xgif_1c xgif_1b xgif_1a xgif_19 xgif_18 write: $0395 xgif read: xgif_17 xgif_16 xgif_15 xgif_14 xgif_13 xgif_12 xgif_11 xgif_10 write: $0396 xgif read: xgif_0f xgif_0e xgif_0d xgif_0c xgif_0b xgif_0a xgif_09 0 write: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 75 $0397 xgif read: 00000000 write: $0398 xgswt (hi) read: 00000000 write: xgswtm[7:0] $0399 xgswt (lo) read: xgswt[7:0] write: $039a xgsem (hi) read: 00000000 write: xgsemm[7:0] $039b xgsem (lo) read: xgsem[7:0] write: $039c reserved read: 00000000 write: $039d xgccr read: 0000 xgn xgz xgv xgc write: $039e xgpc (hi) read: xgpc[15:8] write: $039f xgpc (lo) read: xgpc[7:0] write: $03a0 reserved read: 00000000 write: $03a1 reserved read: 00000000 write: $03a2 xgr1 (hi) read: xgr1[15:8] write: $03a3 xgr1 (lo) read: xgr1[7:0] write: $03a4 xgr2 (hi) read: xgr2[15:8] write: $03a5 xgr2 (lo) read: xgr2[7:0] write: $03a6 xgr3 (hi) read: xgr3[15:8] write: $03a7 xgr3 (lo) read: xgr3[7:0] write: $03a8 xgr4 (hi) read: xgr4[15:8] write: $03a9 xgr4 (lo) read: xgr4[7:0] write: $03aa xgr5 (hi) read: xgr5[15:8] write: $03ab xgr5( lo) read: xgr5[7:0] write: $03ac xgr6 (hi) read: xgr6[15:8] write: $03ad xgr6 ( lo) read: xgr6[7:0] write: $0380 - $03bf xgate map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 76 1.6 part id assignments the part id is located in two 8-bit registers partidh and partidl (addresses $001a and $001b). the read-only value is a unique part id for each revision of the chip. table 1-2 shows the assigned part id number and mask set number. $03ae xgr7 (hi) read: xgr7[15:8] write: $03af xgr7 (lo) read: xgr7[7:0] write: $03b0 - $03bf reserved read: 00000000 write: $03c0 - $07ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $03c0 - $07ff reserved read: 00000000 write: table 1-2 assigned part id numbers device mask set number part id 1 notes : 1. the coding is as follows: bit 15-12: major family identifier bit 11-8: minor family identifier bit 7-4: major mask set revision number including fab transfers bit 3-0: minor - non full - mask set revision mc9s12xdp512 l40v $c400 mc9s12xdp512 l15y $c410 $0380 - $03bf xgate map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 77 section 2 signal description this section describes signals that connect off-chip. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. it is built from the signal description sections of the block user guides of the individual ip blocks on the device. 2.1 device pinout the xd-family of devices offers pin-compatible packaged devices to assist with system development and accommodate expansion of the application. the mc9s12xd-family and mc9s12xa-family devices are offered in the following package options: ? 144-pin lqfp package with an external bus interface (address/data bus) ? 112-pin lqfp without external bus interface ? 80-pin qfp without external bus interface most pins perform two or more functions, as described in more detail in section 2.2 signal properties summary . figure 2-1 , figure 2-2 and figure 2-3 show the pin assignments for the various packages. figure 2-1 mc9s12xd-family pin assignment 144 lqfp package f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 78 ss1/pwm3/kwp3/pp3 sck1/pwm2/kwp2/pp2 mosi1/pwm1/kwp1/pp1 miso1/pwm0/kwp0/pp0 cs1/kwj2/pj2 acc2/addr22/pk6 iqstat3/addr19/pk3 iqstat2/addr18/pk2 iqstat1/addr17/pk1 iqstat0/addr16/pk0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 acc1/addr21/pk5 acc0/addr20/pk4 txd2/kwj1/pj1 cs3/rxd2/kwj0/pj0 modc/bkgd vddx2 vssx2 data8/pc0 data9/pc1 data10/pc2 data11/pc3 uds/addr0/pb0 addr1/pb1 addr2/pb2 addr3/pb3 addr4/pb4 addr5/pb5 addr6/pb6 addr7/pb7 data12/pc4 data13/pc5 data14/pc6 data15/pc7 txd5/ ss2/kwh7/ph7 rxd5/sck2/kwh6/ph6 txd4/mosi2/kwh5/ph5 rxd4/miso2/kwh4/ph 4 xclks/ eclkx2/pe7 t a ghi/modb/pe6 re/t a glo/moda/pe5 eclk/pe4 vssr1 vddr1 reset vddpll xfc vsspll extal xtal test ss1/kwh3/ph3 sck1/kwh2/ph2 mosi1/kwh1/ph1 miso1/kwh0/ph0 pd0/data0 pd1/data1 pd2/data2 pd3/data3 lds/ lstrb/pe3/eromctl we/r/ w/pe2 irq/pe1 xirq/pe0 vrh vdda pad17/an17 pad16/an16 pad15/an15 pad07/an07 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vss2 vdd2 pd7/data7 pd6/data6 pd5/data5 pd4/data4 vddr2 vssr2 pa7/addr15 pa6/addr14 pa5/addr13 pa4/addr12 pa3/addr11 pa2/addr10 pa1/addr9 pa0/addr8 pp4/kwp4/pwm4/miso2 pp5/kpw5/pwm5/mosi2 pp6/kwp6/pwm6/ ss2 pp7/kwp7/pwm7/sck2 pk7/romctl/ ew ait vddx1 vssx1 pm0/rxcan0 pm1/txcan0 pm2/rxcan1/rxcan0/miso0 pm3/txcan1/txcan0/ ss0 pm4/rxcan2/rxcan0/rxcan4/mosi0 pm5/txcan2/txcan0/txcan4/sck0 pj4/kwj4/sda1/ cs0 pj5/kwj5/scl1/ cs2 pj6/kwj6/rxcan4/sda0/rxcan0 pj7/kwj7/txcan4/scl0/txcan0 vregen ps7/ ss0 ps6/sck0 ps5/mosi0 ps4/miso0 ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 pm6/rxcan3/rxcan4/rxd3 pm7/txcan3/txcan4/txd3 pad23/an23 pad22/an22 pad21/an21 pad20/an20 pad19/an19 pad18/an18 vssa vrl mc9s12xd-family 144 lqfp pins shown in bold are not available on the 80 qfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pins shown in bold-italics neither available on the 112 lqfp nor on the 80 qfp package option f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 79 figure 2-2 mc9s12xd-family pin assignments 112 lqfp package vrh vdda pad15/an15 pad07/an07 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vss2 vdd2 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 pp4/kwp4/pwm4/miso2 pp5/kpw5/pwm5/mosi2 pp6/kwp6/pwm6/ ss2 pp7/kwp7/pwm7/sck2 pk7 /romctl vddx vssx pm0/rxcan0 pm1/txcan0 pm2/rxcan1/rxcan0/miso0 pm3/txcan1/txcan0/ ss0 pm4/rxcan2/rxcan0/rxcan4/mosi0 pm5/txcan2/txcan0/txcan4/sck0 pj6/kwj6/rxcan4/sda0/rxcan0 pj7/kwj7/txcan4/scl0/txcan0 vregen ps7/ ss0 ps6/sck0 ps5/mosi0 ps4/miso0 ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 pm6/rxcan3/rxcan4/rxd3 pm7/txcan3/txcan4/txd3 vssa vrl ss1/pwm3/kwp3/pp3 sck1/pwm2/kwp2/pp2 mosi1/pwm1/kwp1/pp1 miso1/pwm0/kwp0/pp0 pk3 pk2 pk1 pk0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 pk5 pk4 txd2/kwj1/pj1 cs3/rxd2/kwj0/pj0 modc/bkgd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 txd5/ ss2/kwh7/ph7 rxd5/sck2/kwh6/ph6 txd4/mosi2/kwh5/ph5 rxd4/miso2/kwh4/ph4 xclks/pe7 modb/pe6 moda/pe5 eclk/pe4 vssr1 vddr1 reset vddpll xfc vsspll extal xtal test ss1/kwh3/ph3 sck1/kwh2/ph2 mosi1/kwh1/ph1 miso1/kwh0/ph0 pe3 pe2 irq/pe1 xirq/pe0 mc9s12xd-family 112lqfp 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 pins shown in bold are not available on the 80 qfp package f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 80 figure 2-3 mc9s12xd-family pin assignments 80 qfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 mc9s12xd-family 80 qfp vrh vdda pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vss2 vdd2 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 pp4/kwp4/pwm4/miso2 pp5/kwp5/pwm5/mosi2 pp7/kwp7/pwm7/sck2 vddx vssx pm0/rxcan0/rxb pm1/txcan0/txb pm2/rxcan1/rxcan0/miso0 pm3/txcan1/txcan0/ ss0 pm4/rxcan2/rxcan0/rxcan4/mosi0 pm5/txcan2/txcan0/txcan4/sck0 pj6/kwj6/rxcan4/sda0/rxcan0 pj7/kwj7/txcan4/scl0/txcan0 vregen ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 vssa vrl ss1/pwm3/kwp3/pp3 sck1/pwm2/kwp2/pp2 mosi1/pwm1/kwp1/pp1 miso1/pwm0/kwp0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 modc/bkgd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 xclks/pe7 modb/pe6 moda/pe5 eclk/pe4 vssr1 vddr1 reset vddpll xfc vsspll extal xtal test pe3 pe2 irq/pe1 xirq/pe0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 81 2.2 signal properties summary table 2-1 summarizes the pin functionality. table 2-1 signal properties summary pin name funct. 1 pin name funct. 2 pin name funct. 3 pin name funct. 4 pin name funct. 5 power supply internal pull resistor description ctrl reset state extal vddpll na na oscillator pins xtal vddpll na na reset vddr pullup external reset test n.a. reset pin down test input vregen vddx always on up voltage regulator enable input xfc vddpll na na pll loop filter bkgd modc vddr always on up background debug pad[23:08] an[23:8] vdda per0 ad1/ per1 ad1 disabled port ad inputs of atd1, analog inputs of atd1 pad[07:00] an[7:0] vdda per1 ad0 disabled port ad inputs of atd0, analog inputs of atd0 pa[7:0] addr[15:8] ivd[15:8] vddr pucr disabled port a i/o, address bus, internal visibility data pb[7:1] addr[7:1] ivd[7:0] vddr pucr disabled port b i/o, address bus, internal visibility data pb0 addr0 uds vddr pucr disabled port b i/o, address bus, upper data strobe pc[7:0] data[15:8] vddr pucr disabled port c i/o, data bus pd[7:0] data[7:0] vddr pucr disabled port d i/o, data bus pe7 eclkx2 xclks vddr pucr up port e i/o, system clock output, clock select pe6 t a ghi modb vddr while reset pin is low: down port e i/o, tag high, mode input pe5 re moda t a glo vddr while reset pin is low: down port e i/o, read enable, mode input, tag low input pe4 eclk vddr pucr up port e i/o, bus clock output pe3 lstrb lds eromctl vddr pucr up port e i/o, low byte data strobe, eromon control pe2 r/ w we vddr pucr up port e i/o, read/write pe1 irq vddr pucr up port e input, maskable interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 82 pe0 xirq vddr pucr up port e input, non maskable interrupt ph7 kwh7 ss2 txd5 vddr perh/ ppsh disabled port h i/o, interrupt, ss of spi2, txd of sci5 ph6 kwh6 sck2 rxd5 vddr perh/ ppsh disabled port h i/o, interrupt, sck of spi2, rxd of sci5 ph5 kwh5 mosi2 txd4 vddr perh/ ppsh disabled port h i/o, interrupt, mosi of spi2, txd of sci4 ph4 kwh4 miso2 rxd4 vddr perh/ ppsh disabled port h i/o, interrupt, miso of spi2, rxd of sci4 ph3 kwh3 ss1 vddr perh/ ppsh disabled port h i/o, interrupt, ss of spi1 ph2 kwh2 sck1 vddr perh/ ppsh disabled port h i/o, interrupt, sck of spi1 ph1 kwh1 mosi1 vddr perh/ ppsh disabled port h i/o, interrupt, mosi of spi1 ph0 kwh0 miso1 vddr perh/ ppsh disabled port h i/o, interrupt, miso of spi1 pj7 kwj7 txcan4 scl0 txcan0 vddx perj/ ppsj up port j i/o, interrupt, tx of can4, scl of iic0, tx of can0 pj6 kwj6 rxcan4 sda0 rxcan0 vddx perj/ ppsj up port j i/o, interrupt, rx of can4, sda of iic0, rx of can0 pj5 kwj5 scl1 cs2 vddx perj/ ppsj up port j i/o, interrupt, scl of iic1, chip select 2 pj4 kwj4 sda1 cs0 vddx perj/ ppsj up port j i/o, interrupt, sda of iic1, chip select 0 pj2 kwj2 cs1 vddx perj/ ppsj up port j i/o, interrupts, chip select 1 pj1 kwj1 txd2 vddx perj/ ppsj up port j i/o, interrupts, txd of sci2 pj0 kwj0 rxd2 cs3 vddx perj/ ppsj up port j i/o, interrupts, rxd of sci2 pk7 ew ait romctl vddx pucr up port k i/o, ewait input , rom on control pk[6:4] addr [22:20] acc[2:0] vddx pucr up port k i/o, extended addresses,access source for external access pk3 addr19 iqstat3 vddx pucr up extended address, pipe status pk2 addr18 iqstat2 vddx pucr up extended address, pipe status pk1 addr17 iqstat1 vddx pucr up extended address, pipe status pk0 addr16 iqstat0 vddx pucr up extended address, pipe status pm7 txcan3 txd3 txcan4 vddx perm/ ppsm disabled port m i/o, tx of can3&4, txd of sci3 pm6 rxcan3 rxd3 rxcan4 vddx perm/ ppsm disabled port m i/o rx of can3&4, rxd of sci3 pin name funct. 1 pin name funct. 2 pin name funct. 3 pin name funct. 4 pin name funct. 5 power supply internal pull resistor description ctrl reset state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 83 pm5 txcan2 txcan0 txcan4 sck0 vddx perm/ ppsm disabled port m i/ocan0, can2, can4, sck of spi0 pm4 rxcan2 rxcan0 rxcan4 mosi0 vddx perm/ ppsm disabled port m i/o, can0, can2, can4, mosi of spi0 pm3 txcan1 txcan0 ss0 vddx perm/ ppsm disabled port m i/o tx of can1, can0, ss of spi0 pm2 rxcan1 rxcan0 miso0 vddx perm/ ppsm disabled port m i/o, rx of can1, can0, miso of spi0 pm1 txcan0 vddx perm/ ppsm disabled port m i/o, tx of can0 pm0 rxcan0 vddx perm/ ppsm disabled port m i/o, rx of can0 pp7 kwp7 pwm7 sck2 vddx perp/ ppsp disabled port p i/o, interrupt, channel 7 of pwm, sck of spi2 pp6 kwp6 pwm6 ss2 vddx perp/ ppsp disabled port p i/o, interrupt, channel 6 of pwm, ss of spi2 pp5 kwp5 pwm5 mosi2 vddx perp/ ppsp disabled port p i/o, interrupt, channel 5 of pwm, mosi of spi2 pp4 kwp4 pwm4 miso2 vddx perp/ ppsp disabled port p i/o, interrupt, channel 4 of pwm, miso2 of spi2 pp3 kwp3 pwm3 ss1 vddx perp/ ppsp disabled port p i/o, interrupt, channel 3 of pwm, ss of spi1 pp2 kwp2 pwm2 sck1 vddx perp/ ppsp disabled port p i/o, interrupt, channel 2 of pwm, sck of spi1 pp1 kwp1 pwm1 mosi1 vddx perp/ ppsp disabled port p i/o, interrupt, channel 1 of pwm, mosi of spi1 pp0 kwp0 pwm0 miso1 vddx perp/ ppsp disabled port p i/o, interrupt, channel 0 of pwm, miso2 of spi1 ps7 ss0 vddx pers/ ppss up port s i/o, ss of spi0 ps6 sck0 vddx pers/ ppss up port s i/o, sck of spi0 ps5 mosi0 vddx pers/ ppss up port s i/o, mosi of spi0 ps4 miso0 vddx pers/ ppss up port s i/o, miso of spi0 ps3 txd1 vddx pers/ ppss up port s i/o, txd of sci1 ps2 rxd1 vddx pers/ ppss up port s i/o, rxd of sci1 ps1 txd0 vddx pers/ ppss up port s i/o, txd of sci0 pin name funct. 1 pin name funct. 2 pin name funct. 3 pin name funct. 4 pin name funct. 5 power supply internal pull resistor description ctrl reset state f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 84 note: for devices assembled in 80-pin and 112-pin packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. refer to table 2-1 for affected pins. 2.3 detailed signal descriptions 2.3.1 extal, xtal oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. 2.3.2 reset external reset pin the reset pin is an active low bidirectional control signal. it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset.the reset pin has an internal pullup device. 2.3.3 test test pin this input only pin is reserved for test. this pin has a pulldown device. note: the test pin must be tied to vss in all applications. 2.3.4 vregen voltage regulator enable pin this input only pin enables or disables the on-chip voltage regulator. the input has a pullup device. ps0 rxd0 vddx pers/ ppss up port s i/o, rxd of sci0 pt[7:0] ioc[7:0] vddx pert/ ppst disabled port t i/o, timer channels pin name funct. 1 pin name funct. 2 pin name funct. 3 pin name funct. 4 pin name funct. 5 power supply internal pull resistor description ctrl reset state . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 85 2.3.5 xfc pll loop filter pin please ask your motorola representative for the interactive application note to compute pll loop filter elements. any current leakage on this pin must be avoided. figure 2-4 pll loop filter connections 2.3.6 bkgd / modc background debug and mode pin the bkgd/modc pin is used as a pseudo-open-drain pin for the background debug communication. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset. the bkgd pin has a pullup device. 2.3.7 pad[23:08] / an[23:8] port ad input pin of atd1 pad[23:08] are general purpose input or output pins and analog inputs an[23:8] of the analog to digital converter atd1. 2.3.8 pad[07:00] / an[7:0] port ad input pins of atd0 pad[07:00] are general purpose input or output pins and analog inputs an[7:0] of the analog to digital converter atd0. 2.3.9 pa[7:0] / addr[15:8] / ivd[15:8] port a i/o pins pa7-pa0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the external address bus. in mcu emulation modes of operation, these pins are used for external address bus and internal visibility read data. 2.3.10 pb[7:1] / addr[7:1] / ivd[7:1] port b i/o pins pb7-pb1 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the external address bus. in mcu emulation modes of operation, these pins are used for external address bus and internal visibility read data. mcu xfc r 0 c s c p vddpll vddpll f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 86 2.3.11 pb0 / addr0 / uds / ivd[0] port b i/o pin pb0 is a general purpose input or output pin. in mcu expanded modes of operation, this pin is used for the external address bus addr0 or as upper data strobe signal. in mcu emulation modes of operation, this pin is used for external address bus addr0 and internal visibility read data ivd0. 2.3.12 pc[7:0] / data [15:8] port c i/o pins pc7-pc0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the external data bus. the input voltage thresholds for pc[7:0] can be configured to reduced levels, to allow data from an external 3.3v peripheral to be read by the mcu operating at 5.0v. the input voltage thresholds for pc[7:0] are configured to reduced levels out of reset in expanded and emulation modes. the input voltage thresholds for pc[7:0] are configured to 5v levels out of reset in normal modes. 2.3.13 pd[7:0] / data [7:0] port d i/o pins pd7-pd0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the external data bus. the input voltage thresholds for pd[7:0] can be configured to reduced levels, to allow data from an external 3.3v peripheral to be read by the mcu operating at 5.0v. the input voltage thresholds for pd[7:0] are configured to reduced levels out of reset in expanded and emulation modes. the input voltage thresholds for pc[7:0] are configured to 5v levels out of reset in normal modes. 2.3.14 pe7 / eclkx2 / xclks port e i/o pin 7 pe7 is a general purpose input or output pin. the xclks is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) pierce oscillator is used or whether full swing pierce oscillator/external clock circuitry is used. the xclks pin selects the oscillator configuration during reset low phase while a clock quality check is ongoing. this is the case for: ? power on reset or low voltage reset ? clock monitor reset ? any reset while in self clock mode or full stop mode the selected oscillator configuration is frozen with the rising edge of reset. the pin can be configured to drive the internal system clock eclkx2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 87 figure 2-5 loop controlled pierce oscillator connections (pe7=1) figure 2-6 full swing pierce oscillator connections (pe7=0) figure 2-7 external clock connections (pe7=0) mcu extal xtal vsspll crystal or ceramic resonator c 2 c 1 mcu extal xtal r s * r b vsspll crystal or ceramic resonator c 2 c 1 mcu extal xtal cmos-compatible external oscillato r not connected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 88 2.3.15 pe6 / modb / taghi port e i/o pin 6 pe6 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset. this pin is an input with a pull-down device which is only active when reset is low. taghi is used to tag the high half of the instruction word being read into the instruction queue. the input voltage threshold for pe6 can be configured to reduced levels, to allow data from an external 3.3v peripheral to be read by the mcu operating at 5.0v. the input voltage threshold for pe6 is configured to reduced levels out of reset in expanded and emulation modes. 2.3.16 pe5 / moda / taglo / re port e i/o pin 5 pe5 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset. this pin is shared with the read enable re output. this pin is an input with a pull-down device which is only active when reset is low. taglo is used to tag the low half of the instruction word being read into the instruction queue. the input voltage threshold for pe5 can be configured to reduced levels, to allow data from an external 3.3v peripheral to be read by the mcu operating at 5.0v. the input voltage threshold for pe5 is configured to reduced levels out of reset in expanded and emulation modes. 2.3.17 pe4 / eclk port e i/o pin 4 pe4 is a general purpose input or output pin. it can be configured to drive the internal bus clock eclk. eclk can be used as a timing reference. 2.3.18 pe3 / lstrb / lds / eromctl port e i/o pin 3 pe3 is a general purpose input or output pin. in mcu expanded modes of operation, lstrb or lds can be used for the low byte strobe function to indicate the type of bus access. at the rising edge of reset the state of this pin is latched to the eromon bit. 2.3.19 pe2 / r/ w / we port e i/o pin 2 pe2 is a general purpose input or output pin. in mcu expanded modes of operations, this pin drives the read/write output signal or write enable output signal for the external bus. it indicates the direction of data on the external bus. 2.3.20 pe1 / irq port e input pin 1 pe1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 89 2.3.21 pe0 / xirq port e input pin 0 pe0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.3.22 ph7 / kwh7 / ss2 / txd5 port h i/o pin 7 ph7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as slave select pin ss of the serial peripheral interface 2 (spi2). it can be configured as the transmit pin txd of serial communication interface 5 (sci5). 2.3.23 ph6 / kwh6 / sck2 / rxd5 port h i/o pin 6 ph6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as serial clock pin sck of the serial peripheral interface 2 (spi2). it can be configured as the receive pin rxd of serial communication interface 5 (sci5). 2.3.24 ph5 / kwh5 / mosi2 / txd4 port h i/o pin 5 ph5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 2 (spi2). it can be configured as the transmit pin txd of serial communication interface 4 (sci4). 2.3.25 ph4 / kwh4 / miso2 / rxd4 port h i/o pin 2 ph4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 2 (spi2). it can be configured as the receive pin rxd of serial communication interface 4 (sci4). 2.3.26 ph3 / kwh3 / ss1 port h i/o pin 3 ph3 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as slave select pin ss of the serial peripheral interface 1 (spi1). 2.3.27 ph2 / kwh2 / sck1 port h i/o pin 2 ph2 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as serial clock pin sck of the serial peripheral interface 1 (spi1). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 90 2.3.28 ph1 / kwh1 / mosi1 port h i/o pin 1 ph1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 1 (spi1). 2.3.29 ph0 / kwh0 / miso1 port h i/o pin 0 ph0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 1 (spi1). 2.3.30 pj7 / kwj7 / txcan4 / scl0 / txcan0 port j i/o pin 7 pj7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the transmit pin txcan for the motorola scalable controller area network controller 0 or 4 (can0 or can4) or as the serial clock pin scl of the iic0 module. 2.3.31 pj6 / kwj6 / rxcan4 / sda0 / rxcan0 port j i/o pin 6 pj6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the receive pin rxcan for the motorola scalable controller area network controller 0 or 4 (can0 or can4) or as the serial data pin sda of the iic0 module. 2.3.32 pj5 / kwj5 / scl1 / cs2 port j i/o pin 5 pj5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the serial clock pin scl of the iic1 module. it can be configured to provide a chip select output. 2.3.33 pj4 / kwj4 / sda1 / cs0 port j i/o pin 4 pj4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the serial data pin sda of the iic1 module. it can be configured to provide a chip select output. 2.3.34 pj2 / kwj2 / cs1 port j i/o pin 2 pj2 is a general purpose input or output pins. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured to provide a chip select output. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 91 2.3.35 pj1 / kwj1 / txd2 port j i/o pin 1 pj1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the transmit pin txd of the serial communication interface 2 (sci2). 2.3.36 pj0 / kwj0 / rxd2 / cs3 port j i/o pin 0 pj0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the receive pin rxd of the serial communication interface 2 (sci2).it can be configured to provide a chip select output. 2.3.37 pk7 / ewait / romctl port k i/o pin 7 pk7 is a general purpose input or output pin. during mcu emulation modes and normal expanded modes of operation, this pin is used to enable the flash eeprom memory in the memory map (romctl). at the rising edge of reset, the state of this pin is latched to the romon bit. the ewait input signal maintains the external bus access until the external device is ready to capture data (write) or provide data (read). the input voltage threshold for pk7 can be configured to reduced levels, to allow data from an external 3.3v peripheral to be read by the mcu operating at 5.0v. the input voltage threshold for pk7 is configured to reduced levels out of reset in expanded and emulation modes. 2.3.38 pk[6:4] / addr[22:20] / acc[2:0] port k i/o pin [6:4] pk[6:4] are general purpose input or output pins. during mcu expanded modes of operation, the acc[2:0] signals are used to indicate the access source of the bus cycle . this pins also provide the expanded addresses addr[22:20] for the external bus. in emulation modes acc[2:0] is available and is time multiplexed with the high addresses 2.3.39 pk[3:0] / addr[19:16] / iqstat[3:0] port k i/o pins [3:0] pk3-pk0 are general purpose input or output pins. in mcu expanded modes of operation, these pins provide the expanded address addr[19:16] for the external bus and carry instruction pipe information. 2.3.40 pm7 / txcan3 / txcan4 / txd3 port m i/o pin 7 pm7 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controller 3 or 4 (can3 or can4). pm7 can be configured as the transmit pin txd3 of the serial communication interface 3 (sci3). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 92 2.3.41 pm6 / rxcan3 / rxcan4 / rxd3 port m i/o pin 6 pm6 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controller 3 or 4 (can3 or can4). pm6 can be configured as the receive pin rxd3 of the serial communication interface 3 (sci3). 2.3.42 pm5 / txcan0 / txcan2 / txcan4 / sck0 port m i/o pin 5 pm5 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controllers 0, 2 or 4 (can0, can2 or can4). it can be configured as the serial clock pin sck of the serial peripheral interface 0 (spi0). 2.3.43 pm4 / rxcan0 / rxcan2 / rxcan4 / mosi0 port m i/o pin 4 pm4 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controllers 0,2 or 4 (can0, can2 or can4). it can be configured as the master output (during master mode) or slave input pin (during slave mode) mosi for the serial peripheral interface 0 (spi0). 2.3.44 pm3 / txcan1 / txcan0 / ss0 port m i/o pin 3 pm3 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controllers 1 or 0 (can1 or can0). it can be configured as the slave select pin ss of the serial peripheral interface 0 (spi0). 2.3.45 pm2 / rxcan1 / rxcan0 / miso0 port m i/o pin 2 pm2 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controllers 1 or 0 (can1 or can0). it can be configured as the master input (during master mode) or slave output pin (during slave mode) miso for the serial peripheral interface 0 (spi0). 2.3.46 pm1 / txcan0 port m i/o pin 1 pm1 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controller 0 (can0). 2.3.47 pm0 / rxcan0 port m i/o pin 0 pm0 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controller 0 (can0). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 93 2.3.48 pp7 / kwp7 / pwm7 / sck2 port p i/o pin 7 pp7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 7 output. it can be configured as serial clock pin sck of the serial peripheral interface 2 (spi2). 2.3.49 pp6 / kwp6 / pwm6 / ss2 port p i/o pin 6 pp6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 6 output. it can be configured as slave select pin ss of the serial peripheral interface 2 (spi2). 2.3.50 pp5 / kwp5 / pwm5 / mosi2 port p i/o pin 5 pp5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 5 output. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 2 (spi2). 2.3.51 pp4 / kwp4 / pwm4 / miso2 port p i/o pin 4 pp4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 4 output. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 2 (spi2). 2.3.52 pp3 / kwp3 / pwm3 / ss1 port p i/o pin 3 pp3 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 3 output. it can be configured as slave select pin ss of the serial peripheral interface 1 (spi1). 2.3.53 pp2 / kwp2 / pwm2 / sck1 port p i/o pin 2 pp2 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 2 output. it can be configured as serial clock pin sck of the serial peripheral interface 1 (spi1). 2.3.54 pp1 / kwp1 / pwm1 / mosi1 port p i/o pin 1 pp1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 1 output. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 1 (spi1). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 94 2.3.55 pp0 / kwp0 / pwm0 / miso1 port p i/o pin 0 pp0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 0 output. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 1 (spi1). 2.3.56 ps7 / ss0 port s i/o pin 7 ps7 is a general purpose input or output pin. it can be configured as the slave select pin ss of the serial peripheral interface 0 (spi0). 2.3.57 ps6 / sck0 port s i/o pin 6 ps6 is a general purpose input or output pin. it can be configured as the serial clock pin sck of the serial peripheral interface 0 (spi0). 2.3.58 ps5 / mosi0 port s i/o pin 5 ps5 is a general purpose input or output pin. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 2.3.59 ps4 / miso0 port s i/o pin 4 ps4 is a general purpose input or output pin. it can be configured as master input (during master mode) or slave output pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 2.3.60 ps3 / txd1 port s i/o pin 3 ps3 is a general purpose input or output pin. it can be configured as the transmit pin txd of serial communication interface 1 (sci1). 2.3.61 ps2 / rxd1 port s i/o pin 2 ps2 is a general purpose input or output pin. it can be configured as the receive pin rxd of serial communication interface 1 (sci1). 2.3.62 ps1 / txd0 port s i/o pin 1 ps1 is a general purpose input or output pin. it can be configured as the transmit pin txd of serial communication interface 0 (sci0). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 95 2.3.63 ps0 / rxd0 port s i/o pin 0 ps0 is a general purpose input or output pin. it can be configured as the receive pin rxd of serial communication interface 0 (sci0). 2.3.64 pt[7:0] / ioc[7:0] port t i/o pins [7:0] pt7-pt0 are general purpose input or output pins. they can be configured as input capture or output compare pins ioc7-ioc0 of the enhanced capture timer (ect). 2.4 power supply pins mc9s12xdp512 power and ground pins are described below. note: all vss pins must be connected together in the application. 2.4.1 vddx1, vddx2, vssx1,vssx2 power & ground pins for i/o drivers external power and ground for i/o drivers. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. 2.4.2 vddr1, vddr2, vssr1, vssr2 power & ground pins for i/o drivers & for internal voltage regulator external power and ground for i/o drivers and input to the internal voltage regulator. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. 2.4.3 vdd1, vdd2, vss1, vss2 core power pins power is supplied to the mcu through vdd and vss. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. this 2.5v supply is derived from the internal voltage regulator. there is no static load on those pins allowed. the internal voltage regulator is turned off, if vregen is tied to ground. note: no load allowed except for bypass capacitors. 2.4.4 vdda, vssa power supply pins for atd and vreg vdda, vssa are the power supply and ground input pins for the voltage regulator and the analog to digital converters. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 96 2.4.5 vrh, vrl atd reference voltage input pins vrh and vrl are the reference voltage input pins for the analog to digital converter. 2.4.6 vddpll, vsspll power supply pins for pll provides operating voltage and ground for the oscillator and the phased-locked loop. this allows the supply voltage to the oscillator and pll to be bypassed independently.this 2.5v voltage is generated by the internal voltage regulator. note: no load allowed except for bypass capacitors. table 2-2 mc9s12xdp512 power and ground connection summary mnemonic pin number nominal voltage description 144-pin lqfp 112-pin lqfp 80-pin qfp vdd1, 2 15, 87 13, 65 9, 49 2.5 v internal power and ground generated by internal regulator vss1, 2 16, 88 14, 66 10, 50 0v vddr1 53 41 29 5.0 v external power and ground, supply to pin drivers and internal voltage regulator vssr1 52 40 28 0 v vddx1 139 107 77 5.0 v external power and ground, supply to pin drivers vssx1 138 106 76 0 v vddx2 26 n.a. n.a. 5.0 v external power and ground, supply to pin drivers vssx2 27 n.a. n.a. 0 v vddr2 82 n.a. n.a. 5.0 v external power and ground, supply to pin drivers vssr2 81 n.a. n.a. 0 v vdda 107 83 59 5.0 v operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the a/d to be bypassed independently. vssa 110 86 62 0 v vrl 109 85 61 0 v reference voltages for the analog-to-digital converter. vrh 108 84 60 5.0 v vddpll 55 43 31 2.5 v provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. vsspll 57 45 33 0 v vregen 127 97 n.a. 5v internal voltage regulator enable/disable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 97 2.4.7 vregen on chip voltage regulator enable enables the internal 5v to 2.5v voltage regulator. if this pin is tied low, vdd1,2 and vddpll must be supplied externally. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 98 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 99 section 3 system clock description 3.1 overview the clock and reset generator module (crg) provides the internal clock signals for the core and all peripheral modules. figure 3-1 shows the clock connections from the crg to all modules. consult the crg block user guide for details on clock generation. figure 3-1 clock connections sci0 . . sci 5 spi0 . . spi2 iic0 & iic1 atd0 & atd1 can0 . . can4 crg bus clock extal xtal core clock oscillator clock ram s12x xgate eeprom flash pit ect pim f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 100 the mcus system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: ? the on chip phase locked loop (pll) ? the pll self clocking ? the oscillator the clock generated by the pll or oscillator provides the main system clock frequencies core clock and bus clock. as shown in figure 3-1 this system clocks are used throughout the mcu to drive the core, the memories and the peripherals. the program flash memory and the eeprom are supplied by the bus clock and the oscillator clock.the oscillator clock is used as a time base to derive the program and erase times for the nvms. consult the ftx512k4 block guide and the eetx4k block guide for more details on the operation of the nvms. the can modules may be configured to have their clock sources derived either from the bus clock or directly from the oscillator clock. this allows the user to select its clock based on the required jitter performance. consult mscan block description for more details on the operation and configuration of the can blocks. the frequency generated by the pll is determined by the two registers refdiv and synr. please note that it is possible to configure the pll to generate a system frequency higher than that supported by the design of the device. it is the responsibility of the user to insure that the device is operated within its specified limits at all time. in order to ensure the presence of the clock the mcu includes an on-chip clock monitor connected to the output of the oscillator. the clock monitor can be configured to invoke the pll self clocking mode or to generate a system reset if it is allowed to time out as a result of no oscillator clock being present. in addition to the clock monitor the mcu also provides a clock quality checker which performs a more accurate check of the clock. the clock quality checker counts a predetermined number of clock edges within a defined time window to insure that the clock is running. the checker can be invoked following specific events such as on wake-up or clock monitor failure. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 101 section 4 modes of operation 4.1 overview the mcu can operate in six different user modes. the different user modes, the state of romctl and eromctl pin on rising edge of reset and the security state of the mcu affects the following device characteristics: ? external bus interface configuration ? flash in memory map or not ? debug features enabled or disabled the xclks pin defines the configuration of the on chip oscillator and the vregen pin defines whether the on chip voltage regulator is enabled or disabled. 4.2 user modes 4.2.1 normal expanded mode ports k, a and b are configured as a 23-bit address bus, ports c and d are configured as a 16-bit data bus, and port e provides bus control and status signals. this mode allows 16-bit external memory and peripheral devices to be interfaced to the system. the fastest external bus rate is divide by 2 from the internal bus rate. 4.2.2 normal single-chip mode there is no external bus in this mode. the processor program is executed from internal memory. ports a, b,c,d, k, and most pins of port e are available as general-purpose i/o. 4.2.3 special single-chip mode this mode is used for debugging single-chip operation, boot-strapping, or security related operations. the background debug module bdm is active in this mode. the cpu executes a monitor program located in an on-chip rom. bdm firmware is waiting for additional serial commands through the bkgd pin. there is no external bus after reset in this mode. 4.2.4 emulation of expanded mode developers use this mode for emulation systems in which the users target application is normal expanded mode. code is executed from external memory or from internal memory depending on the state of romon and eromon bit. in this mode the internal operation is visible on external bus interface. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 102 4.2.5 emulation of single-chip mode developers use this mode for emulation systems in which the user s target application is normal single-chip mode. code is executed from external memory or from internal memory depending on the state of romon and eromon bit . in this mode the internal operation is visible on external bus interface. 4.2.6 special test mode motorola internal use only. 4.3 low power modes the microcontroller features two main low power modes. consult the respective block guide for information on the module behavior in system stop, system pseudo stop, and system wait mode. an important source of information about the clock system is the clock and reset generator block guide (crg). 4.3.1 system stop modes the system stop modes are entered if the cpu executes the stop instruction and the xgate doesnt execute a thread and the xgfact bit in the xgmctl register is cleared. depending on the state of the pstp bit in the clksel register the mcu goes into pseudo stop mode or full stop mode. please refer to crg block guide. asserting reset , xirq , irq or any other interrupt end the system stop modes. 4.3.1.1 pseudo stop mode in this mode the clocks are stopped but the oscillator is still running and the real time interrupt (rti) or watchdog (cop) sub module can stay active. other peripherals are turned off. this mode consumes more current than the system stop mode, but the wake up time from this mode is significantly shorter. 4.3.1.2 full stop mode the oscillator is stopped in this mode. all clocks are switched off. all counters and dividers remain frozen. 4.3.2 system wait mode this mode is entered when the cpu executes the wai instruction. in this mode the cpu will not execute instructions. the internal cpu clock is switched off. all peripherals and the xgate can be active in system wait mode. for further power consumption the peripherals can individually turn off their local clocks. asserting reset , xirq , irq or any other interrupt that has not been masked ends system wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 103 4.3.3 run mode although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. 4.4 freeze mode the enhanced capture timer, pulse width modulator, analog digital converters and the periodic interrupt timer provide a software programmable option to freeze the module status during the background debug module is active. this is useful when debugging application software. for detailed description of the behavior of the atd0, atd1, ect, pwm and pit during background debug module is active consult the corresponding block guides. 4.5 chip configuration summary 4.5.1 mode selection the operating mode out of reset is determined by the states of the modc , modb , and moda pins during reset ( table 4-1 ). the modc, modb, and moda bits in the mode register show the current operating mode and provide limited mode switching during operation. the states of the modc , modb , and moda pins are latched into these bits on the rising edge of reset . table 4-1 mode selection 4.5.2 romon and eromon configuration in normal expanded mode and in emulation modes the romon bit and the eromon bit in the misc register defines if the on chip flash memory is the memory map or not. for a detailed description of the romon and eromon bits refer to the s12xmmc block guide. the state of the romctl pin ( pk7 ) is latched into the romon bit in the misc register on the rising edge of the reset . the state of the eromctl pin ( pe3 ) is latched into the eromon bit in the misc register on the rising edge of the reset . bkgd = modc pe6 = modb pe5 = moda mode description 000 special single chip mode 011 emulation expanded mode 010 special test mode 001 emulation single chip mode 100 normal single chip mode 101 normal expanded mode 11x reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 104 4.5.3 oscillator configuration the configuration of the oscillator can be selected using the xclks pin. (see table 4-2 ) for a detailed description please refer to the crg block guide. 4.5.4 voltage regulator control the logic level on the voltage regulator enable pin vregen determines whether the on chip voltage regulator is enabled or disabled. (see table 4-3 ) 4.6 security the mcu security feature allows the the protection of the on chip flash and eeprom memory. for a detailed description of the security features refer to the s12x9sec block guide. table 4-2 clock selection based on pe7 pe7 = xclks description 0 full swing pierce oscillator or external clock source selected 1 loop controlled pierce oscillator selected table 4-3 voltage regulator vregen vregen description 1 internal voltage regulator enabled 0 internal voltage regulator disabled, vdd1,2 and vddpll must be supplied externally f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 105 section 5 resets and interrupts 5.1 overview consult the s12xcpu block guide for information on exception processing. 5.2 vectors 5.2.1 vector table table 5-1 lists all interrupt sources and vectors in the default order of priority. the interrupt module (s12xint) provides an interrupt vector base register (ivbr) to relocate the vectors. associated with each i-bit maskable service request is a configuration register.it selects if the service request is enabled, the service request priority level and whether the service request is handled either by the s12x cpu or by the xgate module. the hprio register and functionality is no longer supported on the s12x devices. this functionality is superseded by a 7 level service request priority scheme. please refer to the s12xint block guide for detailed information. table 5-1 interrupt vector locations vector address 1 xgate channel id 2 interrupt source ccr mask local enable $fffe, - system reset none none $fffc - clock monitor reset none pllctl (cme, scme) $fffa - cop watchdog reset none cop rate select vector base + $f8 - unimplemented instruction trap none none vector base+ $f6 - swi none none vector base+ $f4 - xirq x-bit none vector base+ $f2 - irq i-bit irqcr (irqen) vector base+ $f0 $78 real time interrupt i-bit crgint (rtie) vector base+ $ee $77 enhanced capture timer channel 0 i-bit tie (c0i) vector base + $ec $76 enhanced capture timer channel 1 i-bit tie (c1i) vector base+ $ea $75 enhanced capture timer channel 2 i-bit tie (c2i) vector base+ $e8 $74 enhanced capture timer channel 3 i-bit tie (c3i) vector base+ $e6 $73 enhanced capture timer channel 4 i-bit tie (c4i) vector base+ $e4 $72 enhanced capture timer channel 5 i-bit tie (c5i) vector base + $e2 $71 enhanced capture timer channel 6 i-bit tie (c6i) vector base+ $e0 $70 enhanced capture timer channel 7 i-bit tie (c7i) vector base+ $de $6f enhanced capture timer over?ow i-bit tsrc2 (tof) vector base+ $dc $6e pulse accumulator a over?ow i-bit pactl (paovi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 106 vector base + $da $6d pulse accumulator input edge i-bit pactl (pai) vector base + $d8 $6c spi0 i-bit spi0cr1 (spie, sptie) vector base+ $d6 $6b sci0 i-bit sci0cr2 (tie, tcie, rie, ilie) vector base + $d4 $6a sci1 i-bit sci1cr2 (tie, tcie, rie, ilie) vector base + $d2 $69 atd0 i-bit atd0ctl2 (ascie) vector base + $d0 $68 atd1 i-bit atd1ctl2 (ascie) vector base + $ce $67 port j i-bit piej (piej7-piej0) vector base + $cc $66 port h i-bit pieh (pieh7-pieh0) vector base + $ca $65 modulus down counter under?ow i-bit mcctl(mczi) vector base + $c8 $64 pulse accumulator b over?ow i-bit pbctl(pbovi) vector base + $c6 $63 crg pll lock i-bit crgint(lockie) vector base + $c4 $62 crg self clock mode i-bit crgint (scmie) vector base + $c2 $61 reserved vector base + $c0 $60 iic0 bus i-bit ibcr0 (ibie) vector base + $be $5f spi1 i-bit spi1cr1 (spie, sptie) vector base + $bc $5e spi2 i-bit spi2cr1 (spie, sptie) vector base + $ba $5d eeprom i-bit ecnfg (ccie, cbeie) vector base + $b8 $5c flash i-bit fcnfg (ccie, cbeie) vector base + $b6 $5b can0 wake-up i-bit can0rier (wupie) vector base + $b4 $5a can0 errors i-bit can0rier (cscie, ovrie) vector base + $b2 $59 can0 receive i-bit can0rier (rxfie) vector base + $b0 $58 can0 transmit i-bit can0tier (txeie2-txeie0) vector base + $ae $57 can1 wake-up i-bit can1rier (wupie) vector base + $ac $56 can1 errors i-bit can1rier (cscie, ovrie) vector base + $aa $55 can1 receive i-bit can1rier (rxfie) vector base + $a8 $54 can1 transmit i-bit can1tier (txeie2-txeie0) vector base + $a6 $53 can2 wake-up i-bit can2rier (wupie) vector base + $a4 $52 can2 errors i-bit can2rier (cscie, ovrie) vector base + $a2 $51 can2 receive i-bit can2rier (rxfie) vector base + $a0 $50 can2 transmit i-bit can2tier (txeie2-txeie0) vector base + $9e $4f can3 wake-up i-bit can3rier (wupie) vector base+ $9c $4e can3 errors i-bit can3rier (cscie, ovrie) vector base+ $9a $4d can3 receive i-bit can3rier (rxfie) vector base + $98 $4c can3 transmit i-bit can3tier (txeie2-txeie0) vector base + $96 $4b can4 wake-up i-bit can4rier (wupie) vector base + $94 $4a can4 errors i-bit can4rier (cscie, ovrie) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 107 5.3 effects of reset when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block guides for register reset states. vector base + $92 $49 can4 receive i-bit can4rier (rxfie) vector base + $90 $48 can4 transmit i-bit can4tier (txeie2-txeie0) vector base + $8e $47 port p interrupt i-bit piep (piep7-piep0) vector base+ $8c $46 pwm emergency shutdown i-bit pwmsdn (pwmie) vector base + $8a $45 sci2 i-bit sci2cr2 (tie, tcie, rie, ilie) vector base + $88 $44 sci3 i-bit sci3cr2 (tie, tcie, rie, ilie) vector base + $86 $43 sci4 i-bit sci4cr2 (tie, tcie, rie, ilie) vector base + $84 $42 sci5 i-bit sci5cr2 (tie, tcie, rie, ilie) vector base + $82 $41 iic1 bus i-bit ibcr (ibie) vector base + $80 $40 low voltage interrupt lvi i-bit vregctrl (lvie) vector base + $7e $3f autonomous periodical interrupt api i-bit vregapictrl (apie) vector base + $7c $3e reserved vector base + $7a $3d periodic interrupt timer i-bit pitinte (pinte0) vector base + $78 $3c periodic interrupt timer i-bit pitinte (pinte1) vector base + $76 $3b periodic interrupt timer i-bit pitinte (pinte2) vector base + $74 $3a periodic interrupt timer i-bit pitinte (pinte3) vector base + $72 $39 xgate software trigger 0 i-bit xgmctl (xgie) vector base + $70 $38 xgate software trigger 1 i-bit xgmctl (xgie) vector base + $6e $37 xgate software trigger 2 i-bit xgmctl (xgie) vector base + $6c $36 xgate software trigger 3 i-bit xgmctl (xgie) vector base + $6a $35 xgate software trigger 4 i-bit xgmctl (xgie) vector base + $68 $34 xgate software trigger 5 i-bit xgmctl (xgie) vector base + $66 $33 xgate software trigger 6 i-bit xgmctl (xgie) vector base + $64 $32 xgate software trigger 7 i-bit xgmctl (xgie) vector base + $62 - xgate software error interrupt i-bit xgmctl (xgie) vector base + $60 - sram32k access violation i-bit ramwpc (avie) vector base+ $12 to vector base + $5e reserved vector base + $10 - spurious interrupt - none notes : 1. 16 bits vector address based 2. for detailed description of xgate channel id refer to xgate block guide f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 108 5.3.1 i/o pins refer to the pim block guide for reset configurations of all peripheral module ports. 5.3.2 memory the ram array is not initialized out of reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 109 section 6 s12x_cpu block description consult the s12x_cpu block guide for information about the s12xcpu module. section 7 s12x_mmc block description consult the s12x_mmc block guide for information about the s12xmmc module. section 8 s12_xebi block description consult the s12x_ebi block guide for information about the s12xebi module. section 9 s12_xint block description consult the s12x_int block guide for information about the s12xint module. section 10 s12x_dbg block description consult the s12x_dbg block guide for information about the s12xdbg module. section 11 s12x_bdm block description consult the s12x_bdm block guide for information about the s12xbdm module. section 12 xgate block description consult the xgate block guide for information about the co-processor. section 13 periodic interrupt timer (pit) block description the periodic interrupt timer module contains four hardware trigger signal lines pittrig0, pittrig1, pittrig2 and pittrig3. one for each timer channel. table 17-1 and table 18-1 show the connection of these trigger outputs on mc9s12xdp512 device. the trigger signal lines pittrig2 and pittrig3 are not used on mc9s12xdp512. consult the pit block guide for information about the periodic interrupt timer module.when the pit block guide refers to freeze mode this is equivalent to active bdm mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 110 section 14 oscillator (osc_lcp) block consult the osc_lcp block guide for information about the oscillator module. section 15 clock and reset generator (crg) block description the cop timeout rate bits cr[2:0] and the wcop bit in the copctl register are loaded on rising edge of reset from the flash control register fctl ($0107) located in the flash eeprom block. see table 15-1 and table 15-2 for coding. the fctl register is loaded from the flash configuration field byte at global address $7f_ff0e during the reset sequence. for more information on fctl register refer to the ftx512k4 block guide. consult the crg block guide for information about the clock and reset generator module. table 15-1 initial cop rate con?guration nv[2:0] in fctl register cr[2:0] in copctl register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000 table 15-2 initial wcop con?guration nv[3] in fctl register wcop in copctl register 10 01 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 111 section 16 enhanced capture timer (ect) block description consult the ect_16b8c block guide for information about the enhanced capture timer module. when the ect_16b8c block guide refers to freeze mode this is equivalent to active bdm mode. section 17 10 bit 8 channel analog to digital converter (atd0) block description the atd_10b8c module includes four external trigger inputs etrig0, etrig1, etrig and etrig3. the external trigger allows the user to synchronize atd conversion to external trigger events. table 17-1 shows the connection of the external trigger inputs on mc9s12xdp512. table 17-1 atd0 external trigger sources consult the atd_10b8c block guide for information about the analog to digital converter module. when the atd_10b8c block guide refers to freeze mode this is equivalent to active bdm mode. section 18 10 bit 16 channel analog to digital converter (atd1) block description the atd_10b16c module includes four external trigger inputs etrig0, etrig1, etrig and etrig3. the external trigger feature allows the user to synchronize atd conversion to external trigger events. table 18-1 shows the connection of the external trigger inputs on mc9s12xdp512. external trigger input connectivity etrig0 pulse width modulator channel 1 etrig1 pulse width modulator channel 3 etrig2 periodic interrupt timer hardware trigger 0 etrig3 periodic interrupt timer hardware trigger 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 112 table 18-1 atd1 external trigger sources consult the atd_10b16c block guide for information about the analog to digital converter module. when the atd_10b16c block guide refers to freeze mode this is equivalent to active bdm mode. section 19 inter-ic bus (iic) block description there are two inter-ic bus blocks implemented (iic0, iic1) on the mc9s12xdp512 device. consult the iic block guide for information about each inter-ic bus module. section 20 serial communications interface (sci) block description there are six serial communications interfaces (sci0, sci1, sci2, sci3, sci4 and sci5) implemented on the mc9s12xdp512 device. consult the sci block guide for information about each serial communications interface module. section 21 serial peripheral interface (spi) block description there are three serial peripheral interfaces(spi0, spi1 and spi2) implemented on mc9s12xdp512. consult the spi block guide for information about each serial peripheral interface module. section 22 pulse width modulator (pwm) block description consult the pwm_8b8c block guide for information about the pulse width modulator module. when the pwm _8b8cblock guide refers to freeze mode this is equivalent to active bdm mode. section 23 flash eeprom 512k block description external trigger input connectivity etrig0 pulse width modulator channel 1 etrig1 pulse width modulator channel 3 etrig2 periodic interrupt timer hardware trigger 0 etrig3 periodic interrupt timer hardware trigger 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 113 consult the ftx512k4 block guide for information about the flash module. the "s12 lrae" is a generic load ram and execute (lrae) program which will be programmed into the flash memory of this device during manufacture. this lrae program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using can or sci after it is assembled on the pcb. use of the lrae program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. for more details of the s12 lrae and its implementation, please see the s12 lrea application note (an2546/d). section 24 eeprom 4k block description consult the eetx4k block guide for information about the eeprom module. section 25 mscan block description there are five mscan modules (can4, can3, can2, can1 and can0) implemented on the mc9s12xdp512. consult the mscan block guide for information about the motorola scalable can module. section 26 port integration module (pim) block description consult the pim_9xd family block guide for information about the port integration module. section 27 voltage regulator (vreg_3v3) block description consult the vreg3v3 block guide for information about the dual output linear voltage regulator. ? vregen is accessible externally ? the api trimming bits apitr[5:0] need to be set by the customer if accurate period is wanted. 27.1 recommended pcb layout the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 114 ? every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (c1 - c6). ? central point of the ground star for lqfp112/qfp80 should be the vssr pin. ? central point of the ground star for lqfp144 should be the vssa pin. ? use low ohmic low inductance connections between vss1, vss2 and vssr. ? vsspll must be directly connected to vssr. ? keep traces of vsspll, extal and xtal as short as possible and occupied board area for c7, c8 and q1 as small as possible. ? do not place other signals or supplies underneath area occupied by c7, c8 and q1 and the connection area to the mcu. ? central power input should be fed in at the vdda/vssa pins. table 27-1 recommended decoupling capacitor choice component purpose type value c1 vdd1 ?lter cap ceramic x7r 220nf c2 vdd2 ?lter cap (not 80 qfp) ceramic x7r 220nf c3 vdda ?lter cap ceramic x7r >=100nf c4 vddr ?lter cap x7r/tantalum >=100nf c5 vddpll ?lter cap ceramic x7r 200nf c6 vddx ?lter cap x7r/tantalum >=100nf c7 osc load cap comes from crystal manufacturer c8 osc load cap c9 pll loop ?lter cap see pll speci?cation chapter c10 pll loop ?lter cap c11 vddx ?lter cap x7r/tantalum >=100nf c12 vddx ?lter cap x7r/tantalum >=100nf r1 pll loop ?lter res see pll speci?cation chapter q1 quartz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 115 figure 27-1 lqfp144 recommended pcb layout c5 c4 c10 c9 r1 vddr1 vssr1 vddpll vsspll c7 c8 q1 c2 vdd2 vss2 c1 vdd1 vss1 c6 vddx c12 vddr2 c11 vddx2 c3 vssa vdda vssr2 vregen vssx2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 116 figure 27-2 lqfp112 recommended pcb layout c5 c4 c1 c6 c3 c2 c10 c9 r1 vddx vssx vddr vssr vdd1 vss1 vdd2 vss2 vddpll vsspll vdda vssa vregen c7 c8 q1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 117 figure 27-3 qfp80 recommended pcb layout c5 c4 c3 c2 c10 c9 r1 c6 c1 vdd1 vss1 vss2 vdd2 vssr vddr vsspll vddpll vdda vssa vssx vregen vddx c7 c8 q1 vsspll f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide 9S12XDP512DGV2/d v02.05 118 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 119 appendix a electrical characteristics a.1 general note: the electrical characteristics given in this section are preliminary and should be used as a guide only. values cannot be guaranteed by motorola and are subject to change without notice. this supplement contains the most accurate electrical information for the mc9s12xdp512 microcontroller available at the time of publication. the information should be considered preliminary and is subject to change. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. note: this classification is shown in the column labeled c in the parameter tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t: those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the mc9s12xdp512 utilizes several pins to supply power to the i/o ports, a/d converter, oscillator and pll as well as the digital core. the vdda, vssa pair supplies the a/d converter and parts of the internal voltage regulator. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 120 the vddx, vssx, vddr and vssr pairs supply the i/o pins, vddr supplies also the internal voltage regulator. vdd1, vss1, vdd2 and vss2 are the supply pins for the digital logic, vddpll, vsspll supply the oscillator and the pll. vss1 and vss2 are internally connected by metal. vdda, vddx, vddr as well as vssa, vssx, vssr are connected by anti-parallel diodes for esd protection. note: in the following context vdd35 is used for either vdda, vddr and vddx; vss35 is used for either vssa, vssr and vssx unless otherwise noted. idd35 denotes the sum of the currents flowing into the vdda, vddx and vddr pins. vdd is used for vdd1, vdd2 and vddpll, vss is used for vss1, vss2 and vsspll. idd is used for the sum of the currents flowing into vdd1 and vdd2. a.1.3 pins there are four groups of functional pins. a.1.3.1 i/o pins those i/o pins have a nominal level in the range of 3.0v to 5.5v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd and the reset pins.the internal structure of all those pins is identical, however some of the functionality may be disabled. e.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. a.1.3.2 analog reference this group is made up by the vrh and vrl pins. a.1.3.3 oscillator the pins xfc, extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddpll. a.1.3.4 test this pin is used for production testing only. a.1.3.5 vregen this pin is used to enable the on chip voltage regulator. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 121 a.1.4 current injection power supply must maintain regulation within operating v dd35 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd35 ) is greater than i dd35 , the injection current may flow out of vdd35 and could result in external power supply going out of regulation. ensure external vdd35 load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss35 or v dd35 ). table a-1 absolute maximum ratings 1 notes : 1. beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd35 -0.3 6.0 v 2 digital logic supply voltage 2 v dd -0.3 3.0 v 3 pll supply voltage (2) v ddpll -0.3 3.0 v 4 voltage difference vddx to vddr and vdda d vddx -0.3 0.3 v 5 voltage difference vssx to vssr and vssa d vssx -0.3 0.3 v 6 digital i/o input voltage v in -0.3 6.0 v 7 analog reference v rh, v rl -0.3 6.0 v 8 xfc, extal, xtal inputs v ilv -0.3 3.0 v 9 test input v test -0.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins 3 i d -25 +25 ma 11 instantaneous maximum current single pin limit for xfc, extal, xtal 4 i dl -25 +25 ma 12 instantaneous maximum current single pin limit for test 5 i dt -0.25 0 ma 13 storage temperature range t stg C 65 155 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 122 a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 2. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. 3. all digital i/o pins are internally clamped to v ssx and v ddx , v ssr and v ddr or v ssa and v dda . 4. those pins are internally clamped to v sspll and v ddpll . 5. this pin is clamped low to v sspll , but not clamped high. this pin must be tied low in applications. table a-2 esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative - - 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative - - 3 3 latch-up minimum input voltage limit -2.5 v maximum input voltage limit 7.5 v table a-3 esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 - v 2 c machine model (mm) v mm 200 - v 3 c charge device model (cdm) v cdm 500 - v 4c latch-up current at t a = 125 c positive negative i lat +100 -100 -ma 5c latch-up current at t a = 27 c positive negative i lat +200 -200 -ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 123 a.1.7 operating conditions this chapter describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note: please refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation calculations refer to section a.1.8 power dissipation and thermal characteristics . a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j )in c can be obtained from: table a-4 operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd35 3 5 5.5 v digital logic supply voltage 1 notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. v dd 2.35 2.5 2.75 v pll supply voltage (2) v ddpll 2.35 2.5 2.75 v voltage difference vddx to vddr and vdda d vddx -0.1 0 0.1 v voltage difference vssx to vssr and vssa d vssx -0.1 0 0.1 v oscillator f osc 0.5 - 16 mhz bus frequency f bus 0.5 - 40 mhz mc9s12xdp512 c operating junction temperature range t j -40 - 100 c operating ambient temperature range 2 2. please refer to section a.1.8 power dissipation and thermal characteristics for more details about the rela- tion between ambient temperature t a and device junction temperature t j . t a -40 27 85 c mc9s12xdp512 v operating junction temperature range t j -40 - 120 c operating ambient temperature range (2) t a -40 27 105 c mc9s12xdp512 m operating junction temperature range t j -40 - 140 c operating ambient temperature range (2) t a -40 27 125 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 124 the total power dissipation can be calculated from: two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled p io is the sum of all output currents on i/o ports associated with vddx and vddr. for r dson is valid: respectively 2. internal voltage regulator enabled i ddr is the current shown in table a-9 and not the overall current flowing into vddr, which additionally contains the current flowing into the external loads with output high. p io is the sum of all output currents on i/o ports associated with vddx and vddr. t j t a p d q ja () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = p d total chip power dissipation, [w] = q ja package thermal resistance, [ c/w] = p d p int p io + = p int chip internal power dissipation, [w] = p int i dd v dd i ddpll v ddpll i dda +v dda + = p io r dson i ? i io i 2 = r dson v ol i ol ------------ for outputs driven low ; = r dson v dd5 v oh C i oh ------------------------------------ for outputs driven high ; = p int i ddr v ddr i dda v dda + = p io r dson i ? i io i 2 = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 125 table a-5 thermal package characteristics 1 notes : 1. the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit 1t thermal resistance lqfp144, single sided pcb 2 q ja --45 o c/w 2t thermal resistance lqfp144, double sided pcb with 2 internal planes 3 q ja --35 o c/w 3t thermal resistance lqfp112, single sided pcb 2 2. pc board according to eia/jedec standard 51-2 q ja --46 o c/w 4t thermal resistance lqfp112, double sided pcb with 2 internal planes 3 3. pc board according to eia/jedec standard 51-7 q ja --36 o c/w 5t thermal resistance qfp 80, single sided pcb 2 q ja --50 o c/w 6t thermal resistance qfp 80, double sided pcb with 2 internal planes 3 q ja --38 o c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 126 a.1.9 i/o characteristics this section describes the characteristics of all i/o pins. table a-6 3.3v i/o characteristics conditions are 3.0v < vdd35 <3.6v temperature from -40c to +140c,unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd35 --v t input high voltage v ih -- v dd35 + 0.3 v 2 p input low voltage v il -- 0.35*v dd35 v t input low voltage v il v ss35 - 0.3 --v 3 c input hysteresis v hys 250 mv 4p input leakage current (pins in high impedance input mode) 1 v in = v dd35 or v ss35 notes : 1. maximum leakage current occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c in the temperature range from 50 c to 125 c. i in C1 - 1 m a 5c output high voltage (pins in output mode) partial drive i oh = C2ma v oh v dd35 C 0.4 --v 6p output high voltage (pins in output mode) full drive ioh = C5.5ma v oh v dd35 C 0.4 --v 7c output low voltage (pins in output mode) partial drive iol = +2ma v ol - - 0.4 v 8p output low voltage (pins in output mode) full drive i ol = +5.5ma v ol - - 0.4 v 9p internal pull up device current, tested at v il max. i pul - - -60 m a 10 c internal pull up device current, tested at v ih min. i puh -6 - - m a 11 p internal pull down device current, tested at v ih min. i pdh --60 m a 12 c internal pull down device current, tested at v il max. i pdl 6- - m a 13 d input capacitance c in 6-pf 14 t injection current 2 single pin limit total device limit. sum of all injected currents 2. refer to section a.1.4 current injection , for more details i ics i icp -2.5 -25 - 2.5 25 ma 15 p port h, j, p interrupt input pulse ?ltered 3 3. parameter only applies in stop or pseudo stop mode. t pulse 3 m s 16 p port h, j, p interrupt input pulse passed (3) t pulse 10 m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 127 table a-7 5v i/o characteristics conditions are 4.5v < vdd35 <5.5v temperature from -40c to +140c,unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd35 --v t input high voltage v ih -- v dd35 + 0.3 v 2 p input low voltage v il -- 0.35*v dd35 v t input low voltage v il v ss35 - 0.3 --v 3 c input hysteresis v hys 250 mv 4p input leakage current (pins in high impedance input mode) 1 v in = v dd35 or v ss35 i in C1 - 1 m a 5c output high voltage (pins in output mode) partial drive i oh = C2ma v oh v dd35 C 0.8 --v 6p output high voltage (pins in output mode) full drive ioh = C10ma v oh v dd35 C 0.8 --v 7c output low voltage (pins in output mode) partial drive iol = +2ma v ol - - 0.8 v 8p output low voltage (pins in output mode) full drive i ol = +10ma v ol - - 0.8 v 9p internal pull up device current, tested at v il max. i pul - - -130 m a 10 c internal pull up device current, tested at v ih min. i puh -10 - - m a 11 p internal pull down device current, tested at v ih min. i pdh - - 130 m a 12 c internal pull down device current, tested at v il max. i pdl 10 - - m a 13 d input capacitance c in 6-pf 14 t injection current 2 single pin limit total device limit. sum of all injected currents i ics i icp -2.5 -25 - 2.5 25 ma 15 p port h, j, p interrupt input pulse ?ltered 3 t pulse 3 m s 16 p port h, j, p interrupt input pulse passed (3) t pulse 10 m s notes : 1. maximum leakage current occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c in the temperature range from 50 c to 125 c. 2. refer to section a.1.4 current injection , for more details 3. parameter only applies in stop or pseudo stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 128 a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. a.1.10.1 measurement conditions all measurements are without output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 40mhz bus frequency using a 4mhz oscillator in loop controlled pierce mode. production testing is performed using a square wave signal at the extal input. a.1.10.2 additional remarks in expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. no generally applicable numbers can table a-8 i/o characteristics for port c, d, pe5, pe6 and pk7 for reduced input voltage thresholds conditions are 4.5v < vdd35 <5.5v temperature from -40c to +140c,unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih tbd --v t input high voltage v ih - - tbd v 2 p input low voltage v il tbd - - v t input low voltage v il - - tbd v 3 c input hysteresis v hys tbd mv f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 129 given. a very good estimate is to take the single chip currents and add the currents due to the external loads. table a-9 supply current characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1p run supply currents single chip, internal regulator enabled i dd35 tbd ma 2p p wait supply current all modules enabled, pll on only rti enabled (1) i ddw tbd tbd ma 3 c p c c p c p c p pseudo stop current (api, rti and cop dis- abled) 1, 2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c notes : 1. pll off 2. at those low power dissipation levels t j = t a can be assumed i ddps tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd m a 4 c c c c c c c pseudo stop current (api, rti and cop enabled) (1), (2) -40 c 27 c 70 c 85 c 105 c 125 c 140 c i ddps tbd tbd tbd tbd tbd tbd tbd m a 5 c p c c p c p c p stop current (2) -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i dds tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd m a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 130 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 131 a.2 atd characteristics this section describes the characteristics of the analog to digital converter. a.2.1 atd operating characteristics the table a-10 and table a-11 show conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. table a-10 atd operating characteristics 5v conditions are shown in table a-4 unless otherwise noted, supply voltage 4.5v < vdda < 5.5v num c rating symbol min typ max unit 1d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 4.50v v rh -v rl 4.50 5.00 5.5 v 3 d atd clock frequency f atdclk 0.5 tbd mhz 4d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles m s 5d atd 8-bit conversion period clock cycles (2) conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles m s 6d recovery time (v dda =5.0 volts) t rec 20 m s 7 p reference supply current 2 atd blocks on i ref 0.750 ma 8 p reference supply current 1 atd block on i ref 0.375 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola confidential proprietary mc9s12xdp512 device user guide v02.05 132 table a-11 atd operating characteristics 3.3v a.2.2 factors influencing accuracy three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the atd. a.2.2.1 source resistance: due to the input pin leakage current as specified in table a-7 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s specifies results in an error of less than 1/2 lsb (2.5mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. a.2.2.2 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb, then the external filter capacitor, c f 3 1024 * (c ins - c inn ). a.2.2.3 current injection there are two cases to consider. conditions are shown in table a-4 unless otherwise noted, supply voltage 3.3v < vdda < 3.6v num c rating symbol min typ max unit 1d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 4.50v v rh -v rl 3.0 3.3 3.6 v 3 d atd clock frequency f atdclk 0.5 tbd mhz 4d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles m s 5d atd 8-bit conversion period clock cycles (2) conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles m s 6d recovery time (v dda =5.0 volts) t rec 20 m s 7 p reference supply current 2 atd blocks on i ref 0.500 ma 8 p reference supply current 1 atd block on i ref 0.250 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 133 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff ($ff in 8-bit mode) for analog inputs greater than v rh and $000 for values less than v rl unless the current is higher than specified as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err =k*r s * i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. a.2.3 atd accuracy a.2.3.1 5v range table a-13 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. table a-12 atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance r s --1k w 2t total input capacitance non sampling sampling c inn c ins 10 22 pf 3 c disruptive analog input current i na -2.5 2.5 ma 4 c coupling ratio positive current injection k p tbd a/a 5 c coupling ratio negative current injection k n tbd a/a table a-13 atd conversion performance 5v conditions are shown in table a-4 unless otherwise noted v ref = v rh - v rl = 5.12v. resulting to one 8 bit count = 20mv and one 10 bit count = 5mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 5 mv 2 p 10-bit differential nonlinearity dnl C1 1 counts 3 p 10-bit integral nonlinearity inl C2.5 1.5 2.5 counts 4p 10-bit absolute error 1 ae -3 2.0 3 counts 5 p 8-bit resolution lsb 20 mv 6 p 8-bit differential nonlinearity dnl C0.5 0.5 counts 7 p 8-bit integral nonlinearity inl C1.0 0.5 1.0 counts 8p 8-bit absolute error (1) ae -1.5 1.0 1.5 counts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola confidential proprietary mc9s12xdp512 device user guide v02.05 134 a.2.3.2 3.3v range table a-14 specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. a.2.3.3 atd accuracy definitions for the following definitions see also figure a-1 . differential non-linearity (dnl) is defined as the difference between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. table a-14 atd conversion performance 3.3v conditions are shown in table a-4 unless otherwise noted v ref = v rh - v rl = 3.328v. resulting to one 8 bit count = 13mv and one 10 bit count = 3.25mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 3.25 mv 2 p 10-bit differential nonlinearity dnl C1.5 1.5 counts 3 p 10-bit integral nonlinearity inl C3.5 1.5 3.5 counts 4p 10-bit absolute error 1 notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. ae -5 2.5 5 counts 5 p 8-bit resolution lsb 13 mv 6 p 8-bit differential nonlinearity dnl C0.5 0.5 counts 7 p 8-bit integral nonlinearity inl C1.5 1.0 1.5 counts 8p 8-bit absolute error (1) ae -2.0 1.5 2.0 counts dnl i () v i v i1 C C 1lsb ------------------------ 1 C = inl n () dnl i () i1 = n ? v n v 0 C 1lsb ------------------- - n C == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 135 figure a-1 atd accuracy definitions note: figure a-1 shows only definitions, for specification values refer to table a-13 . 1 5 vin mv 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 50 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 5055 10-bit absolute error boundary 8-bit absolute error boundary lsb v i-1 v i dnl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola confidential proprietary mc9s12xdp512 device user guide v02.05 136 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 137 a.3 nvm, flash and eeprom note: unless otherwise noted the abbreviation nvm (non volatile memory) is used for both flash and eeprom. a.3.1 nvm timing the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash and eeprom program and erase operations are timed using a clock derived from the oscillator using the fclkdiv and eclkdiv registers respectively. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in table a-15 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2mhz. a.3.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formula. a.3.1.2 burst programming this applies only to the flash where up to 64 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. the time to program a consecutive word can be calculated as: the time to program a whole row is: burst programming is more than 2 times faster than single word programming. t swpgm 9 1 f nvmop --------------------- 25 1 f bus ---------- + = t bwpgm 4 1 f nvmop --------------------- 9 1 f bus ---------- + = t brpgm t swpgm 63 t bwpgm + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 138 a.3.1.3 sector erase erasing a 1024 byte flash sector or a 4 byte eeprom sector takes: the setup time can be ignored for this operation. a.3.1.4 mass erase erasing a nvm block takes: the setup time can be ignored for this operation. a.3.1.5 blank check the time it takes to perform a blank check on the flash or eeprom is dependant on the location of the first non-blank word starting at relative address zero. it takes one bus cycle per word to verify plus a setup of the command. table a-15 nvm timing characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 80 1 notes : 1. restrictions for oscillator in crystal mode apply! mhz 2 d bus frequency for programming or erase operations f nvmbus 1 mhz 3 d operating frequency f nvmop 150 200 khz 4 p single word programming time t swpgm 46 2 2. minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . 74.5 3 m s 5d flash burst programming consecutive word 4 t bwpgm 20.4 (2) 31 (3) m s 6d flash burst programming time for 64 words (4) t brpgm 1331.2 (2) 2027.5 (3) m s 7 p sector erase time t era 20 5 26.7 (3) ms 8 p mass erase time t mass 100 (5) 133 (3) ms 9 d blank check time flash per block t check 11 6 65546 7 t cyc 10 d blank check time eeprom per block t check 11 (6) 2058 (7) t cyc t era 4000 1 f nvmop --------------------- ? t mass 20000 1 f nvmop --------------------- ? t check location t cyc 10 t cyc + ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 139 a.3.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. the failure rates for data retention and program/erase cycling are specified at the operating conditions noted. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. note: all values shown in table a-16 are target values and subject to further extensive characterization. 3. maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formulae in sections section a.3.1.1 single word programming- section a.3.1.4 mass erase for guidance. 4. burst programming operations are not applicable to eeprom 5. minimum erase times are achieved under maximum nvm operating frequency f nvmop . 6. minimum time, if first word in the array is not blank 7. maximum time to complete check on an erased block table a-16 nvm reliability characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1c data retention at an average junction temperature of t javg = 70 c t nvmret 15 years 2 c flash number of program/erase cycles n flpe 1000 10,000 cycles 3c eeprom number of program/erase cycles (C40 c t j 0 c) n eepe 10,000 cycles 4c eeprom number of program/erase cycles (0 c < t j 140 c) n eepe 100,000 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 140 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 141 a.4 voltage regulator table 27-2 voltage regulator electrical characteristics num c characteristic symbol min typical max unit 1 p input voltages v vddr,a 3.15 5.5 v 2p regulator current reduced power mode shutdown mode i reg 20 12 50 40 m a m a 3p output voltage core full performance mode reduced power mode shutdown mode v dd 2.35 1.6 2.5 2.5 1 notes : 1. high impedance output 2.75 2.75 v v v 4p output voltage pll full performance mode reduced power mode 2 reduced power mode 3 shutdown mode 2. current iddpll = 1ma (loop controlled pierce oscillator) 3. current iddpll = 3ma (loop controlled pierce oscillator) v ddpll 2.35 2.0 1.6 2.5 2.5 2.5 4 4. high impedance output 2.75 2.75 2.75 v v v 7p low voltage interrupt 5 assert level deassert level 5. monitors v dda , active only in full performance mode. indicates i/o & adc performance degradation due to low supply voltage. v lvia v lvid 4.1 4.25 4.37 4.52 4.66 4.77 v v 8p low voltage reset 6 assert level 6. monitors v dd , active only in full performance mode. mcu is monitored by the por in rpm (see figure a-1 ) v lvra 2.25 v 9c power-on reset 7 assert level deassert level 7. monitors v dd . active in all modes. note: the electrical characteristics given in this section are preliminary and should be used as a guide only. values in this section cannot be guaranteed by motorola and are subject to change without notice. v pora v pord 0.97 2.05 v v 12 c trimmed api internal clock d f / f nominal df api - 10% + 10% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 142 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 143 a.5 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked-loop (pll). a.5.1 startup table a-17 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block guide. table a-17 startup characteristics a.5.1.1 por the release level v porr and the assert level v pora are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.5.1.2 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when vdd35 is out of specification limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg flags register has not been set. a.5.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. a.5.1.4 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d reset input pulse width, minimum input time pw rstl 2 t osc 2 d startup from reset n rst 192 196 n osc 3 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ns 4 d wait recovery startup time t wrs 14 t cyc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 144 a.5.1.5 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. a.5.2 oscillator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 145 the device features an internal low-power loop controlled pierce oscillator and a full swing pierce oscillator/external clock mode. the selection of loop controlled pierce oscillator or full swing pierce oscillator/external clock depends on the xclks signal which is sampled during reset. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or stop if a proper oscillation is not detected. the quality check also determines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a clock monitor failure is asserted if the frequency of the incoming clock signal is below the assert frequency f cmfa. table a-18 oscillator characteristics conditions are shown in table a-1 unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (loop controlled pierce) f osc 4.0 16 mhz 1b c crystal oscillator range (full swing pierce) 12 notes : 1. depending on the crystal a damping series resistor might be necessary 2. xclks =0 f osc 0.5 40 mhz 2 p startup current i osc 100 m a 3 c oscillator start-up time (loop controlled pierce) t uposc tbd 3 3. f osc = 4mhz, c = 22pf. 50 4 4. maximum value is for extreme cases using high q, low frequency crystals ms 4 d clock quality check time-out t cqout 0.45 2.5 s 5 p clock monitor failure assert frequency f cmfa 50 100 200 kh z 6 p external square wave input frequency f ext 0.5 tbd mhz 7 d external square wave pulse width low t extl tbd ns 8 d external square wave pulse width high t exth tbd ns 9 d external square wave rise time t extr tbd ns 10 d external square wave fall time t extf tbd ns 11 d input capacitance (extal, xtal inputs) c in tbd pf 12 p extal pin input high voltage 5 5. if full swing pierce oscillator/external clock circuitry is used. ( xclks=0) v ih,extal 0.75* v ddpll v t extal pin input high voltage 5 v ih,extal v ddpll + 0.3 v 13 p extal pin input low voltage 5 v il,extal 0.25* v ddpll v t extal pin input low voltage 5 v il,extal v sspll -0.3 v 14 c extal pin input hysteresis 5 v hys,extal 250 mv f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 146 a.5.3 phase locked loop the oscillator provides the reference clock for the pll. the plls voltage controlled oscillator (vco) is also the system clock source in self clock mode. a.5.3.1 xfc component selection this section describes the selection of the xfc components to achieve a good filter characteristics. figure a-2 basic pll functional diagram the following procedure can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from table a-19 . the grey boxes show the calculation for f vco = 80mhz and f ref = 4mhz. e.g., these frequencies are used for f osc = 4mhz and a 40mhz bus clock. the vco gain at the desired vco frequency is approximated by: the phase detector relationship is given by: i ch is the current in tracking mode. f osc 1 refdv+1 f ref phase detector vco k v 1 synr+1 f vco loop divider k f 1 2 d f cmp c s r c p vddpll xfc pin k v k 1 e f 1 f vco C () k 1 1v ----------------------- = 195mhz v C e 126 80 C 195 C ---------------------- = = -154.0mhz/v k f i ch C k v 3.5 m a C 154mhz C v () 539.1hz w == = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 147 the loop bandwidth f c should be chosen to fulfill the gardners stability criteria by at least a factor of 10, typical values are 50. z = 0.9 ensures a good transient response. and finally the frequency relationship is defined as with the above values the resistance can be calculated. the example is shown for a loop bandwidth f c =20khz: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: a.5.3.2 jitter information the basic functionality of the pll is shown in figure a-2 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-3 . f c 2 z f ref pz 1 z 2 + + ? ?? ------------------------------------------ 1 10 ------ f c f ref 410 -------------- z 0.9 = () ; < ? < f c < 100khz n f vco f ref ------------- 2 synr 1 + () == = 20 r 2 p nf c k f ---------------------------- - 2 p 20 20khz 539.1hz ()w -------------------------------------------- 4.7k w = = = c s 2 z 2 p f c r --------------------- - 0.516 f c r -------------- - z 0.9 = () ; == = 5.5nf = ~ 4.7nf c s 20 ------ - c p c s 10 ------ - c p = 470pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 148 figure a-3 jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: for n < 1000, the following equation is a good fit for the maximum jitter: figure a-4 maximum bus clock jitter approximation 2 3 n-1 n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom --------------------- C 1 t min n () nt nom -------------------- - C , ? ? ?? = jn () j 1 n -------- j 2 + = 1 5 10 20 n j (n) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 149 this is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. table a-19 pll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1 5.5 mhz 2 d vco locking range f vco 8 80 mhz 3d lock detector transition from acquisition to tracking mode |d trk | 34 % 1 notes : 1. % deviation from target frequency 4 d lock detection |d lock | 0 1.5 % (1) 5 d un-lock detection |d unl | 0.5 2.5 % (1) 6d lock detector transition from tracking to acquisition mode |d unt | 68 % (1) 7c pllon total stabilization delay (auto mode) 2 2. f osc = 4mhz, f bus = 40mhz equivalent f vco = 80mhz: refdv = #$00, synr = #$09, cs = 4.7nf, cp = 470pf, rs = 4.7k w t stab 0.24 ms 8d pllon acquisition mode stabilization delay (2) t acq 0.09 ms 9d pllon tracking mode stabilization delay (2) t al 0.16 ms 10 d fitting parameter vco loop gain k 1 -195 mhz/v 11 d fitting parameter vco loop frequency f 1 126 mhz 12 d charge pump current acquisition mode | i ch | 38.5 m a 13 d charge pump current tracking mode | i ch | 3.5 m a 14 c jitter ?t parameter 1 (2) j 1 0.9 1.3 % 15 c jitter ?t parameter 2 (2) j 2 0.02 0.12 % f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 150 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 151 a.6 mscan table a-20 mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p mscan wake-up dominant pulse ?ltered t wup 2 m s 2 p mscan wake-up dominant pulse pass t wup 5 m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 152 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 153 appendix b electrical specifications b.1 spi timing this section provides electrical parametrics and ratings for the spi. in table b-1 the measurement conditions are listed. b.1.1 master mode in figure b-1 the timing diagram for master mode with transmission format cpha=0 is depicted. figure b-1 spi master timing (cpha=0) in figure b-2 the timing diagram for master mode with transmission format cpha=1 is depicted. table b-1 measurement conditions description value unit drive mode full drive mode load capacitance c load 1 , on all outputs notes : 1. timing specified for equal load on all spi output pins. avoid asymmetric load. 50 pf thresholds for delay measurement points (20% / 80%) vddx v sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 11 4 4 2 10 (cpol = 0) (cpol = 1) 3 13 13 1.if configured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 12 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 154 figure b-2 spi master timing (cpha=1) in table b-2 the timing characteristics for master mode are listed. table b-2 spi master mode timing characteristics num characteristic symbol unit min typ max 1 sck frequency f sck 1/2048 1 / 2 f bus 1 sck period t sck 2 2048 t bus 2 enable lead time t lead 1/2 t sck 3 enable lag time t lag 1/2 t sck 4 clock (sck) high or low time t wsck 1/2 t sck 5 data setup time (inputs) t su 8 ns 6 data hold time (inputs) t hi 8 ns 9 data valid after sck edge t vsck 29 ns 10 data valid after ss fall (cpha=0) t vss 15 ns 11 data hold time (outputs) t ho 20 ns 12 rise and fall time inputs t r? 8 ns 13 rise and fall time outputs t rfo 8 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 12 13 11 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 2 12 13 3 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 155 b.1.2 slave mode in figure b-3 the timing diagram for slave mode with transmission format cpha=0 is depicted. figure b-3 spi slave timing (cpha=0) in figure a-4 the timing diagram for slave mode with transmission format cpha=1 is depicted. sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in slave msb slave lsb out bit 6 . . . 1 11 4 4 2 7 (cpol = 0) (cpol = 1) 3 13 note: not defined! 12 12 11 see 13 note 8 10 see note f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 156 figure b-4 spi slave timing (cpha=1) in table b-3 the timing characteristics for slave mode are listed. table b-3 spi slave mode timing characteristics num characteristic symbol unit min typ max 1 sck frequency f sck dc 1 / 4 f bus 1 sck period t sck 4 t bus 2 enable lead time t lead 4 t bus 3 enable lag time t lag 4 t bus 4 clock (sck) high or low time t wsck 4 t bus 5 data setup time (inputs) t su 8 ns 6 data hold time (inputs) t hi 8 ns 7 slave access time (time to data active) t a 20 ns 8 slave miso disable time t dis 22 ns 9 data valid after sck edge t vsck 1 notes : 1. 0.5t bus added due to internal synchronization delay ns 10 data valid after ss fall t vss 1 ns 11 data hold time (outputs) t ho 20 ns 12 rise and fall time inputs t r? 8 ns 13 rise and fall time outputs t rfo 8 ns sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 12 13 11 (cpol = 0) (cpol = 1) ss (input) 2 12 13 3 note: not defined! slave 7 8 see note 29 0.5 t bus + 29 0.5 t bus + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 157 b.2 external bus timing the following conditions are assumed for all following external bus timing values: ? crystal input within 45% to 55% duty ? equal loads of pins ? pad full drive (reduced drive must be off) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 158 b.2.1 normal expanded mode (external wait feature disabled) figure b-5 example 1a: normal expanded mode - read followed by write {statement} csx addrx re datax addr1 addr2 (read) data1 (write) data2 we ewait uds, lds 1 3 5 6 7 1 9 8 10 11 2 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 159 table b-4 example 1a: normal expanded mode timing v dd35 =5.0v (ewaite = 0) no. c characteristic symbol min max unit - - frequency of internal bus f i d.c. 40.0 mhz - - internal cycle time t cyc 25 ns - - frequency of external bus f o d.c. 20.0 mhz 1 - external cycle time (selected by exstr) t cyce 50 ns 2d address 1 valid to re fall notes : 1. includes the following signals: addrx, uds, lds, and csx. t adre 5-ns 3 d pulse width, re pw re 35 - ns 4d address 1 valid to we fall t adwe 5-ns 5 d pulse width, we pw we 23 - ns 6 d read data setup time (if ithrs = 0) t dsr 24 - ns c read data setup time (if ithrs = 1) t dsr -ns 7 d read data hold time t dhr 0-ns 8 d read enable access time t accr 11 - ns 9 d write data valid to we fall t wdwe 7-ns 10 d write data setup time t dsw 31 - ns 11 d write data hold time t dhw 8-ns table b-5 example 1a: normal expanded mode timing v dd35 =3.0v (ewaite = 0) all values: to be de?ned! no. c characteristic symbol min max unit - - frequency of internal bus f i d.c. 40.0 mhz - - internal cycle time t cyc 25 ns - - frequency of external bus f o d.c. 20.0 mhz 1 - external cycle time (selected by exstr) t cyce 50 ns 2c address 1 valid to re fall notes : 1. includes the following signals: addrx, uds, lds, and csx. t adre -ns 3 c pulse width, re pw re -ns 4c address 1 valid to we fall t adwe -ns 5 c pulse width, we pw we -ns 6 c read data setup time (if ithrs = 0) t dsr -ns c read data setup time (if ithrs = 1) t dsr n/a ns 7 c read data hold time t dhr -ns 8 c read enable access time t accr -ns 9 c write data valid to we fall t wdwe -ns 10 c write data setup time t dsw -ns 11 c write data hold time t dhw -ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 160 b.2.2 normal expanded mode (external wait feature enabled) figure b-6 example 1b: normal expanded mode - stretched read access csx addrx re datax addr1 (read) data1 we ewait uds, lds 3 6 7 1 8 2 addr2 12 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 161 figure b-7 example 1b: normal expanded mode - stretched write access csx addrx re datax (write) data1 we ewait uds, lds 5 1 9 10 11 4 addr1 addr2 12 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 162 table b-6 example 1b: normal expanded mode timing v dd35 =5.0v (ewaite = 1) no. c characteristic symbol 2 stretch cycles 3 stretch cycles unit min max min max - - frequency of internal bus f i d.c. 40.0 d.c. 40.0 mhz - - internal cycle time t cyc 25 25 ns - - frequency of external bus f o d.c. 13.3 d.c. 10.0 mhz - - external cycle time (selected by exstr) t cyce 75 100 ns 1 - external cycle time (exstr+1ewait) t cycew 100 125 ns 2d address 1 valid to re fall notes : 1. includes the following signals: addrx, uds, lds, and csx. t adre 5-5-ns 3d pulse width, re 2 2. affected by ewait. pw re 85 - 110 - ns 4d address 1 valid to we fall t adwe 5-5-ns 5d pulse width, we 2 pw we 73 - 98 - ns 6 d read data setup time (if ithrs = 0) t dsr 24 - 24 - ns c read data setup time (if ithrs = 1) t dsr --ns 7 d read data hold time t dhr 0-0-ns 8d read enable access time 2 t accr 71 - 86 - ns 9 d write data valid to we fall t wdwe 7-7-ns 10 d write data setup time 2 t dsw 81 - 106 - ns 11 d write data hold time t dhw 8-8-ns 12 d address to ew ait fall t adwf 0 20 0 45 ns 13 d address to ew ait rise t adwr 37 47 62 72 ns table b-7 example 1b: normal expanded mode timing v dd35 =3.0v (ewaite = 1) all values: to be de?ned! no. c characteristic symbol 2 stretch cycles 3 stretch cycles unit min max min max - - frequency of internal bus f i d.c. 40.0 d.c. 40.0 mhz - - internal cycle time t cyc 25 25 ns - - frequency of external bus f o d.c. 13.3 d.c. 10.0 mhz - - external cycle time (selected by exstr) t cyce 75 100 ns 1 - external cycle time (exstr+1ewait) t cycew 100 125 ns 2c address 1 valid to re fall t adre --ns 3c pulse width, re 2 pw re --ns 4c address 1 valid to we fall t adwe --ns 5c pulse width, we 2 pw we --ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 163 6 c read data setup time (if ithrs = 0) t dsr --ns c read data setup time (if ithrs = 1) t dsr n/a ns 7 c read data hold time t dhr --ns 8c read enable access time 2 t accr --ns 9 c write data valid to we fall t wdwe --ns 10 c write data setup time 2 t dsw --ns 11 c write data hold time t dhw --ns 12 c address to ew ait fall t adwf ns 13 c address to ew ait rise t adwr ns notes : 1. includes the following signals: addrx, uds, lds, and csx. 2. affected by ewait. table b-7 example 1b: normal expanded mode timing v dd35 =3.0v (ewaite = 1) all values: to be de?ned! no. c characteristic symbol 2 stretch cycles 3 stretch cycles unit min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 164 b.2.3 emulation single-chip mode (without wait states) figure b-8 example 2a: emulation single-chip mode - read followed by write eclk r/ w datax addr1 ivd0 addr2 ivd1 (read) data1 (write) data2 addr3 lstrb eclk2x 1 1 2 3 4 5 6 7 8 9 10 11 12 12 addr1 acc1 addr2 acc2 addr3 data0 addr1 addr2 addr3 iqstat0 iqstat1 addr addr [19:16]/ addr [22:20]/ [15:0]/ acc [2:0] iqstat [3:0] ivd [15:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 165 table b-8 example 2a: emulation single-chip mode timing v dd35 =5.0v (ewaite = 0) no. c characteristic 1 notes : 1. typical supply and silicon, room temperature only symbol min max unit - - frequency of internal bus f i d.c. 40.0 mhz 1 - cycle time t cyc 25 ns 2 d pulse width, e high pw eh 11.5 - ns 3 d pulse width, e low pw el 11.5 - ns 4 d address delay time t ad -5ns 5 d address hold time t ah 0-ns 6d ivdx delay time 2 2. includes also accx, iqstatx t ivdd - 4.5 ns 7d ivdx hold time 2 t ivdh 0-ns 8 d read data setup time (ithrs = 1 only) t dsr 12 - ns 9 d read data hold time t dhr 0-ns 10 d write data delay time t ddw -5ns 11 d write data hold time t dhw 0-ns 12 d read/write data delay time 3 3. includes lstrb t rwd -1 5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 166 b.2.4 emulation expanded mode (with optional access stretching) figure b-9 example 2b: emulation expanded mode - read with 1 stretch cycle eclk addr r/ w datax lstrb eclk2x 1 2 3 4 5 6 8 9 12 12 addr [19:16]/ (read) data1 7 data0 addr1 ? addr1 addr2 addr1 iqstat0 addr1 addr2 addr [22:20]/ addr1 acc1 addr1 000 addr2 [15:0]/ iqstat1 acc [2:0] iqstat [3:0] ivd [15:0] ivd1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 167 figure b-10 example 2b: emulation expanded mode - write with 1 stretch cycle eclk r/ w datax (write) data1 lstrb eclk2x 11 10 1 2 3 4 5 6 7 12 12 addr1 ? addr1 x addr2 addr1 iqstat0 addr1 addr2 addr1 acc1 addr1 000 addr2 iqstat1 addr addr [19:16]/ addr [22:20]/ [15:0]/ acc [2:0] iqstat [3:0] ivd [15:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 168 table b-9 example 2b: emulation expanded mode timing v dd35 =5.0v (ewaite = 0) no. c characteristic 1 notes : 1. typical supply and silicon, room temperature only symbol 1 stretch cycle 2 stretch cycles 3 stretch cycles unit min max min max min max - - internal cycle time t cyc 25 25 25 25 25 25 ns 1 - cycle time t cyce 50 75 100 ns 2 d pulse width, e high pw eh 11.5 14 11.5 14 11.5 14 ns 3 d e falling to sampling e rising t efsr 35 39.5 60 64.5 85 89.5 ns 4 d address delay time t ad -5-5-5ns 5 d address hold time t ah 0-0-0-ns 6d ivd delay time 2 2. includes also accx, iqstatx t ivdd - 4.5 - 4.5 - 4.5 ns 7d ivd hold time 2 t ivdh 0-0-0-ns 8 d read data setup time t dsr 12-12-12-ns 9 d read data hold time t dhr 0-0-0-ns 10 d write data delay time t ddw -5-5-5ns 11 d write data hold time t dhw 0-0-0-ns 12 d read/write data delay time 3 3. includes lstrb t rwd -1 5 -1 5 -1 5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 169 b.3 external tag trigger timing figure b-11 external trigger timing table b-10 external tag trigger timing vdd35=5.0v no. c characteristic 1 notes : 1. typical supply and silicon, room temperature only symbol min max unit - - frequency of internal bus f i d.c. 40.0 mhz 1 - cycle time t cyc 25 ns 2 d taghi/lo setup time t ts 11.5 - ns 3 d taghi/lo hold time t th 0-ns eclk r/ w datax taghi/ 2 3 data taglo 1 addr addr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 170 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 171 appendix c package information c.1 general this section provides the physical dimensions of the mc9s12xdp512 packages. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 172 c.2 144-pin lqfp figure 27-4 144-pin lqfp mechanical dimensions (case no. 918-03 n 0.20 t l-m 144 gage plane 73 109 37 seating 108 1 36 72 plane 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v p g a s 0.1 c 2 q view ab j1 j1 140x 4x view y plating f aa j d base metal section j1-j1 (rotated 90 ) 144 pl n 0.08 m t l-m q dim a min max 20.00 bsc millimeters a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 q 0 q 07 q 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m, n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.35. 0.05 c l (z) r2 e c2 (y) r1 (k) c1 1 q 0.25 view ab n 0.20 t l-m m l n 2 q t t 144x x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 173 c.3 112-pin lqfp package figure c-1 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 q q q q 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 q 2 q 0.050 seating plane gage plane 1 q q view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46. 8 3 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 174 c.4 80-pin qfp package figure c-2 80-pin qfp mechanical dimensions (case no. 841b) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- datum plane -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 510 n 0.13 0.17 p 0.325 bsc q 07 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 d s a-b m 0.20 d s c s a-b m 0.20 d s c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 175 user guide end sheet f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12xdp512 device user guide v02.05 176 final page of 176 pages f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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