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the mark h shows major revised points. document no. ic - 2518c (o. d. no. ic - 7931c) date published february 1994 p printed in japan ? nec corporation 1990 data sheet mos integrated circuit m pd75048 4-bit single-chip microcomputer applications consumer electronics products, telephones, cameras, automobile audio equipment, electronics measurement equipment, etc. ordering information part number package quality grade m pd75048cw-xxx 64-pin plastic shrink dip (750 mil) standard m pd75048gc-xxx-ab8 64-pin plastic qfp ( 14mm) standard remarks : xxx is rom code number. please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. the information in this document is subject to change without notice. description the m pd75408 is a 4-bit single-chip microcomputer whose data processing capability is comparative to that of an 8-bit microcomputer. the m pd75048 employs a cpu whose minimum instruction execution time is 0.95 m s, and contains the eeprom, a/d converter, multi-function timer, and high performance hardware to provide high cost to performance ratio. detailed functions are described in the following user's manual. read this manual when designing your system. m pd75048 user's manual: ieu-704 features built-in eeprom: 1024 x 4 bits (data memory area) built-in 8-bit resolution a/d converter (successive approximation): 8 channels ? capable of operating at low voltage: v dd = 2.7 to 6.0 v ? reference voltage can be arbitrarily specified between av ref+ and av ref- . built-in multi-function timer which can provide the following functions: ? 8-bit timer ? pwm output ? 16-bit free running timer ? 16-bit integration type a/d converter counter i/o ports: 48 pins ? middle voltage n-ch open drain input/output ports: 12 pins ? 43 i/o lines can be provided with internal pull- down resistors prom version is available: m pd75p048 (one-time prom)
2 m pd75048 functional outline item function instructions 41 instruction exe- ? with main system clock: 0.95, 1.91, 15.3 m s (at 4.19 mhz) cution time ? with subsystem clock: 122 m s (at 32.768 khz) program memory (rom) : 8064 x 8 bits internal memory data memory (ram) : 512 x 4 bits data memory (eeprom) : 1024 x 4 bits ? retains data in case of power failure eeprom ? number of writes: 100,000 times ? write time: 10 ms ? write end, overwrite interrupt functions general-purpose ? 4-bit manipulation: 8 (x, a, b, c, d, e, h, l) register ? 8-bit manipulation: 4 (xa, bc, de, hl) ? bit accumulator (cy) accumulator ? 4-bit accumulator (a) ? 8-bit accumulator (xa) ? abundant bit manipulation instructions ? efficient 4-bit data manipulation instructions instruction set ? 8-bit data manipulation instructions ? geti instruction executing 2-/3-byte instruction with a single byte 12 input pin via software, 24 cmos i/o pin (direct led drive: 4) w/pull-up resistor: 27 i/o line 48 w/pull-down resistor: 4 12 medium-voltage n-ch by mask option, open-drain i/o (direct led drive) w/pull-up resistor: 12 ? 8-bit timer/event counter ? clock source: 4 steps ? can count events ? 8-bit basic interval timer ? reference time generation: 1.95, 7.82, 31.3, 250 ms (at 4.19 mhz) ? can be used as watchdog timer ? clock timer timer 4 chs ? generates 0.5-second time intervals ? count clock source: main system clock or subsystem clock (selectable) ? clock fast forward mode (generates 3.9-ms time intervals) ? buzzer output (2, 4, 32 khz) ? multi-function timer can be used as: ? 8-bit timer ? pwm output ? 16-bit free-running timer ? counter for 16-bit integral a/d converter ? three modes: 8-bit serial ? 3-line serial i/o mode ... msb/lsb first (selectable) interface ? 2-line serial i/o mode ? sbi mode bit sequential special bit manipulation memory: 16 bits buffer ? ideal for remote controller timer/event counter output (pto0): output of square wave at specified frequency clock output clock output (pcl): f /, f x /2 3 , f x /2 4 , f x /2 6 function buzzer output (buz): 2, 4, 32 khz (with main system clock or subsystem clock)
3 m pd75048 (cont'd) item function 8-bit resolution a/d converter (successive approximation type): 8 channels a/d converter ? low-voltage operation: v dd = 2.7 C 6.0 v ? reference voltage setting range: av ref+ C av refC 2.5 v (av ref+ ) C (av refC ) 6.0 v vector interrupt external: 3, internal: 6 test input external: 1, internal: 1 system clock ? ceramic/crystal oscillator circuit for main system clock oscillation oscillator circuit ? crystal oscillator circuit for subsystem clock oscillation standby function ? stop mode: main system clock oscillation stops ? halt mode: system clock oscillation continues (clock supply to cpu stops) package ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp ( 14 mm)
4 m pd75048 contents 1. pin configuration (top view) ........................................................................................ 5 2. block diagram ......................................................................................................................8 3. pin functions ........................................................................................................................9 3.1 port pins ........................................................................................................................................9 3.2 non port pins ............................................................................................................................ 11 3.3 pin input/output circuit ...................................................................................................... 13 3.4 selection of mask options ................................................................................................. 16 3.5 processing of unused pins ................................................................................................ 17 4. memory configuration ................................................................................................. 18 5. eeprom ....................................................................................................................................21 6. peripheral hardware functions ............................................................................... 22 6.1 port ............................................................................................................................................... 22 6.2 clock generator circuit ..................................................................................................... 23 6.3 clock output circuit ............................................................................................................. 24 6.4 basic interval timer .............................................................................................................. 25 6.5 watch timer ............................................................................................................................... 26 6.6 timer/event counter ............................................................................................................. 27 6.7 serial interface ....................................................................................................................... 29 6.8 a/d converter .......................................................................................................................... 31 6.9 multi-function timer (mft) ................................................................................................. 32 6.10 bit sequential buffer ........................................................................................................... 34 7. interrupt functions ....................................................................................................... 34 8. standby functions .......................................................................................................... 36 9. reset function .................................................................................................................. 37 10. instruction set ................................................................................................................. 39 11. electrical specifications ............................................................................................. 45 12. performance curve ......................................................................................................... 59 13. package drawings ........................................................................................................... 61 14. recommended soldering conditions ...................................................................... 63 appendix a. comparison between m pd75048 and 75028/75008 functions .......... 64 appendix b. development tools ....................................................................................... 65
5 m pd75048 1. pin configuration (top view) ? 64-pin plastic shrink dip (750 mil) sb1/si/p03 sb0/so/p02 sck/p01 int4/p00 buz/p23 pcl/p22 pco/p21 pto0/p20 mat/p103 maz/p102 mai/p101 mar/p100 reset x1 x2 ic xt1 xt2 v dd av dd av ref + av ref ? an7 an6 an5 an4 an3/p113 an2/p112 an1/p111 an0/p110 av ss ti0/p13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss p30 p31 p32 p33 p40 p41 p42 p43 p50 p51 p52 p53 p60/kr0 p61/kr1 p62/kr2 p63/kr3 p70/kr4 p71/kr5 p72/kr6 p73/kr7 p80 p81 p82 p83 p90 p91 p92 p93 p10/int0 p11/int1 p12/int2 ?d75048cw ic : internally connected (connect directly to v dd ) xxx
6 m pd75048 ? 64-pin plastic qfp ( 14 mm) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ppo/p21 pcl/p22 buz/p23 int4/p00 sck/p01 sb0/so/p02 sb1/si/p03 v ss p30 p31 p32 p33 p40 p41 p42 p43 an6 an5 an4 an3/p113 an2/p112 an1/p111 an0/p110 av ss ti0/p13 p12/int2 p11/int1 p10/int0 p93 p92 p91 p90 p83 p82 p81 p80 p73/kr7 p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 p60/kr0 p53 p52 p51 p50 an7 av ref ? av ref + av dd v dd xt2 xt1 ic x2 x1 reset mar/p100 mai/p101 maz/p102 mat/p103 pto0/p20 ?d75048gc ?b8 ic : internally connected (connect directly to v dd ) xxx ab8
7 m pd75048 pin identification p00-03 : port0 : port 0 p10-13 : port1 : port 1 p20-23 : port2 : port 2 p30-33 : port3 : port 3 p40-43 : port4 : port 4 p50-53 : port5 : port 5 p60-63 : port6 : port 6 p70-73 : port7 : port 7 p80-83 : port8 : port 8 p90-93 : port9 : port 9 p100-103 : port10 : port 10 p110-113 : port11 : port 11 kr0-7 : key return : key interrupt input sck : serial clock : serial clock input/output si : serial input : serial data input so : serial output : serial data output sb0, 1 : serial bus 0, 1 : serial bus input/output reset : reset input : reset input ti0 : timer input 0 : external event pulse input pto0 : programmable timer output 0 : timer/event counter output buz : buzzer clock : arbitrary frequency output pcl : programmable clock : clock output int0,1,4 : external vectored interrupt 0, 1, 4 : external vector interrupt input int2 : external test input 2 : external test input x1, 2 : main system clock oscillation 1, 2 : main system clock oscillation pin xt1, 2 : subsystem clock oscillation 1, 2 : subsystem clock oscillation pin mar : reference integration control : reference integration signal output mai : integration control : integration signal output maz : autozero control : autozero signal output mat : external comparate timing input : external comparator signal input ppo : programmable pulse output ... : pulse output ... mft timer mode : mft timer mode an0-7 : analog input 0-7 : analog input av ref+ : analog reference (+) : analog reference voltage (+) input (av dd ) av ref- : analog reference (-) : analog reference voltage (-) input (av ss ) av dd : analog v dd : a/d converter positive power supply av ss : analog v ss : a/d converter gnd v dd : positive power supply : positive power supply v ss : ground : gnd remarks : mft: multi-function timer mft a/d mode mft a/d mode
8 m pd75048 bit seq. buffer port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port 10 port 11 p00?03 p10?13 p20?23 p30?33 p40?43 p50?53 p60?63 p70?73 p80?83 p90?93 p100?103 p110?113 sp bank cy data memory general reg. ram 512 4 bits eeprom 1024 4 bits cpu clock f stand by control clock generator main sub clock divider clock output control fx/2 n pcl/p22 xt1 xt2 x1 x2 reset v ss v dd decode and control rom program memory 8064 8 bits alu program counter basic interval timer timer /counter #0 intbt intt0 serial interface intcsi interrupt control watch timer intw a/d converter multi function timer intmft ppo/p21 mat/p103 maz/p102 mai/p101 mar/p100 an0?n3/p110?113 an4?n7 av ss av ref av ref + av dd buz/p23 kr0?r3/p60?63 kr4?r7/p70?73 int4/p00 int2/p12 int1/p11 int0/p10 sck/p01 so/sb0/p02 si/sb1/p03 pto0/p20 ti0/p13 4 4 4 4 4 4 4 4 4 4 4 4 8 8 2. block diagram
9 m pd75048 3. pin functions 3.1 port pins input/ output circuit type* 1 p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30* 2 p31* 2 p32* 2 p33* 2 p40-43* 2 p50-53* 2 pin name input/output function 8-bit i/o when reset also served as input/ output input/ output input/ output input/ output input input/ output input/ output input/ output input/ output int4 sck so/sb0 so/sb1 int0 int1 int2 ti0 pto0 ppo pcl buz 4-bit input/output port(port0) pull up resistros can be specified in 3-bit units for the p01 to p03 pins by software. with noise elimination function 4-bit input port(port1) internal pull-up resistors can be specified in 4-bit units by software. 4-bit input/output port(port2) internal pull-up resistors can be specified in 4-bit units by software. programmable 4-bit input/output port (port3) this port can be specified for input/ output in bit units. internal pull-up resistors can be specified in 4-bit units by software. n-ch open-drain 4-bit input/output port (port4) internal pull-up resistors can be specified in 4-bit units (by mask option). resistive voltage is 10v in the open- drain mode. n-ch open-drain 4-bit input/output port (port5) internal pull-up resistors can be specified in bit units (by mask option). resistive voltage is 10v in the open- drain mode. input input input input b f -a f -b m -c b -c e -b e -b m m x x x x *1: circles indicate schmitt trigger inputs. 2: can directly drive led. high level (with internal pull-up register) or high imped- ance high level (with internal pull-up register) or high imped- ance
10 m pd75048 p60 p61 p62 p63 p70 p71 p72 p73 p80-83 p90-93 p100 p101 p102 p103 p110 p111 p112 p113 kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 mar mai maz mat an0 an1 an2 an3 also served as (cont'd) input/ output circuit type* 1 input/ output input/ output input/ output input/ output input/ output input programmable 4-bit input/output port (port6) this port can be specified for input/ output in bit units. internal pull-up resistors can be specified in 4-bit units by software. input f -a 4-bit input/output port(port7) internal pull-up resistors can be specified in 4-bit units by software. input f -a input 4-bit input/output port(port8) internal pull-up resistors can be specified in 4-bit units by software. e-b input e-d x 4-bit input/output port(port9) internal pull-down resistors can be specified in 4-bit units by software. n-ch open-drain 4-bit input/output port (port10) internal pull-up resistors can be specified in bit units (by mask option). resistive voltage is 10v in the open- drain mode. m 4-bit input port(port11) input y-a x *1: circles indicate schmitt trigger inputs. pin name input/output function 8-bit i/o when reset high level (with internal pull-up resistor) or high imped- ance
11 m pd75048 p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60-63 p70-73 p100 p101 p102 p103 p21 pin name input/output also served as functon when reset input/ output circuit type* 1 3.2 non port pins input input/ output input/ output input/ output input/ output input/ output input/ output input input input input/ output input/ output input/ output input/ output input/ output input/ output input/ output timer/event counter external event pulse input timer/event counter output clock output arbitrary frequency output(for buzzer or for trimming the system clock) serial clock input/output serial data output serial bus input/output serial data input serial bus input/output edge detection vector interrupt input (both rising and falling edge detection are effective) edge detection vector interrupt input (detection edge is selectable) edge detection vector interrupt input (rising edge is detected.) clock synchronous asynchronous asynchronous parallel falling edge detection testable input parallel falling edge detection testable input in the mft integration type a/ d converter mode in the mft timer mode reference integration signal output integration signal output auto zero signal output comparator input timer pulse output input input input input input input input input input input input input *2 input b - c e - b e - b e - b f - a f - b m - c b b - c b - c f - a f - a m e - b *1: circles indicate schmitt trigger inputs. 2: high level (with internal pull-up resistor) or high impedence remarks: mft: multi-function timer ti0 pto0 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0-kr3 kr4-kr7 mar mai maz mat ppo
12 m pd75048 (cont'd) input/ output circuit type* 1 also served as input input input pins only for a/d converter input y-a y z-a z-a 8-bit analog input reference voltage input (av dd side) reference voltage input (av ss side) positive power supply gnd a crystal/ceramic resonator for the main system clock is connected across these pins. when using the external clock, the x1 pin inputs the external clock, and the x2 pin inputs the reverse phase of the external clock signal. input input a crystal resonator for the subsystem clock is connected across these pins. when using the external clock, the xt1 pin inputs the external clock, and the xt2 pin inputs the reverse phase of the external clock signal. the xt1 pin can be used as a 1-bit input(test) pin. system reset input b internally connected. should be connected directly to v dd . positive power supply gnd *1: circles indicate schmitt trigger inputs. input pin name input/output function when reset an0-an3 an4-an7 av ref+ av ref- av dd av ss x1, x2 xt1, xt2 reset ic v dd v ss
13 m pd75048 3.3 pin input/output circuits the following shows a simplified input/output circuit diagram for each pin of the m pd75048. type a (for type e?) type d (for type e b, f-a) type b type e? in v dd p?h n?h input buffer of cmos standard data output disable out p?h n?h push?ull output that can be set in the output high?mpedance state (both p?h and n?h are off) in schmitt trigger input with hysteresis characteristics data output disable type d type a p.u.r. enable v dd p.u.r. p?h in/out p.u.r. : pull?p resistor v dd
14 m pd75048 p.u.r. enable v dd p.u.r. p?h type b? type e? type f? type m? in data output disable p.u.r. enable v dd p.u.r. in/out p.u.r. : pull?p resistor p?h data output disable type d type b p.u.r. enable v dd p.u.r. p?h in/out p.u.r. : pull?p resistor n-ch p.u.r. : pull?p resistor p.d.r. : pull?own resistor p.u.r. enable p.d.r. n?h data output disable type d in/out type a
15 m pd75048 type f? type y type m type y? data output disable p.u.r. enable v dd in/out middle voltage input buffer (resistive voltage: +10 v) n-ch (resistive voltage: +10 v) p.u.r. : pull?p resistor data output disable p.u.r. enable v dd p.u.r. p?h n-ch p-ch output disable (p) output disable (n) v dd (mask option) p.u.r. : pull?p resistor n?h in p?h av ss av dd av dd av ss sampling c + input enable reference voltage (from a voltage tap of series resistor string) n?h in p?h av ss av dd av dd av ss sampling c + reference voltage (from a voltage tap of series resistor string) input buffer in instruction in/out
16 m pd75048 av ref + av ref reference voltage type z? 3.4 selection of mask options the following mask options are available: pin mask option p40 - p43, 1 w/pull-up resistor 2 w/o pull-up resistor p50 - p53, (can be specified bitwise) (can be specified bitwise) p100 - p103 1 w/feedback resistor 2 w/o feedback resistor xt1, xt2 (with subsystem clock used) (without subsystem clock used)
17 m pd75048 3.5 processing of unused pins pin recommended condition p00/int4 connect to v ss p01/sck p02/so/sb0 connect to v ss or v dd p03/si/sb1 p10/int0-p12/int2 p13/ti0 p20/pto0 p21/ppo p22/pcl p23/buz p30-p33 p40-p43 p50-p53 p60/kr0-p63/kr3 input: connect to v ss or v dd p70/kr4-p73/kr7 output: open p80-p83 p90-p93 p100/mar p101/mai p102/maz p103/mat p110/an0-p113/an3 an4-an7 av ref+ av ref- connect to v ss av ss av dd connect to v dd xt1 connect to v ss or v dd xt2 open ic connect directly to v dd connect to v ss connect to v ss or v dd h
18 m pd75048 4. memory configuration ? program memory (rom)...8064 x 8 bits (0000h-1f7fh) ? 0000h, 0001h: vector table to which address from which program is started is written after reset ? 0002h-000fh: vector table to which address from which program is started is written after interrupt ? 0020h-007fh: table area referenced by geti instruction ? data memory ? data area static ram....512 x 4 bits (000h-1ffh) eeprom....1024 x 4 bits (400h-7ffh) ? peripheral hardware area....128 x 4 bits (f80h-fffh)
19 m pd75048 fig. 4-1 program memory map 765 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 internal reset start address (upper 5 bits) internal reset start address (lower 8 bits) intbt/int4 start address (upper 5 bits) intbt/int4 start address (lower 8 bits) int0 start address (upper 5 bits) int0 start address (lower 8 bits) int1 start address (upper 5 bits) int1 start address (lower 8 bits) intcsi start address (upper 5 bits) intcsi start address (lower 8 bits) intt0 start address (upper 5 bits) intt0 start address (lower 8 bits) intmft start address (upper 5 bits) intmft start address (lower 8 bits) intee/intow start address (upper 5 bits) intee/intow start address (lower 8 bits) mbe 0 0 0000h 0002h 0004h 0006h 0008h 000ah 000ch 000eh 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1f7fh geti instruction reference table 0 brcb ! caddr instruction branch address callf ! faddr instruction entry address br ! addr instruction branch address call ! addr instruction subroutine entry address br $addr instruction relational branch address (?5 to ?, +2 to +16) branch destination address and subroutine entry address for geti instruction address brcb ! caddr instruction branch address
20 m pd75048 data memory (8 4) 256 4 (248 4) 256 4 unmapped 256 4 256 4 256 4 256 4 unmapped 128 4 memory bank 000h 007h 0ffh 100h 1ffh 400h 4ffh 500h 5ffh 600h 6ffh 700h 7ffh f80h fffh 0 1 4 5 6 7 15 general-purpose register area stack area data area static ram (512 4) data area eeprom (1024 4) peripheral hardware area fig. 4-2 data memory map
21 m pd75048 5. eeprom the m pd75048 contains the 1024-word x 4-bit eeprom (electrically erasable prom). the eeprom of the m pd75048 has the following characteristics. ? the eeprom can retain its contents even if the power is turned off. ? in the same manner as the static ram, data can be manipulated (auto-erase/write/read) in 4-bit or 8-bit units by using a memory manipulation instruction ? the contens of eeprom are automatically erased or written by hardware, so that the overhead of the software is alleviated. ? write time .... 10 ms. ? number of write operation100,000 times (guaranteed). ? write operation can be controlled by interrupt. ? when write operation is completed an interrupt occurs. ? when overwrite is executed. (write operation is executed during write operation) ? whether or not the eeprom is possible to be written can be checked by individually checking the write status flag.
22 m pd75048 6. peripheral hardware functions 6.1 port i/o ports are classified into the following three inds: ? cmos input (port0, 1, 11) : 12 ? cmos i/o (port2, 3, 6, 7, 8, 9) : 24 ? n-ch open-drain i/o (port4, 5, 10) : 12 total 48 table 6-1 port function port (symbol) function operation/feature remarks can be read or tested regardless also serves as the so/sb0, si/sb1, 4-bit input of the operation mode of the sck, int0 to 2, int4, and ti0 pins shared pin. port3* can be specified for input/output port 6 can also serve as the kr0 to port6 in 1-bit units. kr3 pins. port2 4-bit input/output can be specified for input/output port 2 can also serve as the pto0, port7 in 4-bit units. ports 6 and 7 can ppo, pcl, and buz pins. be paired to input/ output data also serves as the kr4 to kr7 pins. in 8-bit units. port4* can be specified for input/output whether or not the internal pull-up port5* 4-bit input/output in 4-bit units. ports 4 and 5 can resistor is provided can be specified port10* (n-ch open-drain, be paired to input/output data in f or each bit by mask option. can sustain with 10v) 8-bit units. port8 4-bit input/output can be specified for input/output port9 in 4-bit units. port11 4-bit input 4-bit input-only port. port 11 can also serve as the an0 to an3 pins. *: can directly drive led. port 10 can also serve as the mar, mai, maz, and mat pins. port0 port1
23 m pd75048 v dd internal bus xt1 v dd xt2 x1 x2 subsystem clock oscillator main system clock oscillator watch timer f xt f x 1/2 to 1/4096 frequency divider 1/2 1/16 multi-function timer basic interval timer (bt) timer/event counter serial interface watch timer a/d converter (successive approximation) int0 noise rejecter circuit clock output circuit . . . . . . . . selector selector frequency divider cpu int0 noise rejecter circuit clock output circuit . . . wm.3 oscillator disable signal scc scc3 scc0 pcc0 pcc1 pcc2 pcc3 4 halt* stop* pcc2, pcc3 clear signal stop f/f qs r halt f/f s rq wait release signal from bt reset signal standby release signal from interrupt control circuit 1/4 f pcc remarks 1: f x = main system clock frequency 2: f xt = subsystem clock frequency 3: f= cpu clock 4: pcc: processor clock control register 5: scc: system clock control register 6: * indicates instruction execution. 7: one clock cysle (t cy ) of f is one machine cycle of an instruction. for t cy , refer to ac characteristics in 11. electrical specifications. fig. 6-1 clock generator block diagram 6.2 clock generator circuit the operation of the clock generator circuit is determined by the processor clock control regiser (ppc) and system clock control register (scc). this circuit can generate two types of clocks: main system clock and subsystem clock. in addition, it can also change the instruction execution time. ? 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 mhz) ? 122 m s (subsystem clock: 32.768 khz)
24 m pd75048 6.3 clock output circuit the clock output circuit outputs clock pulse from the p22/pcl pin. this clock pulse is used for supplying clock pulses to the remote control output, peripheral lsis, etc. ? clock output (pcl): f , 524 khz, 65.5 khz (at 4.19 mhz) selector output buffer pcl/p22 bit 2 of pmgb port2.2 port 2 input/ output mode specification bit p22 output latch internal bus clom3 clom2 clom1 clom0 clom 4 f f x /2 3 f x /2 4 f x /2 6 from the clock generator fig. 6-2 clock output circuit configuration remarks: a measures to prevent outputting narrow width pulse when selecting clock output enable/disable is taken.
25 m pd75048 6.4 basic interval timer the basic interval timer has these functions: ? interval timer operation which generates a reference time interrupt ? watchdog timer application which detects a program runaway ? selects the wait time for releasing the standby mode and counts the wait time ? reads out the count value from the clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx clear basic interval timer (8-bit frequency divider circuit) 3 4 8 bt clear set signal bt interrupt request flag irqbt wait release signal for standby release vector interrupt request signal internal bus btm3 btm2 btm1 btm0 btm *set1 remarks : *: instruction execution fig. 6-3 basic interval timer configuration
26 m pd75048 6.5 watch timer the m pd75048 has a built-in 1-ch watch timer. the clock timer has the following functions. ? sets the test flag (irqw) with 0.5sec interval. the standby mode can be released by irqw. ? 0.5 second interval can be generated either from the main system clock or subsystem clock. ? time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. this is convenient for program debugging, test, etc. ? arbitrary frequency (2.048khz/4.096khz/32.768khz) can be output to the p23/buz pin. this can be used for beep and system clock frequency trimming. ? the frequency divider circuit can be cleared so that zero second clock start is possible. ( ) is for f x = 4.194304 mhz, f xt = 32.768 khz. fig. 6-4 clock timer block diagram f w (32.768 khz) frequency divider selector selector clear selector output buffer p23/buz bit 2 of pmgb port 2 input/output mode p23 output latch port2.3 wm wm7 0 wm5 wm4 wm3 wm2 wm1 wm0 bit test instruction internal bus 8 4 khz 2 khz intw irqw set signal ( ) 2 hz 0.5 sec ( ) f w 2 7 (256 hz:3.91 ms) f x 128 (32.768 khz) f xt (32.768 khz) from the clock generator f w 2 14
27 m pd75048 6.6 timer/event counter the m pd75048 has a built-in 1-ch timer/event counter. the timer/event counter has the following functions. ? programmable interval timer operation ? outputs square-wave signal of an arbitrary frequency to the pto0 pin. ? event counter operation ? divides the ti0 pin input in n and outputs to the pto0 pin (frequency divider operation). ? supplies serial shift clock to the serial interface circuit. ? count condition read out function
28 m pd75048 fig. 6-5 timer/event counter block diagram internal bus 8 8 set1* tm07 tm06 tm05 tm04 tm03 tm02 tm01 tm00 tm0 port1.3 input buffer p13/ti0 from the clock generator mpx *: instruction execution timer operation start signal cp 8 8 modulo register (8) comparator (8) count register (8) clear t0 tmod0 reset toe0 port2.0 bit 2 of pgmb to serial interface p20/pto0 intt0 irqt0 set signal () reset irqt0 clear signal output buffer tout f/f to enable flag p20 output latch port 2 input/ output mode coinci- dence 8
29 m pd75048 6.7 serial interface the m pd75048 is equipped with an 8-bit clocked serial interface that operates in the following four modes: ? operation stop mode ? three-line serial i/o mode ? two-line serial i/o mode ? sbi mode (serial bus interface mode)
30 m pd75048 internal bus 8/4 8 88 csim p03/si/sb1 p02/so/sb0 p01/sck p01 output latch selector selector bit test slave address register (sva) address comparator shift register (sio) set clr bit manipulation (8) (8) coincidence signal sbic relt cmdt so latch bit test ackt acke bsye busy/ acknowledge output circuit bus release/ command/ acknowledge detector circuit reld cmdd ackd serial clock counter serial clock control circuit intcsi control circuit serial clock selector i ntcsi irqcsi set signal ( ) dq f x /2 3 f x /2 4 f x /2 6 tout f/f (from timer/ event counter) external sck (8) fig. 6-6 serial interface block diagram
31 m pd75048 6.8 a/d converter the m pd75048 has an 8-bit precision successive approximation a/d converter with 8 analog input channels (an0 to an7). fig. 6-7 a/d converter block diagram an0/p110 an1/p111 an2/p112 an3/p113 an4 an5 an6 an7 av ref+ av ref- multiplexer sample hold circuit + ? tap decoder r/2 r/2 rr r serial resister string 8 8 sa register (8) control circuit internal bus 0 adm6 adm5 adm4 soc eoc 00 adm comparator
32 m pd75048 6.9 multi-function timer (mft) the m pd75048 contains 1 channel of multi-function timer (mft). the mft has the following four modes and functions: 8-bit timer mode functions as programmable interval timer outputs square waves of arbitrary frequency to the ppo pin pwm mode outputs 6/7/8-bit precision pwm signal to the ppo pin 16-bit free running timer mode functions as interval timer which generates an interrupt with specified interval can be used as one-shot timer integration type a/d converter mode outputs 16-bit integration type a/d converter control signal 13/14/15/16-bit precision selectable
33 m pd75048 fig. 6-8 multi-function timer block diagram internal bus output latch p21 p100 p101 p102 input/ output mode register maz/p102 mai/p101 mar/p100 ppo/p21 intmft irqmft set signal () integration type a/d converter controller mft f/f reset irqmft clear signal interrupt selector tap selector overflow count register (mfth) selector selector comparator selector count register (mftl) modulo latch clear 88 mpx edge selector mat/p103 mftm7 mftm6 mftm5 mftm4 mftm3 mftm2 mftm1 mftm0 mftm 8 1/4 mftc3 mftc2 mftc1 mftc0 f x /2 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 internal bus mftc 8 coinci -dence
34 m pd75048 6.10 bit sequential buffer .... 16 bits the bit sequential buffer is a data memory specifically provided for bit manipulation. with this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. therefore, this buffer is very useful for processing long data in bit units. remarks: for the pmem.@l addressing, the specification bit is shifted according to the l register. fig. 6-9 bit sequential buffer format address bit symbol l register 32103210 32103210 l = f l = c l = b l = 8 l = 7 l = 4 l = 3 l = 0 bsb3 bsb2 bsb1 bsb0 decs l incs l fc3h fc2h fc1h fc0h 7. interrupt functions the m pd75048 has 9 different interrupt sources. in addition to that, multiple interrupt by software control is also possible. the m pd75048 is also provided with two types of test sources, of which int2 was two types of edge detection testable inputs. the interrupt control circuit of the m pd75048 has these functions: ? hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (iexxx) and interrupt master enable flag (ime). ? the interrupt start address can be arbitrarily set. ? interrupt request flag (irqxxx) test function (an interrupt generation can be confirmed by means of software). ? standby mode release (interrupts to be released can be selected by the interrupt enable flag).
35 m pd75048 fig. 7-1 interrupt control circuit block diagram 2 13 im2 im1 im0 irqbt irq4 irq0 irq1 irqcsi irqt0 irqmft irqee irqow irqw irq2 im2 int bt int4 /p00 int0 /p10 int1 /p11 intcsi intt0 intmft intee intow intw kr0/p60 int2 / p12 kr7/p73 selector edge detection circuit edge detection circuit both edge detection circuit interrupt enable flag (iexxx) internal bus ime ist0 decoder vrqn priority control circuit vector table address generator standby release signal * : noise elimination circuit * rising edge detection circuit falling edge detection circuit
36 m pd75048 8. standby functions the m pd75048 has two different standby modes (stop mode and halt mode) to reduce the power consumption while waiting for program execution. table 8-1 each status in standby mode stop mode halt mode setting instruction stop instrtuction halt instruction can be set only when operating on the main system clock can be set either with the main system clock or the subsystem clock operation status clock generator only the main system clock stops its operation only the cpu clock f stops its operation (oscillation continues) basic interval timer no operation operates only when main system clock oscillates (sets irqbt at reference time interval) serial interface can operate only when the external sck input is selected for the serial clock operates only when external sck input is selected as serial clock, or when main system clock oscillates timer/event counter can operate only when the ti0 pin input is selected for the count clock operates only when ti0 pin input is selected as count clock, or when main system clock oscillates watch timer can operate when f xt is selected as the count clock can operate a/d convertor no operation can operate * multi function timer no operation can operate * eeprom no operation can operate * external interrupt int1, int2, and int4 can operate. only int0 can not operate. cpu no operation release signal an interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the reset input. an interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the reset input. system clock for setting *: operation is possible only when the main system clock is operating.
37 m pd75048 timer/event counter (t0) 0 0 counter modulo register ffh ffh (tmod0) mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 watch timer mode register (wm) 0 0 9. reset function when the reset signal is input, the m pd75048 is reset and each hardware is initialized as indicated in table 9-1. fig. 9-1 shows the reset operation timing. reset input wait (31.3ms/4.19mhz) operation mode or standby mode halt mode operation mode internal reset operation fig. 9-1 reset operation by reset input table 9-1 status of each hardware after reset (1/2) hardware reset input in standby mode reset input during operation program counter (pc) the contents of the lower 5 bits of address 0000h of the program memory are set to pc12-8, and the contents of address 0001h are set to pc7-0. the contents of the lower 5 bits of address 0000h of the program memory are set to pc12-8, and the contents of address 0001h are set to pc7-0. psw carry flag (cy) retained undefined skip flag (sk0-2) interrupt status flag (ist0) bank enable flag (mbe) the contents of bit 7 of address 0000h of the program memory is set to mbe. stack pointer (sp) undefined undefined data memory (ram) retained * undefined data memory (eeprom) eeprom contents of address being written is undefined. contents of address being written is undefined. eeprom write control register general-purpose register (x, a, h, l, d, e, b, c) retained undefined bank selection register (mbs) basic interval timer counter (bt) undefined undefined mode register (btm) the contents of bit 7 of address 0000h of the program memory is set to mbe. *: the data at the addresses 0f8h-0fdh of data memory is undefined by reset input. 0 0 0 0 0 0 0 0 0 0
38 m pd75048 serial shift register (sio) retained undefined interface operation mode 0 0 register (csim) sbi control register 0 0 (sbic) slave address register retained undefined (sva) clock processor clock control 0 0 generator, register (pcc) clock output system clock control 0 0 circuit register (scc) clock output mode 0 0 register (clom) irq1, irq2, undefined undefined irq4 other than 0 0 above interrupt interrupt enable flag 0 0 function (iexxx) interrupt master enable 0 0 flag (ime) int0, int1, int2 mode 0, 0, 0 0, 0, 0 registers (im0, im1, im2) digital port output buffer off off output latch clear (0) clear (0) input/output mode 0 0 register (pmga, pmgb, pmgc) pull-up resistor 0 0 specification register (poga, pogb) pull-down resistor 0 0 specification register (pdgb) counter (mftl) ffh ffh counter (mfth) 0 0 mode register (mftm) 0 0 control register (mftc) 0 0 a/d converter mode register (adm) 04h 04h sa register (sa) retained undefined bit sequential buffer (bsb0-3) retained undefined table 9-1 status of each hardware after reset (2/2) hardware reset input in standby mode reset input during operation interrupt request flag (irqxxx) h multi-function timer
39 m pd75048 10. instruction set (1) operand representation and description describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to ra75x assembler package user's manual - language (eeu-730). with some instructions, only one operand should be selected from several operands. the uppercase characters, +, and - are keywords and must be described as is. describe an appropriate numeric value or label as immediate data. the symbols of the register flags can be described in the places of mem, fmem, pmem, and bit. (for details, refer to m pd75048 user's manual (ieu-704). however, fmem and pmem restricts the label that can be described. representation description reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rpa hl, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem* 8-bit immediate data or label bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label addr 0000h to 1f7fh immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (where bit0=0) or label portn port0 to port11 iexxx iebt, iecsi, iet0, ie0, ie1, ie2, ie4, iew, iemft, ieee, ieow mbn mb0, mb1, mb4, mb5, mb6, mb7, mb15 *: only even addresses can be described as mem for 8-bit data processing.
40 m pd75048 (2) legend of operation field a : a register; 4-bit accumulator b : b register; 4-bit accumulator c : c register; 4-bit accumulator d : d register; 4-bit accumulator e : e register; 4-bit accumulator h : h register; 4-bit accumulator l : l register; 4-bit accumulator x : x register; 4-bit accumulator xa : register pair (xa); 8-bit accumulator bc : register pair (bc); 8-bit accumulator de : register pair (de); 8-bit accumulator hl : register pair (hl); 8-bit accumulator pc : program counter sp : stack pointer cy : carry flag; or bit accumulator psw : program status word mbe : memory bank enable flag portn : port n (n = 0 to 11) ime : interrupt master enable flag iexxx : interrupt enable flag mbs : memory bank selector register pcc : processor clock control register . : delimiter of address and bit (xx) : contents addressed by xx xxh : hexadecimal data
41 m pd75048 (3) symbols in addressing area field *1 mb = mbe . mbs (mbs = 0, 1, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (00h-7fh) data memory mb = 15 (80h-ffh) addressing mbe = 1 : mb = mbs (mbs = 0, 1, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 addr = 0000h-1f7fh *7 addr = (current pc) -15 to (current pc) - 1 (current pc) +2 to (current pc) + 16 program *8 caddr = 0000h-0fffh (pc 12 = 0) or memory 1000h-1f7fh (pc 12 = 1) addressing *9 faddr = 0000h-07ffh *10 taddr = 0020h-007fh *11 mb = mbe . mbs (mbs = 0, 1, 4, 5, 6, 7, 15) data memory *12 mbe = 0: mb = 0 (00h-7fh) addressing mb = 15 (80h-ffh) mbe = 1: mb = mbs (mbs = 0, 1, 4, 5, 6, 7, 15) remarks 1: mb indicates memory bank that can be accessed. 2: in *2, mb = 0 regardless of mbe and mbs. 3: in *4 and *5, mb = 15 regardless of mbe and mbs. 4: *6 to *10 indicate areas that can be addressed. 5: when mbs is 4, 5, 6 or 7, addressing area is in the eeprom area. (4) machine cycle field in this field, s indicates the number of machine cycles required when an instruction having a skip function skips. the value of s varies as follows: when no instruction is skipped .................................................................................. s = 0 when 1-byte or 2-byte instruction is skipped ........................................................... s = 1 when 3-byte instruction (br !addr or call !addr) is skipped .............................. s = 2 note : the geti instruction is skipped in one machine cycle. one machine cycle equals to one cycle of the cpu clock f , (=t cy ), and can be changed in three steps depending on the setting of the processor clock control register (pcc).
42 m pd75048 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area transfer mov a, #n4 1 1 a ? n4 string effect a reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 string effect a hl, #n8 2 2 hl ? n8 string effect b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *11 a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *11 @hl, a 1 1 (hl) ? a *11 @hl, xa 2 2 (hl) ? xa *11 a,mem 2 2 a ? (mem) *12 xa, mem 2 2 xa ? (mem) *12 mem, a 2 2 (mem) ? a *12 mem, xa 2 2 (mem) ? xa *12 a, reg 2 2 a ? reg xa, rp 2 2 xa ? rp reg1, a 2 2 reg1 ? a rp1, xa 2 2 rp1 ? xa xch a, @hl 1 1 a ? (hl) *11 a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *11 a, mem 2 2 a ? (mem) *12 xa, mem 2 2 xa ? (mem) *12 a, reg1 1 1 a ? reg1 xa, rp 2 2 xa ? rp table movt xa, @pcde 1 3 xa ? (pc 12-8 +de) rom reference xa, @pcxa 1 3 xa ? (pc 12-8 +xa) rom arith- adds a, #n4 1 1+s a ? a+n4 carry metic a, @hl 1 1+s a ? a+(hl) *11 carry opera- addc a, @hl 1 1 a, cy ? a+(hl)+cy *11 tion subs a, @hl 1 1+s a ? a-(hl) *11 borrow subc a, @hl 1 1 a, cy ? a-(hl)-cy *11 and a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *11 or a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *11 xor a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *11 accumu- rorc a 1 1 cy ? a 0 , a 3 ? cy, a n-1 ? a n lator manipu- not a 2 2 a ? a lation
43 m pd75048 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area incre- incs reg 1 1+s reg ? reg+1 reg = 0 ment/ @hl 2 2+s (hl) ? (hl)+1 *11 (hl) = 0 decre- mem 2 2+s (mem) ? (mem)+1 *12 (mem) = 0 ment decs reg 1 1+s reg ? reg-1 reg = fh compare ske reg, #n4 2 2+s skip if reg = n4 reg = n4 @hl, #n4 2 2+s skip if (hl) = n4 *11 (hl) = n4 a, @hl 1 1+s skip if a = (hl) *11 a = (hl) a, reg 2 2+s skip if a = reg a = reg carry set1 cy 1 1 cy ? 1 flag clr1 cy 1 1 cy ? 0 manipu- skt cy 1 1+s skip if cy = 1 cy = 1 lation not1 cy 1 1 cy ? cy memory/ set1 mem.bit 2 2 (mem.bit) ? 1 *3 bit fmem.bit 2 2 (fmem.bit) ? 1 *4 manipu- pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 1*5 lation @h+mem.bit 2 2 (h + mem 3-0 .bit) ? 1*1 clr1 mem.bit 2 2 (mem.bit) ? 0 *3 fmem.bit 2 2 (fmem.bit) ? 0 *4 pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 ) ? 0*5 @h+mem.bit 2 2 (h+mem 3-0 .bit) ? 0*1 skt mem.bit 2 2+s skip if(mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+s skip if(fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit (l 1-0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2+s skip if(h + mem 3-0 .bit) = 1 *1 (@h+mem.bit) = 1 skf mem.bit 2 2+s skip if(mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+s skip if(fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit (l 1-0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2+s skip if (h + mem 3-0 .bit) = 0 *1 (@h+mem.bit) = 0 sktclr fmem.bit 2 2+s skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit *5 (pmem.@l) = 1 (l 1-0 )) = 1 and clear @h+mem.bit 2 2+s skip if (h+mem 3-0 . bit) = 1 and clear *1 (@h+mem.bit) = 1 and1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1 or1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit (l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1 xor1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit (l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1
44 m pd75048 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area branch br addr pc 12-0 ? addr *6 (the most suitable instruction is selectable from among br !addr, brcb !caddr, and br $addr depending on the assembler.) !addr 3 3 pc 12-0 ? addr *6 $addr 1 2 pc 12-0 ? addr *7 brcb !caddr 2 2 pc 12-0 ? pc 12 + caddr 11-0 *8 subrou- call !addr 3 3 (sp-4)(sp-1)(sp-2) ? pc 11-0 *6 tine/ (sp-3) ? mbe,0, 0, pc 12 stack pc 12-0 ? addr,sp ? sp-4 callf !faddr 2 2 (sp-4)(sp-1)(sp-2) ? pc 11-0 *9 (sp-3) ? mbe,0, 0, pc 12 pc 12-0 ? 00,faddr,sp ? sp-4 ret 1 3 mbe,x,x,pc 12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) sp ? sp+4 rets 1 3+s mbe,x,x,pc 12 ? (sp+1) unconditional pc 11-0 ? (sp)(sp+3)(sp+2) sp ? sp+4, then skip unconditionally reti 1 3 mbe,x,x,pc 12 ? (sp+1) pc 11-0 ? (sp)(sp+3)(sp+2) psw ? (sp+4)(sp+5), sp ? sp+6 push rp 1 1 (sp-1)(sp-2) ? rp, sp ? sp-2 bs 2 2 (sp-1) ? mbs,(sp-2) ? 0,sp ? sp-2 pop rp 1 1 rp ? (sp+1)(sp),sp ? sp+2 bs 2 2 mbs ? (sp+1),sp ? sp+2 inter- ei 2 2 ime ? 1 rupt iexxx 2 2 iexxx ? 1 control di 2 2 ime ? 0 iexxx 2 2 iexxx ? 0 i/o in a,portn 2 2 a ? port n (n = 0-11) xa,portn 2 2 xa ? port n+1 ,port n (n = 4, 6) out portn,a 2 2 port n ? a (n = 2-10) portn,xa 2 2 port n+1 ,port n ? xa (n = 4, 6) cpu halt 2 2 set halt mode(pcc.2 ? 1) control stop 2 2 set stop mode (pcc.3 ? 1) nop 1 1 no operation special sel mbn 2 2 mbs ? n(n=0, 1, 4, 5, 6, 7, 15) geti taddr 1 3 . where tbr instruction, *10 pc 12-0 ? (taddr) 4-0 +(taddr+1) . where tcall instruction, (sp-4)(sp-1)(sp-2) ? pc 11-0 (sp-3) ? mbe, 0, 0, pc 12 pc 12-0 ? (taddr) 4-0 +(taddr+1) sp ? sp-4 . except for tbr and tcall depends on instructions, referenced instruction execution of instruction (taddr)(taddr+1) note : when executing the in/out instruction, mbe = 0, or mbe = 1, and mbs = 15. remarks : tbr and tcall instructions are assembler seudo-instructions for the table definition of geti instruction. h control
45 m pd75048 11. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd -0.3 to +7.0 v input voltage v i1 other than ports 4, 5, 10 -0.3 to v dd +0.3 v v i2 ports 4, 5, 10 w/pull-up -0.3 to v dd +0.3 v resistor open drain -0.3 to +11 v output voltage v o -0.3 to v dd +0.3 v high-level output i oh 1 pin -10 ma current all pins -30 ma low-level output i ol * ports 0, 3, 4, 5 peak 30 ma current 1 pin rms 15 ma other than ports 0, 3, 4, 5 peak 20 ma 1 pin rms 5 ma total of ports 0, 3 - 9, 11 peak 170 ma rms 120 ma total of ports 0, 2, 10 peak 30 ma rms 20 ma operating temperature t opt -10 to +70 c storage temperature t stg -65 to +150 c *: rms = peak value x ? duty note : even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure not to exceed or fall below this value when using the product. eeprom ratings (t a = -10 to +70 c, v dd = 2.7 to 6.0 v) parameter symbol conditions m write times 100,000 times data retention time 10 years capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 15 pf output capacitance c o pins other than thosemeasured are at 0 v 15 pf input/output c io 15 pf h
46 m pd75048 main system clock oscillator circuit characteristics (t a = -10 to +70 c, v dd = 2.7 to 6.0 v) oscillator recommended item conditions min. typ. max. unit constants ceramic oscillation v dd = oscillation 2.0 5.0 * 3 mhz frequency(f x )* 1 voltage range oscillation stabiliza- after v dd come to tion time* 2 min. value of oscillation voltage 4ms range crystal oscillation 2.0 4.19 5.0 * 3 mhz frequency (f x )* 1 oscillation stabiliza- v dd = 4.5 to 6.0 v 10 ms tion time* 2 30 ms external clock x1 input frequency 2.0 5.0 * 3 mhz (f x )* 1 x1 input high-, low-level widths (t xh , t xl ) 100 250 ns *1: only to express the characteristics of the oscillator circuit. for instruction execution time, refer to ac characteristics. 2: time required for oscillation to stabilize after v dd has reached the minimum volue of the oscillation voltage range or the stop mode has been released. 3: when the oscillation frequency is 4.19 mhz < fx 5.0 mhz, do not select pcc = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 m s, falling short of the rated minimum value of 0.95 m s. note : when using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: ? keep the wiring length as short as possible. ? do not cross the wiring over the other signal lines. ? do not route the wiring in the vicinity of lines through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as v dd . do not connect the ground pattern through which a high curent flows. ? do not extract signals from the oscillation circuit. x1 x2 pd74hcu04 m x1 x2 c1 c2 v dd x1 x2 c1 c2 v dd h
47 m pd75048 subsystem clock oscillator circuit characteristics (t a = -10 to +70 c, v dd = 2.7 to 6.0 v) oscillator recommended item conditions min. typ. max. unit constants crystal oscillation 32 32.768 35 khz frequency (f xt )* 1 oscillation stabiliza- v dd = 4.5 to 6.0 v 1.0 2 ms tion time* 2 10 ms external clock xt1 input frequency 32 100 khz (f xt )* 1 xt1 input high-, low-level widths (t xth , t xtl ) 515 m s *1: indicates only the characteristics of the oscillator circuit. for instruction execution time, refer to ac characteristics. 2: time required for oscillation to stabilize after v dd has reached the minimum value of the oscillation voltage range. note : when using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: ? keep the wiring length as short as possible. ? do not cross the wiring over the other signal lines. ? do not route the wiring in the vicinity of lines through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as v dd . do not connect the ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. the amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. when using the subsystem clock, therefore, exercise utmost care in wiring the circuit. xt1 xt2 r c3 c4 v dd xt1 xt2 h
48 m pd75048 dc characteristics (t a = -10 to +70 c, v dd = 2.7 to 6.0 v) parameter symbol conditions min. typ. max. unit high-level input v ih1 ports 2,3,8,9,11 0.7v dd v dd v voltage v ih2 ports 0,1,6,7, reset 0.8v dd v dd v v ih3 ports 4,5,10 w/pull-up resistor 0.7v dd v dd v open-drain 0.7v dd 10 v v ih4 x1, x2, xt1, xt2 v dd -0.5 v dd v low-level input v il1 ports 2-5, 8-11 0 0.3v dd v voltage v il2 ports 0, 1, 6, 7, reset 0 0.2v dd v v il3 x1, x2, xt1, xt2 0 0.4 v high-level output v oh v dd = 4.5 to 6.0v, i oh = -1 ma v dd -1.0 v voltage i oh = -100 m av dd -0.5 v low-level output v ol ports 3,4,5 v dd = 4.5 to 6.0v, 0.4 2.0 v voltage i ol = 15ma v dd = 4.5 to 6.0v, i ol = 1.6 ma 0.4 v i ol = 400 m a 0.5 v sb0, 1 open-drain pull-up 0.2v dd v resistor 3 1 k w high-level input i lih1 v i = v dd other than below 3 m a leakage current i lih2 x1,x2,xt1 20 m a i lih3 v i = 9v ports 4,5,10 20 m a (open-drain) low-level input i lil1 v i = 0v other than below -3 m a leakage current i lil2 x1,x2,xt1 -20 m a high-level output i loh1 v o = v dd other than below 3 m a leakage current i loh2 v o = 9v ports 4,5,10 20 m a (open-drain) low-level output i lol v o = 0v -3 m a leakage current internal pull-up resistor r u1 ports 0,1,2,3,6,7,8 v dd = 5.0v 10% 15 40 80 k w (except p00) v i = 0v v dd = 3.0v 10% 30 300 k w r u2 ports 4,5,10 v dd = 5.0v 10% 15 40 70 k w v o = v dd -2.0 v v dd = 3.0v 10% 10 60 k w internal pull-down r d port 9 v in = v dd v dd = 5.0v 10% 15 40 70 k w resistor v dd = 3.0v 10% 10 60 k w
49 m pd75048 parameter symbol conditions min. typ. max. unit supply current * 1 i dd1 4.19mhz crystal v dd = 5v 10%* 2 3.5 10 ma oscillator v dd = 3v 10%* 3 0.65 1.8 ma i dd2 c1 = c2 = 22pf halt mode v dd = 5v 10% 800 2400 m a v dd = 3v 10% 350 1000 m a i dd3 32.768khz* 4 crystal operation v dd = 3v 10% 70 210 m a oscillator mode i dd4 halt mode v dd = 3v 10% 20 60 m a i dd5 xt1 = 0v v dd = 5v 10% 0.5 20 m a stop mode v dd = 3v 10% 0.3 10 m a t a = 25 c5 m a i dd6 32.768khz oscillator v dd = 3v 10%* 5 620 m a stop mode *1: current flowing through internal pull-up resistor. current flowing when eeprom is accessed is not included. 2: when m pd75048 operates in high-speed mode with processor clock control register (pcc) set to 0011. 3: when m pd75048 operates in low-speed mode with pcc set to 0000. 4: when the system clock control register (scc) is set to 1001, the oscillation of the main system clock is stopped, and the subsystem clock is used. 5: when stop instruction is executed with scc set to 0000. note : supply current when eeprom is accessed is shown in eeprom characteristics.
50 m pd75048 ac characteristics (t a = -10 to +70 c, v dd = 2.7 to 6.0 v) parameter symbol conditions min. typ. max. unit cpu clock cycle time t cy w/main system clock v dd = 4.5-6.0v 0.95 32 m s (minimum instruction 3.8 32 m s execution time w/subsystem clock 114 122 125 m s = 1 machine cycle)* 1 ti0 input frequency f ti v dd = 4.5 to 6.0 v 0 1 mhz 0 275 khz ti0 input high-, low- t tih ,v dd = 4.5 to 6.0 v 0.48 m s level widths t til 1.8 m s interrupt input high-, t inth , int0 *2 m s low-level widths t intl int1, 2, 4 10 m s kr0-7 10 m s reset low-level width t rsl 10 m s *1: the cpu clock ( f ) cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (scc), and processor clock control register (pcc). the figure on the right is cycle time t cy vs. supply voltage v dd characteristics at the main system clock. *2: 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). 0123 456 0.5 1 2 3 4 5 6 32 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (with main system clock) operation guaranteed range m [ m s]
51 m pd75048 serial transfer operation two-line and three-line serial i/o modes (sck: internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-, low-level t kl1 v dd = 4.5 to 6.0 v t kcy1 /2-50 ns widths t kh1 t kcy1 /2-150 ns si set-up time (vs. sck - ) t sik1 150 ns si hold time (vs. sck - ) t ksi1 400 ns sck ? so output t kso1 r l = 1k w , c l = 100pf* v dd = 4.5 to 6.0v 250 ns delay time 1000 ns two-line and three-line serial i/o modes (sck: external clock input) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 4.5 to 6.0v 800 ns 3200 ns sck high-, low-level t kl2 v dd = 4.5 to 6.0v 400 ns widths t kh2 1600 ns si set-up time (vs. sck - ) t sik2 100 ns si hold time (vs. sck - )t ksi2 400 ns sck ? so output t kso2 r l = 1k w , c l = 100 pf* v dd = 4.5 to 6.0v 300 ns delay time 1000 ns *: r l and c l are load resistance and load capacitance of the so output line.
52 m pd75048 sbi mode (sck: internal clock output (master)) parameter symbol conditions min. typ. max. unit sck cycle time t kcy3 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-, low-level t kl3 v dd = 4.5 to 6.0 v t kcy3 /2-50 ns widths t kh3 t kcy3 /2-150 ns sb0, 1 set-up time t sik3 150 ns (vs. sck - ) sb0, 1 hold time t ksi3 t kcy3 /2 ns (vs. sck - ) sck ? sb0, 1 output t kso3 r l = 1k w , c l = 100pf* v dd = 4.5 to 6.0v 0 250 ns delay time 0 1000 ns sck -? sb0, 1 t ksb t kcy3 ns sb0,1 ? sck t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns sbi mode (sck: external clock input (slave)) parameter symbol conditions min. typ. max. unit sck cycle time t kcy4 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck ligh-, low-level t kl4 v dd = 4.5 to 6.0 v 400 ns widths t kh4 1600 ns sb0, 1 set-up time t sik4 100 ns (vs. sck - ) sb0, 1 hold time t ksi4 t kcy4/2 ns (vs. sck - ) sck ? sb0, 1 output t kso4 r l = 1k w , c l = 100pf* v dd = 4.5 to 6.0v 0 300 ns delay time 0 1000 ns sck -? sb0, 1 t ksb t kcy4 ns sb0,1 ? sck t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns *: r l and c l are load resistance and load capacitance of the sb0 and sb1 output lines.
53 m pd75048 a/d converter (t a = -10 to +70 c, v dd = 2.7 to 6.0v, av ss = v ss = 0v) parameter symbol conditions min. typ. max. unit resolution 88 8bit absolute accuracy* 1 2.5v av ref v dd 1.5 lsb conversion time* 2 t conv 168/f x m s sampling time* 3 t samp 44/f x m s analog input voltage v ian av ref- av ref+ v analog supply voltage av dd 2.5 v dd v reference input voltage av ref+ 2.5v (av ref+ ) C (av ref- ) 2.5 av dd v reference input voltage av ref- 2.5v (av ref+ ) C (av ref- ) 0 1.0 v analog input impedance r an 1000 m w av ref current ai ref 0.25 2.0 ma *1: absolute accuracy excluding quantization error ( 1 C 2 lsb) 2: time since execution of conversion start instruction until end of conversion (eoc = 1) (40.1 m s: f x = 4.19 mhz) 3: time since execution of conversion start instruction until end of sampling (10.5 m s: f x = 4.19 mhz)
54 m pd75048 ac timing test point (excluding x1 and xt1 inputs) test points 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd clock timing x1 input v dd ?.5v 0.4 v t xl t xh 1/f x xt1 input v dd ?.5v 0.4 v t xtl t xth 1/f xt ti0 timing ti0 t til t tih 1/f ti
55 m pd75048 serial transfer timing three-line serial i/o mode: sck t kl1 t kh1 t kcy1 output data t sik1 t ksi1 t ks01 input data si so two-line serial i/o mode: sck t kl2 t kh2 t kcy2 t sik2 t ksi2 t kso2 sb0,1
56 m pd75048 serial transfer timing bus release signal transfer: command signal transfer: sck t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t ks03,4 sb0,1 t kh3,4 t sbk t ksb interrupt input timing int0, 1, 2, 4 kr0-7 t intl t inth reset input timing reset t rsl sck t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t ks03,4 sb0,1 t kh3,4 t sbk t sbh t sbl t ksb
57 m pd75048 eeprom characteristics parameter symbol conditions min. typ. max. unit supply current for i dd7 4.19mhz crystal oscillator v dd = 5v+10%* 2 6.5 20 ma eeprom access* 1 c1 = c = 22pf v dd = 3v+10%* 3 26ma *1: current flowing through the internal pull-up resistor is not included. 2: when the processor clock control register (pcc) is set to 0011 and the high-speed mode is used. 3: when pcc is set to 0000 and the low-speed mode is used. eeprom write time select the write time of the eeprom in accordance with the oscillation frequency of the main system clock as follows: oscillation frequency of main setting of eeprom control register write time system clock (f x ) ewtc1 ewtc0 f x = 2.0 to 5.0 mhz 0 0 2 12 x 18/f x (17.6 ms) f x = 2.0 to 4.2 mhz 0 1 2 11 x 18/f x (8.8 ms) f x = 2.0 mhz 1 0 2 10 x 18/f x remarks: ( ): f x = 4.19 mhz low-voltage data retention characteristics of data memory in stop mode (t a = C10 to +70 c) parameter symbol conditions min. typ. max. unit data retention supply v dddr 2.0 6.0 v voltage i dddr v dddr = 2.0 v 0.1 10 m a release signal set time t srel 0 m s t wait released by reset 2 17 /f x ms released by interrupt request ms *1: does not include current flowing through internal pull-up resistor 2: the oscillation stabilization wait time is the time during which the cpu is stopped to prevent unstable operation when oscillation is started. 3: depends on the setting of the basic interval timer mode register (btm) as follows: btm3 btm2 btm1 btm0 wait time ( ): f x = 4.19 mhz C 0002 20 /f x (approx. 250 ms) C 0112 17 /f x (approx. 31.3 ms) C 1012 15 /f x (approx. 7.82 ms) C 1112 13 /f x (approx. 1.95 ms) oscillation stabilization wait time *2 data retention supply current *1 *3
58 m pd75048 data retention timing (releasing stop mode by reset) stop mode data retention mode stop instruction execution v dd reset v dddr t srel t wait operation mode internal reset operation halt mode data retention timing (standby release signal: releasing stop mode by interrupt) stop mode data retention mode stop instruction execution v dd v dddr t srel t wait operation mode halt mode standby release signal (interrupt request)
59 m pd75048 12. performance curve x1 x2 xt1 xt2 v dd v dd crystal crystal 4.19 mhz 32.768 khz 22 pf 22 pf 22 pf 22 pf 330 k w 01234567 supply voltage v dd (v) i dd vs v dd (crystal oscillation) (t = 25 c) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 supply current i dd (ma) high-speed mode pcc = 0011 main system clock halt mode subsystem clock operation mode subsystem clock halt mode subsystem clock oscillation medium-speed mode pcc = 0010 low-speed mode pcc = 0000 main system clock stop mode with main system clock stopped a
60 m pd75048 x1 x2 xt1 xt2 v dd v dd crystal crystal 2.0 mhz 32.768 khz 22 pf 22 pf 22 pf 22 pf 330 k w 01234567 supply voltage v dd (v) i dd vs v dd (crystal oscillation) (t = 25 c) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 supply current i dd (ma) high-speed mode pcc = 0011 low-speed mode pcc = 0000 main system clock halt mode subsystem clock operation mode subsystem clock halt mode subsystem clock oscillation medium-speed mode pcc = 0010 with main system clock stopped main system clock stop mode a
61 m pd75048 13. package drawings a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15? 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15? +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil)
62 m pd75048 n a m f b 48 49 32 k l 64 pin plastic qfp ( 14) 64 1 17 16 33 d c detail of lead end s q 55? p m i h j g p64gc-80-ab8-3 item millimeters inches a b c d f g h i j k l 17.6 0.4 14.0 0.2 1.0 0.35 0.10 0.15 14.0 0.2 0.693 0.016 0.039 0.039 0.006 0.031 (t.p.) 0.551 note m n 0.10 0.15 1.8 0.2 0.8 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.008 0.014 0.551 0.8 0.2 0.031 p 2.55 0.100 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 2.85 max. 0.112 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008
63 m pd75048 14. recommended soldering conditions it is recommended that m pd75048 be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document "semiconductor devices mounting manual" (iei-616). for other soldering methods and conditions, consult nec. table 14-1 soldering conditions of surface mount type m pd75048gc - xxx - ab8: 64-pin plastic qfp ( 14 mm) soldering method soldering conditions symbol for recommended condition ware soldering soldering bath temperature: 260 c max., ws60-162-1 time: 10 seconds max., number of times: 1, maximum number of days: 2 days*, (beyond this period, 16 hours of pre-baking is required at 125 c), pre-heating temperature: 120 c max. infrared reflow package peak temperature: 230 c, ir30-162-1 time: 30 seconds max. (210 c min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125 c) vps package peak temperature: 215 c, vp15-162-1 time: 40 seconds max. (200 c min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125 c) pin partial heating pin temperature: 300 c max., time: 3 seconds max. (per side) *: number of days after unpacking the dry pack. storage conditions are 25 c and 65%rh max. note: do not use two or more soldering methods in combination (except the pin partial heating method). table 14-2 soldering conditions of through-hole type m pd75048cw - xxx: 64-pin plastic shrink dip (750 mil) soldering method soldering conditions wave soldering soldering bath temperature: 260 c max., (lead parts only) time: 10 seconds max., pin partial heating pin temperature: 260 o c max., time: 10 seconds max. caution: the wave soldering must be performed at the lead part only. note that the soldering must not be directly contacted to the board. a model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235 c, numbver of times:2, and an extended number of days) is also available. for details, consult nec. notice
64 m pd75048 appendix a. differences between m pd75048 and 75028/75008 functions item m pd75048 m pd75028 m pd75008 rom (bytes) 8064 ram (x4 bits) 512 eeprom (x4 bits) 1024 none instruction main system clock 0.95 m s, 1.91 m s, 15.3 m s (4.19 mhz) cycle subsystem clock 122 m s (32.768 khz) i/o port cmos input pull-up via software: 27 (except p00) pull-up via software cmos i/o 48 24 pull-down via software: 4 34 18 (except p00) n-ch open- (10 v, pull-up by mask option) (10 v, pull-up drain i/o by mask option) a/d converter 8-bit resolution x 8 channels none low-voltage operation: v dd = 2.7 - 6.0 16-bit multifunction timer 8-bit timer mode 1 ch pwm output mode none 16-bit free running timer mode 16-bit integral a/d converter mode vector interrupt external: 3, internal: 6 external: 3, internal: 4 external: 3, internal: 3 test input external: 1, internal: 1 buzzer output (buz) 2 khz, 4 khz, 32 khz (at 4.19 mhz, 32.768 khz operation) 2 khz (at 4.19 mhz, 32.768 khz operation) package 64-pin plastic shrink dip (750 mil) 42-pin plastic shrink dip (600 mil) 64-pin plastic qfp ( 14 mm) 44-pin plastic qfp ( 10 mm) supply voltage v dd = 2.7 - 6.0 v operating temperature -10 to +70 c -40 to +70 c -40 to +85 c prom model m pd75p048 m pd75p036 m pd75p008 8 8 12 12 h
65 m pd75048 appendix b. development tools the following development tools are readily available to support development of systems using m pd75048: hardware ie-75000-r *1 in-circuit emulator for 75x series ie-75001-r ie-75000-r-em *2 emulation board for ie-75000-r and ie-75001-r ep-75028cw-r emulation prove for m pd75048 ep-75028gc-r emulation prove for m pd75048, provided with ev-9200gc-64, 64-pin conversion socket pg-1500 prom programmer pa-75p036gc prom programmer adapter solely used for m pd75p048gc. it is connected to pg-1500. pa-75p036cw prom programmer adapter solely used for m pd75p048cw. it is connected to pg-1500. software ie control program host machine pg-1500 controller pc-9800 series (ms-dos tm ver. 3.30 to ver. 5.00a *3 ) ra75x relocatable ibm pc/at tm (pc dos tm ver. 3.1) assembler *1: maintenance product 2: not provided with ie-75001-r. 3: ver. 5.00/5.00a has a task swap function, but this function cannot be used with this software. remarks : for development tools from other companies, refer to 75x series selection guide (if- 151). ev-9200gc-64
66 m pd75048 [memo]
67 m pd75048 static electricity (all mos devices) exercise care so that mos devices are not adversely influenced by static electricity while being handled. the insulation of the gates of the mos device may be destroyed by a strong static charge. therefore, when transporting or storing the mos device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case nec uses for packaging and shipment, and use grounding when assembling the mos device system. do not leave the mos device on a plastic plate and do not touch the pins of the device. handle boards on which mos devices are mounted similarly . processing of unused pins (cmos devices only) fix the input level of cmos devices. unlike bipolar or nmos devices, if a cmos device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. therefore, fix the input level of the device by using a pull-down or pull-up resistor. if there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to v dd or gnd through a resistor. refer to processing of unused pins in the documents of each devices. a status before initialization (all mos devices) the initial status of mos devices is undefined upon power application. since the characteristics of an mos device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. the output status of pins, i/o setting, and register contents upon power application are not guaranteed. however, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. when using a device with a reset function, be sure to reset the device after power application. general notes on cmos devices
68 m pd75048 nec is manufacturing and selling the products under microcomputer (with on-chip eeprom) patent license with the bull cp8. this product should not be used for ic cards (smart card). no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for the applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime system, etc. ms-dos is a trademark of microsoft corporation. pc dos and pc/at are trademarks of ibm corporation. [memo] m4 92.6

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