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hd66205 (dot matrix liquid crystal graphic display common driver with 80-channel outputs) description the hd66205f/hd66205fl/hd66205tf/hd 66205tfl/hd66205t/hd66205tl, the row lcd driver, features low output impedance and as many as 80 lcd outputs powered by 80 internal lcd drive circuits, and can drive a large liquid crystal graphic display. because this device is fabricated by the cmos process, it is suitable for battery- driven portable equipment, which fully utilizes the low power dissipation of liquid crystal elements. the hd66205 has a complete line-up: the hd66205f, a standard device powered by 5 v 10%; the hd66205fl, a 2.7 to 5.5 v, low power dissipation device; the hd66205tf and hd66205tfl, thin film package devices each powered by 5 v 10% and 2.7 to 5.5 v; and the hd66205t, tape carrier package (tcp) devices powered by 2.7 to 5.5 v, respectively. features duty cycle: 1/64 to 1/240 high voltage lcd drive: 10 to 28 v display off function internal 80-bit shift register various lcd controller interfaces lctc series: hd63645, hd64645, hd64646 lvic series: hd66840, hd66841 cline: hd66850
ordering information 1 (flat package and die shipment) type no. voltage range package hd66205f 5 v 10% 100-pin plastic qfp (fp-100) hd66205fl 2.7 to 5.5 v 100-pin plastic qfp (fp-100) hd66205tf 5 v 10% 100-pin thin plastic qfp (tfp-100) hd66205tfl 2.7 to 5.5 v 100-pin thin plastic qfp (tfp-100) HCD66205 5 v 10% chip HCD66205l 2.7 to 5.5 v chip ordering information 2 (tape carrier package) type no. voltage range outer lead pitch 1 outer lead pitch 2 device length hd66205ta1 2.7 to 5.5v 0.15mm 0.80mm 4 sprocket holes hd66205ta2 2.7 to 5.5v 0.18mm 0.80mm 4 sprocket holes hd66205ta3 2.7 to 5.5v 0.20mm 0.80mm 4 sprocket holes hd66205ta6 2.7 to 5.5v 0.22mm 0.70mm 4 sprocket holes hd66205ta7 2.7 to 5.5v 0.25mm 0.70mm 4 sprocket holes hd66205ta9l 2.7 to 5.5v 0.22mm 0.70mm 3 sprocket holes notes: 1. outer lead pitch 1 is for lcd drive output pins, and outer lead pitch 2 for the other pins. 2. device length includes test pad areas. 3. spacing between two sprocket holes is 4.75mm. 4. tape film is upirex (a trademark of ube industries, ltd.). 5. 35-mm-wide tape is used. 6. leads are plated with sn. 7. the details of tcp pattern are shown in ?he information of tcp. 1000 hd66205
pin arrangement hd66205 1001 hd66205f hd66205fl (fp-100) (top view) x30 x29 x28 x27 x26 x25 x24 x23 x22 x21 x20 x19 x18 x17 x16 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x51 x52 x53 x54 x55 x56 x57 x58 x59 x60 x61 x62 x63 x64 x65 x66 x67 x68 x69 x70 x71 x72 x73 x74 x75 x76 x77 x78 x79 x80 x50 x49 x48 x47 x46 x45 x44 x43 x42 x41 x40 x39 x38 x37 x36 x35 x34 x33 x32 x31 nc dc nc v ee v5 v6 v1 nc dispoff v cc shl gnd nc m nc cl nc di nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1002 hd66205 x52 x51 x50 x49 x48 x47 x46 x45 x44 x43 x42 x41 x40 x39 x38 x37 x36 x35 x34 x33 x32 x31 x30 x29 x28 x27 x26 x25 x24 x23 x22 x21 x20 x19 x18 x17 x16 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x53 x54 x55 x56 x57 x58 x59 x60 x61 x62 x63 x64 x65 x66 x67 x68 x69 x70 x71 x72 x73 x74 x75 x76 x77 x78 x79 x80 nc nc do v ee v5 v6 v1 nc dispoff v cc shl gnd nc m nc cl nc di nc nc x1 x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 hd66205tf hd66205tfl (tfp-100) (top view)
pin description pin no. symbol (fp-100/tfp-100) pin name input/output classification v cc 40/38 v cc power supply gnd 42/40 gnd power supply v ee 34/32 v ee power supply v1 37/35 v1 input power supply v5 35/33 v5 input power supply v6 36/34 v6 input power supply cl 46/44 clock input control signal m 44/42 m input control signal di 48/46 data in input control signal do 32/31 data out output control signal shl 41/39 shift left input control signal dispoff 39/37 display off input control signal x 1 ? 80 51?00, 1?0/ x1?80 output lcd drive output 1?8, 49?00 nc 31, 33, 38, 43, no connection 45, 47, 49, 50/ 29, 30, 36, 41, 43, 45, 47, 48 hd66205 1003
pin functions power supply v cc , v ee , gnd: v cc ?nd supplies power to the internal logic circuits. v cc ? ee supplies power to the lcd drive circuits. v1, v5, v6: supply different levels of power to drive the lcd. v1 and v ee are selected levels, and v5 and v6 are non-selected levels. see figure 1. control signal cl: inputs data shift clock pulses for the shift register. at the falling edge of each cl pulse, the shift register shifts display data input via the di pin. m: changes lcd drive outputs to ac. di: inputs display data. di of the first hd66205 must be connected to an lcd controller, and those of the other hd66205s must be connected to di of the previous hd66205. do: outputs display data. do of the last hd66205 must be open, and those of the other hd66205s must be connected to di of the next hd66205. shl: selects the data shiftt direction for the shift register. see figure 2. dispoff : a low dispoff sets lcd drive outputs x1?80 to v1 level. lcd drive output x1?80: each x outputs one of the four voltage levels v1, v5, v6, or v ee , depending on a combination of the m signal and display data levels. see figure 3. other nc: must be open. 1004 hd66205 figure 1 different power supply voltage levels for lcd drive circuits v1 v6 v5 v ee
figure 2 selection of display data shift direction figure 3 selection of lcd drive output level hd66205 1005 di sr80 sr79 sr1 x1 x80 di sr1 sr2 sr80 x80 x1 low high common signal scan direction data shift direction shl level 10 0 11 0 v1 v5 v ee v6 m d x output level
block functions lcd drive circuit the 80-bit lcd drive circuit generates four voltage levels v1, v5, v6, and v ee , for driving an lcd panel. one of the four levels is output to the corresponding y pin, depending on a combination of the m signal and the data in the shift register. level shifter the level shifter changes 5-v signals into high- voltage signals for the lcd drive circuit. shift register the 80-bit shift register shifts data input via the di pin by one bit, and the one bit of shifted-out data is output from the do pin. both actions occur simultaneously at the falling edge of each shift clock (cl) pulse. 1006 hd66205 block diagram lcd drive circuit level shifter shift register x1?80 m dispoff cl di logic do shl v6, v ee v1, v5
comparison of the hd66205 with the hd61105 item hd66205 hd61105 display off function provided not provided lcd drive voltage range 10 to 28 v 10 to 26 v shift clock phase selection function not provided provided (fcs pin) relation between shl and see figure 4 see figure 4 lcd output destinations relation between lcd output see figure 5 see figure 5 levels, m, and data lcd drive v pins v1, v5, v6 v1, v2, v5, v6 (v2 level is the same as v ee level) figure 4 relation between shl and lcd output destinations for the hd66205 and hd61105 figure 5 relation between lcd output levels, m, and data for the hd66205 and hd61105 hd66205 1007 hd61105 hd66205 di sr80 sr79 sr1 x1 x80 di sr1 sr2 sr80 x80 x1 low high common signal scan direction data shift direction shl level di sr1 sr2 sr80 x80 x1 di sr80 sr79 sr1 x1 x80 low high common signal scan direction data shift direction shl level note the exact reverse relation for the two devices. hd61105 m d 1 0 1 0 1 0 v1 v5 v ee v6 x output level hd66205 v2 v6 v1 v5 x output level m d 1 0 1 0 1 0
operation timing figure 6 shows the operation timing for the appli- cation example. 1008 hd66205 figure 6 relation between shl and lcd output destinations 12 240 3 1 2 80 3 1 2 240 3 1 2 80 3 12 160 3 1 2 240 3 12 160 3 v1 v6 v5 v2 v6 v1 v5 v1 v6 v5 v5 v6 v5 v6 v5 v6 v5 v6 v5 v6 v5 v6 v5 v1 v5 v2 v1 v5 v1 v5 v1 v5 v1 v5 v6 v5 v2 v6 v6 v5 v1 v6 v6 v6 v6 v6 v6 v6 v1 v2 v6 v5 v2 v6 v2 v6 v2 v6 v2 v6 v2 v6 v1 v5 v5 v5 v5 v5 v5 v5 v2 1 frame 1 frame m dl cl x80 (com1) x79 (com2) x1 (com80) do x80 (com81) x79 (com82) x1 (com160) do x80 (com161) x79 (com162) x1 (com240) from lcd controller hd66205 (1) hd66205 (2) hd66205 (3)
application example hd66205 1009 car dispoff d0Cd3 m cl2 cl1 v4 v3 v1 v ee gnd v cc e shl hd66204 (8) v cc car dispoff d0Cd3 m cl2 cl1 v1 gnd v cc e shl hd66204 (2) v cc car y1Cy80 dispoff d0Cd3 m cl2 cl1 v4 v3 v1 shl hd66204 (1) v cc hd66205 (1) x1Cx80 shl di do m v cc gnd cl v ee v6 v5 v1 dispoff hd66205 (3) shl di do m v cc gnd cl v ee v6 v5 v1 dispoff com1 com2 com3 com239 com240 lcd panel of 640 240 dots; 1/240 duty cycle seg640 seg639 seg638 seg3 seg2 seg1 + e + e + e + e v ee r1 r1 r2 r1 r1 v cc gnd m dispoff d0Cd3 cl2 cl1 flm lcd controller v ee gnd v cc e the resistances of r1 and r2 depend on the type of the lcd panel used. for example, for an lcd panel with a 1/15 bias, r1 and r2 must be 3 k w and 33 k w , respectively. that is, r1/(4r1 + r2) should be 1/15. to stabilize the power supply, place two 0.1- m f capacitors near each lcd driver: one between the v cc and gnd pins, and the other between the v cc and v ee pins. notes: 1. 2. v cc v cc x1ex80 y1ey80 v4 v3 v ee y1ey80
absolute maximum ratings item symbol rating unit notes power supply voltage for logic circuits v cc ?.3 to +7.0 v 1 power supply voltage for lcd drive circuits v ee v cc ?30.0 to v cc + 0.3 v input voltage 1 v t1 ?.3 to v cc + 0.3 v 1, 2 input voltage 2 v t2 v ee ?0.3 to v cc + 0.3 v 1, 3 operating temperature t opr ?0 to +75 ? storage temperature t stg ?5 to +125 ? 4 notes: 1. the reference point is gnd (0 v). 2. applies to pins cl, m, shl, di, dispoff . 3. applies to pins v1, v5, and v6. 4. ?0 to +125? for tcp devices. 5. if the lsi is used beyond its absolute maximum ratings, it may be permanently damaged. it should always be used within its electrical characteristics in order to prevent malfunctioning or degradation of reliability. electrical characteristics dc characteristics for the hd66205f/hd66205tf (v cc = 5 v 10%, gnd = 0 v, v cc ?v ee = 10 to 28 v, and ta = ?0 to +75?, unless otherwise noted) item symbol pins min typ max unit condition notes input high voltage v ih 1 0.7 v cc ? cc v input low voltage v il 1 0 0.3 v cc v output high voltage v oh 2v cc ?0.4 v i oh = ?.4 ma output low voltage v ol 2 0.4 v i ol = 0.4 ma vi?j on resistance r on 3 2.0 k w i on = 100 m a1 input leakage current 1 i il1 1 ?.0 1.0 m av in = v cc to gnd input leakage current 2 i il2 4 ?5 25 m av in = v cc to v ee current consumption 1 i gnd 100 m af cl = 20 khz 2 v cc ?v ee = 28 v current consumption 2 i ee 150 500 m a same as above 2 pins and notes on next page. 1010 hd66205
dc characteristics for the hd66205fl/hd66205tfl/hd66205t (v cc = 2.7 to 5.5 v, gnd = 0 v, v cc ?v ee = 10 to 28 v, and ta = ?0 to +75?, unless otherwise noted) item symbol pins min max unit condition notes input high voltage v ih 1 0.7 v cc v cc v input low voltage v il 1 0 0.3 v cc v output high voltage v oh 2v cc ?0.4 v i oh = ?.4 ma output low voltage v ol 2 0.4 v i ol = 0.4 ma vi?j on resistance r on 3 2.0 k w i on = 100 a 1 input leakage current 1 i il1 1 ?.0 1.0 m av in = v cc to gnd input leakage current 2 i il2 4 ?5 25 m av in = v cc to v ee current consumption 1 i gnd 100 m af cl = 16.8 khz 2 f m = 35 hz v cc = 3.0 v v cc ?v ee = 28 v current consumption 2 i ee 250 m a same as above 2 pins: 1. cl, m, shl, di, dispoff 2. do 3. x1?80, v1, v5, v6 4. v1, v5, v6 notes: 1. indicates the resistance between one pin from x1?80 and another pin from v1, v5, v6, and v ee , when load current is applied to the x pin; defined under the following conditions. v cc ?v ee = 28 v v1, v6 = v cc ?{1/10(v cc ?v ee )} v5 = v ee + {1/10(v cc ?v ee )} v1 and v6 should be near v cc level, and v5 should be near v ee level (figure 7). all voltage must be within d v. d v is the range within which r on , the lcd drive circuits?output impedance, is stable. note that d v depends on power supply voltage v cc ? ee (figure 8). 2. input and output current is excluded. when a cmos input is floating, excess current flows from the power supply through the input circuit. to avoid this, v ih and v il must be held to v cc and gnd levels, respectively. 3. applies to standby mode. hd66205 1011
figure 7 relation between driver output waveform and level voltages figure 8 relation between v cc ?v ee and d v 1012 hd66205 d v d v v cc v1 v6 v5 v ee 2.8 1.0 10 28 d v (v) v cc e v ee (v) level voltage range
ac characteristics for the hd66205f/hd66205tf (v cc = 5 v 10%, gnd = 0 v, and ta = ?0 to +75?, unless otherwise noted) item symbol pins min max unit note clock cycle time t cyc cl 10 m s clock high-level width t cwh cl 50 ns clock low-level width t cwl cl 1.0 m s clock rise time t r cl 30 ns clock fall time t f cl 30 ns data setup time t ds di, cl 100 ns data hold time t dh di, cl 100 ns data output delay time t dd do, cl 3.0 m s1 data output hold time t dhw do, cl 100 ns disp off ( dispoff ) rise time t r2 dispoff 200 ns disp off ( dispoff ) fall time t f2 dispoff 200 ns ac characteristics for the hd66205fl/hd66205tfl/hd66205t (v cc = 2.7 to 5.5 v, gnd = 0 v, and ta = ?0 to +75?, unless otherwise noted) item symbol pins min max unit note clock cycle time t cyc cl 10 m s clock high-level width t cwh cl 80 ns clock low-level width t cwl cl 1.0 m s clock rise time t r cl 30 ns clock fall time t f cl 30 ns data setup time t ds di, cl 100 ns data hold time t dh di, cl 100 ns data output delay time t dd do, cl 7.0 m s1 data output hold time t dhw do, cl 100 ns disp off ( dispoff ) rise time t r2 dispoff 200 ns disp off ( dispoff ) fall time t f2 dispoff 200 ns note: 1. the load circuit shown in figure 9 is connected. figure 9 load circuit hd66205 1013 30 pf test point
figure 10 lcd controller interface timing 1014 hd66205 cl di do 0.7v cc 0.3v cc 0.8v cc 0.2v cc 0.7v cc 0.3v cc t f t cwl t cwh t r t cyc t dh t ds t dd t dhw t f2 t r2 0.7v cc 0.3v cc 0.7v cc 0.3v cc dispoff

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